From patchwork Thu Aug 18 23:41:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 12948177 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1BFDEC00140 for ; Thu, 18 Aug 2022 23:43:25 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2727E10E6C3; Thu, 18 Aug 2022 23:42:54 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 65BC910E10E; Thu, 18 Aug 2022 23:42:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660866150; x=1692402150; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=kdvVoIeLy0iXAJCCpVUxcEBeGS0iH6SL6YNTPZx4BK4=; b=ltEErDgFsYho5bCoA4YQYZ7zOv5oRWCJPGAoXA964FXG98nLF6sF1eNp ast+aFGIIXXpOq0LdMyimqT9KC6z22sMajONFIPLaQ2xP1CjqSyBxS2+s YM5N2Y4cmYNsRtubAZYnmv9BvAqFBONEUSLfhujy/QE8NJBjG8e2/Yqpo zPt3vS6FEMTbsP+AYhjeeXlvOwiGjRzaGXcOmdhFpT9hiXdpwE0Gpx8d8 SkLrKf89jipeoc1T0AGAYjniDPER/kUIFnmAhp+4Pm5h6AgOTXX+1fglA ethf5wviAYBSBMWKdUChGJSwW2vsXjSD/ipdind9KmVJdqIGw6C0lD/2p w==; X-IronPort-AV: E=McAfee;i="6500,9779,10443"; a="275938510" X-IronPort-AV: E=Sophos;i="5.93,247,1654585200"; d="scan'208";a="275938510" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Aug 2022 16:42:28 -0700 X-IronPort-AV: E=Sophos;i="5.93,247,1654585200"; d="scan'208";a="783953283" Received: from invictus.jf.intel.com ([10.165.21.205]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Aug 2022 16:42:28 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Subject: [PATCH v2 01/21] drm/i915: Read graphics/media/display arch version from hw Date: Thu, 18 Aug 2022 16:41:42 -0700 Message-Id: <20220818234202.451742-2-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220818234202.451742-1-radhakrishna.sripada@intel.com> References: <20220818234202.451742-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Matt Roper Going forward, the hardware teams no longer consider new platforms to have a "generation" in the way we've defined it for past platforms. Instead, each IP block (graphics, media, display) will have their own architecture major.minor versions and stepping ID's which should be read directly from a register in the MMIO space. New hardware programming styles, features, and workarounds should be conditional solely on the architecture version, and should no longer be derived from the PCI device ID, revision ID, or platform-specific feature flags. v1.1: Fix build error Bspec: 63361, 64111 Signed-off-by: Matt Roper Signed-off-by: Rodrigo Vivi Signed-off-by: Radhakrishna Sripada --- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 + drivers/gpu/drm/i915/i915_driver.c | 80 ++++++++++++++++++- drivers/gpu/drm/i915/i915_drv.h | 16 ++-- drivers/gpu/drm/i915/i915_pci.c | 1 + drivers/gpu/drm/i915/i915_reg.h | 6 ++ drivers/gpu/drm/i915/intel_device_info.c | 32 ++++---- drivers/gpu/drm/i915/intel_device_info.h | 14 ++++ .../gpu/drm/i915/selftests/mock_gem_device.c | 1 + 8 files changed, 128 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h index 94f9ddcfb3a5..a053493dae24 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h @@ -39,6 +39,8 @@ #define FORCEWAKE_ACK_RENDER_GEN9 _MMIO(0xd84) #define FORCEWAKE_ACK_MEDIA_GEN9 _MMIO(0xd88) +#define GMD_ID_GRAPHICS _MMIO(0xd8c) + #define MCFG_MCR_SELECTOR _MMIO(0xfd0) #define SF_MCR_SELECTOR _MMIO(0xfd8) #define GEN8_MCR_SELECTOR _MMIO(0xfdc) diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c index deb8a8b76965..33566f6e9546 100644 --- a/drivers/gpu/drm/i915/i915_driver.c +++ b/drivers/gpu/drm/i915/i915_driver.c @@ -70,6 +70,7 @@ #include "gem/i915_gem_pm.h" #include "gt/intel_gt.h" #include "gt/intel_gt_pm.h" +#include "gt/intel_gt_regs.h" #include "gt/intel_rc6.h" #include "pxp/intel_pxp_pm.h" @@ -306,15 +307,83 @@ static void sanitize_gpu(struct drm_i915_private *i915) __intel_gt_reset(to_gt(i915), ALL_ENGINES); } +#define IP_VER_READ(offset, ri_prefix) \ + addr = pci_iomap_range(pdev, 0, offset, sizeof(u32)); \ + if (drm_WARN_ON(&i915->drm, !addr)) { \ + /* Fall back to whatever was in the device info */ \ + RUNTIME_INFO(i915)->ri_prefix.ver = INTEL_INFO(i915)->ri_prefix.ver; \ + RUNTIME_INFO(i915)->ri_prefix.rel = INTEL_INFO(i915)->ri_prefix.rel; \ + goto ri_prefix##done; \ + } \ + \ + ver = ioread32(addr); \ + pci_iounmap(pdev, addr); \ + \ + RUNTIME_INFO(i915)->ri_prefix.ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, ver); \ + RUNTIME_INFO(i915)->ri_prefix.rel = REG_FIELD_GET(GMD_ID_RELEASE_MASK, ver); \ + RUNTIME_INFO(i915)->ri_prefix.step = REG_FIELD_GET(GMD_ID_STEP, ver); \ + \ + /* Sanity check against expected versions from device info */ \ + if (RUNTIME_INFO(i915)->ri_prefix.ver != INTEL_INFO(i915)->ri_prefix.ver || \ + RUNTIME_INFO(i915)->ri_prefix.rel > INTEL_INFO(i915)->ri_prefix.rel) \ + drm_dbg(&i915->drm, \ + "Hardware reports " #ri_prefix " IP version %u.%u but minimum expected is %u.%u\n", \ + RUNTIME_INFO(i915)->ri_prefix.ver, \ + RUNTIME_INFO(i915)->ri_prefix.rel, \ + INTEL_INFO(i915)->ri_prefix.ver, \ + INTEL_INFO(i915)->ri_prefix.rel); \ +ri_prefix##done: + +/** + * intel_ipver_early_init - setup IP version values + * @dev_priv: device private + * + * Setup the graphics version for the current device. This must be done before + * any code that performs checks on GRAPHICS_VER or DISPLAY_VER, so this + * function should be called very early in the driver initialization sequence. + * + * Regular MMIO access is not yet setup at the point this function is called so + * we peek at the appropriate MMIO offset directly. The GMD_ID register is + * part of an 'always on' power well by design, so we don't need to worry about + * forcewake while reading it. + */ +static void intel_ipver_early_init(struct drm_i915_private *i915) +{ + struct pci_dev *pdev = to_pci_dev(i915->drm.dev); + void __iomem *addr; + u32 ver; + + if (!HAS_GMD_ID(i915)) { + drm_WARN_ON(&i915->drm, INTEL_INFO(i915)->graphics.ver > 12); + + RUNTIME_INFO(i915)->graphics.ver = INTEL_INFO(i915)->graphics.ver; + RUNTIME_INFO(i915)->graphics.rel = INTEL_INFO(i915)->graphics.rel; + /* media ver = graphics ver for older platforms */ + RUNTIME_INFO(i915)->media.ver = INTEL_INFO(i915)->graphics.ver; + RUNTIME_INFO(i915)->media.rel = INTEL_INFO(i915)->graphics.rel; + RUNTIME_INFO(i915)->display.ver = INTEL_INFO(i915)->display.ver; + RUNTIME_INFO(i915)->display.rel = INTEL_INFO(i915)->display.rel; + return; + } + + IP_VER_READ(i915_mmio_reg_offset(GMD_ID_GRAPHICS), graphics); + IP_VER_READ(i915_mmio_reg_offset(GMD_ID_DISPLAY), display); + IP_VER_READ(MTL_MEDIA_GSI_BASE + i915_mmio_reg_offset(GMD_ID_GRAPHICS), + media); +} + /** * i915_driver_early_probe - setup state not requiring device access * @dev_priv: device private + * @ent: PCI device info entry matched * * Initialize everything that is a "SW-only" state, that is state not * requiring accessing the device or exposing the driver via kernel internal * or userspace interfaces. Example steps belonging here: lock initialization, * system memory allocation, setting up device specific attributes and * function hooks not requiring accessing the device. + * + * GRAPHICS_VER, DISPLAY_VER, etc. are not yet usable at this point. For */ static int i915_driver_early_probe(struct drm_i915_private *dev_priv) { @@ -855,13 +924,22 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent) return PTR_ERR(i915); /* Disable nuclear pageflip by default on pre-ILK */ - if (!i915->params.nuclear_pageflip && DISPLAY_VER(i915) < 5) + if (!i915->params.nuclear_pageflip && + !HAS_GMD_ID(i915) && DISPLAY_VER(i915) < 5) i915->drm.driver_features &= ~DRIVER_ATOMIC; ret = pci_enable_device(pdev); if (ret) goto out_fini; + /* + * GRAPHICS_VER() and DISPLAY_VER() will return 0 before this is + * called, so we want to take care of this very early in the + * initialization process (as soon as we can peek into the MMIO BAR), + * even before we setup regular MMIO access. + */ + intel_ipver_early_init(i915); + ret = i915_driver_early_probe(i915); if (ret < 0) goto out_pci_disable; diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 086bbe8945d6..7ebddde200bc 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -856,19 +856,19 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915) #define IP_VER(ver, rel) ((ver) << 8 | (rel)) -#define GRAPHICS_VER(i915) (INTEL_INFO(i915)->graphics.ver) -#define GRAPHICS_VER_FULL(i915) IP_VER(INTEL_INFO(i915)->graphics.ver, \ - INTEL_INFO(i915)->graphics.rel) +#define GRAPHICS_VER(i915) (RUNTIME_INFO(i915)->graphics.ver) +#define GRAPHICS_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->graphics.ver, \ + RUNTIME_INFO(i915)->graphics.rel) #define IS_GRAPHICS_VER(i915, from, until) \ (GRAPHICS_VER(i915) >= (from) && GRAPHICS_VER(i915) <= (until)) -#define MEDIA_VER(i915) (INTEL_INFO(i915)->media.ver) -#define MEDIA_VER_FULL(i915) IP_VER(INTEL_INFO(i915)->media.ver, \ - INTEL_INFO(i915)->media.rel) +#define MEDIA_VER(i915) (RUNTIME_INFO(i915)->media.ver) +#define MEDIA_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->media.ver, \ + RUNTIME_INFO(i915)->media.rel) #define IS_MEDIA_VER(i915, from, until) \ (MEDIA_VER(i915) >= (from) && MEDIA_VER(i915) <= (until)) -#define DISPLAY_VER(i915) (INTEL_INFO(i915)->display.ver) +#define DISPLAY_VER(i915) (RUNTIME_INFO(i915)->display.ver) #define IS_DISPLAY_VER(i915, from, until) \ (DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until)) @@ -1300,6 +1300,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, */ #define NEEDS_COMPACT_PT(dev_priv) (INTEL_INFO(dev_priv)->needs_compact_pt) +#define HAS_GMD_ID(i915) INTEL_INFO(i915)->has_gmd_id + #define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc) #define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i)) diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 9fd788e147a3..b60f01d072a7 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -1127,6 +1127,7 @@ static const struct intel_device_info mtl_info = { PLATFORM(INTEL_METEORLAKE), .display.has_modular_fia = 1, .has_flat_ccs = 0, + .has_gmd_id = 1, .has_snoop = 1, .memory_regions = REGION_SMEM | REGION_STOLEN_LMEM, .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(CCS0), diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 50d7bfd541ad..15a53cb5e1ee 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5860,6 +5860,11 @@ #define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29) #define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz (2 << 29) +#define GMD_ID_DISPLAY _MMIO(0x510a0) +#define GMD_ID_ARCH_MASK REG_GENMASK(31, 22) +#define GMD_ID_RELEASE_MASK REG_GENMASK(21, 14) +#define GMD_ID_STEP REG_GENMASK(5, 0) + /*GEN11 chicken */ #define _PIPEA_CHICKEN 0x70038 #define _PIPEB_CHICKEN 0x71038 @@ -8353,4 +8358,5 @@ enum skl_power_gate { #define GEN12_CULLBIT2 _MMIO(0x7030) #define GEN12_STATE_ACK_DEBUG _MMIO(0x20BC) +#define MTL_MEDIA_GSI_BASE 0x380000 #endif /* _I915_REG_H_ */ diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index d98fbbd589aa..4ca8f78bfbd7 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -91,22 +91,6 @@ const char *intel_platform_name(enum intel_platform platform) void intel_device_info_print_static(const struct intel_device_info *info, struct drm_printer *p) { - if (info->graphics.rel) - drm_printf(p, "graphics version: %u.%02u\n", info->graphics.ver, - info->graphics.rel); - else - drm_printf(p, "graphics version: %u\n", info->graphics.ver); - - if (info->media.rel) - drm_printf(p, "media version: %u.%02u\n", info->media.ver, info->media.rel); - else - drm_printf(p, "media version: %u\n", info->media.ver); - - if (info->display.rel) - drm_printf(p, "display version: %u.%02u\n", info->display.ver, info->display.rel); - else - drm_printf(p, "display version: %u\n", info->display.ver); - drm_printf(p, "gt: %d\n", info->gt); drm_printf(p, "memory-regions: %x\n", info->memory_regions); drm_printf(p, "page-sizes: %x\n", info->page_sizes); @@ -127,6 +111,22 @@ void intel_device_info_print_static(const struct intel_device_info *info, void intel_device_info_print_runtime(const struct intel_runtime_info *info, struct drm_printer *p) { + if (info->graphics.rel) + drm_printf(p, "graphics version: %u.%02u\n", info->graphics.ver, + info->graphics.rel); + else + drm_printf(p, "graphics version: %u\n", info->graphics.ver); + + if (info->media.rel) + drm_printf(p, "media version: %u.%02u\n", info->media.ver, info->media.rel); + else + drm_printf(p, "media version: %u\n", info->media.ver); + + if (info->display.rel) + drm_printf(p, "display version: %u.%02u\n", info->display.ver, info->display.rel); + else + drm_printf(p, "display version: %u\n", info->display.ver); + drm_printf(p, "rawclk rate: %u kHz\n", info->rawclk_freq); } diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index 23bf230aa104..327e62875871 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -146,6 +146,7 @@ enum intel_ppgtt_type { func(has_64bit_reloc); \ func(has_64k_pages); \ func(needs_compact_pt); \ + func(has_gmd_id); \ func(gpu_reset_clobbers_display); \ func(has_reset_engine); \ func(has_3d_pipeline); \ @@ -200,6 +201,7 @@ enum intel_ppgtt_type { struct ip_version { u8 ver; u8 rel; + u8 step; }; struct intel_device_info { @@ -271,6 +273,18 @@ struct intel_runtime_info { */ u32 platform_mask[2]; + /* + * On modern platforms, the architecture major.minor version numbers + * and stepping are read directly from the hardware rather than derived + * from the PCI device and revision ID's. + * + * Note that the hardware gives us a single "graphics" number that + * should represent render, compute, and copy behavior. + */ + struct ip_version graphics; + struct ip_version media; + struct ip_version display; + u16 device_id; u8 num_sprites[I915_MAX_PIPES]; diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c index 9c31a16f8380..91ad444cd532 100644 --- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c +++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c @@ -173,6 +173,7 @@ struct drm_i915_private *mock_gem_device(void) drm_mode_config_init(&i915->drm); mkwrite_device_info(i915)->graphics.ver = -1; + RUNTIME_INFO(i915)->graphics.ver = ~0; mkwrite_device_info(i915)->page_sizes = I915_GTT_PAGE_SIZE_4K | From patchwork Thu Aug 18 23:41:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 12948178 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 86252C00140 for ; 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a="275938511" X-IronPort-AV: E=Sophos;i="5.93,247,1654585200"; d="scan'208";a="275938511" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Aug 2022 16:42:28 -0700 X-IronPort-AV: E=Sophos;i="5.93,247,1654585200"; d="scan'208";a="783953285" Received: from invictus.jf.intel.com ([10.165.21.205]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Aug 2022 16:42:28 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Subject: [PATCH v2 02/21] drm/i915: Parse and set stepping for platforms with GMD Date: Thu, 18 Aug 2022 16:41:43 -0700 Message-Id: <20220818234202.451742-3-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220818234202.451742-1-radhakrishna.sripada@intel.com> References: <20220818234202.451742-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: José Roberto de Souza The GMD step field do not properly match the current stepping convention that we use(STEP_A0, STEP_A1, STEP_B0...). One platform could have { arch = 12, rel = 70, step = 1 } and the actual stepping is STEP_B0 but without the translation of the step field would mean STEP_A1. That is why we will need to have gmd_to_intel_step tables for each IP. Signed-off-by: José Roberto de Souza Signed-off-by: Radhakrishna Sripada Reviewed-by: Balasubramani Vivekanandan --- drivers/gpu/drm/i915/intel_step.c | 60 +++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c index 42b3133d8387..0fa7147c7d0f 100644 --- a/drivers/gpu/drm/i915/intel_step.c +++ b/drivers/gpu/drm/i915/intel_step.c @@ -135,6 +135,48 @@ static const struct intel_step_info adlp_n_revids[] = { [0x0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_D0 }, }; +struct gmd_to_intel_step { + struct ip_version gmd; + enum intel_step step; +}; + +static const struct gmd_to_intel_step gmd_graphics_table[] = { + { .gmd.ver = 12, .gmd.rel = 70, .gmd.step = 0, .step = STEP_A0 }, + { .gmd.ver = 12, .gmd.rel = 70, .gmd.step = 4, .step = STEP_B0 }, + { .gmd.ver = 12, .gmd.rel = 71, .gmd.step = 0, .step = STEP_A0 }, + { .gmd.ver = 12, .gmd.rel = 71, .gmd.step = 4, .step = STEP_B0 }, + { .gmd.ver = 12, .gmd.rel = 73, .gmd.step = 0, .step = STEP_A0 }, + { .gmd.ver = 12, .gmd.rel = 73, .gmd.step = 4, .step = STEP_B0 }, +}; + +static const struct gmd_to_intel_step gmd_media_table[] = { + { .gmd.ver = 13, .gmd.rel = 70, .gmd.step = 0, .step = STEP_A0 }, + { .gmd.ver = 13, .gmd.rel = 70, .gmd.step = 4, .step = STEP_B0 }, +}; + +static const struct gmd_to_intel_step gmd_display_table[] = { + { .gmd.ver = 14, .gmd.rel = 0, .gmd.step = 0, .step = STEP_A0 }, + { .gmd.ver = 14, .gmd.rel = 0, .gmd.step = 4, .step = STEP_B0 }, +}; + +static u8 gmd_to_intel_step(struct drm_i915_private *i915, + struct ip_version *gmd, + const struct gmd_to_intel_step *table, + int len) +{ + int i; + + for (i = 0; i < len; i++) { + if (table[i].gmd.ver == gmd->ver && + table[i].gmd.rel == gmd->rel && + table[i].gmd.step == gmd->step) + return table[i].step; + } + + drm_dbg(&i915->drm, "Using future steppings\n"); + return STEP_FUTURE; +} + static void pvc_step_init(struct drm_i915_private *i915, int pci_revid); void intel_step_init(struct drm_i915_private *i915) @@ -144,6 +186,24 @@ void intel_step_init(struct drm_i915_private *i915) int revid = INTEL_REVID(i915); struct intel_step_info step = {}; + if (HAS_GMD_ID(i915)) { + step.graphics_step = gmd_to_intel_step(i915, + &RUNTIME_INFO(i915)->graphics, + gmd_graphics_table, + ARRAY_SIZE(gmd_graphics_table)); + step.media_step = gmd_to_intel_step(i915, + &RUNTIME_INFO(i915)->media, + gmd_media_table, + ARRAY_SIZE(gmd_media_table)); + step.display_step = gmd_to_intel_step(i915, + &RUNTIME_INFO(i915)->display, + gmd_display_table, + ARRAY_SIZE(gmd_display_table)); + RUNTIME_INFO(i915)->step = step; + + return; + } + if (IS_PONTEVECCHIO(i915)) { pvc_step_init(i915, revid); return; From patchwork Thu Aug 18 23:41:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 12948180 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C8028C00140 for ; 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a="275938512" X-IronPort-AV: E=Sophos;i="5.93,247,1654585200"; d="scan'208";a="275938512" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Aug 2022 16:42:28 -0700 X-IronPort-AV: E=Sophos;i="5.93,247,1654585200"; d="scan'208";a="783953286" Received: from invictus.jf.intel.com ([10.165.21.205]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Aug 2022 16:42:28 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Subject: [PATCH v2 03/21] drm/i915/mtl: MMIO range is now 4MB Date: Thu, 18 Aug 2022 16:41:44 -0700 Message-Id: <20220818234202.451742-4-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220818234202.451742-1-radhakrishna.sripada@intel.com> References: <20220818234202.451742-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Matt Roper Previously only dgfx platforms had a 4MB MMIO range, but starting with MTL we now use the larger range for all platforms. Bspec: 63834, 63830 Signed-off-by: Matt Roper Signed-off-by: Radhakrishna Sripada Reviewed-by: Balasubramani Vivekanandan --- drivers/gpu/drm/i915/intel_uncore.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index a852c471d1b3..e0a8a8cb2052 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -2232,14 +2232,15 @@ int intel_uncore_setup_mmio(struct intel_uncore *uncore, phys_addr_t phys_addr) * clobbering the GTT which we want ioremap_wc instead. Fortunately, * the register BAR remains the same size for all the earlier * generations up to Ironlake. - * For dgfx chips register range is expanded to 4MB. + * For dgfx chips register range is expanded to 4MB, and this larger + * range is also used for integrated gpus beginning with Meteor Lake. */ - if (GRAPHICS_VER(i915) < 5) - mmio_size = 512 * 1024; - else if (IS_DGFX(i915)) + if (IS_DGFX(i915) || GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) mmio_size = 4 * 1024 * 1024; - else + else if (GRAPHICS_VER(i915) >= 5) mmio_size = 2 * 1024 * 1024; + else + mmio_size = 512 * 1024; uncore->regs = ioremap(phys_addr, mmio_size); if (uncore->regs == NULL) { From patchwork Thu Aug 18 23:41:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 12948176 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 40B97C00140 for ; Thu, 18 Aug 2022 23:43:21 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E3F7F10E5B5; Thu, 18 Aug 2022 23:42:53 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5147010E0F5; Thu, 18 Aug 2022 23:42:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660866151; x=1692402151; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=PoL3yK0ImehlOTU2l+wQfLBeHG0RQjyduAp5rYKn0b0=; b=T4AEgpRjmUf0g2nE1nGbQ0zZ/EiXBMbNJcm6Vh9pS1HTK53y7BgTUWr6 N2CMXW+aZa5L133F6VN1/jQSTEjCNp6AN41sS5neHw04qfmpZ797QcQFG DPn0Q/tYx3uEzqWxbwuyj2KZ9tMBgtWqu14/a4BPYOYQCHQSO8fuWovOI GtGGmINEftMevYYcAAxaD9krr36a5cdu68z7O5JTCVfzaY1xvaf2i7K0w iHFByYHFPkstyPgKMVmKqaH3IAtpliMhYXVdumO9x2PCMkidejMmXHFoB lNPu2blI99jSsWoKOk5UfxZyyao4H5waxS6J/+N2+rPG6/wZYAjH2SN+4 g==; X-IronPort-AV: E=McAfee;i="6500,9779,10443"; a="275938515" X-IronPort-AV: E=Sophos;i="5.93,247,1654585200"; d="scan'208";a="275938515" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Aug 2022 16:42:28 -0700 X-IronPort-AV: E=Sophos;i="5.93,247,1654585200"; d="scan'208";a="783953287" Received: from invictus.jf.intel.com ([10.165.21.205]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Aug 2022 16:42:28 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Subject: [PATCH v2 04/21] drm/i915/mtl: Don't mask off CCS according to DSS fusing Date: Thu, 18 Aug 2022 16:41:45 -0700 Message-Id: <20220818234202.451742-5-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220818234202.451742-1-radhakrishna.sripada@intel.com> References: <20220818234202.451742-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Matt Roper Unlike the Xe_HP platforms, MTL only has a single CCS engine; the quad-based engine masking logic does not apply to this platform (or presumably any future platforms that only have 0 or 1 CCS). Signed-off-by: Matt Roper Signed-off-by: Radhakrishna Sripada Reviewed-by: Balasubramani Vivekanandan --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index 37fa813af766..17e7f20bbb48 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -672,7 +672,7 @@ static void engine_mask_apply_compute_fuses(struct intel_gt *gt) unsigned long ccs_mask; unsigned int i; - if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50)) + if (hweight32(CCS_MASK(gt)) <= 1) return; ccs_mask = intel_slicemask_from_xehp_dssmask(info->sseu.compute_subslice_mask, From patchwork Thu Aug 18 23:41:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 12948179 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B7E06C00140 for ; Thu, 18 Aug 2022 23:43:34 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 42DF510E665; Thu, 18 Aug 2022 23:42:57 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5192110E3EE; Thu, 18 Aug 2022 23:42:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660866151; x=1692402151; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=tbEtRN6dHvsMKxZq3oAz70k5dFqtVETWUR2Hrdut4Ag=; b=WSl4NvQvLS3bub2HB2FVkivTPaZo4WPjWbQ8Gq5vh+pQp7rPSB7YvaXJ MwKDD2Xs7QJaIbSEAukxHZCwySB9Xb6Kl6X66+FnQsjZqtxs9tLUIz2qh zIhZ9B+BfYk6izJjTiY7yciYB5EoQB41Na/X+Gb1AUQmRVVWZSTDqYoVb h4W37JUHdOiT5dRE56Pkyfj9IVa9xaRQLg27C3Ufl0RHYfwgpsMXJ9GxM sDEiF903xhh2W1neNWZvdsl9t+nHZHJ+SY911Kj2NfS8N99x5vmsa751P IFcX2lPcB0oqJpkUp3TVyk0+BtDAoE8u1izkuWP5VmGhVig6QR3K8Q4Eu g==; X-IronPort-AV: E=McAfee;i="6500,9779,10443"; a="275938516" X-IronPort-AV: E=Sophos;i="5.93,247,1654585200"; d="scan'208";a="275938516" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Aug 2022 16:42:28 -0700 X-IronPort-AV: E=Sophos;i="5.93,247,1654585200"; d="scan'208";a="783953288" Received: from invictus.jf.intel.com ([10.165.21.205]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Aug 2022 16:42:28 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Subject: [PATCH v2 05/21] drm/i915/mtl: Define engine context layouts Date: Thu, 18 Aug 2022 16:41:46 -0700 Message-Id: <20220818234202.451742-6-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220818234202.451742-1-radhakrishna.sripada@intel.com> References: <20220818234202.451742-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Matt Roper The part of the media and blitter engine contexts that we care about for setting up an initial state are the same on MTL as they were on DG2 (and PVC), so we need to update the driver conditions to re-use the DG2 context table. For render/compute engines, the part of the context images are nearly the same, although the layout had a very slight change --- one POSH register was removed and the placement of some LRI/noops adjusted slightly to compensate. Bspec: 46261, 46260, 45585 Signed-off-by: Matt Roper Signed-off-by: Radhakrishna Sripada --- drivers/gpu/drm/i915/gt/intel_lrc.c | 47 ++++++++++++++++++++++++++++- 1 file changed, 46 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index eec73c66406c..d3833cbaabcb 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -606,6 +606,49 @@ static const u8 dg2_rcs_offsets[] = { END }; +static const u8 mtl_rcs_offsets[] = { + NOP(1), + LRI(15, POSTED), + REG16(0x244), + REG(0x034), + REG(0x030), + REG(0x038), + REG(0x03c), + REG(0x168), + REG(0x140), + REG(0x110), + REG(0x1c0), + REG(0x1c4), + REG(0x1c8), + REG(0x180), + REG16(0x2b4), + REG(0x120), + REG(0x124), + + NOP(1), + LRI(9, POSTED), + REG16(0x3a8), + REG16(0x28c), + REG16(0x288), + REG16(0x284), + REG16(0x280), + REG16(0x27c), + REG16(0x278), + REG16(0x274), + REG16(0x270), + + NOP(2), + LRI(2, POSTED), + REG16(0x5a8), + REG16(0x5ac), + + NOP(6), + LRI(1, 0), + REG(0x0c8), + + END +}; + #undef END #undef REG16 #undef REG @@ -624,7 +667,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine) !intel_engine_has_relative_mmio(engine)); if (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE) { - if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55)) + if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 70)) + return mtl_rcs_offsets; + else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55)) return dg2_rcs_offsets; else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50)) return xehp_rcs_offsets; From patchwork Thu Aug 18 23:41:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 12948174 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1B3D3C00140 for ; Thu, 18 Aug 2022 23:43:10 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 310A810E2ED; Thu, 18 Aug 2022 23:42:51 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id AEE8F10E22D; Thu, 18 Aug 2022 23:42:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660866150; x=1692402150; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=0f3s7kZPDS7+F8oYlXP6s6G+BXn33hxP3bZbP5oe0ZY=; b=BIiAJY2zTLR9kILUAlW846VghFVhoDI/JoKKqhtRHlR4B7bjHIODb7ux G/5h3hN72KbLURy/1Ny/FWWRm4G8k7DQYRYs8/nCrCNixb6mIlUQNC154 vZnAqr4HXErS4D6hdQUKxXPuw4X8xwXSrgF81HizOqbrzid3maSW2g7UY m6MrNc2mgf5aV6qKi31AiRNLjANrAwNs63F687iSzzZWWcSsY3WR1h3pX PLjX9iZsq2gaBmaDbXEhGvvOaU91JklyAUuUFUf201DDE09rvCn9NsjKq x//cwDHrjTHjWvsTCd5qt5qQBfKWz1gGKaaRghRo40VazMBwq2yyYXSdS Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10443"; a="275938513" X-IronPort-AV: E=Sophos;i="5.93,247,1654585200"; d="scan'208";a="275938513" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Aug 2022 16:42:28 -0700 X-IronPort-AV: E=Sophos;i="5.93,247,1654585200"; d="scan'208";a="783953289" Received: from invictus.jf.intel.com ([10.165.21.205]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Aug 2022 16:42:28 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Subject: [PATCH v2 06/21] drm/i915/mtl: Add PCH support Date: Thu, 18 Aug 2022 16:41:47 -0700 Message-Id: <20220818234202.451742-7-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220818234202.451742-1-radhakrishna.sripada@intel.com> References: <20220818234202.451742-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add support for Meteorpoint(MTP) PCH used with Meteorlake. Cc: Matt Roper Reviewed-by: Anusha Srivatsa Signed-off-by: Clint Taylor Signed-off-by: Radhakrishna Sripada --- drivers/gpu/drm/i915/intel_pch.c | 9 ++++++++- drivers/gpu/drm/i915/intel_pch.h | 4 ++++ 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_pch.c b/drivers/gpu/drm/i915/intel_pch.c index 0fec25be146a..ba9843cb1b13 100644 --- a/drivers/gpu/drm/i915/intel_pch.c +++ b/drivers/gpu/drm/i915/intel_pch.c @@ -138,6 +138,11 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id) drm_WARN_ON(&dev_priv->drm, !IS_ALDERLAKE_S(dev_priv) && !IS_ALDERLAKE_P(dev_priv)); return PCH_ADP; + case INTEL_PCH_MTP_DEVICE_ID_TYPE: + case INTEL_PCH_MTP2_DEVICE_ID_TYPE: + drm_dbg_kms(&dev_priv->drm, "Found Meteor Lake PCH\n"); + drm_WARN_ON(&dev_priv->drm, !IS_METEORLAKE(dev_priv)); + return PCH_MTP; default: return PCH_NONE; } @@ -166,7 +171,9 @@ intel_virt_detect_pch(const struct drm_i915_private *dev_priv, * make an educated guess as to which PCH is really there. */ - if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) + if (IS_METEORLAKE(dev_priv)) + id = INTEL_PCH_MTP_DEVICE_ID_TYPE; + else if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) id = INTEL_PCH_ADP_DEVICE_ID_TYPE; else if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv)) id = INTEL_PCH_TGP_DEVICE_ID_TYPE; diff --git a/drivers/gpu/drm/i915/intel_pch.h b/drivers/gpu/drm/i915/intel_pch.h index 7c8ce9781d1a..32aff5a70d04 100644 --- a/drivers/gpu/drm/i915/intel_pch.h +++ b/drivers/gpu/drm/i915/intel_pch.h @@ -25,6 +25,7 @@ enum intel_pch { PCH_ICP, /* Ice Lake/Jasper Lake PCH */ PCH_TGP, /* Tiger Lake/Mule Creek Canyon PCH */ PCH_ADP, /* Alder Lake PCH */ + PCH_MTP, /* Meteor Lake PCH */ /* Fake PCHs, functionality handled on the same PCI dev */ PCH_DG1 = 1024, @@ -57,12 +58,15 @@ enum intel_pch { #define INTEL_PCH_ADP2_DEVICE_ID_TYPE 0x5180 #define INTEL_PCH_ADP3_DEVICE_ID_TYPE 0x7A00 #define INTEL_PCH_ADP4_DEVICE_ID_TYPE 0x5480 +#define INTEL_PCH_MTP_DEVICE_ID_TYPE 0x7E00 +#define INTEL_PCH_MTP2_DEVICE_ID_TYPE 0xAE00 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */ #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type) #define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id) +#define HAS_PCH_MTP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_MTP) #define HAS_PCH_DG2(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_DG2) #define HAS_PCH_ADP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ADP) #define HAS_PCH_DG1(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_DG1) From patchwork Thu Aug 18 23:41:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 12948175 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 45FCDC00140 for ; Thu, 18 Aug 2022 23:43:14 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2A8F110E27A; Thu, 18 Aug 2022 23:42:51 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id F06B510E2BF; Thu, 18 Aug 2022 23:42:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660866151; x=1692402151; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=oxp/KT3lcoH1nMx4gHY3iAIRxIofieLfnONlm/0JH8k=; b=ELL5uynEmacOHGdlCyfWETZUIcDBoPXFNXyBNt/pF37rSWkUxPR1Yq3V T0T6EBvNqsSB9/a9iHrum0WhFzNPbAsKo5TgpvjSFQbFK5o5rGkj20K7t UYeTjbcTnPLHVC+LdZn2Zp5frqdocXak2RmGeo+eVgY7yy2j2SY3JhEe7 tkKFEvDWPWParnNJVtR/3s7KgTyBQ+IITyhbsUHifFkYGAGCERxQPfQqe g+DElhM7xjMQDD3lcu88ckELUsFRMPee/o0SFUE/0X/ie4CB62mriKFk4 0qwYp/ODvvT8T/hHEDYth3Nfuf6+qSgNDj3NePfbUt1TC5RjDV2nOTIc2 w==; X-IronPort-AV: E=McAfee;i="6500,9779,10443"; a="275938514" X-IronPort-AV: E=Sophos;i="5.93,247,1654585200"; d="scan'208";a="275938514" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Aug 2022 16:42:28 -0700 X-IronPort-AV: E=Sophos;i="5.93,247,1654585200"; d="scan'208";a="783953290" Received: from invictus.jf.intel.com ([10.165.21.205]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Aug 2022 16:42:28 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Subject: [PATCH v2 07/21] drm/i915/mtl: Add gmbus and gpio support Date: Thu, 18 Aug 2022 16:41:48 -0700 Message-Id: <20220818234202.451742-8-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220818234202.451742-1-radhakrishna.sripada@intel.com> References: <20220818234202.451742-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add tables to map the GMBUS pin pairs to GPIO registers and port to DDC. From spec we have registers GPIO_CTL[1-5] mapped to native display phys and GPIO_CTL[9-14] are mapped to TC ports. BSpec: 49306 Original Author: Brian J Lovin Signed-off-by: Radhakrishna Sripada --- drivers/gpu/drm/i915/display/intel_gmbus.c | 17 +++++++++++++++++ drivers/gpu/drm/i915/display/intel_gmbus.h | 1 + 2 files changed, 18 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c index a6ba7fb72339..542b8b2654be 100644 --- a/drivers/gpu/drm/i915/display/intel_gmbus.c +++ b/drivers/gpu/drm/i915/display/intel_gmbus.c @@ -116,6 +116,20 @@ static const struct gmbus_pin gmbus_pins_dg2[] = { [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ }, }; +static const struct gmbus_pin gmbus_pins_mtp[] = { + [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, + [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, + [GMBUS_PIN_3_BXT] = { "dpc", GPIOD }, + [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, + [GMBUS_PIN_5_MTP] = { "dpe", GPIOF }, + [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ }, + [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK }, + [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL }, + [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM }, + [GMBUS_PIN_13_TC5_TGP] = { "tc5", GPION }, + [GMBUS_PIN_14_TC6_TGP] = { "tc6", GPIOO }, +}; + static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *i915, unsigned int pin) { @@ -128,6 +142,9 @@ static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *i915, } else if (INTEL_PCH_TYPE(i915) >= PCH_DG1) { pins = gmbus_pins_dg1; size = ARRAY_SIZE(gmbus_pins_dg1); + } else if (INTEL_PCH_TYPE(i915) >= PCH_MTP) { + pins = gmbus_pins_mtp; + size = ARRAY_SIZE(gmbus_pins_mtp); } else if (INTEL_PCH_TYPE(i915) >= PCH_ICP) { pins = gmbus_pins_icp; size = ARRAY_SIZE(gmbus_pins_icp); diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.h b/drivers/gpu/drm/i915/display/intel_gmbus.h index 8edc2e99cf53..20f704bd4e70 100644 --- a/drivers/gpu/drm/i915/display/intel_gmbus.h +++ b/drivers/gpu/drm/i915/display/intel_gmbus.h @@ -24,6 +24,7 @@ struct i2c_adapter; #define GMBUS_PIN_2_BXT 2 #define GMBUS_PIN_3_BXT 3 #define GMBUS_PIN_4_CNP 4 +#define GMBUS_PIN_5_MTP 5 #define GMBUS_PIN_9_TC1_ICP 9 #define GMBUS_PIN_10_TC2_ICP 10 #define GMBUS_PIN_11_TC3_ICP 11 From patchwork Thu Aug 18 23:41:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 12953919 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0BC69C00140 for ; Wed, 24 Aug 2022 19:14:42 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 802C8C358F; Wed, 24 Aug 2022 19:13:51 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id B34D710E277; Thu, 18 Aug 2022 23:42:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660866151; x=1692402151; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=xGQDS/i9Ej4d+vuzoYhYvXD0SDdxQY9cGkH9iMkRuCo=; b=Uu03HMIetkzhjzdcjMzwV2oYDKj+8DZc5JzvkbVGo7Lk++ggBR3aBUPP LCZiN4q6wNlKaz58LHSPOLYq/gvLnhUX79F4AyyauVGru8ZCTmpat12K9 BwWUm0TDjawPDM3c+Yiju5kG0HM3Cc8wzVz2BysNDZ0qdnqNdHT+IkmkF tfAPgPhA6D215uXnTIfCSagGn97lIt1ogDtHIHYR8yuzRLb4FGOcMgH6f DPu9mMJ7BnSfPTzMq+SX2bZSjDHcQXfEwrposmMMUjoWXvLDZ+3hehZsw UOm9apfwldklTgejpwNYR7lKjXtM1/cMreLOe2NmBx+FOZ0OfszBD9JnV Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10443"; a="275938519" X-IronPort-AV: E=Sophos;i="5.93,247,1654585200"; d="scan'208";a="275938519" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Aug 2022 16:42:28 -0700 X-IronPort-AV: E=Sophos;i="5.93,247,1654585200"; d="scan'208";a="783953291" Received: from invictus.jf.intel.com ([10.165.21.205]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Aug 2022 16:42:28 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Subject: [PATCH v2 08/21] drm/i915/mtl: Add VBT port and AUX_CH mapping Date: Thu, 18 Aug 2022 16:41:49 -0700 Message-Id: <20220818234202.451742-9-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220818234202.451742-1-radhakrishna.sripada@intel.com> References: <20220818234202.451742-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Imre Deak Add the proper VBT port,AUX_CH -> i915 port,AUX_CH mapping which just follows the ADL_P one. Reviewed-by: Matt Roper Signed-off-by: Imre Deak Signed-off-by: Radhakrishna Sripada --- drivers/gpu/drm/i915/display/intel_bios.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index 198a2f4920cc..81d6cfbd2615 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c @@ -2420,7 +2420,7 @@ static enum port dvo_port_to_port(struct drm_i915_private *i915, [PORT_TC4] = { DVO_PORT_HDMII, DVO_PORT_DPI, -1 }, }; - if (DISPLAY_VER(i915) == 13) + if (DISPLAY_VER(i915) >= 13) return __dvo_port_to_port(ARRAY_SIZE(xelpd_port_mapping), ARRAY_SIZE(xelpd_port_mapping[0]), xelpd_port_mapping, @@ -3578,7 +3578,7 @@ enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *i915, aux_ch = AUX_CH_C; break; case DP_AUX_D: - if (DISPLAY_VER(i915) == 13) + if (DISPLAY_VER(i915) >= 13) aux_ch = AUX_CH_D_XELPD; else if (IS_ALDERLAKE_S(i915)) aux_ch = AUX_CH_USBC3; @@ -3588,7 +3588,7 @@ enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *i915, aux_ch = AUX_CH_D; break; case DP_AUX_E: - if (DISPLAY_VER(i915) == 13) + if (DISPLAY_VER(i915) >= 13) aux_ch = AUX_CH_E_XELPD; else if (IS_ALDERLAKE_S(i915)) aux_ch = AUX_CH_USBC4; @@ -3596,25 +3596,25 @@ enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *i915, aux_ch = AUX_CH_E; break; case DP_AUX_F: - if (DISPLAY_VER(i915) == 13) + if (DISPLAY_VER(i915) >= 13) aux_ch = AUX_CH_USBC1; else aux_ch = AUX_CH_F; break; case DP_AUX_G: - if (DISPLAY_VER(i915) == 13) + if (DISPLAY_VER(i915) >= 13) aux_ch = AUX_CH_USBC2; else aux_ch = AUX_CH_G; break; case DP_AUX_H: - if (DISPLAY_VER(i915) == 13) + if (DISPLAY_VER(i915) >= 13) aux_ch = AUX_CH_USBC3; else aux_ch = AUX_CH_H; break; case DP_AUX_I: - if (DISPLAY_VER(i915) == 13) + if (DISPLAY_VER(i915) >= 13) aux_ch = AUX_CH_USBC4; else aux_ch = AUX_CH_I; From patchwork Thu Aug 18 23:41:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 12953918 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 290FEC00140 for ; Wed, 24 Aug 2022 19:14:38 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9E57CC235E; Wed, 24 Aug 2022 19:13:48 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 02A0110E2ED; Thu, 18 Aug 2022 23:42:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660866151; x=1692402151; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=w9x3LUIn4oimxR2CE7FJ8TX1PXrOjxZaZM7xDOB9638=; b=fcjcOFhz5bo4V1d6pIuiJ+a3ufir6UGGcqd+DiqaeXQyT8Am8H4Y/qok qmGJ4doT3zy821qVz7cQjuIeO6VcirMb/93MJ6waHQBuIPirAie8Ss2IL knyff3VrwCwurIYNGm8NdLzeZPy/clJ22rzeNVBgQZJj4eQq8sIc5wiaO Ws1O7JZThdRBJKz6W++EajgX9Aml+xG47tG+HdLLIhcWz2M8ei++8ZAwP EBuIy3hq5167E5SeEkXAuHjGNdvR5IGuNDU8OjoMQ6nS+GE1bHknQmbiX Bze0OiI8MSR9NHeRWAMSXWKHg84qqNfkID8tGqfJ9sWX1hRhZN35DwuNd g==; X-IronPort-AV: E=McAfee;i="6500,9779,10443"; a="275938517" X-IronPort-AV: E=Sophos;i="5.93,247,1654585200"; d="scan'208";a="275938517" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Aug 2022 16:42:28 -0700 X-IronPort-AV: E=Sophos;i="5.93,247,1654585200"; d="scan'208";a="783953293" Received: from invictus.jf.intel.com ([10.165.21.205]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Aug 2022 16:42:28 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Subject: [PATCH v2 09/21] drm/i915/mtl: Add support for MTL in Display Init sequences Date: Thu, 18 Aug 2022 16:41:50 -0700 Message-Id: <20220818234202.451742-10-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220818234202.451742-1-radhakrishna.sripada@intel.com> References: <20220818234202.451742-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The initialization sequence for Meteorlake reuses the sequence for icelake for most parts. Some changes viz. reset PICA handshake are added. Bspec: 49189 Reviewed-by: Matt Roper Signed-off-by: Radhakrishna Sripada --- drivers/gpu/drm/i915/display/intel_display_power.c | 3 +++ drivers/gpu/drm/i915/i915_reg.h | 3 ++- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index f7e8d1ff62cf..9c1fefb2da55 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -1382,6 +1382,9 @@ static void intel_pch_reset_handshake(struct drm_i915_private *dev_priv, reset_bits = RESET_PCH_HANDSHAKE_ENABLE; } + if (DISPLAY_VER(dev_priv) >= 14) + reset_bits |= MTL_RESET_PICA_HANDSHAKE_EN; + val = intel_de_read(dev_priv, reg); if (enable) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 15a53cb5e1ee..e2e9932fa484 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5821,7 +5821,8 @@ _BW_BUDDY1_PAGE_MASK)) #define HSW_NDE_RSTWRN_OPT _MMIO(0x46408) -#define RESET_PCH_HANDSHAKE_ENABLE (1 << 4) +#define MTL_RESET_PICA_HANDSHAKE_EN REG_BIT(6) +#define RESET_PCH_HANDSHAKE_ENABLE REG_BIT(4) #define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430) #define SKL_SELECT_ALTERNATE_DC_EXIT REG_BIT(30) From patchwork Thu Aug 18 23:41:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 12948188 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9C744C00140 for ; Thu, 18 Aug 2022 23:45:00 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7B46510EA7C; Thu, 18 Aug 2022 23:43:50 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id E989F10E10E; Thu, 18 Aug 2022 23:42:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660866152; x=1692402152; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1UrX/dZpc2UuOQcihhzqWV6q8zibT2osAdCA0luCYzc=; b=dtAH7c7YeiaAjuHvqIRJtrP4Yge6r7hxMy3a3HhHaoHsg1fdIkVVrpVB CtcaXy8xDMu6a/JwKsLgRw+Mxzv1argFDxl+fgFupGKpM+KOfJeHQefdy OyEFrQ4uwCwMR0inAR8OdWEJhnXAprideSnj8O8zbGeYE/SuymKoPOie2 qC0If0WtttvaIxdWcsjRk+HaEiI/Rex5Hb5Dhfu1lFOpjhklyH56baIhq Kbmz7i1M7Nj2MKBJKL1nNDT+lNDWYsIfqkA33OG6GS+7oTMijn3469RDf z9f9bCg1nlLYsmd79JmCuvt2q5x91vQms2/TngIiS2gx3Ra7oIxbu4q/I A==; X-IronPort-AV: E=McAfee;i="6500,9779,10443"; a="275938520" X-IronPort-AV: E=Sophos;i="5.93,247,1654585200"; d="scan'208";a="275938520" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Aug 2022 16:42:28 -0700 X-IronPort-AV: E=Sophos;i="5.93,247,1654585200"; d="scan'208";a="783953294" Received: from invictus.jf.intel.com ([10.165.21.205]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Aug 2022 16:42:28 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Subject: [PATCH v2 10/21] drm/i915/mtl: Add display power wells Date: Thu, 18 Aug 2022 16:41:51 -0700 Message-Id: <20220818234202.451742-11-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220818234202.451742-1-radhakrishna.sripada@intel.com> References: <20220818234202.451742-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Imre Deak Add support for display power wells on MTL. The differences from XE_LPD: - The AUX HW block is moved to the PICA block, where the registers are on an always-on power well and the functionality needs to be powered on/off via the AUX_CH_CTL register: [1], [2] - The DDI IO power on/off programming sequence is moved to the PHY PLL enable/disable sequence. [3], [4], [5] Bspec: [1] 49233, [2] 65247, [3] 64568, [4] 65451, [5] 65450 v2: - Update the comment in aux power well enable - Reuse the noop sync fn for aux sync. - Use REG_BIT for new register bit definitions Signed-off-by: Imre Deak Signed-off-by: Radhakrishna Sripada --- .../i915/display/intel_display_power_map.c | 115 +++++++++++++++++- .../i915/display/intel_display_power_well.c | 44 +++++++ .../i915/display/intel_display_power_well.h | 4 + drivers/gpu/drm/i915/display/intel_dp_aux.c | 8 ++ drivers/gpu/drm/i915/i915_reg.h | 21 ++++ 5 files changed, 191 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c index 97b367f39f35..cd28976f8076 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power_map.c +++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c @@ -1350,6 +1350,117 @@ static const struct i915_power_well_desc_list xelpd_power_wells[] = { I915_PW_DESCRIPTORS(xelpd_power_wells_main), }; +/* + * MTL is based on XELPD power domains with the exception of power gating for: + * - DDI_IO (moved to PLL logic) + * - AUX and AUX_IO functionality and register access for USBC1-4 (PICA always-on) + */ +#define XELPDP_PW_2_POWER_DOMAINS \ + XELPD_PW_B_POWER_DOMAINS, \ + XELPD_PW_C_POWER_DOMAINS, \ + XELPD_PW_D_POWER_DOMAINS, \ + POWER_DOMAIN_AUDIO_PLAYBACK, \ + POWER_DOMAIN_VGA, \ + POWER_DOMAIN_PORT_DDI_LANES_TC1, \ + POWER_DOMAIN_PORT_DDI_LANES_TC2, \ + POWER_DOMAIN_PORT_DDI_LANES_TC3, \ + POWER_DOMAIN_PORT_DDI_LANES_TC4 + +I915_DECL_PW_DOMAINS(xelpdp_pwdoms_pw_2, + XELPDP_PW_2_POWER_DOMAINS, + POWER_DOMAIN_INIT); + +I915_DECL_PW_DOMAINS(xelpdp_pwdoms_dc_off, + XELPDP_PW_2_POWER_DOMAINS, + POWER_DOMAIN_AUDIO_MMIO, + POWER_DOMAIN_MODESET, + POWER_DOMAIN_AUX_A, + POWER_DOMAIN_AUX_B, + POWER_DOMAIN_INIT); + +I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc1, + POWER_DOMAIN_AUX_USBC1, + POWER_DOMAIN_AUX_TBT1); + +I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc2, + POWER_DOMAIN_AUX_USBC2, + POWER_DOMAIN_AUX_TBT2); + +I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc3, + POWER_DOMAIN_AUX_USBC3, + POWER_DOMAIN_AUX_TBT3); + +I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc4, + POWER_DOMAIN_AUX_USBC4, + POWER_DOMAIN_AUX_TBT4); + +static const struct i915_power_well_desc xelpdp_power_wells_main[] = { + { + .instances = &I915_PW_INSTANCES( + I915_PW("DC_off", &xelpdp_pwdoms_dc_off, + .id = SKL_DISP_DC_OFF), + ), + .ops = &gen9_dc_off_power_well_ops, + }, { + .instances = &I915_PW_INSTANCES( + I915_PW("PW_2", &xelpdp_pwdoms_pw_2, + .hsw.idx = ICL_PW_CTL_IDX_PW_2, + .id = SKL_DISP_PW_2), + ), + .ops = &hsw_power_well_ops, + .has_vga = true, + .has_fuses = true, + }, { + .instances = &I915_PW_INSTANCES( + I915_PW("PW_A", &xelpd_pwdoms_pw_a, + .hsw.idx = XELPD_PW_CTL_IDX_PW_A), + ), + .ops = &hsw_power_well_ops, + .irq_pipe_mask = BIT(PIPE_A), + .has_fuses = true, + }, { + .instances = &I915_PW_INSTANCES( + I915_PW("PW_B", &xelpd_pwdoms_pw_b, + .hsw.idx = XELPD_PW_CTL_IDX_PW_B), + ), + .ops = &hsw_power_well_ops, + .irq_pipe_mask = BIT(PIPE_B), + .has_fuses = true, + }, { + .instances = &I915_PW_INSTANCES( + I915_PW("PW_C", &xelpd_pwdoms_pw_c, + .hsw.idx = XELPD_PW_CTL_IDX_PW_C), + ), + .ops = &hsw_power_well_ops, + .irq_pipe_mask = BIT(PIPE_C), + .has_fuses = true, + }, { + .instances = &I915_PW_INSTANCES( + I915_PW("PW_D", &xelpd_pwdoms_pw_d, + .hsw.idx = XELPD_PW_CTL_IDX_PW_D), + ), + .ops = &hsw_power_well_ops, + .irq_pipe_mask = BIT(PIPE_D), + .has_fuses = true, + }, { + .instances = &I915_PW_INSTANCES( + I915_PW("AUX_A", &icl_pwdoms_aux_a, .xelpdp.aux_ch = AUX_CH_A), + I915_PW("AUX_B", &icl_pwdoms_aux_b, .xelpdp.aux_ch = AUX_CH_B), + I915_PW("AUX_TC1", &xelpdp_pwdoms_aux_tc1, .xelpdp.aux_ch = AUX_CH_USBC1), + I915_PW("AUX_TC2", &xelpdp_pwdoms_aux_tc2, .xelpdp.aux_ch = AUX_CH_USBC2), + I915_PW("AUX_TC3", &xelpdp_pwdoms_aux_tc3, .xelpdp.aux_ch = AUX_CH_USBC3), + I915_PW("AUX_TC4", &xelpdp_pwdoms_aux_tc4, .xelpdp.aux_ch = AUX_CH_USBC4), + ), + .ops = &xelpdp_aux_power_well_ops, + }, +}; + +static const struct i915_power_well_desc_list xelpdp_power_wells[] = { + I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), + I915_PW_DESCRIPTORS(icl_power_wells_pw_1), + I915_PW_DESCRIPTORS(xelpdp_power_wells_main), +}; + static void init_power_well_domains(const struct i915_power_well_instance *inst, struct i915_power_well *power_well) { @@ -1457,7 +1568,9 @@ int intel_display_power_map_init(struct i915_power_domains *power_domains) return 0; } - if (DISPLAY_VER(i915) >= 13) + if (DISPLAY_VER(i915) >= 14) + return set_power_wells(power_domains, xelpdp_power_wells); + else if (DISPLAY_VER(i915) >= 13) return set_power_wells(power_domains, xelpd_power_wells); else if (IS_DG1(i915)) return set_power_wells(power_domains, dg1_power_wells); diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c index 7044016d4d98..aedaf75355f7 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c @@ -1798,6 +1798,43 @@ tgl_tc_cold_off_power_well_is_enabled(struct drm_i915_private *dev_priv, return intel_power_well_refcount(power_well); } +static void xelpdp_aux_power_well_enable(struct drm_i915_private *dev_priv, + struct i915_power_well *power_well) +{ + enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch; + + intel_de_rmw(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch), + XELPDP_DP_AUX_CH_CTL_POWER_REQUEST, + XELPDP_DP_AUX_CH_CTL_POWER_REQUEST); + + /* + * The power status flag cannot be used to determine whether aux + * power wells have finished powering up. Instead we're + * expected to just wait a fixed 600us after raising the request + * bit. + */ + usleep_range(600, 1200); +} + +static void xelpdp_aux_power_well_disable(struct drm_i915_private *dev_priv, + struct i915_power_well *power_well) +{ + enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch; + + intel_de_rmw(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch), + XELPDP_DP_AUX_CH_CTL_POWER_REQUEST, + 0); + usleep_range(10, 30); +} + +static bool xelpdp_aux_power_well_enabled(struct drm_i915_private *dev_priv, + struct i915_power_well *power_well) +{ + enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch; + + return intel_de_read(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch)) & + XELPDP_DP_AUX_CH_CTL_POWER_STATUS; +} const struct i915_power_well_ops i9xx_always_on_power_well_ops = { .sync_hw = i9xx_power_well_sync_hw_noop, @@ -1911,3 +1948,10 @@ const struct i915_power_well_ops tgl_tc_cold_off_ops = { .disable = tgl_tc_cold_off_power_well_disable, .is_enabled = tgl_tc_cold_off_power_well_is_enabled, }; + +const struct i915_power_well_ops xelpdp_aux_power_well_ops = { + .sync_hw = i9xx_power_well_sync_hw_noop, + .enable = xelpdp_aux_power_well_enable, + .disable = xelpdp_aux_power_well_disable, + .is_enabled = xelpdp_aux_power_well_enabled, +}; diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.h b/drivers/gpu/drm/i915/display/intel_display_power_well.h index d0624642dcb6..03d11576327d 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power_well.h +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.h @@ -80,6 +80,9 @@ struct i915_power_well_instance { */ u8 idx; } hsw; + struct { + u8 aux_ch; + } xelpdp; }; }; @@ -169,5 +172,6 @@ extern const struct i915_power_well_ops vlv_dpio_power_well_ops; extern const struct i915_power_well_ops icl_aux_power_well_ops; extern const struct i915_power_well_ops icl_ddi_power_well_ops; extern const struct i915_power_well_ops tgl_tc_cold_off_ops; +extern const struct i915_power_well_ops xelpdp_aux_power_well_ops; #endif diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c index 2bc119374555..40c4bdd9cb26 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c @@ -150,6 +150,7 @@ static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp, u32 unused) { struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); u32 ret; /* @@ -170,6 +171,13 @@ static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp, if (intel_tc_port_in_tbt_alt_mode(dig_port)) ret |= DP_AUX_CH_CTL_TBT_IO; + /* + * Power request bit is already set during aux power well enable. + * Preserve the bit across aux transactions. + */ + if (DISPLAY_VER(i915) >= 14) + ret |= XELPDP_DP_AUX_CH_CTL_POWER_REQUEST; + return ret; } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index e2e9932fa484..234c17596c3a 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3514,6 +3514,25 @@ #define DP_AUX_CH_CTL(aux_ch) _MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL) #define DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */ +#define _XELPDP_USBC1_AUX_CH_CTL 0x16F210 +#define _XELPDP_USBC2_AUX_CH_CTL 0x16F410 +#define _XELPDP_USBC3_AUX_CH_CTL 0x16F610 +#define _XELPDP_USBC4_AUX_CH_CTL 0x16F810 + +#define _XELPDP_USBC1_AUX_CH_DATA1 0x16F214 +#define _XELPDP_USBC2_AUX_CH_DATA1 0x16F414 +#define _XELPDP_USBC3_AUX_CH_DATA1 0x16F614 +#define _XELPDP_USBC4_AUX_CH_DATA1 0x16F814 + +#define XELPDP_DP_AUX_CH_CTL(aux_ch) _MMIO(_PICK(aux_ch, \ + _DPA_AUX_CH_CTL, \ + _DPB_AUX_CH_CTL, \ + 0, /* port/aux_ch C is non-existent */ \ + _XELPDP_USBC1_AUX_CH_CTL, \ + _XELPDP_USBC2_AUX_CH_CTL, \ + _XELPDP_USBC3_AUX_CH_CTL, \ + _XELPDP_USBC4_AUX_CH_CTL)) + #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31) #define DP_AUX_CH_CTL_DONE (1 << 30) #define DP_AUX_CH_CTL_INTERRUPT (1 << 29) @@ -3526,6 +3545,8 @@ #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25) #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20) #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20 +#define XELPDP_DP_AUX_CH_CTL_POWER_REQUEST REG_BIT(19) +#define XELPDP_DP_AUX_CH_CTL_POWER_STATUS REG_BIT(18) #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16) #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16 #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15) From patchwork Thu Aug 18 23:41:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 12948186 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 993E3C00140 for ; Thu, 18 Aug 2022 23:44:11 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0159E10E361; Thu, 18 Aug 2022 23:43:12 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3EE1710E536; Thu, 18 Aug 2022 23:42:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660866152; x=1692402152; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Eu7K5qTPnucX3SyoUhZKYrXZJKpcePF5Vk+KhXw/DGA=; b=OpWth7sDvEvocxnR81AaDVbY5VU8XPhIqu6VTviCW9c+Z3p9/+AAS7KG 1wkA0RPcCio/8Fi0DFrM/vgnuHXypQ5ziW5641dcyMvrKAmEdMJ2T/e/L srW9SMtaB5FSwCaWBf1F04R6grzP9395sponZ0hrMXlj2oB9vs1mkd120 BJ0MKrktf+ACGlzz/7YLgA3EiuyzDXc4/qUKM2vj5dpV9PWoxlmHSXcoe 46zxBWXpV8J9DPCK0ZjpX+MCI/D0waEJhnknkot/LKiE0DFewMJaL7F9T OfJYpJxhDhcsewhYSbd/3q74a3YafbrVytFYx9EgwnTu74aL/5nfWGtVY g==; X-IronPort-AV: E=McAfee;i="6500,9779,10443"; a="275938522" X-IronPort-AV: E=Sophos;i="5.93,247,1654585200"; d="scan'208";a="275938522" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Aug 2022 16:42:28 -0700 X-IronPort-AV: E=Sophos;i="5.93,247,1654585200"; d="scan'208";a="783953295" Received: from invictus.jf.intel.com ([10.165.21.205]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Aug 2022 16:42:28 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Subject: [PATCH v2 11/21] drm/i915/mtl: Add DP AUX support on TypeC ports Date: Thu, 18 Aug 2022 16:41:52 -0700 Message-Id: <20220818234202.451742-12-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220818234202.451742-1-radhakrishna.sripada@intel.com> References: <20220818234202.451742-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Imre Deak On MTL TypeC ports the AUX_CH_CTL and AUX_CH_DATA addresses have changed wrt. previous platforms, adjust the code accordingly. Signed-off-by: Imre Deak Signed-off-by: Radhakrishna Sripada --- drivers/gpu/drm/i915/display/intel_dp_aux.c | 45 ++++++++++++++++++++- drivers/gpu/drm/i915/i915_reg.h | 9 +++++ 2 files changed, 53 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c index 40c4bdd9cb26..10616e18dc18 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c @@ -637,6 +637,46 @@ static i915_reg_t tgl_aux_data_reg(struct intel_dp *intel_dp, int index) } } +static i915_reg_t xelpdp_aux_ctl_reg(struct intel_dp *intel_dp) +{ + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); + enum aux_ch aux_ch = dig_port->aux_ch; + + switch (aux_ch) { + case AUX_CH_A: + case AUX_CH_B: + case AUX_CH_USBC1: + case AUX_CH_USBC2: + case AUX_CH_USBC3: + case AUX_CH_USBC4: + return XELPDP_DP_AUX_CH_CTL(aux_ch); + default: + MISSING_CASE(aux_ch); + return XELPDP_DP_AUX_CH_CTL(AUX_CH_A); + } +} + +static i915_reg_t xelpdp_aux_data_reg(struct intel_dp *intel_dp, int index) +{ + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); + enum aux_ch aux_ch = dig_port->aux_ch; + + switch (aux_ch) { + case AUX_CH_A: + case AUX_CH_B: + case AUX_CH_USBC1: + case AUX_CH_USBC2: + case AUX_CH_USBC3: + case AUX_CH_USBC4: + return XELPDP_DP_AUX_CH_DATA(aux_ch, index); + default: + MISSING_CASE(aux_ch); + return XELPDP_DP_AUX_CH_DATA(AUX_CH_A, index); + } +} + void intel_dp_aux_fini(struct intel_dp *intel_dp) { if (cpu_latency_qos_request_active(&intel_dp->pm_qos)) @@ -652,7 +692,10 @@ void intel_dp_aux_init(struct intel_dp *intel_dp) struct intel_encoder *encoder = &dig_port->base; enum aux_ch aux_ch = dig_port->aux_ch; - if (DISPLAY_VER(dev_priv) >= 12) { + if (DISPLAY_VER(dev_priv) >= 14) { + intel_dp->aux_ch_ctl_reg = xelpdp_aux_ctl_reg; + intel_dp->aux_ch_data_reg = xelpdp_aux_data_reg; + } else if (DISPLAY_VER(dev_priv) >= 12) { intel_dp->aux_ch_ctl_reg = tgl_aux_ctl_reg; intel_dp->aux_ch_data_reg = tgl_aux_data_reg; } else if (DISPLAY_VER(dev_priv) >= 9) { diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 234c17596c3a..04a269fa8717 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3533,6 +3533,15 @@ _XELPDP_USBC3_AUX_CH_CTL, \ _XELPDP_USBC4_AUX_CH_CTL)) +#define XELPDP_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PICK(aux_ch, \ + _DPA_AUX_CH_DATA1, \ + _DPB_AUX_CH_DATA1, \ + 0, /* port/aux_ch C is non-existent */ \ + _XELPDP_USBC1_AUX_CH_DATA1, \ + _XELPDP_USBC2_AUX_CH_DATA1, \ + _XELPDP_USBC3_AUX_CH_DATA1, \ + _XELPDP_USBC4_AUX_CH_DATA1) + (i) * 4) + #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31) #define DP_AUX_CH_CTL_DONE (1 << 30) #define DP_AUX_CH_CTL_INTERRUPT (1 << 29) From patchwork Thu Aug 18 23:41:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 12948182 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 88226C25B0E for ; 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a="275938523" X-IronPort-AV: E=Sophos;i="5.93,247,1654585200"; d="scan'208";a="275938523" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Aug 2022 16:42:28 -0700 X-IronPort-AV: E=Sophos;i="5.93,247,1654585200"; d="scan'208";a="783953297" Received: from invictus.jf.intel.com ([10.165.21.205]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Aug 2022 16:42:28 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Subject: [PATCH v2 12/21] drm/i915/mtl: Fix rawclk for Meteorlake PCH Date: Thu, 18 Aug 2022 16:41:53 -0700 Message-Id: <20220818234202.451742-13-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220818234202.451742-1-radhakrishna.sripada@intel.com> References: <20220818234202.451742-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Clint Taylor MTL has a fixed rawclk of 38400Khz. Register does not need to be reprogrammed. Bspec: 49304 Reviewed-by: Matt Roper Signed-off-by: Clint Taylor Signed-off-by: Radhakrishna Sripada --- drivers/gpu/drm/i915/display/intel_cdclk.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 86a22c3766e5..1ee61abd40bc 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -3036,6 +3036,13 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv) if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) freq = dg1_rawclk(dev_priv); + else if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTP) + /* + * MTL always uses a 38.4 MHz rawclk. The bspec tells us + * "RAWCLK_FREQ defaults to the values for 38.4 and does + * not need to be programmed." + */ + freq = 38400; else if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP) freq = cnp_rawclk(dev_priv); else if (HAS_PCH_SPLIT(dev_priv)) From patchwork Thu Aug 18 23:41:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 12948181 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1AC89C00140 for ; Thu, 18 Aug 2022 23:43:43 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1EA3210E9A1; Thu, 18 Aug 2022 23:43:00 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id AFDCD10E034; Thu, 18 Aug 2022 23:42:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660866151; x=1692402151; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=MtFCra1ufjdEZ1lMUAXUIcmSQvC0TpBT4UG0KjhcJi0=; b=eN+m23ccKziclRExfUKmxwO4HJPTGpZTBnxOpPnpYewE4IsYgyg0yiUk J6jHThxpoLbLl6CGldAwWBlN2jU1eOVyqbhvZmuoeTSC9AY8SB6n3mLIM gEhzxtWzI8HGcajPEA/UU/lJyVzDzf7QwyQwMBGj+tShkfPtAV/tGPD8V zdlSxiMEqMR6agv0RPlUDOdniMifgjTWKx6kYUz0K7ut+46k8hKJsG7wy Ur+0PIQFninqsWc2r+9PZl0Hjmh48FFitbw1yfKRm+eR4cUI6aOqS5We4 wtvyZebDvymAUnnBT7Ezp57FOFBg+IHSzoEMlf0CSneMUwHUOQwRvjlKY w==; X-IronPort-AV: E=McAfee;i="6500,9779,10443"; a="275938521" X-IronPort-AV: E=Sophos;i="5.93,247,1654585200"; d="scan'208";a="275938521" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Aug 2022 16:42:28 -0700 X-IronPort-AV: E=Sophos;i="5.93,247,1654585200"; d="scan'208";a="783953298" Received: from invictus.jf.intel.com ([10.165.21.205]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Aug 2022 16:42:28 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Subject: [PATCH v2 13/21] drm/i915: Extract wm latency adjustment to its own function Date: Thu, 18 Aug 2022 16:41:54 -0700 Message-Id: <20220818234202.451742-14-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220818234202.451742-1-radhakrishna.sripada@intel.com> References: <20220818234202.451742-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Watermark latency is adjusted in cases when latency is 0us for level greater than 1, the subsequent levels are disabled. Extract this logic into its own function. Suggested-by: Matt Roper Signed-off-by: Radhakrishna Sripada Reviewed-by: Matt Roper --- drivers/gpu/drm/i915/intel_pm.c | 88 ++++++++++++++++++--------------- 1 file changed, 48 insertions(+), 40 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index ef7553b494ea..898e56d2eaf7 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -2861,15 +2861,59 @@ static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv, result->enable = true; } +static void +adjust_wm_latency(u16 wm[], int max_level, int read_latency, + bool wm_lv_0_adjust_needed) +{ + int i, level; + + /* + * If a level n (n > 1) has a 0us latency, all levels m (m >= n) + * need to be disabled. We make sure to sanitize the values out + * of the punit to satisfy this requirement. + */ + for (level = 1; level <= max_level; level++) { + if (wm[level] == 0) { + for (i = level + 1; i <= max_level; i++) + wm[i] = 0; + + max_level = level - 1; + break; + } + } + + /* + * WaWmMemoryReadLatency + * + * punit doesn't take into account the read latency so we need + * to add proper adjustement to each valid level we retrieve + * from the punit when level 0 response data is 0us. + */ + if (wm[0] == 0) { + for (level = 0; level <= max_level; level++) + wm[level] += read_latency; + } + + /* + * WA Level-0 adjustment for 16GB DIMMs: SKL+ + * If we could not get dimm info enable this WA to prevent from + * any underrun. If not able to get Dimm info assume 16GB dimm + * to avoid any underrun. + */ + if (wm_lv_0_adjust_needed) + wm[0] += 1; +} + static void intel_read_wm_latency(struct drm_i915_private *dev_priv, u16 wm[]) { struct intel_uncore *uncore = &dev_priv->uncore; if (DISPLAY_VER(dev_priv) >= 9) { + int read_latency = DISPLAY_VER(dev_priv) >= 12 ? 3 : 2; u32 val; - int ret, i; - int level, max_level = ilk_wm_max_level(dev_priv); + int ret; + int max_level = ilk_wm_max_level(dev_priv); int mult = IS_DG2(dev_priv) ? 2 : 1; /* read the first set of memory latencies[0:3] */ @@ -2909,44 +2953,8 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv, wm[7] = ((val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) & GEN9_MEM_LATENCY_LEVEL_MASK) * mult; - /* - * If a level n (n > 1) has a 0us latency, all levels m (m >= n) - * need to be disabled. We make sure to sanitize the values out - * of the punit to satisfy this requirement. - */ - for (level = 1; level <= max_level; level++) { - if (wm[level] == 0) { - for (i = level + 1; i <= max_level; i++) - wm[i] = 0; - - max_level = level - 1; - - break; - } - } - - /* - * WaWmMemoryReadLatency - * - * punit doesn't take into account the read latency so we need - * to add proper adjustement to each valid level we retrieve - * from the punit when level 0 response data is 0us. - */ - if (wm[0] == 0) { - u8 adjust = DISPLAY_VER(dev_priv) >= 12 ? 3 : 2; - - for (level = 0; level <= max_level; level++) - wm[level] += adjust; - } - - /* - * WA Level-0 adjustment for 16GB DIMMs: SKL+ - * If we could not get dimm info enable this WA to prevent from - * any underrun. If not able to get Dimm info assume 16GB dimm - * to avoid any underrun. - */ - if (dev_priv->dram_info.wm_lv_0_adjust_needed) - wm[0] += 1; + adjust_wm_latency(wm, max_level, read_latency, + dev_priv->dram_info.wm_lv_0_adjust_needed); } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { u64 sskpd = intel_uncore_read64(uncore, MCH_SSKPD); From patchwork Thu Aug 18 23:41:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 12948185 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8F72AC00140 for ; Thu, 18 Aug 2022 23:44:04 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B8E8A10E536; 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18 Aug 2022 16:42:28 -0700 X-IronPort-AV: E=Sophos;i="5.93,247,1654585200"; d="scan'208";a="783953299" Received: from invictus.jf.intel.com ([10.165.21.205]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Aug 2022 16:42:28 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Subject: [PATCH v2 14/21] drm/i915/mtl: memory latency data from LATENCY_LPX_LPY for WM Date: Thu, 18 Aug 2022 16:41:55 -0700 Message-Id: <20220818234202.451742-15-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220818234202.451742-1-radhakrishna.sripada@intel.com> References: <20220818234202.451742-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Since Xe LPD+, Memory latency data are in LATENCY_LPX_LPY registers instead of GT driver mailbox. v2: Use the extracted wm latency adjustment function(Matt) Bspec: 64608 Cc: Matt Roper Original Author: Caz Yokoyama Signed-off-by: Radhakrishna Sripada Reviewed-by: Matt Roper --- drivers/gpu/drm/i915/i915_reg.h | 7 +++++++ drivers/gpu/drm/i915/intel_pm.c | 21 ++++++++++++++++++--- 2 files changed, 25 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 04a269fa8717..b2d5e1230c25 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8390,4 +8390,11 @@ enum skl_power_gate { #define GEN12_STATE_ACK_DEBUG _MMIO(0x20BC) #define MTL_MEDIA_GSI_BASE 0x380000 + +#define MTL_LATENCY_LP0_LP1 _MMIO(0x45780) +#define MTL_LATENCY_LP2_LP3 _MMIO(0x45784) +#define MTL_LATENCY_LP4_LP5 _MMIO(0x45788) +#define MTL_LATENCY_LEVEL0_2_4_MASK REG_GENMASK(12, 0) +#define MTL_LATENCY_LEVEL1_3_5_MASK REG_GENMASK(28, 16) + #endif /* _I915_REG_H_ */ diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 898e56d2eaf7..fac565d23d57 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -2908,13 +2908,28 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv, u16 wm[]) { struct intel_uncore *uncore = &dev_priv->uncore; + int max_level = ilk_wm_max_level(dev_priv); - if (DISPLAY_VER(dev_priv) >= 9) { + if (DISPLAY_VER(dev_priv) >= 14) { + u32 val; + + val = intel_uncore_read(uncore, MTL_LATENCY_LP0_LP1); + wm[0] = REG_FIELD_GET(MTL_LATENCY_LEVEL0_2_4_MASK, val); + wm[1] = REG_FIELD_GET(MTL_LATENCY_LEVEL1_3_5_MASK, val); + val = intel_uncore_read(uncore, MTL_LATENCY_LP2_LP3); + wm[2] = REG_FIELD_GET(MTL_LATENCY_LEVEL0_2_4_MASK, val); + wm[3] = REG_FIELD_GET(MTL_LATENCY_LEVEL1_3_5_MASK, val); + val = intel_uncore_read(uncore, MTL_LATENCY_LP4_LP5); + wm[4] = REG_FIELD_GET(MTL_LATENCY_LEVEL0_2_4_MASK, val); + wm[5] = REG_FIELD_GET(MTL_LATENCY_LEVEL1_3_5_MASK, val); + + adjust_wm_latency(wm, max_level, 6, + dev_priv->dram_info.wm_lv_0_adjust_needed); + } else if (DISPLAY_VER(dev_priv) >= 9) { int read_latency = DISPLAY_VER(dev_priv) >= 12 ? 3 : 2; + int mult = IS_DG2(dev_priv) ? 2 : 1; u32 val; int ret; - int max_level = ilk_wm_max_level(dev_priv); - int mult = IS_DG2(dev_priv) ? 2 : 1; /* read the first set of memory latencies[0:3] */ val = 0; /* data0 to be programmed to 0 for first set */ From patchwork Thu Aug 18 23:41:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 12953920 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 823A1C00140 for ; Wed, 24 Aug 2022 19:14:48 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 64DFAC13E0; Wed, 24 Aug 2022 19:13:56 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5F7F610E5A5; Thu, 18 Aug 2022 23:42:32 +0000 (UTC) DKIM-Signature: v=1; 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18 Aug 2022 16:42:28 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Subject: [PATCH v2 15/21] drm/i915/mtl: Obtain SAGV values from MMIO instead of GT pcode mailbox Date: Thu, 18 Aug 2022 16:41:56 -0700 Message-Id: <20220818234202.451742-16-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220818234202.451742-1-radhakrishna.sripada@intel.com> References: <20220818234202.451742-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From Meteorlake, Latency Level, SAGV bloack time are read from LATENCY_SAGV register instead of the GT driver pcode mailbox. DDR type and QGV information are also to be read from Mem SS registers. v2: - Simplify MTL_MEM_SS_INFO_QGV_POINT macro(MattR) - Nit: Rearrange the bit def's from higher to lower(MattR) - Restore platform definition for ADL-P(MattR) - Move back intel_qgv_point def to intel_bw.c(Jani) Bspec: 64636, 64608 Cc: Matt Roper Cc: Jani Nikula Original Author: Caz Yokoyama Signed-off-by: José Roberto de Souza Signed-off-by: Radhakrishna Sripada Reviewed-by: Matt Roper --- drivers/gpu/drm/i915/display/intel_bw.c | 42 ++++++++++++++++++++++--- drivers/gpu/drm/i915/i915_reg.h | 16 ++++++++++ drivers/gpu/drm/i915/intel_dram.c | 41 +++++++++++++++++++++++- drivers/gpu/drm/i915/intel_pm.c | 8 ++++- 4 files changed, 100 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c index 79269d2c476b..46b63afd536a 100644 --- a/drivers/gpu/drm/i915/display/intel_bw.c +++ b/drivers/gpu/drm/i915/display/intel_bw.c @@ -137,6 +137,42 @@ int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv, return 0; } +static int mtl_read_qgv_point_info(struct drm_i915_private *dev_priv, + struct intel_qgv_point *sp, int point) +{ + u32 val, val2; + u16 dclk; + + val = intel_uncore_read(&dev_priv->uncore, + MTL_MEM_SS_INFO_QGV_POINT_LOW(point)); + val2 = intel_uncore_read(&dev_priv->uncore, + MTL_MEM_SS_INFO_QGV_POINT_HIGH(point)); + dclk = REG_FIELD_GET(MTL_DCLK_MASK, val); + sp->dclk = DIV_ROUND_UP((16667 * dclk), 1000); + sp->t_rp = REG_FIELD_GET(MTL_TRP_MASK, val); + sp->t_rcd = REG_FIELD_GET(MTL_TRCD_MASK, val); + + sp->t_rdpre = REG_FIELD_GET(MTL_TRDPRE_MASK, val2); + sp->t_ras = REG_FIELD_GET(MTL_TRAS_MASK, val2); + + sp->t_rc = sp->t_rp + sp->t_ras; + + return 0; +} + +static int +intel_read_qgv_point_info(struct drm_i915_private *dev_priv, + struct intel_qgv_point *sp, + int point) +{ + if (DISPLAY_VER(dev_priv) >= 14) + return mtl_read_qgv_point_info(dev_priv, sp, point); + else if (IS_DG1(dev_priv)) + return dg1_mchbar_read_qgv_point_info(dev_priv, sp, point); + else + return icl_pcode_read_qgv_point_info(dev_priv, sp, point); +} + static int icl_get_qgv_points(struct drm_i915_private *dev_priv, struct intel_qgv_info *qi, bool is_y_tile) @@ -193,11 +229,7 @@ static int icl_get_qgv_points(struct drm_i915_private *dev_priv, for (i = 0; i < qi->num_points; i++) { struct intel_qgv_point *sp = &qi->points[i]; - if (IS_DG1(dev_priv)) - ret = dg1_mchbar_read_qgv_point_info(dev_priv, sp, i); - else - ret = icl_pcode_read_qgv_point_info(dev_priv, sp, i); - + ret = intel_read_qgv_point_info(dev_priv, sp, i); if (ret) return ret; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index b2d5e1230c25..5245af8d0ea8 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8397,4 +8397,20 @@ enum skl_power_gate { #define MTL_LATENCY_LEVEL0_2_4_MASK REG_GENMASK(12, 0) #define MTL_LATENCY_LEVEL1_3_5_MASK REG_GENMASK(28, 16) +#define MTL_LATENCY_SAGV _MMIO(0x4578c) +#define MTL_LATENCY_QCLK_SAGV REG_GENMASK(12, 0) + +#define MTL_MEM_SS_INFO_GLOBAL _MMIO(0x45700) +#define MTL_DDR_TYPE_MASK REG_GENMASK(3, 0) +#define MTL_N_OF_POPULATED_CH_MASK REG_GENMASK(7, 4) +#define MTL_N_OF_ENABLED_QGV_POINTS_MASK REG_GENMASK(11, 8) + +#define MTL_MEM_SS_INFO_QGV_POINT_LOW(point) _MMIO(0x45710 + (point) * 2) +#define MTL_MEM_SS_INFO_QGV_POINT_HIGH(point) _MMIO(0x45714 + (point) * 2) +#define MTL_TRCD_MASK REG_GENMASK(31, 24) +#define MTL_TRP_MASK REG_GENMASK(23, 16) +#define MTL_TRAS_MASK REG_GENMASK(16, 8) +#define MTL_DCLK_MASK REG_GENMASK(15, 0) +#define MTL_TRDPRE_MASK REG_GENMASK(7, 0) + #endif /* _I915_REG_H_ */ diff --git a/drivers/gpu/drm/i915/intel_dram.c b/drivers/gpu/drm/i915/intel_dram.c index 437447119770..2403ccd52c74 100644 --- a/drivers/gpu/drm/i915/intel_dram.c +++ b/drivers/gpu/drm/i915/intel_dram.c @@ -466,6 +466,43 @@ static int gen12_get_dram_info(struct drm_i915_private *i915) return icl_pcode_read_mem_global_info(i915); } +static int xelpdp_get_dram_info(struct drm_i915_private *i915) +{ + u32 val = intel_uncore_read(&i915->uncore, MTL_MEM_SS_INFO_GLOBAL); + struct dram_info *dram_info = &i915->dram_info; + + val = REG_FIELD_GET(MTL_DDR_TYPE_MASK, val); + switch (val) { + case 0: + dram_info->type = INTEL_DRAM_DDR4; + break; + case 1: + dram_info->type = INTEL_DRAM_DDR5; + break; + case 2: + dram_info->type = INTEL_DRAM_LPDDR5; + break; + case 3: + dram_info->type = INTEL_DRAM_LPDDR4; + break; + case 4: + dram_info->type = INTEL_DRAM_DDR3; + break; + case 5: + dram_info->type = INTEL_DRAM_LPDDR3; + break; + default: + MISSING_CASE(val); + return -EINVAL; + } + + dram_info->num_channels = REG_FIELD_GET(MTL_N_OF_POPULATED_CH_MASK, val); + dram_info->num_qgv_points = REG_FIELD_GET(MTL_N_OF_ENABLED_QGV_POINTS_MASK, val); + /* PSF GV points not supported in D14+ */ + + return 0; +} + void intel_dram_detect(struct drm_i915_private *i915) { struct dram_info *dram_info = &i915->dram_info; @@ -480,7 +517,9 @@ void intel_dram_detect(struct drm_i915_private *i915) */ dram_info->wm_lv_0_adjust_needed = !IS_GEN9_LP(i915); - if (GRAPHICS_VER(i915) >= 12) + if (DISPLAY_VER(i915) >= 14) + ret = xelpdp_get_dram_info(i915); + else if (GRAPHICS_VER(i915) >= 12) ret = gen12_get_dram_info(i915); else if (GRAPHICS_VER(i915) >= 11) ret = gen11_get_dram_info(i915); diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index fac565d23d57..f71b3b8b590c 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3698,7 +3698,13 @@ intel_has_sagv(struct drm_i915_private *dev_priv) static u32 intel_sagv_block_time(struct drm_i915_private *dev_priv) { - if (DISPLAY_VER(dev_priv) >= 12) { + if (DISPLAY_VER(dev_priv) >= 14) { + u32 val; + + val = intel_uncore_read(&dev_priv->uncore, MTL_LATENCY_SAGV); + + return REG_FIELD_GET(MTL_LATENCY_QCLK_SAGV, val); + } else if (DISPLAY_VER(dev_priv) >= 12) { u32 val = 0; int ret; From patchwork Thu Aug 18 23:41:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 12948184 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7E3DEC00140 for ; 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a="275938526" X-IronPort-AV: E=Sophos;i="5.93,247,1654585200"; d="scan'208";a="275938526" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Aug 2022 16:42:29 -0700 X-IronPort-AV: E=Sophos;i="5.93,247,1654585200"; d="scan'208";a="783953301" Received: from invictus.jf.intel.com ([10.165.21.205]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Aug 2022 16:42:28 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Subject: [PATCH v2 16/21] drm/i915/mtl: Update memory bandwidth parameters Date: Thu, 18 Aug 2022 16:41:57 -0700 Message-Id: <20220818234202.451742-17-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220818234202.451742-1-radhakrishna.sripada@intel.com> References: <20220818234202.451742-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Like ADL_P, Meteorlake has different memory characteristics from past platforms. Update the values used by our memory bandwidth calculations accordingly. Bspec: 64631 Reviewed-by: Matt Roper Signed-off-by: Radhakrishna Sripada Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_bw.c | 40 +++++++++++++++++++++++-- 1 file changed, 37 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c index 46b63afd536a..0182f0948fb9 100644 --- a/drivers/gpu/drm/i915/display/intel_bw.c +++ b/drivers/gpu/drm/i915/display/intel_bw.c @@ -183,7 +183,32 @@ static int icl_get_qgv_points(struct drm_i915_private *dev_priv, qi->num_points = dram_info->num_qgv_points; qi->num_psf_points = dram_info->num_psf_gv_points; - if (DISPLAY_VER(dev_priv) >= 12) + if (DISPLAY_VER(dev_priv) >= 14) { + switch (dram_info->type) { + case INTEL_DRAM_DDR4: + qi->t_bl = 4; + qi->max_numchannels = 2; + qi->channel_width = 64; + qi->deinterleave = 2; + break; + case INTEL_DRAM_DDR5: + qi->t_bl = 8; + qi->max_numchannels = 4; + qi->channel_width = 32; + qi->deinterleave = 2; + break; + case INTEL_DRAM_LPDDR4: + case INTEL_DRAM_LPDDR5: + qi->t_bl = 16; + qi->max_numchannels = 8; + qi->channel_width = 16; + qi->deinterleave = 4; + break; + default: + MISSING_CASE(dram_info->type); + return -EINVAL; + } + } else if (DISPLAY_VER(dev_priv) >= 12) { switch (dram_info->type) { case INTEL_DRAM_DDR4: qi->t_bl = is_y_tile ? 8 : 4; @@ -217,7 +242,7 @@ static int icl_get_qgv_points(struct drm_i915_private *dev_priv, qi->max_numchannels = 1; break; } - else if (DISPLAY_VER(dev_priv) == 11) { + } else if (DISPLAY_VER(dev_priv) == 11) { qi->t_bl = dev_priv->dram_info.type == INTEL_DRAM_DDR4 ? 4 : 8; qi->max_numchannels = 1; } @@ -316,6 +341,13 @@ static const struct intel_sa_info adlp_sa_info = { .derating = 20, }; +static const struct intel_sa_info mtl_sa_info = { + .deburst = 32, + .deprogbwlimit = 38, /* GB/s */ + .displayrtids = 256, + .derating = 20, +}; + static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel_sa_info *sa) { struct intel_qgv_info qi = {}; @@ -590,7 +622,9 @@ void intel_bw_init_hw(struct drm_i915_private *dev_priv) if (!HAS_DISPLAY(dev_priv)) return; - if (IS_DG2(dev_priv)) + if (DISPLAY_VER(dev_priv) >= 14) + tgl_get_bw_info(dev_priv, &mtl_sa_info); + else if (IS_DG2(dev_priv)) dg2_get_bw_info(dev_priv); else if (IS_ALDERLAKE_P(dev_priv)) tgl_get_bw_info(dev_priv, &adlp_sa_info); From patchwork Thu Aug 18 23:41:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 12948189 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A8BD0C00140 for ; Thu, 18 Aug 2022 23:45:07 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E424510EA96; Thu, 18 Aug 2022 23:43:51 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 80BFE10E5C0; Thu, 18 Aug 2022 23:42:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660866152; x=1692402152; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=/7WvPMC9huOIXcbhdlOo/PfYIak7wQ5anMupKq3mPDU=; b=WbFGLGusugiKRW+MNBJMNOaVWnATxWhGIXzvVvotZUJBhlMwF03ww5b+ 1P+FaX0AcTkCbfxrAbYeq0s1PBor7KP8/HLf/9qrn+ws1u4Ek8VNBCuOd h1a2XyoAvovQCxomvV0ZOvvFHt0Dt4Lq0I5gfHUxkxmT4btKV6ncUHVjV COFQCVOPcsYqyBHQxCOfQp5P4f/gshqZQz3vOHE8dFtPdIf6T1smKSU6k g4WtsNaoeKEaYBxV0DMi0NzyPLjc4MxaXCk7UPGNPwUM52BSXVmlesP9T 4DPcIcHdrbpZ4V2QB9TnouvJor4LmVJLSrxmlW8WB4eA2DLNDiGJL6s7d A==; X-IronPort-AV: E=McAfee;i="6500,9779,10443"; a="275938527" X-IronPort-AV: E=Sophos;i="5.93,247,1654585200"; d="scan'208";a="275938527" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Aug 2022 16:42:29 -0700 X-IronPort-AV: E=Sophos;i="5.93,247,1654585200"; d="scan'208";a="783953302" Received: from invictus.jf.intel.com ([10.165.21.205]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Aug 2022 16:42:28 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Subject: [PATCH v2 17/21] drm/i915/mtl: Update MBUS_DBOX credits Date: Thu, 18 Aug 2022 16:41:58 -0700 Message-Id: <20220818234202.451742-18-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220818234202.451742-1-radhakrishna.sripada@intel.com> References: <20220818234202.451742-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Display version 14 platforms have different credits values compared to ADL-P. Update the credits based on pipe usage. v2: Simplify DBOX BW Credit definition(MattR) Bspec: 49213 Cc: Jose Roberto de Souza Cc: Matt Roper Original Author: Caz Yokoyama Signed-off-by: José Roberto de Souza Signed-off-by: Radhakrishna Sripada --- drivers/gpu/drm/i915/i915_reg.h | 4 +++ drivers/gpu/drm/i915/intel_pm.c | 47 ++++++++++++++++++++++++++++++--- 2 files changed, 47 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 5245af8d0ea8..b2b06c080d09 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1125,8 +1125,12 @@ #define MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN REG_BIT(16) /* tgl+ */ #define MBUS_DBOX_BW_CREDIT_MASK REG_GENMASK(15, 14) #define MBUS_DBOX_BW_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_BW_CREDIT_MASK, x) +#define MBUS_DBOX_BW_4CREDITS_MTL REG_FIELD_PREP(MBUS_DBOX_BW_CREDIT_MASK, 0x2) +#define MBUS_DBOX_BW_8CREDITS_MTL REG_FIELD_PREP(MBUS_DBOX_BW_CREDIT_MASK, 0x3) #define MBUS_DBOX_B_CREDIT_MASK REG_GENMASK(12, 8) #define MBUS_DBOX_B_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_B_CREDIT_MASK, x) +#define MBUS_DBOX_I_CREDIT_MASK REG_GENMASK(7, 5) +#define MBUS_DBOX_I_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_I_CREDIT_MASK, x) #define MBUS_DBOX_A_CREDIT_MASK REG_GENMASK(3, 0) #define MBUS_DBOX_A_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_A_CREDIT_MASK, x) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index f71b3b8b590c..5cdc2ce4f42b 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -8443,6 +8443,27 @@ void intel_dbuf_post_plane_update(struct intel_atomic_state *state) new_dbuf_state->enabled_slices); } +static bool xelpdp_is_one_pipe_per_dbuf_bank(enum pipe pipe, u8 active_pipes) +{ + switch (pipe) { + case PIPE_A: + case PIPE_D: + if (is_power_of_2(active_pipes & (BIT(PIPE_A) | BIT(PIPE_D)))) + return true; + break; + case PIPE_B: + case PIPE_C: + if (is_power_of_2(active_pipes & (BIT(PIPE_B) | BIT(PIPE_C)))) + return true; + break; + default: /* to suppress compiler warning */ + MISSING_CASE(pipe); + break; + } + + return false; +} + void intel_mbus_dbox_update(struct intel_atomic_state *state) { struct drm_i915_private *i915 = to_i915(state->base.dev); @@ -8462,20 +8483,28 @@ void intel_mbus_dbox_update(struct intel_atomic_state *state) new_dbuf_state->active_pipes == old_dbuf_state->active_pipes)) return; + if (DISPLAY_VER(i915) >= 14) + val |= MBUS_DBOX_I_CREDIT(2); + if (DISPLAY_VER(i915) >= 12) { val |= MBUS_DBOX_B2B_TRANSACTIONS_MAX(16); val |= MBUS_DBOX_B2B_TRANSACTIONS_DELAY(1); val |= MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN; } - /* Wa_22010947358:adl-p */ - if (IS_ALDERLAKE_P(i915)) + if (DISPLAY_VER(i915) >= 14) + val |= new_dbuf_state->joined_mbus ? MBUS_DBOX_A_CREDIT(12) : + MBUS_DBOX_A_CREDIT(8); + else if (IS_ALDERLAKE_P(i915)) + /* Wa_22010947358:adl-p */ val |= new_dbuf_state->joined_mbus ? MBUS_DBOX_A_CREDIT(6) : MBUS_DBOX_A_CREDIT(4); else val |= MBUS_DBOX_A_CREDIT(2); - if (IS_ALDERLAKE_P(i915)) { + if (DISPLAY_VER(i915) >= 14) { + val |= MBUS_DBOX_B_CREDIT(0xA); + } else if (IS_ALDERLAKE_P(i915)) { val |= MBUS_DBOX_BW_CREDIT(2); val |= MBUS_DBOX_B_CREDIT(8); } else if (DISPLAY_VER(i915) >= 12) { @@ -8487,10 +8516,20 @@ void intel_mbus_dbox_update(struct intel_atomic_state *state) } for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { + u32 pipe_val = val; + if (!new_crtc_state->hw.active || !intel_crtc_needs_modeset(new_crtc_state)) continue; - intel_de_write(i915, PIPE_MBUS_DBOX_CTL(crtc->pipe), val); + if (DISPLAY_VER(i915) >= 14) { + if (xelpdp_is_one_pipe_per_dbuf_bank(crtc->pipe, + new_dbuf_state->active_pipes)) + pipe_val |= MBUS_DBOX_BW_8CREDITS_MTL; + else + pipe_val |= MBUS_DBOX_BW_4CREDITS_MTL; + } + + intel_de_write(i915, PIPE_MBUS_DBOX_CTL(crtc->pipe), pipe_val); } } From patchwork Thu Aug 18 23:41:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 12948187 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 92EA7C00140 for ; Thu, 18 Aug 2022 23:44:25 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0160610E43C; Thu, 18 Aug 2022 23:43:13 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id AD93310E665; Thu, 18 Aug 2022 23:42:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660866153; x=1692402153; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=B/jdwWrSBKrdnDrbs8PCH+tbMmvku9GrwhVCFQE8gmQ=; b=I2cEqkpodOsWm4qcei+YoLZ5VrfmzcDoFq00Ebq+MqWR6xlIIS47fVk4 UgEWTsZoKIbFoBtzM+apCoF1+Fb9RujGJ7yeQMtxYJKPpAcPCyd4Ii4Ex GtkWpPaFvDu1OPKuY3m3XqqsoxcLNJQIpgViWkei2AodBdgxyte96Ciug lA4lkFGvK6jwmivWZfcT2Rrg33GdcUe7S/ODROlxcLBGq6E6B/e1hJN3V dBwsrZ9F6VPZk3m+f04pylqsju6Hoaod5vcQUJElMFd4652Pe74AUU1ea KroBaIJTvnHj5pan/hwSzE+/VLezXb+MxJ7CbNsP4ZN0vuoKZZvhKfjxp w==; X-IronPort-AV: E=McAfee;i="6500,9779,10443"; a="275938528" X-IronPort-AV: E=Sophos;i="5.93,247,1654585200"; d="scan'208";a="275938528" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Aug 2022 16:42:29 -0700 X-IronPort-AV: E=Sophos;i="5.93,247,1654585200"; d="scan'208";a="783953303" Received: from invictus.jf.intel.com ([10.165.21.205]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Aug 2022 16:42:28 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Subject: [PATCH v2 18/21] drm/i915/mtl: Reuse adl-p DBUF calculations Date: Thu, 18 Aug 2022 16:41:59 -0700 Message-Id: <20220818234202.451742-19-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220818234202.451742-1-radhakrishna.sripada@intel.com> References: <20220818234202.451742-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Meteorlake uses a similar DBUF calculations as ADL-P. Reuse the call flow for meteorlake. Bspec: 49255 Original Author: Caz Yokoyama Reviewed-by: Matt Roper Signed-off-by: Radhakrishna Sripada --- drivers/gpu/drm/i915/intel_pm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 5cdc2ce4f42b..d09e9e5f4481 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4934,7 +4934,7 @@ static u8 skl_compute_dbuf_slices(struct intel_crtc *crtc, u8 active_pipes, bool if (IS_DG2(dev_priv)) return dg2_compute_dbuf_slices(pipe, active_pipes, join_mbus); - else if (IS_ALDERLAKE_P(dev_priv)) + else if (DISPLAY_VER(dev_priv) >= 13) return adlp_compute_dbuf_slices(pipe, active_pipes, join_mbus); else if (DISPLAY_VER(dev_priv) == 12) return tgl_compute_dbuf_slices(pipe, active_pipes, join_mbus); From patchwork Thu Aug 18 23:42:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 12948190 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 870EDC00140 for ; Thu, 18 Aug 2022 23:45:14 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6985410EAFA; Thu, 18 Aug 2022 23:44:01 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 126E010E22D; Thu, 18 Aug 2022 23:42:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660866153; x=1692402153; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=5YGbXa5N/pi+vOMd2xkvNWpva0Zk+ETnf2BxwdGx0Q4=; b=ZShWavzMe1Pa6WAn78xHbYKh+chEozBHXc46uYfylhUJWVS+0MBMmbO0 0/nwyzU/0tLfLZ8cPmhuKxF7D8jcwRDaIEwelpGGN9QvbObsZhI5woBvu zXVEbvWBC+01N+nb/gguBp2PHYn1QJJh+jTqRyHxWBl8OQd69/dEDpPMc CJOouuQn9qB/jxXU8eKicBH7atXJtIapE71HYNeMaSAA105odb79qDPUq Jh082OrOiTayECxfskBxBILSeV9aM58kM1u8l+lPZ55onolHiTo3odE5a YoSqj+WZ61ujgaSFhYJ3a+8juJzmfymIEEhmaf/gWf0dehA6P8qvv66/S A==; X-IronPort-AV: E=McAfee;i="6500,9779,10443"; a="275938530" X-IronPort-AV: E=Sophos;i="5.93,247,1654585200"; d="scan'208";a="275938530" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Aug 2022 16:42:29 -0700 X-IronPort-AV: E=Sophos;i="5.93,247,1654585200"; d="scan'208";a="783953304" Received: from invictus.jf.intel.com ([10.165.21.205]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Aug 2022 16:42:28 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Subject: [PATCH v2 19/21] drm/i915/display/mtl: Extend MBUS programming Date: Thu, 18 Aug 2022 16:42:00 -0700 Message-Id: <20220818234202.451742-20-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220818234202.451742-1-radhakrishna.sripada@intel.com> References: <20220818234202.451742-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: José Roberto de Souza Display version 14 also supports MBUS joining just like ADL-P and also it does not need MBUS initialization, so extending ADL-P code paths to display version 14 and higher. Bspec: 49213 Reviewed-by: Matt Roper Signed-off-by: José Roberto de Souza Signed-off-by: Radhakrishna Sripada --- drivers/gpu/drm/i915/display/intel_display_power.c | 2 +- drivers/gpu/drm/i915/i915_drv.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 9c1fefb2da55..439d56c3814f 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -1102,7 +1102,7 @@ static void icl_mbus_init(struct drm_i915_private *dev_priv) unsigned long abox_regs = INTEL_INFO(dev_priv)->display.abox_mask; u32 mask, val, i; - if (IS_ALDERLAKE_P(dev_priv)) + if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14) return; mask = MBUS_ABOX_BT_CREDIT_POOL1_MASK | diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 7ebddde200bc..2d658ddcf3c7 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1360,7 +1360,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define HAS_D12_PLANE_MINIMIZATION(dev_priv) (IS_ROCKETLAKE(dev_priv) || \ IS_ALDERLAKE_S(dev_priv)) -#define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915)) +#define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14) #define HAS_3D_PIPELINE(i915) (INTEL_INFO(i915)->has_3d_pipeline) From patchwork Thu Aug 18 23:42:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 12948191 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0AA10C00140 for ; Thu, 18 Aug 2022 23:45:19 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D26C610F2FF; Thu, 18 Aug 2022 23:44:12 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3B0C910E1BA; Thu, 18 Aug 2022 23:42:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660866153; x=1692402153; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=FEu/aSMwHZGS6MsYOeZ798Oc85gNIiTSx509KCO76tw=; b=adtOImjcThc24tCGLhPNvXW1V5StsiMVmAqtFNJm0y+dprE/B2YXsRIe 3fwlp60oB0XaTbUazXcFru3uqbOam8TkZZLaUHm5+kCZiEw42SDCzUFPo /JcqT6kbeFZ7I+zZLMqNP3/EW+CUbnTo3+XYS0j1RNx+Wt3wmq71wlOOw WR3iEO/7nXJdb/R+rNdTEDrjgHm+SRgaKIWJhZlebvWSC1k6wN7fIb0I+ rL1kJDm4r3c8hRpgAQwGB30OHgquJ1mC1VS+k7t42ag3uvD+s3KK4PGQ5 QEbhmgyybO+6KmrktyfATrfBWCFnCphbZATfwdE5rtwy9zGr1eF9/aH6a A==; X-IronPort-AV: E=McAfee;i="6500,9779,10443"; a="275938531" X-IronPort-AV: E=Sophos;i="5.93,247,1654585200"; d="scan'208";a="275938531" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Aug 2022 16:42:29 -0700 X-IronPort-AV: E=Sophos;i="5.93,247,1654585200"; d="scan'208";a="783953305" Received: from invictus.jf.intel.com ([10.165.21.205]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Aug 2022 16:42:28 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Subject: [PATCH v2 20/21] drm/i915/mtl: Update CHICKEN_TRANS* register addresses Date: Thu, 18 Aug 2022 16:42:01 -0700 Message-Id: <20220818234202.451742-21-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220818234202.451742-1-radhakrishna.sripada@intel.com> References: <20220818234202.451742-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Madhumitha Tolakanahalli Pradeep In Display version 14, Transcoder Chicken Registers are moved from DPRZ to DRPOS to reduce register signal crossings for Unit Interface Optimization. This patch modifies the CHICKEN_TRANS macro to add a DISPLAY_VER check for calculating the correct platform offsets. (And also updates existing CHICKEN_TRANS occurrences to the new definition) v2: Omit display version check in i915_reg.h(Jani) Bspec: 34387, 50054 Cc: Jani Nikula Signed-off-by: Madhumitha Tolakanahalli Pradeep Signed-off-by: Radhakrishna Sripada --- drivers/gpu/drm/i915/display/intel_display.c | 14 ++++++++--- drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 +++- drivers/gpu/drm/i915/display/intel_psr.c | 6 +++-- drivers/gpu/drm/i915/i915_reg.h | 25 +++++++++++++++----- 4 files changed, 38 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 533fff79aeda..52570d1eb72e 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -618,7 +618,10 @@ void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state) if (!IS_I830(dev_priv)) val &= ~PIPECONF_ENABLE; - if (DISPLAY_VER(dev_priv) >= 12) + if (DISPLAY_VER(dev_priv) >= 14) + intel_de_rmw(dev_priv, MTL_CHICKEN_TRANS(cpu_transcoder), + FECSTALL_DIS_DPTSTREAM_DPTTG, 0); + else if (DISPLAY_VER(dev_priv) >= 12) intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), FECSTALL_DIS_DPTSTREAM_DPTTG, 0); @@ -1838,7 +1841,9 @@ static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - i915_reg_t reg = CHICKEN_TRANS(crtc_state->cpu_transcoder); + enum transcoder transcoder = crtc_state->cpu_transcoder; + i915_reg_t reg = DISPLAY_VER(dev_priv) >= 14 ? MTL_CHICKEN_TRANS(transcoder) : + CHICKEN_TRANS(transcoder); u32 val; val = intel_de_read(dev_priv, reg); @@ -4033,6 +4038,7 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc, { struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); struct intel_display_power_domain_set power_domain_set = { }; + i915_reg_t reg; bool active; u32 tmp; @@ -4124,7 +4130,9 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc, } if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) { - tmp = intel_de_read(dev_priv, CHICKEN_TRANS(pipe_config->cpu_transcoder)); + reg = DISPLAY_VER(dev_priv) >= 14 ? MTL_CHICKEN_TRANS(pipe_config->cpu_transcoder) : + CHICKEN_TRANS(pipe_config->cpu_transcoder); + tmp = intel_de_read(dev_priv, reg); pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1; } else { diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 14d2a64193b2..a987e88c00d4 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -590,7 +590,10 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state, drm_dp_update_payload_part2(&intel_dp->mst_mgr); - if (DISPLAY_VER(dev_priv) >= 12 && pipe_config->fec_enable) + if (DISPLAY_VER(dev_priv) >= 14 && pipe_config->fec_enable) + intel_de_rmw(dev_priv, MTL_CHICKEN_TRANS(trans), 0, + FECSTALL_DIS_DPTSTREAM_DPTTG); + else if (DISPLAY_VER(dev_priv) >= 12 && pipe_config->fec_enable) intel_de_rmw(dev_priv, CHICKEN_TRANS(trans), 0, FECSTALL_DIS_DPTSTREAM_DPTTG); diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 98c3c8015a5c..15e649269fa1 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1139,7 +1139,8 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp, if (intel_dp->psr.psr2_enabled) { if (DISPLAY_VER(dev_priv) == 9) - intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 0, + intel_de_rmw(dev_priv, + CHICKEN_TRANS(cpu_transcoder), 0, PSR2_VSC_ENABLE_PROG_HEADER | PSR2_ADD_VERTICAL_LINE_COUNT); @@ -1149,7 +1150,8 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp, * cause issues if non-supported panels are used. */ if (IS_ALDERLAKE_P(dev_priv)) - intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 0, + intel_de_rmw(dev_priv, + CHICKEN_TRANS(cpu_transcoder), 0, ADLP_1_BASED_X_GRANULARITY); /* Wa_16011168373:adl-p */ diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index b2b06c080d09..f364051fd192 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5780,17 +5780,30 @@ #define SKL_PLANE1_STRETCH_MAX_X1 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 3) #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B) +#define _MTL_CHICKEN_TRANS_A 0x604e0 +#define _MTL_CHICKEN_TRANS_B 0x614e0 +#define _MTL_CHICKEN_TRANS_C 0x624e0 +#define _MTL_CHICKEN_TRANS_D 0x634e0 + #define _CHICKEN_TRANS_A 0x420c0 #define _CHICKEN_TRANS_B 0x420c4 #define _CHICKEN_TRANS_C 0x420c8 #define _CHICKEN_TRANS_EDP 0x420cc #define _CHICKEN_TRANS_D 0x420d8 -#define CHICKEN_TRANS(trans) _MMIO(_PICK((trans), \ - [TRANSCODER_EDP] = _CHICKEN_TRANS_EDP, \ - [TRANSCODER_A] = _CHICKEN_TRANS_A, \ - [TRANSCODER_B] = _CHICKEN_TRANS_B, \ - [TRANSCODER_C] = _CHICKEN_TRANS_C, \ - [TRANSCODER_D] = _CHICKEN_TRANS_D)) + +#define CHICKEN_TRANS(trans) _MMIO(_PICK((trans), \ + [TRANSCODER_EDP] = _CHICKEN_TRANS_EDP, \ + [TRANSCODER_A] = _CHICKEN_TRANS_A, \ + [TRANSCODER_B] = _CHICKEN_TRANS_B, \ + [TRANSCODER_C] = _CHICKEN_TRANS_C, \ + [TRANSCODER_D] = _CHICKEN_TRANS_D)) + +#define MTL_CHICKEN_TRANS(trans) _MMIO(_PICK((trans), \ + [TRANSCODER_A] = _MTL_CHICKEN_TRANS_A, \ + [TRANSCODER_B] = _MTL_CHICKEN_TRANS_B, \ + [TRANSCODER_C] = _MTL_CHICKEN_TRANS_C, \ + [TRANSCODER_D] = _MTL_CHICKEN_TRANS_D)) + #define HSW_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) #define HSW_FRAME_START_DELAY(x) REG_FIELD_PREP(HSW_FRAME_START_DELAY_MASK, x) #define VSC_DATA_SEL_SOFTWARE_CONTROL REG_BIT(25) /* GLK */ From patchwork Thu Aug 18 23:42:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 12948183 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 79C81C00140 for ; Thu, 18 Aug 2022 23:43:51 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AE86110EA0C; Thu, 18 Aug 2022 23:43:03 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id AD1A310E62B; Thu, 18 Aug 2022 23:42:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660866153; x=1692402153; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=37lE3FD1iHRf26LEpCBliMaodGJ8MIyIAzQNYCyiVEY=; b=A0/O04ESkAWhpoJ9VDipqOYSfl4KOmMNrFm33H0VhPI/fRvVm7Bx9qcU vUjE5qprOzdVw+mbbgkk1HsdsIotxhRakthqU+qt/JoVq/Dc8uZqbFJT6 SadG4F7mQd2tm7uWuMdTYh8Os84u+Nev80w+knqCFvV0S/9s04Tao9tS/ mo97+eaUvAMGNd3CfNsGahk5Y8KBj+gEdHSanCAUFvZX29tonCDfyPmej x1DuaiSkLs1snlLj23IO8A7P+XT6/cL+jkCWa1WYLM4irSeknJaaoeEKi gRS3EG1Ad37BWRBSjMVczHDzoLGLijl1rPcOPlGLEDSTORRHE+ozgs20g w==; X-IronPort-AV: E=McAfee;i="6500,9779,10443"; a="275938529" X-IronPort-AV: E=Sophos;i="5.93,247,1654585200"; d="scan'208";a="275938529" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Aug 2022 16:42:29 -0700 X-IronPort-AV: E=Sophos;i="5.93,247,1654585200"; d="scan'208";a="783953306" Received: from invictus.jf.intel.com ([10.165.21.205]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Aug 2022 16:42:28 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Subject: [PATCH v2 21/21] drm/i915/mtl: Do not update GV point, mask value Date: Thu, 18 Aug 2022 16:42:02 -0700 Message-Id: <20220818234202.451742-22-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220818234202.451742-1-radhakrishna.sripada@intel.com> References: <20220818234202.451742-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" No need to update mask value/restrict because "Pcode only wants to use GV bandwidth value, not the mask value." for Display version greater than 14. Bspec: 646365 Cc: Matt Roper Original Author: Caz Yokoyama Signed-off-by: Radhakrishna Sripada --- drivers/gpu/drm/i915/intel_pm.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index d09e9e5f4481..47869fe964ba 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3924,6 +3924,14 @@ void intel_sagv_pre_plane_update(struct intel_atomic_state *state) { struct drm_i915_private *i915 = to_i915(state->base.dev); + /* + * No need to update mask value/restrict because + * "Pcode only wants to use GV bandwidth value, not the mask value." + * for DISPLAY_VER() >= 14. + */ + if (DISPLAY_VER(i915) >= 14) + return; + /* * Just return if we can't control SAGV or don't have it. * This is different from situation when we have SAGV but just can't @@ -3944,6 +3952,16 @@ void intel_sagv_post_plane_update(struct intel_atomic_state *state) { struct drm_i915_private *i915 = to_i915(state->base.dev); + /* + * No need to update mask value/restrict because + * "Pcode only wants to use GV bandwidth value, not the mask value." + * for DISPLAY_VER() >= 14. + * + * GV bandwidth will be set by intel_pmdemand_post_plane_update() + */ + if (DISPLAY_VER(i915) >= 14) + return; + /* * Just return if we can't control SAGV or don't have it. * This is different from situation when we have SAGV but just can't