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Fri, 19 Aug 2022 07:47:43 +0000 From: wei.fang@nxp.com To: davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, andrew@lunn.ch, f.fainelli@gmail.com, hkallweit1@gmail.com, linux@armlinux.org.uk Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 1/2] dt-bindings: net: tja11xx: add nxp,refclk_in property Date: Fri, 19 Aug 2022 15:47:27 +0800 Message-Id: <20220819074729.1496088-2-wei.fang@nxp.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220819074729.1496088-1-wei.fang@nxp.com> References: <20220819074729.1496088-1-wei.fang@nxp.com> X-ClientProxiedBy: SG2PR03CA0122.apcprd03.prod.outlook.com (2603:1096:4:91::26) To DB9PR04MB8106.eurprd04.prod.outlook.com (2603:10a6:10:24b::13) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ec6961f1-3478-477b-ac13-08da81b71972 X-MS-TrafficTypeDiagnostic: VI1PR04MB7199:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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This patch add the property to make the REF_CLK can be configurable. Signed-off-by: Wei Fang --- .../devicetree/bindings/net/nxp,tja11xx.yaml | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/Documentation/devicetree/bindings/net/nxp,tja11xx.yaml b/Documentation/devicetree/bindings/net/nxp,tja11xx.yaml index d51da24f3505..c51ee52033e8 100644 --- a/Documentation/devicetree/bindings/net/nxp,tja11xx.yaml +++ b/Documentation/devicetree/bindings/net/nxp,tja11xx.yaml @@ -31,6 +31,22 @@ patternProperties: description: The ID number for the child PHY. Should be +1 of parent PHY. + nxp,rmii_refclk_in: + type: boolean + description: | + The REF_CLK is provided for both transmitted and receivced data + in RMII mode. This clock signal is provided by the PHY and is + typically derived from an external 25MHz crystal. Alternatively, + a 50MHz clock signal generated by an external oscillator can be + connected to pin REF_CLK. A third option is to connect a 25MHz + clock to pin CLK_IN_OUT. So, the REF_CLK should be configured + as input or output according to the actual circuit connection. + If present, indicates that the REF_CLK will be configured as + interface reference clock input when RMII mode enabled. + If not present, the REF_CLK will be configured as interface + reference clock output when RMII mode enabled. + Only supported on TJA1100 and TJA1101. + required: - reg @@ -44,6 +60,7 @@ examples: tja1101_phy0: ethernet-phy@4 { reg = <0x4>; + nxp,rmii_refclk_in; }; }; - | From patchwork Fri Aug 19 07:47:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wei Fang X-Patchwork-Id: 12948493 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A79FAC32771 for ; Fri, 19 Aug 2022 07:48:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347230AbiHSHsN (ORCPT ); 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: PC2+My2SEif23aULljofHCvPz2ihaAU84qF0f8oEaCUuDlLH6EUGyRfHyGnMdw6elgbDG9DusNY+6HIV+RBDWA6m66wBR0GjqlV50Gyy4kCgAl0h421LzorytcO4F9FKMNRXt0EwFfphd/AtO8N0XnbgqhsV5psOcEZxj4yp5mtGB5IWbdekYT4Jg+PbGNef8C6j50Z5pahsjaMBRYWqrpGfjCBOcFEmnW4KBPu6yYgGM7Sj/osOQOgVIz6ohj9tVQvzq2Hh6Me1goY7E6CIBQ0vrtiNtj9RR/nvFPAl1B1QOvADJ1Tz4xTLDvmr7PRVm3WvHLLMIm7/5OkX1/MkGZrfDNQvUk24hX4BM500ZBknNQ2Hyfq9q4QqgW2TQ5HdJwdPi4rU4mLrtahdhfNe9HQsRk33GLwFkNcrGq5mXL8lJZy5o0vhOyYg5qQfNSdx3bCMWx+kV9WTJ9KwyVZjrGfmwhoAqyb4llCA0bR213MpvgKC8Amd2x06kI+ccwlCHxriUdqsoBV9hUSliZgbtBQPyWrKUS8IQC0B5N8ZOs3OKVUk4fZNNXbGu6UPRpBxDZGHb6PzAvcIcXb57WaPL1fM3YSMxq2To7GMresOCwHIFU712ziRh0ZYwwxVEdNOScTRWGmtSMRpqtWF7QYds3bRFIvTXIHPk2tj7UvjdYhVdp6zykyZ/GNGltOacWp0o6haCq62ATg167PGWgh1sTeuvmVQ4ADcFemLOAJasIQeiU1ISFvUDJzIBWg+rxljvA4xr/I5v/A2sNxxK/V1AOLGuXpmgOVzqR9BrN04T277WwH7S1qunshkD+AbK7EISG0o4wgmKh6QqSP8n3CuNxK2ox81TUASQEMWTTOr0yW6cAhVmPWYMyXjj+ndjOwHZCHSPipAmSsigliBgWrwCgBVZg340279ffN0OK5IwOr2pBPSTw7c1HxfVk4Iupy/ljpCi6TtrT/tt1T2jvVGGzDo77VtCxrkgGEphpPWBgGtwkYMIZDDGZfNBg2C3juRQX8OukHqIxJ9H9FDWpipsLbBE8Vt9hKj6ojHIFyICtvpuA8SBaPTKPOxNGWu2nonCzwDWZFGh6K4eG4dl9Rj1OxGew1/hNcCnMPM5pmiPUqmNvTa3/GjSj58ggpjz2EPJOarjMnw0yf8Ur/BDLQAa47dxGepdLHqsKAxoNgMDJVk1AsrRKggiMKtZoBBUEvTgqv7muOIv3Qt/b2b0aoJ2GWTgOTykLrSAvZ5KZYVC9vvqbQt7EnWKfvqrE5oLyNb3VOf0Y/h9nLpnpB3dv6YnzAoOjyVn9PPr6T5gJ90SMcT+f7JnbClIXVZYXcK5bjs05tzRhkAZZmRdI1lWjRzwWo0B/NIresGRY23wg1Iv+uWtbBIko//OdRoUjVznSe189Vu3MXuDLEQ/CRMDNyjOA/XthOheEDgloqYzAMpHuOG+JPjWs+DXAURPzh6ICYQ4VOjzM807j8RoFYN+LuI5Pt7cxfCpi3NYo0UUxQHawu5Pz35SzdTGSob9GO5ujaM4pFkbQFaJl56ubGYL8eFTKtx65uQXUC1sNZAuOFhBXDjJk595KAQq9zQrZIRp7jk X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: c6f4c99c-0bed-443f-7dfe-08da81b71d68 X-MS-Exchange-CrossTenant-AuthSource: DB9PR04MB8106.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Aug 2022 07:47:50.0606 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: deTyQeDxLyPaXpmKZocoXAM/gFgMoOHC4ZRaCITALrHIVOg2zNOfplVYvkYXFdWiUQK/JwSEtdCIEl/WYQjN6A== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB6238 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org From: Wei Fang Add below features support for both TJA1100 and TJA1101 cards: - Add MII and RMII mode support. - Add REF_CLK input/output support for RMII mode. Signed-off-by: Wei Fang --- drivers/net/phy/nxp-tja11xx.c | 83 ++++++++++++++++++++++++++++++++--- 1 file changed, 78 insertions(+), 5 deletions(-) diff --git a/drivers/net/phy/nxp-tja11xx.c b/drivers/net/phy/nxp-tja11xx.c index 2a8195c50d14..487c881d20b1 100644 --- a/drivers/net/phy/nxp-tja11xx.c +++ b/drivers/net/phy/nxp-tja11xx.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -34,6 +35,11 @@ #define MII_CFG1 18 #define MII_CFG1_MASTER_SLAVE BIT(15) #define MII_CFG1_AUTO_OP BIT(14) +#define MII_CFG1_INTERFACE_MODE_MASK GENMASK(9, 8) +#define MII_CFG1_MII_MODE (0x0 << 8) +#define MII_CFG1_RMII_MODE_REFCLK_IN BIT(8) +#define MII_CFG1_RMII_MODE_REFCLK_OUT BIT(9) +#define MII_CFG1_REVMII_MODE GENMASK(9, 8) #define MII_CFG1_SLEEP_CONFIRM BIT(6) #define MII_CFG1_LED_MODE_MASK GENMASK(5, 4) #define MII_CFG1_LED_MODE_LINKUP 0 @@ -72,11 +78,15 @@ #define MII_COMMCFG 27 #define MII_COMMCFG_AUTO_OP BIT(15) +/* Configure REF_CLK as input in RMII mode */ +#define TJA110X_RMII_MODE_REFCLK_IN BIT(0) + struct tja11xx_priv { char *hwmon_name; struct device *hwmon_dev; struct phy_device *phydev; struct work_struct phy_register_work; + u32 quirks; }; struct tja11xx_phy_stats { @@ -251,8 +261,34 @@ static int tja11xx_config_aneg(struct phy_device *phydev) return __genphy_config_aneg(phydev, changed); } +static int tja11xx_get_interface_mode(struct phy_device *phydev) +{ + struct tja11xx_priv *priv = phydev->priv; + int mii_mode; + + switch (phydev->interface) { + case PHY_INTERFACE_MODE_MII: + mii_mode = MII_CFG1_MII_MODE; + break; + case PHY_INTERFACE_MODE_REVMII: + mii_mode = MII_CFG1_REVMII_MODE; + break; + case PHY_INTERFACE_MODE_RMII: + if (priv->quirks & TJA110X_RMII_MODE_REFCLK_IN) + mii_mode = MII_CFG1_RMII_MODE_REFCLK_IN; + else + mii_mode = MII_CFG1_RMII_MODE_REFCLK_OUT; + break; + default: + return -EINVAL; + } + + return mii_mode; +} + static int tja11xx_config_init(struct phy_device *phydev) { + u16 reg_mask, reg_val; int ret; ret = tja11xx_enable_reg_write(phydev); @@ -265,15 +301,32 @@ static int tja11xx_config_init(struct phy_device *phydev) switch (phydev->phy_id & PHY_ID_MASK) { case PHY_ID_TJA1100: - ret = phy_modify(phydev, MII_CFG1, - MII_CFG1_AUTO_OP | MII_CFG1_LED_MODE_MASK | - MII_CFG1_LED_ENABLE, - MII_CFG1_AUTO_OP | MII_CFG1_LED_MODE_LINKUP | - MII_CFG1_LED_ENABLE); + reg_mask = MII_CFG1_AUTO_OP | MII_CFG1_LED_MODE_MASK | + MII_CFG1_LED_ENABLE; + reg_val = MII_CFG1_AUTO_OP | MII_CFG1_LED_MODE_LINKUP | + MII_CFG1_LED_ENABLE; + + reg_mask |= MII_CFG1_INTERFACE_MODE_MASK; + ret = tja11xx_get_interface_mode(phydev); + if (ret < 0) + return ret; + + reg_val |= (ret & 0xffff); + ret = phy_modify(phydev, MII_CFG1, reg_mask, reg_val); if (ret) return ret; break; case PHY_ID_TJA1101: + reg_mask = MII_CFG1_INTERFACE_MODE_MASK; + ret = tja11xx_get_interface_mode(phydev); + if (ret < 0) + return ret; + + reg_val = ret & 0xffff; + ret = phy_modify(phydev, MII_CFG1, reg_mask, reg_val); + if (ret) + return ret; + fallthrough; case PHY_ID_TJA1102: ret = phy_set_bits(phydev, MII_COMMCFG, MII_COMMCFG_AUTO_OP); if (ret) @@ -458,16 +511,36 @@ static int tja11xx_hwmon_register(struct phy_device *phydev, return PTR_ERR_OR_ZERO(priv->hwmon_dev); } +static int tja11xx_parse_dt(struct phy_device *phydev) +{ + struct device_node *node = phydev->mdio.dev.of_node; + struct tja11xx_priv *priv = phydev->priv; + + if (!IS_ENABLED(CONFIG_OF_MDIO)) + return 0; + + if (of_property_read_bool(node, "nxp,rmii_refclk_in")) + priv->quirks |= TJA110X_RMII_MODE_REFCLK_IN; + + return 0; +} + static int tja11xx_probe(struct phy_device *phydev) { struct device *dev = &phydev->mdio.dev; struct tja11xx_priv *priv; + int ret; priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); if (!priv) return -ENOMEM; priv->phydev = phydev; + phydev->priv = priv; + + ret = tja11xx_parse_dt(phydev); + if (ret) + return ret; return tja11xx_hwmon_register(phydev, priv); }