From patchwork Fri Aug 19 11:09:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Like Xu X-Patchwork-Id: 12948715 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 14FC5C32773 for ; Fri, 19 Aug 2022 11:10:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348688AbiHSLKE (ORCPT ); Fri, 19 Aug 2022 07:10:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33696 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348685AbiHSLKC (ORCPT ); Fri, 19 Aug 2022 07:10:02 -0400 Received: from mail-pl1-x629.google.com (mail-pl1-x629.google.com [IPv6:2607:f8b0:4864:20::629]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 52D95F6196 for ; Fri, 19 Aug 2022 04:10:01 -0700 (PDT) Received: by mail-pl1-x629.google.com with SMTP id c2so3866867plo.3 for ; Fri, 19 Aug 2022 04:10:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=5lQJ9N30h1dB8N7TzTDJkwsX1gtcyo4Gy4YtWgKBu68=; b=LnzQGiiilGD6zlGZe8zwajQL1Q3GOpb/Dusxo+sumHtwXzttoDW0jvFBco8EPnn05M jGlT1ASU35x/Ykb5EFk3pALaSKIp/Mb15DIaBnU4gJ8ezo8CIj2cryEmJFwDt+ZMX3cs 2pl5gq/iyPCNd7GlKb6BQ4J7W+B+w+bQUUwHGsFz1kVDJFTcRoT28HVI7qiE9W3fQDVy 6M/O70nJ1bvNTqhThvaxkZhSikJqsKF8Mi7Qj2m3DEzYzqEWzPOTkPLpKoVeOhQdUnAi 4+nwz7PM/tdqaKwbmsda3irH3CBkKIPjCcMMqMOUhdqN/qCB/u6HHaocS1LwcVW3mF0s +bKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=5lQJ9N30h1dB8N7TzTDJkwsX1gtcyo4Gy4YtWgKBu68=; b=ANTlWtQrOU19FIebKS8omurknFDb1Z6vzj1D3P+LaIJ1ynl6cYAQdrASIRUix+z67F OFLhSoDflVCoPKe6rnfYKkuoB+/7dnPP0TMQJoUq/8Ewhs+X8sybavOYTbDNJjw15G27 3LpIxB7daOBrPrNQLdFoqehBiVmVn7al0k5x5lagT7VxzVWSs95RR2uU6jHTxE1S01I8 m3JWu1KbenEFhv5mTzuubWryu0j18YB+LRVEGCYj85pi5C7kHAXwAPJ+4KFpI+BJhx6q tF/EJ2nJSbaeturqkOEmk9tIah/nhYdOvMDA3CO6QxV0Co9EgeePNqa3c87Nczct7nwi teRg== X-Gm-Message-State: ACgBeo1ap6prim8rlo2x9cOpBBzRjA2wJKmypn14u2TYzLoKCAZB3BPN BfggqH5ySZhb2R+VmY2p87g= X-Google-Smtp-Source: AA6agR5QBDDDkc1ojy8pcoBATPfG8lhzulQwxUNqzjyjdroF0TGPVPwUifZDL8HiLHE+l2kWIs+pSw== X-Received: by 2002:a17:902:8e8c:b0:171:2a36:e390 with SMTP id bg12-20020a1709028e8c00b001712a36e390mr7015103plb.77.1660907400820; Fri, 19 Aug 2022 04:10:00 -0700 (PDT) Received: from localhost.localdomain ([103.7.29.32]) by smtp.gmail.com with ESMTPSA id jd7-20020a170903260700b0016bfbd99f64sm2957778plb.118.2022.08.19.04.09.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Aug 2022 04:10:00 -0700 (PDT) From: Like Xu X-Google-Original-From: Like Xu To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org Subject: [kvm-unit-tests PATCH v3 01/13] x86/pmu: Introduce __start_event() to drop all of the manual zeroing Date: Fri, 19 Aug 2022 19:09:27 +0800 Message-Id: <20220819110939.78013-2-likexu@tencent.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220819110939.78013-1-likexu@tencent.com> References: <20220819110939.78013-1-likexu@tencent.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Like Xu Most invocation of start_event() and measure() first sets evt.count=0. Instead of forcing each caller to ensure count is zeroed, optimize the count to zero during start_event(), then drop all of the manual zeroing. Accumulating counts can be handled by reading the current count before start_event(), and doing something like stuffing a high count to test an edge case could be handled by an inner helper, __start_event(). For overflow, just open code measure() for that one-off case. Requiring callers to zero out a field in most common cases isn't exactly flexible. Suggested-by: Sean Christopherson Signed-off-by: Like Xu --- x86/pmu.c | 31 ++++++++++++++++--------------- 1 file changed, 16 insertions(+), 15 deletions(-) diff --git a/x86/pmu.c b/x86/pmu.c index d59baf1..817b4d0 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -137,9 +137,9 @@ static void global_disable(pmu_counter_t *cnt) ~(1ull << cnt->idx)); } - -static void start_event(pmu_counter_t *evt) +static void __start_event(pmu_counter_t *evt, uint64_t count) { + evt->count = count; wrmsr(evt->ctr, evt->count); if (is_gp(evt)) wrmsr(MSR_P6_EVNTSEL0 + event_to_global_idx(evt), @@ -162,6 +162,11 @@ static void start_event(pmu_counter_t *evt) apic_write(APIC_LVTPC, PC_VECTOR); } +static void start_event(pmu_counter_t *evt) +{ + __start_event(evt, 0); +} + static void stop_event(pmu_counter_t *evt) { global_disable(evt); @@ -186,6 +191,13 @@ static void measure(pmu_counter_t *evt, int count) stop_event(&evt[i]); } +static void __measure(pmu_counter_t *evt, uint64_t count) +{ + __start_event(evt, count); + loop(); + stop_event(evt); +} + static bool verify_event(uint64_t count, struct pmu_event *e) { // printf("%d <= %ld <= %d\n", e->min, count, e->max); @@ -208,7 +220,6 @@ static void check_gp_counter(struct pmu_event *evt) int i; for (i = 0; i < nr_gp_counters; i++, cnt.ctr++) { - cnt.count = 0; measure(&cnt, 1); report(verify_event(cnt.count, evt), "%s-%d", evt->name, i); } @@ -235,7 +246,6 @@ static void check_fixed_counters(void) int i; for (i = 0; i < nr_fixed_counters; i++) { - cnt.count = 0; cnt.ctr = fixed_events[i].unit_sel; measure(&cnt, 1); report(verify_event(cnt.count, &fixed_events[i]), "fixed-%d", i); @@ -253,14 +263,12 @@ static void check_counters_many(void) if (!pmu_gp_counter_is_available(i)) continue; - cnt[n].count = 0; cnt[n].ctr = gp_counter_base + n; cnt[n].config = EVNTSEL_OS | EVNTSEL_USR | gp_events[i % ARRAY_SIZE(gp_events)].unit_sel; n++; } for (i = 0; i < nr_fixed_counters; i++) { - cnt[n].count = 0; cnt[n].ctr = fixed_events[i].unit_sel; cnt[n].config = EVNTSEL_OS | EVNTSEL_USR; n++; @@ -283,9 +291,8 @@ static void check_counter_overflow(void) pmu_counter_t cnt = { .ctr = gp_counter_base, .config = EVNTSEL_OS | EVNTSEL_USR | gp_events[1].unit_sel /* instructions */, - .count = 0, }; - measure(&cnt, 1); + __measure(&cnt, 0); count = cnt.count; /* clear status before test */ @@ -311,7 +318,7 @@ static void check_counter_overflow(void) else cnt.config &= ~EVNTSEL_INT; idx = event_to_global_idx(&cnt); - measure(&cnt, 1); + __measure(&cnt, cnt.count); report(cnt.count == 1, "cntr-%d", i); status = rdmsr(MSR_CORE_PERF_GLOBAL_STATUS); report(status & (1ull << idx), "status-%d", i); @@ -329,7 +336,6 @@ static void check_gp_counter_cmask(void) pmu_counter_t cnt = { .ctr = gp_counter_base, .config = EVNTSEL_OS | EVNTSEL_USR | gp_events[1].unit_sel /* instructions */, - .count = 0, }; cnt.config |= (0x2 << EVNTSEL_CMASK_SHIFT); measure(&cnt, 1); @@ -415,7 +421,6 @@ static void check_running_counter_wrmsr(void) pmu_counter_t evt = { .ctr = gp_counter_base, .config = EVNTSEL_OS | EVNTSEL_USR | gp_events[1].unit_sel, - .count = 0, }; report_prefix_push("running counter wrmsr"); @@ -430,7 +435,6 @@ static void check_running_counter_wrmsr(void) wrmsr(MSR_CORE_PERF_GLOBAL_OVF_CTRL, rdmsr(MSR_CORE_PERF_GLOBAL_STATUS)); - evt.count = 0; start_event(&evt); count = -1; @@ -454,13 +458,11 @@ static void check_emulated_instr(void) .ctr = MSR_IA32_PERFCTR0, /* branch instructions */ .config = EVNTSEL_OS | EVNTSEL_USR | gp_events[5].unit_sel, - .count = 0, }; pmu_counter_t instr_cnt = { .ctr = MSR_IA32_PERFCTR0 + 1, /* instructions */ .config = EVNTSEL_OS | EVNTSEL_USR | gp_events[1].unit_sel, - .count = 0, }; report_prefix_push("emulated instruction"); @@ -589,7 +591,6 @@ static void set_ref_cycle_expectations(void) pmu_counter_t cnt = { .ctr = MSR_IA32_PERFCTR0, .config = EVNTSEL_OS | EVNTSEL_USR | gp_events[2].unit_sel, - .count = 0, }; uint64_t tsc_delta; uint64_t t0, t1, t2, t3; From patchwork Fri Aug 19 11:09:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Like Xu X-Patchwork-Id: 12948716 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C12F1C32771 for ; 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Fri, 19 Aug 2022 04:10:02 -0700 (PDT) From: Like Xu X-Google-Original-From: Like Xu To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org Subject: [kvm-unit-tests PATCH v3 02/13] x86/pmu: Introduce multiple_{one, many}() to improve readability Date: Fri, 19 Aug 2022 19:09:28 +0800 Message-Id: <20220819110939.78013-3-likexu@tencent.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220819110939.78013-1-likexu@tencent.com> References: <20220819110939.78013-1-likexu@tencent.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Like Xu The current measure_one() forces the common case to pass in unnecessary information in order to give flexibility to a single use case. It's just syntatic sugar, but it really does help readers as it's not obvious that the "1" specifies the number of events, whereas multiple_many() and measure_one() are relatively self-explanatory. Suggested-by: Sean Christopherson Signed-off-by: Like Xu --- x86/pmu.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/x86/pmu.c b/x86/pmu.c index 817b4d0..45ca2c6 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -181,7 +181,7 @@ static void stop_event(pmu_counter_t *evt) evt->count = rdmsr(evt->ctr); } -static void measure(pmu_counter_t *evt, int count) +static void measure_many(pmu_counter_t *evt, int count) { int i; for (i = 0; i < count; i++) @@ -191,6 +191,11 @@ static void measure(pmu_counter_t *evt, int count) stop_event(&evt[i]); } +static void measure_one(pmu_counter_t *evt) +{ + measure_many(evt, 1); +} + static void __measure(pmu_counter_t *evt, uint64_t count) { __start_event(evt, count); @@ -220,7 +225,7 @@ static void check_gp_counter(struct pmu_event *evt) int i; for (i = 0; i < nr_gp_counters; i++, cnt.ctr++) { - measure(&cnt, 1); + measure_one(&cnt); report(verify_event(cnt.count, evt), "%s-%d", evt->name, i); } } @@ -247,7 +252,7 @@ static void check_fixed_counters(void) for (i = 0; i < nr_fixed_counters; i++) { cnt.ctr = fixed_events[i].unit_sel; - measure(&cnt, 1); + measure_one(&cnt); report(verify_event(cnt.count, &fixed_events[i]), "fixed-%d", i); } } @@ -274,7 +279,7 @@ static void check_counters_many(void) n++; } - measure(cnt, n); + measure_many(cnt, n); for (i = 0; i < n; i++) if (!verify_counter(&cnt[i])) @@ -338,7 +343,7 @@ static void check_gp_counter_cmask(void) .config = EVNTSEL_OS | EVNTSEL_USR | gp_events[1].unit_sel /* instructions */, }; cnt.config |= (0x2 << EVNTSEL_CMASK_SHIFT); - measure(&cnt, 1); + measure_one(&cnt); report(cnt.count < gp_events[1].min, "cmask"); } From patchwork Fri Aug 19 11:09:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Like Xu X-Patchwork-Id: 12948717 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CEE69C32772 for ; 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Fri, 19 Aug 2022 04:10:03 -0700 (PDT) From: Like Xu X-Google-Original-From: Like Xu To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org Subject: [kvm-unit-tests PATCH v3 03/13] x86/pmu: Reset the expected count of the fixed counter 0 when i386 Date: Fri, 19 Aug 2022 19:09:29 +0800 Message-Id: <20220819110939.78013-4-likexu@tencent.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220819110939.78013-1-likexu@tencent.com> References: <20220819110939.78013-1-likexu@tencent.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Like Xu The pmu test check_counter_overflow() always fails with the "./configure --arch=i386". The cnt.count obtained from the latter run of measure() (based on fixed counter 0) is not equal to the expected value (based on gp counter 0) and there is a positive error with a value of 2. The two extra instructions come from inline wrmsr() and inline rdmsr() inside the global_disable() binary code block. Specifically, for each msr access, the i386 code will have two assembly mov instructions before rdmsr/wrmsr (mark it for fixed counter 0, bit 32), but only one assembly mov is needed for x86_64 and gp counter 0 on i386. Fix the expected init cnt.count for fixed counter 0 overflow based on the same fixed counter 0, not always using gp counter 0. Signed-off-by: Like Xu --- x86/pmu.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/x86/pmu.c b/x86/pmu.c index 45ca2c6..057fd4a 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -315,6 +315,9 @@ static void check_counter_overflow(void) if (i == nr_gp_counters) { cnt.ctr = fixed_events[0].unit_sel; + __measure(&cnt, 0); + count = cnt.count; + cnt.count = 1 - count; cnt.count &= (1ull << pmu_fixed_counter_width()) - 1; } From patchwork Fri Aug 19 11:09:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Like Xu X-Patchwork-Id: 12948718 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BB430C32773 for ; Fri, 19 Aug 2022 11:10:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348703AbiHSLKJ (ORCPT ); Fri, 19 Aug 2022 07:10:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33820 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348694AbiHSLKH (ORCPT ); Fri, 19 Aug 2022 07:10:07 -0400 Received: from mail-pf1-x42f.google.com (mail-pf1-x42f.google.com [IPv6:2607:f8b0:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 49A1CF6196 for ; Fri, 19 Aug 2022 04:10:06 -0700 (PDT) Received: by mail-pf1-x42f.google.com with SMTP id k14so4063655pfh.0 for ; Fri, 19 Aug 2022 04:10:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=DsUNkpvOMHdR49JPNiJyAnTXkdk3lRpHK1A3nq8N0v4=; b=AklcV29sl4eiNHQjUriB7F69bIxN7m1obab/P2uGARfEDjf4gHG6GImykULsm12ka3 o6wniu8cOv1Ken6ci1diFggcThBUyHpBbu+vx03vsf9Nu9C3xAxz79tTxUHnC3NU4JuY 7Bf8b3yLypOIxMuj4LCyZwi6YujB02o6pdCLrNMAS4xsKmb8adjn09dcQpkAgzSfGNqt bmvGjgdLtQxW6Nm0kr9OF0HCPF3sXIawuob3VxGCa61/I58v9QXwNvIXRr48EUcagXip JVIadDPYdSSoBIF+tIzt3Ze2XOmYLU1DypsYOycZTmqfsWVS9/jurdMv/MwxWqckdIsD B11w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=DsUNkpvOMHdR49JPNiJyAnTXkdk3lRpHK1A3nq8N0v4=; b=1VDZcFUo71mutofw9sCAQCeNc35WMwkFXqLIcsZhBovlnhP5FlC1clJJ7e29XE9So6 PWnilVvb1ViiUrYG0DbVdyb2lrK3b8s/1Nif8gijBJZ3ABs+R68nuoI0PCmpg+SsfAEH YcpAxlu7gmITKKcI/+xXCnd1sXJ8pqEIGTSMCRQTtWm0YeL0i5B7YfcLzJsXzjLR5XZ+ wkY/O0OiB6gYF+qBkDWrxQsKopnPir21BAZ0Hc3WNNDTOR68Yi8HmnZtDVYz0ColF1B5 TIKNdFuRc9rHyvteaSukfV+uO1lvYl4iGiQqj8amvXwkT7PvlYwqfxFdAvzi1JwyZRlU L11A== X-Gm-Message-State: ACgBeo3yURK/uM+PwbWp1vcPEoJ1Pu4HPi1jsA5TLwsRtpYVDlO1+x6D 1nH6DI8eyD8vyEdqf7Vr7cUzXloNMf02XQ== X-Google-Smtp-Source: AA6agR4z1upAUPaTdQSe3duoVQcuO0VZnPZPEXm6KB3HURZ58eHbAlObgPQTvfdHlJ2WuK1IHVm+nQ== X-Received: by 2002:a05:6a00:1409:b0:52e:d946:b2f5 with SMTP id l9-20020a056a00140900b0052ed946b2f5mr7251888pfu.20.1660907405756; Fri, 19 Aug 2022 04:10:05 -0700 (PDT) Received: from localhost.localdomain ([103.7.29.32]) by smtp.gmail.com with ESMTPSA id jd7-20020a170903260700b0016bfbd99f64sm2957778plb.118.2022.08.19.04.10.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Aug 2022 04:10:05 -0700 (PDT) From: Like Xu X-Google-Original-From: Like Xu To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org Subject: [kvm-unit-tests PATCH v3 04/13] x86/pmu: Add tests for Intel Processor Event Based Sampling (PEBS) Date: Fri, 19 Aug 2022 19:09:30 +0800 Message-Id: <20220819110939.78013-5-likexu@tencent.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220819110939.78013-1-likexu@tencent.com> References: <20220819110939.78013-1-likexu@tencent.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Like Xu This unit-test is intended to test the KVM's support for the Processor Event Based Sampling (PEBS) which is another PMU feature on Intel processors (start from Ice Lake Server). If a bit in PEBS_ENABLE is set to 1, its corresponding counter will write at least one PEBS records (including partial state of the vcpu at the time of the current hardware event) to the guest memory on counter overflow, and trigger an interrupt at a specific DS state. The format of a PEBS record can be configured by another register. These tests cover most usage scenarios, for example there are some specially constructed scenarios (not a typical behaviour of Linux PEBS driver). It lowers the threshold for others to understand this feature and opens up more exploration of KVM implementation or hw feature itself. Signed-off-by: Like Xu --- lib/x86/msr.h | 1 + x86/Makefile.x86_64 | 1 + x86/pmu_pebs.c | 486 ++++++++++++++++++++++++++++++++++++++++++++ x86/unittests.cfg | 7 + 4 files changed, 495 insertions(+) create mode 100644 x86/pmu_pebs.c diff --git a/lib/x86/msr.h b/lib/x86/msr.h index fa1c0c8..252e041 100644 --- a/lib/x86/msr.h +++ b/lib/x86/msr.h @@ -52,6 +52,7 @@ #define MSR_IA32_MCG_CTL 0x0000017b #define MSR_IA32_PEBS_ENABLE 0x000003f1 +#define MSR_PEBS_DATA_CFG 0x000003f2 #define MSR_IA32_DS_AREA 0x00000600 #define MSR_IA32_PERF_CAPABILITIES 0x00000345 diff --git a/x86/Makefile.x86_64 b/x86/Makefile.x86_64 index 8f9463c..bd827fe 100644 --- a/x86/Makefile.x86_64 +++ b/x86/Makefile.x86_64 @@ -33,6 +33,7 @@ tests += $(TEST_DIR)/vmware_backdoors.$(exe) tests += $(TEST_DIR)/rdpru.$(exe) tests += $(TEST_DIR)/pks.$(exe) tests += $(TEST_DIR)/pmu_lbr.$(exe) +tests += $(TEST_DIR)/pmu_pebs.$(exe) ifeq ($(CONFIG_EFI),y) tests += $(TEST_DIR)/amd_sev.$(exe) diff --git a/x86/pmu_pebs.c b/x86/pmu_pebs.c new file mode 100644 index 0000000..db4ecbf --- /dev/null +++ b/x86/pmu_pebs.c @@ -0,0 +1,486 @@ +#include "x86/msr.h" +#include "x86/processor.h" +#include "x86/isr.h" +#include "x86/apic.h" +#include "x86/apic-defs.h" +#include "x86/desc.h" +#include "alloc.h" + +#include "vm.h" +#include "types.h" +#include "processor.h" +#include "vmalloc.h" +#include "alloc_page.h" + +#define PC_VECTOR 32 + +#define X86_FEATURE_PDCM (CPUID(0x1, 0, ECX, 15)) + +#define PERF_CAP_PEBS_FORMAT 0xf00 +#define PMU_CAP_FW_WRITES (1ULL << 13) +#define PMU_CAP_PEBS_BASELINE (1ULL << 14) + +#define INTEL_PMC_IDX_FIXED 32 + +#define GLOBAL_STATUS_BUFFER_OVF_BIT 62 +#define GLOBAL_STATUS_BUFFER_OVF BIT_ULL(GLOBAL_STATUS_BUFFER_OVF_BIT) + +#define EVNTSEL_USR_SHIFT 16 +#define EVNTSEL_OS_SHIFT 17 +#define EVNTSEL_EN_SHIF 22 + +#define EVNTSEL_EN (1 << EVNTSEL_EN_SHIF) +#define EVNTSEL_USR (1 << EVNTSEL_USR_SHIFT) +#define EVNTSEL_OS (1 << EVNTSEL_OS_SHIFT) + +#define PEBS_DATACFG_MEMINFO BIT_ULL(0) +#define PEBS_DATACFG_GP BIT_ULL(1) +#define PEBS_DATACFG_XMMS BIT_ULL(2) +#define PEBS_DATACFG_LBRS BIT_ULL(3) + +#define ICL_EVENTSEL_ADAPTIVE (1ULL << 34) +#define PEBS_DATACFG_LBR_SHIFT 24 +#define MAX_NUM_LBR_ENTRY 32 + +static u64 gp_counter_base = MSR_IA32_PERFCTR0; +static unsigned int max_nr_gp_events; +static unsigned long *ds_bufer; +static unsigned long *pebs_buffer; +static u64 ctr_start_val; +static u64 perf_cap; + +struct debug_store { + u64 bts_buffer_base; + u64 bts_index; + u64 bts_absolute_maximum; + u64 bts_interrupt_threshold; + u64 pebs_buffer_base; + u64 pebs_index; + u64 pebs_absolute_maximum; + u64 pebs_interrupt_threshold; + u64 pebs_event_reset[64]; +}; + +struct pebs_basic { + u64 format_size; + u64 ip; + u64 applicable_counters; + u64 tsc; +}; + +struct pebs_meminfo { + u64 address; + u64 aux; + u64 latency; + u64 tsx_tuning; +}; + +struct pebs_gprs { + u64 flags, ip, ax, cx, dx, bx, sp, bp, si, di; + u64 r8, r9, r10, r11, r12, r13, r14, r15; +}; + +struct pebs_xmm { + u64 xmm[16*2]; /* two entries for each register */ +}; + +struct lbr_entry { + u64 from; + u64 to; + u64 info; +}; + +enum pmc_type { + GP = 0, + FIXED, +}; + +static uint32_t intel_arch_events[] = { + 0x00c4, /* PERF_COUNT_HW_BRANCH_INSTRUCTIONS */ + 0x00c5, /* PERF_COUNT_HW_BRANCH_MISSES */ + 0x0300, /* PERF_COUNT_HW_REF_CPU_CYCLES */ + 0x003c, /* PERF_COUNT_HW_CPU_CYCLES */ + 0x00c0, /* PERF_COUNT_HW_INSTRUCTIONS */ + 0x013c, /* PERF_COUNT_HW_BUS_CYCLES */ + 0x4f2e, /* PERF_COUNT_HW_CACHE_REFERENCES */ + 0x412e, /* PERF_COUNT_HW_CACHE_MISSES */ +}; + +static u64 pebs_data_cfgs[] = { + PEBS_DATACFG_MEMINFO, + PEBS_DATACFG_GP, + PEBS_DATACFG_XMMS, + PEBS_DATACFG_LBRS | ((MAX_NUM_LBR_ENTRY -1) << PEBS_DATACFG_LBR_SHIFT), +}; + +/* Iterating each counter value is a waste of time, pick a few typical values. */ +static u64 counter_start_values[] = { + /* if PEBS counter doesn't overflow at all */ + 0, + 0xfffffffffff0, + /* normal counter overflow to have PEBS records */ + 0xfffffffffffe, + /* test whether emulated instructions should trigger PEBS */ + 0xffffffffffff, +}; + +static inline u8 pebs_format(void) +{ + return (perf_cap & PERF_CAP_PEBS_FORMAT ) >> 8; +} + +static inline bool pebs_has_baseline(void) +{ + return perf_cap & PMU_CAP_PEBS_BASELINE; +} + +static unsigned int get_adaptive_pebs_record_size(u64 pebs_data_cfg) +{ + unsigned int sz = sizeof(struct pebs_basic); + + if (!pebs_has_baseline()) + return sz; + + if (pebs_data_cfg & PEBS_DATACFG_MEMINFO) + sz += sizeof(struct pebs_meminfo); + if (pebs_data_cfg & PEBS_DATACFG_GP) + sz += sizeof(struct pebs_gprs); + if (pebs_data_cfg & PEBS_DATACFG_XMMS) + sz += sizeof(struct pebs_xmm); + if (pebs_data_cfg & PEBS_DATACFG_LBRS) + sz += MAX_NUM_LBR_ENTRY * sizeof(struct lbr_entry); + + return sz; +} + +static void cnt_overflow(isr_regs_t *regs) +{ + apic_write(APIC_EOI, 0); +} + +static inline void workload(void) +{ + asm volatile( + "mov $0x0, %%eax\n" + "cmp $0x0, %%eax\n" + "jne label2\n" + "jne label2\n" + "jne label2\n" + "jne label2\n" + "mov $0x0, %%eax\n" + "cmp $0x0, %%eax\n" + "jne label2\n" + "jne label2\n" + "jne label2\n" + "jne label2\n" + "mov $0xa, %%eax\n" + "cpuid\n" + "mov $0xa, %%eax\n" + "cpuid\n" + "mov $0xa, %%eax\n" + "cpuid\n" + "mov $0xa, %%eax\n" + "cpuid\n" + "mov $0xa, %%eax\n" + "cpuid\n" + "mov $0xa, %%eax\n" + "cpuid\n" + "label2:\n" + : + : + : "eax", "ebx", "ecx", "edx"); +} + +static inline void workload2(void) +{ + asm volatile( + "mov $0x0, %%eax\n" + "cmp $0x0, %%eax\n" + "jne label3\n" + "jne label3\n" + "jne label3\n" + "jne label3\n" + "mov $0x0, %%eax\n" + "cmp $0x0, %%eax\n" + "jne label3\n" + "jne label3\n" + "jne label3\n" + "jne label3\n" + "mov $0xa, %%eax\n" + "cpuid\n" + "mov $0xa, %%eax\n" + "cpuid\n" + "mov $0xa, %%eax\n" + "cpuid\n" + "mov $0xa, %%eax\n" + "cpuid\n" + "mov $0xa, %%eax\n" + "cpuid\n" + "mov $0xa, %%eax\n" + "cpuid\n" + "label3:\n" + : + : + : "eax", "ebx", "ecx", "edx"); +} + +static void alloc_buffers(void) +{ + ds_bufer = alloc_page(); + force_4k_page(ds_bufer); + memset(ds_bufer, 0x0, PAGE_SIZE); + + pebs_buffer = alloc_page(); + force_4k_page(pebs_buffer); + memset(pebs_buffer, 0x0, PAGE_SIZE); +} + +static void free_buffers(void) +{ + if (ds_bufer) + free_page(ds_bufer); + + if (pebs_buffer) + free_page(pebs_buffer); +} + +static void pebs_enable(u64 bitmask, u64 pebs_data_cfg) +{ + static struct debug_store *ds; + u64 baseline_extra_ctrl, fixed_ctr_ctrl = 0; + unsigned int idx; + + if (pebs_has_baseline()) + wrmsr(MSR_PEBS_DATA_CFG, pebs_data_cfg); + + ds = (struct debug_store *)ds_bufer; + ds->pebs_index = ds->pebs_buffer_base = (unsigned long)pebs_buffer; + ds->pebs_absolute_maximum = (unsigned long)pebs_buffer + PAGE_SIZE; + ds->pebs_interrupt_threshold = ds->pebs_buffer_base + + get_adaptive_pebs_record_size(pebs_data_cfg); + + for (idx = 0; idx < pmu_nr_fixed_counters(); idx++) { + if (!(BIT_ULL(INTEL_PMC_IDX_FIXED + idx) & bitmask)) + continue; + baseline_extra_ctrl = pebs_has_baseline() ? + (1ULL << (INTEL_PMC_IDX_FIXED + idx * 4)) : 0; + wrmsr(MSR_CORE_PERF_FIXED_CTR0 + idx, ctr_start_val); + fixed_ctr_ctrl |= (0xbULL << (idx * 4) | baseline_extra_ctrl); + } + if (fixed_ctr_ctrl) + wrmsr(MSR_CORE_PERF_FIXED_CTR_CTRL, fixed_ctr_ctrl); + + for (idx = 0; idx < max_nr_gp_events; idx++) { + if (!(BIT_ULL(idx) & bitmask)) + continue; + baseline_extra_ctrl = pebs_has_baseline() ? + ICL_EVENTSEL_ADAPTIVE : 0; + wrmsr(MSR_P6_EVNTSEL0 + idx, + EVNTSEL_EN | EVNTSEL_OS | EVNTSEL_USR | + intel_arch_events[idx] | baseline_extra_ctrl); + wrmsr(gp_counter_base + idx, ctr_start_val); + } + + wrmsr(MSR_IA32_DS_AREA, (unsigned long)ds_bufer); + wrmsr(MSR_IA32_PEBS_ENABLE, bitmask); + wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, bitmask); +} + +static void pmu_env_cleanup(void) +{ + unsigned int idx; + + memset(ds_bufer, 0x0, PAGE_SIZE); + memset(pebs_buffer, 0x0, PAGE_SIZE); + wrmsr(MSR_IA32_PEBS_ENABLE, 0); + wrmsr(MSR_IA32_DS_AREA, 0); + if (pebs_has_baseline()) + wrmsr(MSR_PEBS_DATA_CFG, 0); + + wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, 0); + + wrmsr(MSR_CORE_PERF_FIXED_CTR_CTRL, 0); + for (idx = 0; idx < pmu_nr_fixed_counters(); idx++) { + wrmsr(MSR_CORE_PERF_FIXED_CTR0 + idx, 0); + } + + for (idx = 0; idx < pmu_nr_gp_counters(); idx++) { + wrmsr(MSR_P6_EVNTSEL0 + idx, 0); + wrmsr(MSR_IA32_PERFCTR0 + idx, 0); + } + + wrmsr(MSR_CORE_PERF_GLOBAL_OVF_CTRL, rdmsr(MSR_CORE_PERF_GLOBAL_STATUS)); +} + +static inline void pebs_disable_1(void) +{ + wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, 0); +} + +static inline void pebs_disable_2(void) +{ + wrmsr(MSR_IA32_PEBS_ENABLE, 0); + wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, 0); +} + +static void pebs_disable(unsigned int idx) +{ + if (idx % 2) { + pebs_disable_1(); + } else { + pebs_disable_2(); + } +} + +static void check_pebs_records(u64 bitmask, u64 pebs_data_cfg) +{ + struct pebs_basic *pebs_rec = (struct pebs_basic *)pebs_buffer; + struct debug_store *ds = (struct debug_store *)ds_bufer; + unsigned int pebs_record_size = get_adaptive_pebs_record_size(pebs_data_cfg); + unsigned int count = 0; + bool expected, pebs_idx_match, pebs_size_match, data_cfg_match; + void *vernier; + + expected = (ds->pebs_index == ds->pebs_buffer_base) && !pebs_rec->format_size; + if (!(rdmsr(MSR_CORE_PERF_GLOBAL_STATUS) & GLOBAL_STATUS_BUFFER_OVF)) { + report(expected, "No OVF irq, none PEBS records."); + return; + } + + if (expected) { + report(!expected, "A OVF irq, but none PEBS records."); + return; + } + + expected = ds->pebs_index >= ds->pebs_interrupt_threshold; + vernier = (void *)pebs_buffer; + do { + pebs_rec = (struct pebs_basic *)vernier; + pebs_record_size = pebs_rec->format_size >> 48; + pebs_idx_match = + pebs_rec->applicable_counters & bitmask; + pebs_size_match = + pebs_record_size == get_adaptive_pebs_record_size(pebs_data_cfg); + data_cfg_match = + (pebs_rec->format_size & 0xffffffffffff) == pebs_data_cfg; + expected = pebs_idx_match && pebs_size_match && data_cfg_match; + report(expected, + "PEBS record (written seq %d) is verified (inclduing size, counters and cfg).", count); + vernier = vernier + pebs_record_size; + count++; + } while (expected && (void *)vernier < (void *)ds->pebs_index); + + if (!expected) { + if (!pebs_idx_match) + printf("FAIL: The applicable_counters (0x%lx) doesn't match with pmc_bitmask (0x%lx).\n", + pebs_rec->applicable_counters, bitmask); + if (!pebs_size_match) + printf("FAIL: The pebs_record_size (%d) doesn't match with MSR_PEBS_DATA_CFG (%d).\n", + pebs_record_size, get_adaptive_pebs_record_size(pebs_data_cfg)); + if (!data_cfg_match) + printf("FAIL: The pebs_data_cfg (0x%lx) doesn't match with MSR_PEBS_DATA_CFG (0x%lx).\n", + pebs_rec->format_size & 0xffffffffffff, pebs_data_cfg); + } +} + +static void check_one_counter(enum pmc_type type, + unsigned int idx, u64 pebs_data_cfg) +{ + report_prefix_pushf("%s counter %d (0x%lx)", + type == FIXED ? "Extended Fixed" : "GP", idx, ctr_start_val); + pmu_env_cleanup(); + pebs_enable(BIT_ULL(type == FIXED ? INTEL_PMC_IDX_FIXED + idx : idx), pebs_data_cfg); + workload(); + pebs_disable(idx); + check_pebs_records(BIT_ULL(type == FIXED ? INTEL_PMC_IDX_FIXED + idx : idx), pebs_data_cfg); + report_prefix_pop(); +} + +static void check_multiple_counters(u64 bitmask, u64 pebs_data_cfg) +{ + pmu_env_cleanup(); + pebs_enable(bitmask, pebs_data_cfg); + workload2(); + pebs_disable(0); + check_pebs_records(bitmask, pebs_data_cfg); +} + +static void check_pebs_counters(u64 pebs_data_cfg) +{ + unsigned int idx; + u64 bitmask = 0; + + for (idx = 0; idx < pmu_nr_fixed_counters(); idx++) + check_one_counter(FIXED, idx, pebs_data_cfg); + + for (idx = 0; idx < max_nr_gp_events; idx++) + check_one_counter(GP, idx, pebs_data_cfg); + + for (idx = 0; idx < pmu_nr_fixed_counters(); idx++) + bitmask |= BIT_ULL(INTEL_PMC_IDX_FIXED + idx); + for (idx = 0; idx < max_nr_gp_events; idx += 2) + bitmask |= BIT_ULL(idx); + report_prefix_pushf("Multiple (0x%lx)", bitmask); + check_multiple_counters(bitmask, pebs_data_cfg); + report_prefix_pop(); +} + +int main(int ac, char **av) +{ + unsigned int i, j; + + setup_vm(); + + max_nr_gp_events = MIN(pmu_nr_gp_counters(), ARRAY_SIZE(intel_arch_events)); + + printf("PMU version: %d\n", pmu_version()); + if (this_cpu_has(X86_FEATURE_PDCM)) + perf_cap = rdmsr(MSR_IA32_PERF_CAPABILITIES); + + if (perf_cap & PMU_CAP_FW_WRITES) + gp_counter_base = MSR_IA32_PMC0; + + if (!is_intel()) { + report_skip("PEBS is only supported on Intel CPUs (ICX or later)"); + return report_summary(); + } else if (pmu_version() < 2) { + report_skip("Architectural PMU version is not high enough"); + return report_summary(); + } else if (!pebs_format()) { + report_skip("PEBS not enumerated in PERF_CAPABILITIES"); + return report_summary(); + } else if (rdmsr(MSR_IA32_MISC_ENABLE) & MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL) { + report_skip("PEBS unavailable according to MISC_ENABLE"); + return report_summary(); + } + + printf("PEBS format: %d\n", pebs_format()); + printf("PEBS GP counters: %d\n", pmu_nr_gp_counters()); + printf("PEBS Fixed counters: %d\n", pmu_nr_fixed_counters()); + printf("PEBS baseline (Adaptive PEBS): %d\n", pebs_has_baseline()); + + printf("Known reasons for none PEBS records:\n"); + printf("1. The selected event does not support PEBS;\n"); + printf("2. From a core pmu perspective, the vCPU and pCPU models are not same;\n"); + printf("3. Guest counter has not yet overflowed or been cross-mapped by the host;\n"); + + handle_irq(PC_VECTOR, cnt_overflow); + alloc_buffers(); + + for (i = 0; i < ARRAY_SIZE(counter_start_values); i++) { + ctr_start_val = counter_start_values[i]; + check_pebs_counters(0); + if (!pebs_has_baseline()) + continue; + + for (j = 0; j < ARRAY_SIZE(pebs_data_cfgs); j++) { + report_prefix_pushf("Adaptive (0x%lx)", pebs_data_cfgs[j]); + check_pebs_counters(pebs_data_cfgs[j]); + report_prefix_pop(); + } + } + + free_buffers(); + + return report_summary(); +} diff --git a/x86/unittests.cfg b/x86/unittests.cfg index ed65185..c5efb25 100644 --- a/x86/unittests.cfg +++ b/x86/unittests.cfg @@ -198,6 +198,13 @@ check = /sys/module/kvm/parameters/ignore_msrs=N check = /proc/sys/kernel/nmi_watchdog=0 accel = kvm +[pmu_pebs] +arch = x86_64 +file = pmu_pebs.flat +extra_params = -cpu host,migratable=no +check = /proc/sys/kernel/nmi_watchdog=0 +accel = kvm + [vmware_backdoors] file = vmware_backdoors.flat extra_params = -machine vmport=on -cpu max From patchwork Fri Aug 19 11:09:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Like Xu X-Patchwork-Id: 12948719 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D4384C32771 for ; Fri, 19 Aug 2022 11:10:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348705AbiHSLKK (ORCPT ); Fri, 19 Aug 2022 07:10:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33864 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348702AbiHSLKJ (ORCPT ); Fri, 19 Aug 2022 07:10:09 -0400 Received: from mail-pf1-x430.google.com (mail-pf1-x430.google.com [IPv6:2607:f8b0:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CFA9FF6196 for ; Fri, 19 Aug 2022 04:10:08 -0700 (PDT) Received: by mail-pf1-x430.google.com with SMTP id y141so4027612pfb.7 for ; Fri, 19 Aug 2022 04:10:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=ql4Rh8J556MPf2Buydi+F1rT3HDm+TzYYIHtdS57x/8=; b=hWiHFMXb6+MFVTZZmTw1b9P4JoH/CDLCxcyA1O8o6MnJUQ3hweHY87uCtMDs0UGVw8 D2wba4Vd7I85zoki8pPHyybY8iUjl8fCNCPlloWyi0DrPwEL2eUahYzZnVCSxq60GeWI O7D/PtUqo0fa99QxfbOx6UR0oSfZEeGg9hqh/yRiJYgSknOC8QQa2ISSQVUDcBQYAFds SZcvP2sWcJAw0VfKbx9HBe18qSOiBA7IRo4T9am9ExVVOEuEDDlSAwNmCeHTUq9cYT5/ CCMIEiqwXB1zVNnvEmd5XppXaho0JN2nDWZt84h5/pc7Amvi8j0vYPgXPby9o97C7U07 ARng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=ql4Rh8J556MPf2Buydi+F1rT3HDm+TzYYIHtdS57x/8=; b=BuYrAEw3JC59sP4n4jTjq9qDRS9h+XEWMaz3cllqqvGXMrnRqRl1oB03KAD79p0JWQ Qhz0mruWWmr4etJZpSVW/zzCteoQcbpoPR8knXQNfWhqLlfaLXMc4qNVhuLN8vNbS7Gn RsiNkKD9E9waAGe7mPwY3cwLZfMCjbPd+PAaQ1DgL/cl+qO2EdUkMfPYkJoV23uOLaEk 5FOtBTwXJyUssBN4SsQcKg7zNsCO84A/8jOhW3QkgH+wr5JAn2zkZRruqrNmi5iIMMck LAiEysUHdHEi5d9J8sEKM29PFUKK3y9XMr8e/65sOcWtwvhQMDg8A7p69WkXSpXIP/gH Yh0A== X-Gm-Message-State: ACgBeo02TjbJRezxaTvCnK5b/PjwJDmiy8ak8A83A77pw9Xt8GJSW3ch T9vzqE0ibx1StHRYIaSKqQ8= X-Google-Smtp-Source: AA6agR6GHDYB2k/X8SDCiZT+zsVh22Jp3c/OSBri0Tw6naniRZ90C1BDGcFO9VG/6/+RUEcYFOSipw== X-Received: by 2002:a05:6a00:1813:b0:52d:cccf:e443 with SMTP id y19-20020a056a00181300b0052dcccfe443mr7332139pfa.81.1660907407360; Fri, 19 Aug 2022 04:10:07 -0700 (PDT) Received: from localhost.localdomain ([103.7.29.32]) by smtp.gmail.com with ESMTPSA id jd7-20020a170903260700b0016bfbd99f64sm2957778plb.118.2022.08.19.04.10.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Aug 2022 04:10:07 -0700 (PDT) From: Like Xu X-Google-Original-From: Like Xu To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org Subject: [kvm-unit-tests PATCH v3 05/13] x86: create pmu group for quick pmu-scope testing Date: Fri, 19 Aug 2022 19:09:31 +0800 Message-Id: <20220819110939.78013-6-likexu@tencent.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220819110939.78013-1-likexu@tencent.com> References: <20220819110939.78013-1-likexu@tencent.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Like Xu Any agent can run "./run_tests.sh -g pmu" for vPMU-related testcases. Signed-off-by: Like Xu Reviewed-by: Sean Christopherson --- x86/unittests.cfg | 3 +++ 1 file changed, 3 insertions(+) diff --git a/x86/unittests.cfg b/x86/unittests.cfg index c5efb25..54f0437 100644 --- a/x86/unittests.cfg +++ b/x86/unittests.cfg @@ -189,6 +189,7 @@ file = pmu.flat extra_params = -cpu max check = /proc/sys/kernel/nmi_watchdog=0 accel = kvm +groups = pmu [pmu_lbr] arch = x86_64 @@ -197,6 +198,7 @@ extra_params = -cpu host,migratable=no check = /sys/module/kvm/parameters/ignore_msrs=N check = /proc/sys/kernel/nmi_watchdog=0 accel = kvm +groups = pmu [pmu_pebs] arch = x86_64 @@ -204,6 +206,7 @@ file = pmu_pebs.flat extra_params = -cpu host,migratable=no check = /proc/sys/kernel/nmi_watchdog=0 accel = kvm +groups = pmu [vmware_backdoors] file = vmware_backdoors.flat From patchwork Fri Aug 19 11:09:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Like Xu X-Patchwork-Id: 12948720 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 56E1FC32774 for ; Fri, 19 Aug 2022 11:10:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348709AbiHSLKM (ORCPT ); Fri, 19 Aug 2022 07:10:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33888 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348704AbiHSLKK (ORCPT ); Fri, 19 Aug 2022 07:10:10 -0400 Received: from mail-pj1-x102c.google.com (mail-pj1-x102c.google.com [IPv6:2607:f8b0:4864:20::102c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 90A1CFBA6A for ; Fri, 19 Aug 2022 04:10:09 -0700 (PDT) Received: by mail-pj1-x102c.google.com with SMTP id a8so4295471pjg.5 for ; Fri, 19 Aug 2022 04:10:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=2rwDhftcDKKq4CQuzXLKUT9Zt9Zd73y4NeTayZ73PF4=; b=KV7LJq3BR+TBx8fVhLx0SrEQegdcWhcZcvr08Gv3fB8Nq5GcowE2HRZAAfwvS90H4U /qluVKnYhetGxbYpfzDaVmJp1VYXN64WfDxtZcWl89BYH8UF4ApC930PPn9eq+YMnnfr O1K4FjV+Hsj6EqsX1NLEaAzlUk4PTpITHyhjkD6F2uMc9u4EpOIvXT3R7xBtsWFAX0Ge 53lmHDQRozFMn892xG3mJMmx7SI52ta2S+kMr2eCnjVwlB9UdZW1nV5o4xFIOhAxauJZ 87vkiPTkpbtq8/xvqBVYLU2pdqJSjqne+BxBS0Dsm/O/pvtWwGKHEfCcvUi7ry+nPYQS rXYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=2rwDhftcDKKq4CQuzXLKUT9Zt9Zd73y4NeTayZ73PF4=; b=EEgWeowlzWL/zdV83OLaXiBUzKVmbLp8g+e/f/YNI8Oc54HRyKqO+7FR9akk9CiMcj RVc2aaIcJWcEQcu2xMN5JZwC7vOrX2OEaKObPsmTxP9ti/Simd2qkeR4fQOGpMBbREpU Jm5rrEQcEYafzHSCIAjBc+Z/qZcweymMubF9xF8Si9wHogH2mjnQD6KktN58O3Q+yDVj hBFB0NM7jl8u6IBxWKLkQbbizJdHByM+Ruz0hM34HP3BltpY/vZt7cLZG2OWqD4o6DeV 3IzaVIGZUC3eMPw1dM8CGkp+5P6HKRNEgvS4f+ZBd0NBqjq5EY7bPDqaK2XSzB0guhim sx5w== X-Gm-Message-State: ACgBeo1vSjVB1KBbKFIbWibc++epZguORYfOi7aKu7vBTHUV7RSsbcJL BYGJXxJteK1PwECVmYeRRo0= X-Google-Smtp-Source: AA6agR74QeVAbSs2O61j1YbI80hZ0Xyp8BtBGGpjZgm0zVkvFEjnDmGPS3uEgT30thW4MQzNM65Rrg== X-Received: by 2002:a17:902:ce84:b0:16f:81d2:60c with SMTP id f4-20020a170902ce8400b0016f81d2060cmr6877132plg.57.1660907409094; Fri, 19 Aug 2022 04:10:09 -0700 (PDT) Received: from localhost.localdomain ([103.7.29.32]) by smtp.gmail.com with ESMTPSA id jd7-20020a170903260700b0016bfbd99f64sm2957778plb.118.2022.08.19.04.10.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Aug 2022 04:10:08 -0700 (PDT) From: Like Xu X-Google-Original-From: Like Xu To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org Subject: [kvm-unit-tests PATCH v3 06/13] x86/pmu: Test emulation instructions on full-width counters Date: Fri, 19 Aug 2022 19:09:32 +0800 Message-Id: <20220819110939.78013-7-likexu@tencent.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220819110939.78013-1-likexu@tencent.com> References: <20220819110939.78013-1-likexu@tencent.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Like Xu Move check_emulated_instr() into check_counters() so that full-width counters could be tested with ease by the same test case. Signed-off-by: Like Xu --- x86/pmu.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/x86/pmu.c b/x86/pmu.c index 057fd4a..9262f3c 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -530,6 +530,9 @@ static void check_emulated_instr(void) static void check_counters(void) { + if (is_fep_available()) + check_emulated_instr(); + check_gp_counters(); check_fixed_counters(); check_rdpmc(); @@ -664,9 +667,6 @@ int main(int ac, char **av) apic_write(APIC_LVTPC, PC_VECTOR); - if (is_fep_available()) - check_emulated_instr(); - check_counters(); if (rdmsr(MSR_IA32_PERF_CAPABILITIES) & PMU_CAP_FW_WRITES) { From patchwork Fri Aug 19 11:09:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Like Xu X-Patchwork-Id: 12948721 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9CF22C32771 for ; Fri, 19 Aug 2022 11:10:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348711AbiHSLKN (ORCPT ); Fri, 19 Aug 2022 07:10:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33934 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348708AbiHSLKL (ORCPT ); Fri, 19 Aug 2022 07:10:11 -0400 Received: from mail-pj1-x1032.google.com (mail-pj1-x1032.google.com [IPv6:2607:f8b0:4864:20::1032]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1EDE2FBA6A for ; Fri, 19 Aug 2022 04:10:11 -0700 (PDT) Received: by mail-pj1-x1032.google.com with SMTP id o5-20020a17090a3d4500b001ef76490983so4541913pjf.2 for ; Fri, 19 Aug 2022 04:10:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=c216Il+C/yqgokZi4GVwSSSatg+JxksECsNr0y7HZCI=; b=OgxgUa9jARhd43kvqO1LfMR8lnynBFoE700aj5dA7F1V8x5XQL9lqcHGvhTZoB3XYp 7tvn9pDiJuCAXDYayJi/m/4vbDcGncdzMYtKyVJ7SFTotJpjHsI/6XV2BjwPkjQjvPw0 eyFpc3XH5E2xWPfwaznyXawD3henoh3vb1kigzVDm95KMRdzkDL96BMKJA/0Klo5fpA1 w1AvGdCXE9ocyBafwi6PwNeG3YSiBDGz9X/iRq9Iv+gh8C1RIhuJRNMZrul8e/W/8CkO ADxpC4sC3+hlU5905LtWXk2D1yzXz9oXtERI0F6OzijrLOiOBfHYByG4TFvdd7VfKmPP acUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=c216Il+C/yqgokZi4GVwSSSatg+JxksECsNr0y7HZCI=; b=w8jgcaWnLfjoEqiWdnKSZuob5nE6usXJ66H5uPr6Ny/A1TSNC5vpZA+jca2hdEMmyu JwquxurAiYxZRU2dnWSnPM3ofNrjlrtUcwx6MamuOZ/sB0lQcyu3tzC1daNW/NKZ6n+D PTln1H/lmhBw423o/3CcjuJYMwyGHQcl/3ySRcwZFzefWap36tplepNHQ5psLmQQDQni K/1DzW016soDSNPf4/8JCvpxCqRWsipFKokrlWmZVcBisCrkxMnq2cZ6GIecT4sDmDEo XhJQxJn3gjUXXbpa4X5sqgpybwdkK7PvWRLDbDnidPA6uLzq45LR1b2ZJasMP5EXALcn 0kWg== X-Gm-Message-State: ACgBeo0emkPsMrSsUnlod8E7S25Bro81ZJyxB1H6NARGwW8eXSI8A3eV RTBmgORqiGa/Z1dfHEAJtU+IHG1duyD2HA== X-Google-Smtp-Source: AA6agR4ZUI1woj9YSbhTHhzB1vRWTEt4kzOQHgzfedlkrjeRLrXcfCZhaTDzHs1k3SY08xcujJozog== X-Received: by 2002:a17:902:e804:b0:172:812f:ad0b with SMTP id u4-20020a170902e80400b00172812fad0bmr6791421plg.26.1660907410667; Fri, 19 Aug 2022 04:10:10 -0700 (PDT) Received: from localhost.localdomain ([103.7.29.32]) by smtp.gmail.com with ESMTPSA id jd7-20020a170903260700b0016bfbd99f64sm2957778plb.118.2022.08.19.04.10.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Aug 2022 04:10:10 -0700 (PDT) From: Like Xu X-Google-Original-From: Like Xu To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org Subject: [kvm-unit-tests PATCH v3 07/13] x86/pmu: Pop up FW prefix to avoid out-of-context propagation Date: Fri, 19 Aug 2022 19:09:33 +0800 Message-Id: <20220819110939.78013-8-likexu@tencent.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220819110939.78013-1-likexu@tencent.com> References: <20220819110939.78013-1-likexu@tencent.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Like Xu The inappropriate prefix may be propagated to later test cases if any. Signed-off-by: Like Xu Reviewed-by: Sean Christopherson --- x86/pmu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/x86/pmu.c b/x86/pmu.c index 9262f3c..4eb92d8 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -674,6 +674,7 @@ int main(int ac, char **av) report_prefix_push("full-width writes"); check_counters(); check_gp_counters_write_width(); + report_prefix_pop(); } return report_summary(); From patchwork Fri Aug 19 11:09:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Like Xu X-Patchwork-Id: 12948722 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C22AAC32771 for ; Fri, 19 Aug 2022 11:10:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348713AbiHSLKO (ORCPT ); Fri, 19 Aug 2022 07:10:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33946 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348704AbiHSLKN (ORCPT ); Fri, 19 Aug 2022 07:10:13 -0400 Received: from mail-pj1-x1029.google.com (mail-pj1-x1029.google.com [IPv6:2607:f8b0:4864:20::1029]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C6700FBA6A for ; Fri, 19 Aug 2022 04:10:12 -0700 (PDT) Received: by mail-pj1-x1029.google.com with SMTP id s4-20020a17090a5d0400b001fabc6bb0baso4455601pji.1 for ; Fri, 19 Aug 2022 04:10:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=RRIrXHQwZ3S+bg/R1JplX5ItK+RwG3sr4MtSf2FKtng=; b=enswTMYUmwG1NFALvRJnrC7wdXhQjysRXvq6ErjhwpOGEZrjYNVStu96tXyO83EbCe 8/tQZWSazb1XE6DRxKcSdKk4Et7XgBTSkWjibalJddWyP5N4w7yfH8ozOLGZNXRh3LOE TSbeCdGWUREOwAKIeH9Gj5+NJ5mNKnJJ5VBLhV4g9gA0HmHl1rSMPihHVGSIRfFg+z+n gF4huhwZutBh7zKdHi78LAMVUlS9suqUZyY9DJUJz1isOUyIxDe8UV0CUXga6/YLQmuJ yRB0qoTSHtNdcK/Sguy1/EBpVpJjycSsK5DQ3N6SQvGzfrTVjSVdIuhJ7ivRTEgW87mb VPxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=RRIrXHQwZ3S+bg/R1JplX5ItK+RwG3sr4MtSf2FKtng=; b=V6Z8nJExTbrXLosec+MCgbXZvRTroXvFRVyRXOmkMU1xV7MAa6It9RS/XwXXzSSZEc dlH9jLtNa9FefS+ipoAIfCpCX1knFTLKzT7qf5TAprWs0ZvU0r9U0Tcc6tSmXDN9RRBr YgwLOMgjxDq6EY/bu0ONZizKsc/DvUzbjlQjUHkPIlpfcaAWrYiJykv4LJEbTjHD8WH1 AvnCMBN+SDEh72h0ryPx0klY0xL0PeO/aFHgzSyQyS+sjrcuRLU/jSAE4rkkgghQDeoE eKMBDtDM+y9al3PWNy3TtnE1Tst4YZv/Mznul0mKJDuGU2Gb3OSJq3xL4IY4bnnOYlUe NsHQ== X-Gm-Message-State: ACgBeo1sH+Cuh7Z1QXIvmP2VR9zFYkGS83f04ynk57XNrPkjRyOrQlF0 LCoKRRgqzXosxid5AqVGBFWbOKTJ4sahvg== X-Google-Smtp-Source: AA6agR5+vBadt4Sab8K4yAh3fzk9VuLJ7RUCk72cSngQdBWKXTQBz9VoHTJg8clhHcKVvQg5OQHftQ== X-Received: by 2002:a17:90b:1a8f:b0:1f4:fb36:a9b3 with SMTP id ng15-20020a17090b1a8f00b001f4fb36a9b3mr7910020pjb.186.1660907412346; Fri, 19 Aug 2022 04:10:12 -0700 (PDT) Received: from localhost.localdomain ([103.7.29.32]) by smtp.gmail.com with ESMTPSA id jd7-20020a170903260700b0016bfbd99f64sm2957778plb.118.2022.08.19.04.10.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Aug 2022 04:10:11 -0700 (PDT) From: Like Xu X-Google-Original-From: Like Xu To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org Subject: [kvm-unit-tests PATCH v3 08/13] x86/pmu: Add PDCM check before accessing PERF_CAP register Date: Fri, 19 Aug 2022 19:09:34 +0800 Message-Id: <20220819110939.78013-9-likexu@tencent.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220819110939.78013-1-likexu@tencent.com> References: <20220819110939.78013-1-likexu@tencent.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Like Xu On virtual platforms without PDCM support (e.g. AMD), #GP failure on MSR_IA32_PERF_CAPABILITIES is completely avoidable. Signed-off-by: Like Xu --- x86/pmu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/x86/pmu.c b/x86/pmu.c index 4eb92d8..25fafbe 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -669,7 +669,8 @@ int main(int ac, char **av) check_counters(); - if (rdmsr(MSR_IA32_PERF_CAPABILITIES) & PMU_CAP_FW_WRITES) { + if (this_cpu_has(X86_FEATURE_PDCM) && + (rdmsr(MSR_IA32_PERF_CAPABILITIES) & PMU_CAP_FW_WRITES)) { gp_counter_base = MSR_IA32_PMC0; report_prefix_push("full-width writes"); check_counters(); From patchwork Fri Aug 19 11:09:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Like Xu X-Patchwork-Id: 12948723 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 44B87C32773 for ; Fri, 19 Aug 2022 11:10:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348717AbiHSLKQ (ORCPT ); Fri, 19 Aug 2022 07:10:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33956 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348714AbiHSLKO (ORCPT ); Fri, 19 Aug 2022 07:10:14 -0400 Received: from mail-pl1-x62f.google.com (mail-pl1-x62f.google.com [IPv6:2607:f8b0:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 71218FBA6A for ; Fri, 19 Aug 2022 04:10:14 -0700 (PDT) Received: by mail-pl1-x62f.google.com with SMTP id d10so3856186plr.6 for ; Fri, 19 Aug 2022 04:10:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=0YGFLPFovyB+DyTae27PXjktmX2sRvaYGC3mBGAT3Tc=; b=YLq5SKA6Z5IdKifhlt6auyqTc9VCJLJq7++qeGbUrDwi3KyKHmPbxcuApBHNUzC+PR RMiuifxbmKh3TQdzKlFtxpb5dSYx4e92wSmYSawl2czBNkWj8HcZoBvmn2crJwEF+JKB 38YXfYEZ2tzWBpuWedNKqfhOgyMpY25CLyzvGJ+q1OD7i5AD7rkw2KkCwubSv3x0oMRe mtom6rjmMTVQT25P6ISz1Ue/CT30oKQrobBlgI2JQG/eRB/T5Rlj0HQRbuY/dvPlJh5p cro94k+SHqWZ4e+mFb+E9LSN48sGg67l3ASNXpvieYIthotNbL5dmh0JlDzlTMtT1tK9 s4FA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=0YGFLPFovyB+DyTae27PXjktmX2sRvaYGC3mBGAT3Tc=; b=FGwiGfqwYqlCPqzXWJjJH39QRUJOmWn8VGfs0iff818dCzHANFvQocFo692/+72Pju 2xb5dEHeXmklnHFKH4aW7SZvuttHUxgF1DrYHWUsIuTeWZL4Z7NbsHoxvZofFqulR/yN MfFvgOpG6RqqMrEghW4oQjs1KE+z1dh2uUaweGY4np9V2sc5LE113PcVuffkwPJGJNIc jVISzF4EFYEJ31n0y2pbRsevLSjtuQCfQWtHbCx5rBPzVFsyNqx8gbe/y+WscWJQVVQQ uqpeALXcLk+pa4xMgp06QeAoQgutnywGtAxi+ZJRGzdeCMGViyRx/tJwvTq5VOpNAp+6 h1Nw== X-Gm-Message-State: ACgBeo0c+7kPjuKiN2Ey+jGagpl+vGZobvYYOLO4pCdq5uSisyTt9uFh vA5/pf2CsenNYNJ6suXi1xo= X-Google-Smtp-Source: AA6agR7rBjM6wWBALIACLDH7k+lh8VTq8e61TARHo4KALoCdWQC5rcPnhLz2ZzuDVU3MIXVQi8IF2w== X-Received: by 2002:a17:90a:e7d1:b0:1f5:665:4607 with SMTP id kb17-20020a17090ae7d100b001f506654607mr13635154pjb.77.1660907413969; Fri, 19 Aug 2022 04:10:13 -0700 (PDT) Received: from localhost.localdomain ([103.7.29.32]) by smtp.gmail.com with ESMTPSA id jd7-20020a170903260700b0016bfbd99f64sm2957778plb.118.2022.08.19.04.10.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Aug 2022 04:10:13 -0700 (PDT) From: Like Xu X-Google-Original-From: Like Xu To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org Subject: [kvm-unit-tests PATCH v3 09/13] x86/pmu: Report SKIP when testing Intel LBR on AMD platforms Date: Fri, 19 Aug 2022 19:09:35 +0800 Message-Id: <20220819110939.78013-10-likexu@tencent.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220819110939.78013-1-likexu@tencent.com> References: <20220819110939.78013-1-likexu@tencent.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Like Xu The test conclusion of running Intel LBR on AMD platforms should not be PASS, but SKIP, fix it. Signed-off-by: Like Xu Reviewed-by: Sean Christopherson --- x86/pmu_lbr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/x86/pmu_lbr.c b/x86/pmu_lbr.c index 8dad1f1..4a9e24d 100644 --- a/x86/pmu_lbr.c +++ b/x86/pmu_lbr.c @@ -59,7 +59,7 @@ int main(int ac, char **av) if (!is_intel()) { report_skip("PMU_LBR test is for intel CPU's only"); - return 0; + return report_summary(); } if (!this_cpu_has_pmu()) { From patchwork Fri Aug 19 11:09:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Like Xu X-Patchwork-Id: 12948724 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AE493C32772 for ; Fri, 19 Aug 2022 11:10:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348719AbiHSLKS (ORCPT ); Fri, 19 Aug 2022 07:10:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33964 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348704AbiHSLKR (ORCPT ); Fri, 19 Aug 2022 07:10:17 -0400 Received: from mail-pl1-x62a.google.com (mail-pl1-x62a.google.com [IPv6:2607:f8b0:4864:20::62a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0BAB7FBA6A for ; Fri, 19 Aug 2022 04:10:16 -0700 (PDT) Received: by mail-pl1-x62a.google.com with SMTP id w14so3845967plp.9 for ; Fri, 19 Aug 2022 04:10:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=z6evWdl7qRpX717ycIDK2BtR5ifsL2gP87zXn8UQIMk=; b=J+XUAOeTv4KVFy0O5O6g70qCT4WkhMpYcqqI9RXS+Qe3vLZ5Qkp/eSH1z2s0TUNffl nQt7sRy2ReCywvyxYR4qiWfg8f6006Hzk0pg+ix1J1Ez8WPRVWExGSqEU1kZWZTQvo+H hHgA8OeyFUTAEpnkbcgAjEPhf+z0Iizn+nqxO+9rdFIc9efFoUMj9ceoX23MWoMhNe7Z va13J59UEvLTrogYbyTS6nHvBHbfwgbP5KfF6O36cGIkgZrRoURFczaQUlXm/oJoKLGs I/qAHYn1ys+w0U09MBltgBkEwL2WpKOQ4yOIihMiDa4W9GTN+XypwtGDo4zy9RnjMpyv cDSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=z6evWdl7qRpX717ycIDK2BtR5ifsL2gP87zXn8UQIMk=; b=7yOUWBLPR6ViT4HE/7FKE3mgWFPrwOBDNk2+8DxJYQOOiWuVkfnUxVwqcdb2z3+Cg5 kFYLPgiV8D4IX4g23pnQx80n49Xmg+X/Jy+TXbbbios0xUGRcxdyy6ZmLx+P42G/AsUr KyIuNMRNIMzGa5NLqKfWo2ClnpmUIv7RRNEtplRBedTF/MLF6E5gQEMoCFiE/kb/Mmtq HhHItlIsEKZBoxejtz2rFKpTBPSZRdN+/stccLVeRsrVZkW+qbPRMHkdqC4JdUykiFA1 Nu10SSD0NXHVAaOrdHPZjkBgZhM+st8FofN8Vw+fcXV8d567yaQNSuQLKDDAacYpOrDz BhLw== X-Gm-Message-State: ACgBeo2rePcpbAq3jG2kAG+r6mBGmXJ2Vyb67SdvFvbpOLhibNMRrH8a /hrHeJTH2zsoN7NbcEHrHuQ= X-Google-Smtp-Source: AA6agR7wAnLOGEGU2fMgNFFSibTKkGzmPbCDFhT9yiYtoWt3IKi8sOULrUTNZwGEUQxmWKaOWJcl3A== X-Received: by 2002:a17:90b:3511:b0:1f4:e0cd:1e04 with SMTP id ls17-20020a17090b351100b001f4e0cd1e04mr13839797pjb.154.1660907415600; Fri, 19 Aug 2022 04:10:15 -0700 (PDT) Received: from localhost.localdomain ([103.7.29.32]) by smtp.gmail.com with ESMTPSA id jd7-20020a170903260700b0016bfbd99f64sm2957778plb.118.2022.08.19.04.10.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Aug 2022 04:10:15 -0700 (PDT) From: Like Xu X-Google-Original-From: Like Xu To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org Subject: [kvm-unit-tests PATCH v3 10/13] x86/pmu: Update testcases to cover Intel Arch PMU Version 1 Date: Fri, 19 Aug 2022 19:09:36 +0800 Message-Id: <20220819110939.78013-11-likexu@tencent.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220819110939.78013-1-likexu@tencent.com> References: <20220819110939.78013-1-likexu@tencent.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Like Xu For most unit tests, the basic framework and use cases which test any PMU counter do not require any changes, except for two things: - No access to registers introduced only in PMU version 2 and above; - Expanded tolerance for testing counter overflows due to the loss of uniform control of the gloabl_ctrl register Adding some pmu_version() return value checks can seamlessly support Intel Arch PMU Version 1, while opening the door for AMD PMUs tests. Signed-off-by: Like Xu --- x86/pmu.c | 64 +++++++++++++++++++++++++++++++++++++------------------ 1 file changed, 43 insertions(+), 21 deletions(-) diff --git a/x86/pmu.c b/x86/pmu.c index 25fafbe..826472c 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -125,14 +125,19 @@ static struct pmu_event* get_counter_event(pmu_counter_t *cnt) static void global_enable(pmu_counter_t *cnt) { - cnt->idx = event_to_global_idx(cnt); + if (pmu_version() < 2) + return; + cnt->idx = event_to_global_idx(cnt); wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, rdmsr(MSR_CORE_PERF_GLOBAL_CTRL) | (1ull << cnt->idx)); } static void global_disable(pmu_counter_t *cnt) { + if (pmu_version() < 2) + return; + wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, rdmsr(MSR_CORE_PERF_GLOBAL_CTRL) & ~(1ull << cnt->idx)); } @@ -301,7 +306,10 @@ static void check_counter_overflow(void) count = cnt.count; /* clear status before test */ - wrmsr(MSR_CORE_PERF_GLOBAL_OVF_CTRL, rdmsr(MSR_CORE_PERF_GLOBAL_STATUS)); + if (pmu_version() > 1) { + wrmsr(MSR_CORE_PERF_GLOBAL_OVF_CTRL, + rdmsr(MSR_CORE_PERF_GLOBAL_STATUS)); + } report_prefix_push("overflow"); @@ -327,13 +335,21 @@ static void check_counter_overflow(void) cnt.config &= ~EVNTSEL_INT; idx = event_to_global_idx(&cnt); __measure(&cnt, cnt.count); - report(cnt.count == 1, "cntr-%d", i); + + report(check_irq() == (i % 2), "irq-%d", i); + if (pmu_version() > 1) + report(cnt.count == 1, "cntr-%d", i); + else + report(cnt.count < 4, "cntr-%d", i); + + if (pmu_version() < 2) + continue; + status = rdmsr(MSR_CORE_PERF_GLOBAL_STATUS); report(status & (1ull << idx), "status-%d", i); wrmsr(MSR_CORE_PERF_GLOBAL_OVF_CTRL, status); status = rdmsr(MSR_CORE_PERF_GLOBAL_STATUS); report(!(status & (1ull << idx)), "status clear-%d", i); - report(check_irq() == (i % 2), "irq-%d", i); } report_prefix_pop(); @@ -440,8 +456,10 @@ static void check_running_counter_wrmsr(void) report(evt.count < gp_events[1].min, "cntr"); /* clear status before overflow test */ - wrmsr(MSR_CORE_PERF_GLOBAL_OVF_CTRL, - rdmsr(MSR_CORE_PERF_GLOBAL_STATUS)); + if (pmu_version() > 1) { + wrmsr(MSR_CORE_PERF_GLOBAL_OVF_CTRL, + rdmsr(MSR_CORE_PERF_GLOBAL_STATUS)); + } start_event(&evt); @@ -453,8 +471,11 @@ static void check_running_counter_wrmsr(void) loop(); stop_event(&evt); - status = rdmsr(MSR_CORE_PERF_GLOBAL_STATUS); - report(status & 1, "status"); + + if (pmu_version() > 1) { + status = rdmsr(MSR_CORE_PERF_GLOBAL_STATUS); + report(status & 1, "status"); + } report_prefix_pop(); } @@ -474,8 +495,10 @@ static void check_emulated_instr(void) }; report_prefix_push("emulated instruction"); - wrmsr(MSR_CORE_PERF_GLOBAL_OVF_CTRL, - rdmsr(MSR_CORE_PERF_GLOBAL_STATUS)); + if (pmu_version() > 1) { + wrmsr(MSR_CORE_PERF_GLOBAL_OVF_CTRL, + rdmsr(MSR_CORE_PERF_GLOBAL_STATUS)); + } start_event(&brnch_cnt); start_event(&instr_cnt); @@ -509,7 +532,8 @@ static void check_emulated_instr(void) : : "eax", "ebx", "ecx", "edx"); - wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, 0); + if (pmu_version() > 1) + wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, 0); stop_event(&brnch_cnt); stop_event(&instr_cnt); @@ -520,10 +544,13 @@ static void check_emulated_instr(void) "instruction count"); report(brnch_cnt.count - brnch_start >= EXPECTED_BRNCH, "branch count"); - // Additionally check that those counters overflowed properly. - status = rdmsr(MSR_CORE_PERF_GLOBAL_STATUS); - report(status & 1, "instruction counter overflow"); - report(status & 2, "branch counter overflow"); + + if (pmu_version() > 1) { + // Additionally check that those counters overflowed properly. + status = rdmsr(MSR_CORE_PERF_GLOBAL_STATUS); + report(status & 1, "instruction counter overflow"); + report(status & 2, "branch counter overflow"); + } report_prefix_pop(); } @@ -647,12 +674,7 @@ int main(int ac, char **av) buf = malloc(N*64); if (!pmu_version()) { - report_skip("No pmu is detected!"); - return report_summary(); - } - - if (pmu_version() == 1) { - report_skip("PMU version 1 is not supported."); + report_skip("No Intel Arch PMU is detected!"); return report_summary(); } From patchwork Fri Aug 19 11:09:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Like Xu X-Patchwork-Id: 12948725 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6C703C32773 for ; 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Fri, 19 Aug 2022 04:10:16 -0700 (PDT) From: Like Xu X-Google-Original-From: Like Xu To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org Subject: [kvm-unit-tests PATCH v3 11/13] x86/pmu: Refine message when testing PMU on AMD platforms Date: Fri, 19 Aug 2022 19:09:37 +0800 Message-Id: <20220819110939.78013-12-likexu@tencent.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220819110939.78013-1-likexu@tencent.com> References: <20220819110939.78013-1-likexu@tencent.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Like Xu Add an Intel PMU detection step with a vendor prefix, and report SKIP naturally on unsupported AMD platforms. Signed-off-by: Like Xu --- x86/pmu.c | 25 ++++++++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-) diff --git a/x86/pmu.c b/x86/pmu.c index 826472c..b22f255 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -667,16 +667,35 @@ static void set_ref_cycle_expectations(void) gp_events[2].max = (gp_events[2].max * cnt.count) / tsc_delta; } +static bool detect_intel_pmu(void) +{ + if (!pmu_version()) { + report_skip("No Intel Arch PMU is detected!"); + return false; + } + + report_prefix_push("Intel"); + return true; +} + +static bool pmu_is_detected(void) +{ + if (!is_intel()) { + report_skip("AMD PMU is not supported."); + return false; + } + + return detect_intel_pmu(); +} + int main(int ac, char **av) { setup_vm(); handle_irq(PC_VECTOR, cnt_overflow); buf = malloc(N*64); - if (!pmu_version()) { - report_skip("No Intel Arch PMU is detected!"); + if (!pmu_is_detected()) return report_summary(); - } set_ref_cycle_expectations(); From patchwork Fri Aug 19 11:09:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Like Xu X-Patchwork-Id: 12948726 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AE4BBC32771 for ; Fri, 19 Aug 2022 11:10:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348740AbiHSLKW (ORCPT ); Fri, 19 Aug 2022 07:10:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33982 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348731AbiHSLKU (ORCPT ); Fri, 19 Aug 2022 07:10:20 -0400 Received: from mail-pj1-x102d.google.com (mail-pj1-x102d.google.com [IPv6:2607:f8b0:4864:20::102d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6AE83F4936 for ; Fri, 19 Aug 2022 04:10:19 -0700 (PDT) Received: by mail-pj1-x102d.google.com with SMTP id s31-20020a17090a2f2200b001faaf9d92easo7208469pjd.3 for ; Fri, 19 Aug 2022 04:10:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=KabTlyKzWR46PecaMYP6VWE+yqk+UVkCY71aNb5hRPE=; b=O69HxEELCoriQTXrZJpSJf2t49KXDxLOlvQtHIvGgTj/p65Uu3a4VNUF4StQAuVjY1 2JBW6S3eqRDhekx5P4H/K6chUKdXNApPeZgLJFoqmPv7MfYIxq/pn+3rp8uugsV0xBR5 8VLe/1DM0WVEp4pD/YEmZWuj3rXJ850uWejHPbPKz4Jy1MNCCFuNy4oObFpGhyT9DyaX GHPREJqjB51uEUtB3NxIkUjc/FaImQzIkMIbGl5vxiZzyrsYHNg8jyXJmGsf3l/fw29y wzLUuVo2Z1C8Zg3Ci6N7hcJVHF8KlZPXfbObqc6G60C5pKjZYOvms3tTyU1k4pkdsJuF D4mQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=KabTlyKzWR46PecaMYP6VWE+yqk+UVkCY71aNb5hRPE=; b=gp59H5RhsPFa0Uq9C/6cFNbIs0Z1hRTLegGF9H2bZN49nyNDeNp7um5gZO5x5ZtvXe TVQFpPmOSBG7QpEVmnHqyA1fxqCy5DAvB44YWFytOJhFepz+BFH0W5VUX/D05NV+nRND pGdQfo16Ib8hcj5P3tG99g9XMFHq2OrPsEoAXStCB4BBAIBAaImNHDHtyhhR86nDYT70 0SoHNGmEkMPmFlB8GDuCcSRL4kMcs4ZISl98zN7FbGwa+KylQj/G5nbO4lowy3/kRZ77 Mj81bJgqkYluZqMJQdHlQMA6arnIzZZtMwDbhWCBvOkgFOvyPqCw4n7DqXY1MS2tNuuI b2xQ== X-Gm-Message-State: ACgBeo1Y4HWyASmRegBFmIlU2L/VVl3PyUakH1t/CfzUAfH+5hEmDXAq EuNXNf3mZiumsm6FQx1cHYj33nC264qsAQ== X-Google-Smtp-Source: AA6agR5ge/9GGg8W946H0BK+pJwqsQmp5aWqC8ErjR3U4yInjpbGCOPvT5T9zAFetAEjY+syVYhC7Q== X-Received: by 2002:a17:902:7247:b0:16e:ecb2:4870 with SMTP id c7-20020a170902724700b0016eecb24870mr6862654pll.110.1660907418870; Fri, 19 Aug 2022 04:10:18 -0700 (PDT) Received: from localhost.localdomain ([103.7.29.32]) by smtp.gmail.com with ESMTPSA id jd7-20020a170903260700b0016bfbd99f64sm2957778plb.118.2022.08.19.04.10.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Aug 2022 04:10:18 -0700 (PDT) From: Like Xu X-Google-Original-From: Like Xu To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org Subject: [kvm-unit-tests PATCH v3 12/13] x86/pmu: Add assignment framework for Intel-specific HW resources Date: Fri, 19 Aug 2022 19:09:38 +0800 Message-Id: <20220819110939.78013-13-likexu@tencent.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220819110939.78013-1-likexu@tencent.com> References: <20220819110939.78013-1-likexu@tencent.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Like Xu This is a pre-requisite operation for adding AMD PMU tests. AMD and Intel PMU are different in counter registers, event selection registers, number of generic registers and generic hardware events. By introducing a set of global variables to facilitate assigning different values on different platforms. Signed-off-by: Like Xu Reviewed-by: Sandipan Das --- x86/pmu.c | 99 ++++++++++++++++++++++++++++++++----------------------- 1 file changed, 58 insertions(+), 41 deletions(-) diff --git a/x86/pmu.c b/x86/pmu.c index b22f255..0706cb1 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -50,7 +50,7 @@ struct pmu_event { uint32_t unit_sel; int min; int max; -} gp_events[] = { +} intel_gp_events[] = { {"core cycles", 0x003c, 1*N, 50*N}, {"instructions", 0x00c0, 10*N, 10.2*N}, {"ref cycles", 0x013c, 1*N, 30*N}, @@ -65,7 +65,13 @@ struct pmu_event { }; #define PMU_CAP_FW_WRITES (1ULL << 13) -static u64 gp_counter_base = MSR_IA32_PERFCTR0; +static u32 gp_counter_base; +static u32 gp_select_base; +static unsigned int gp_events_size; +static unsigned int nr_gp_counters; + +typedef struct pmu_event PMU_EVENTS_ARRAY_t[]; +static PMU_EVENTS_ARRAY_t *gp_events = NULL; char *buf; @@ -114,9 +120,9 @@ static struct pmu_event* get_counter_event(pmu_counter_t *cnt) if (is_gp(cnt)) { int i; - for (i = 0; i < sizeof(gp_events)/sizeof(gp_events[0]); i++) - if (gp_events[i].unit_sel == (cnt->config & 0xffff)) - return &gp_events[i]; + for (i = 0; i < gp_events_size; i++) + if ((*gp_events)[i].unit_sel == (cnt->config & 0xffff)) + return &(*gp_events)[i]; } else return &fixed_events[cnt->ctr - MSR_CORE_PERF_FIXED_CTR0]; @@ -142,12 +148,22 @@ static void global_disable(pmu_counter_t *cnt) ~(1ull << cnt->idx)); } +static inline uint32_t get_gp_counter_msr(unsigned int i) +{ + return gp_counter_base + i; +} + +static inline uint32_t get_gp_select_msr(unsigned int i) +{ + return gp_select_base + i; +} + static void __start_event(pmu_counter_t *evt, uint64_t count) { evt->count = count; wrmsr(evt->ctr, evt->count); if (is_gp(evt)) - wrmsr(MSR_P6_EVNTSEL0 + event_to_global_idx(evt), + wrmsr(get_gp_select_msr(event_to_global_idx(evt)), evt->config | EVNTSEL_EN); else { uint32_t ctrl = rdmsr(MSR_CORE_PERF_FIXED_CTR_CTRL); @@ -176,7 +192,7 @@ static void stop_event(pmu_counter_t *evt) { global_disable(evt); if (is_gp(evt)) - wrmsr(MSR_P6_EVNTSEL0 + event_to_global_idx(evt), + wrmsr(get_gp_select_msr(event_to_global_idx(evt)), evt->config & ~EVNTSEL_EN); else { uint32_t ctrl = rdmsr(MSR_CORE_PERF_FIXED_CTR_CTRL); @@ -222,14 +238,13 @@ static bool verify_counter(pmu_counter_t *cnt) static void check_gp_counter(struct pmu_event *evt) { - int nr_gp_counters = pmu_nr_gp_counters(); pmu_counter_t cnt = { - .ctr = gp_counter_base, .config = EVNTSEL_OS | EVNTSEL_USR | evt->unit_sel, }; int i; - for (i = 0; i < nr_gp_counters; i++, cnt.ctr++) { + for (i = 0; i < nr_gp_counters; i++) { + cnt.ctr = get_gp_counter_msr(i); measure_one(&cnt); report(verify_event(cnt.count, evt), "%s-%d", evt->name, i); } @@ -239,12 +254,11 @@ static void check_gp_counters(void) { int i; - for (i = 0; i < sizeof(gp_events)/sizeof(gp_events[0]); i++) + for (i = 0; i < gp_events_size; i++) if (pmu_gp_counter_is_available(i)) - check_gp_counter(&gp_events[i]); + check_gp_counter(&(*gp_events)[i]); else - printf("GP event '%s' is disabled\n", - gp_events[i].name); + printf("GP event '%s' is disabled\n", (*gp_events)[i].name); } static void check_fixed_counters(void) @@ -265,7 +279,6 @@ static void check_fixed_counters(void) static void check_counters_many(void) { int nr_fixed_counters = pmu_nr_fixed_counters(); - int nr_gp_counters = pmu_nr_gp_counters(); pmu_counter_t cnt[10]; int i, n; @@ -273,9 +286,8 @@ static void check_counters_many(void) if (!pmu_gp_counter_is_available(i)) continue; - cnt[n].ctr = gp_counter_base + n; - cnt[n].config = EVNTSEL_OS | EVNTSEL_USR | - gp_events[i % ARRAY_SIZE(gp_events)].unit_sel; + cnt[n].ctr = get_gp_counter_msr(n); + cnt[n].config = EVNTSEL_OS | EVNTSEL_USR | (*gp_events)[i % gp_events_size].unit_sel; n++; } for (i = 0; i < nr_fixed_counters; i++) { @@ -295,12 +307,11 @@ static void check_counters_many(void) static void check_counter_overflow(void) { - int nr_gp_counters = pmu_nr_gp_counters(); uint64_t count; int i; pmu_counter_t cnt = { .ctr = gp_counter_base, - .config = EVNTSEL_OS | EVNTSEL_USR | gp_events[1].unit_sel /* instructions */, + .config = EVNTSEL_OS | EVNTSEL_USR | (*gp_events)[1].unit_sel /* instructions */, }; __measure(&cnt, 0); count = cnt.count; @@ -313,10 +324,11 @@ static void check_counter_overflow(void) report_prefix_push("overflow"); - for (i = 0; i < nr_gp_counters + 1; i++, cnt.ctr++) { + for (i = 0; i < nr_gp_counters + 1; i++) { uint64_t status; int idx; + cnt.ctr = get_gp_counter_msr(i); cnt.count = 1 - count; if (gp_counter_base == MSR_IA32_PMC0) cnt.count &= (1ull << pmu_gp_counter_width()) - 1; @@ -359,11 +371,11 @@ static void check_gp_counter_cmask(void) { pmu_counter_t cnt = { .ctr = gp_counter_base, - .config = EVNTSEL_OS | EVNTSEL_USR | gp_events[1].unit_sel /* instructions */, + .config = EVNTSEL_OS | EVNTSEL_USR | (*gp_events)[1].unit_sel /* instructions */, }; cnt.config |= (0x2 << EVNTSEL_CMASK_SHIFT); measure_one(&cnt); - report(cnt.count < gp_events[1].min, "cmask"); + report(cnt.count < (*gp_events)[1].min, "cmask"); } static void do_rdpmc_fast(void *ptr) @@ -383,7 +395,6 @@ static void check_rdpmc(void) int fixed_counter_width = pmu_fixed_counter_width(); int nr_fixed_counters = pmu_nr_fixed_counters(); u8 gp_counter_width = pmu_gp_counter_width(); - int nr_gp_counters = pmu_nr_gp_counters(); uint64_t val = 0xff0123456789ull; bool exc; int i; @@ -393,7 +404,7 @@ static void check_rdpmc(void) for (i = 0; i < nr_gp_counters; i++) { uint64_t x; pmu_counter_t cnt = { - .ctr = gp_counter_base + i, + .ctr = get_gp_counter_msr(i), .idx = i }; @@ -409,7 +420,7 @@ static void check_rdpmc(void) /* Mask according to the number of supported bits */ x &= (1ull << gp_counter_width) - 1; - wrmsr(gp_counter_base + i, val); + wrmsr(get_gp_counter_msr(i), val); report(rdpmc(i) == x, "cntr-%d", i); exc = test_for_exception(GP_VECTOR, do_rdpmc_fast, &cnt); @@ -444,7 +455,7 @@ static void check_running_counter_wrmsr(void) uint64_t count; pmu_counter_t evt = { .ctr = gp_counter_base, - .config = EVNTSEL_OS | EVNTSEL_USR | gp_events[1].unit_sel, + .config = EVNTSEL_OS | EVNTSEL_USR | (*gp_events)[1].unit_sel, }; report_prefix_push("running counter wrmsr"); @@ -453,7 +464,7 @@ static void check_running_counter_wrmsr(void) loop(); wrmsr(gp_counter_base, 0); stop_event(&evt); - report(evt.count < gp_events[1].min, "cntr"); + report(evt.count < (*gp_events)[1].min, "cntr"); /* clear status before overflow test */ if (pmu_version() > 1) { @@ -483,15 +494,16 @@ static void check_running_counter_wrmsr(void) static void check_emulated_instr(void) { uint64_t status, instr_start, brnch_start; + unsigned int branch_idx = 5; pmu_counter_t brnch_cnt = { - .ctr = MSR_IA32_PERFCTR0, + .ctr = get_gp_counter_msr(0), /* branch instructions */ - .config = EVNTSEL_OS | EVNTSEL_USR | gp_events[5].unit_sel, + .config = EVNTSEL_OS | EVNTSEL_USR | (*gp_events)[branch_idx].unit_sel, }; pmu_counter_t instr_cnt = { - .ctr = MSR_IA32_PERFCTR0 + 1, + .ctr = get_gp_counter_msr(1), /* instructions */ - .config = EVNTSEL_OS | EVNTSEL_USR | gp_events[1].unit_sel, + .config = EVNTSEL_OS | EVNTSEL_USR | intel_gp_events[1].unit_sel, }; report_prefix_push("emulated instruction"); @@ -505,8 +517,8 @@ static void check_emulated_instr(void) brnch_start = -EXPECTED_BRNCH; instr_start = -EXPECTED_INSTR; - wrmsr(MSR_IA32_PERFCTR0, brnch_start); - wrmsr(MSR_IA32_PERFCTR0 + 1, instr_start); + wrmsr(get_gp_counter_msr(0), brnch_start); + wrmsr(get_gp_counter_msr(1), instr_start); // KVM_FEP is a magic prefix that forces emulation so // 'KVM_FEP "jne label\n"' just counts as a single instruction. asm volatile( @@ -579,7 +591,6 @@ static void check_gp_counters_write_width(void) u64 val_64 = 0xffffff0123456789ull; u64 val_32 = val_64 & ((1ull << 32) - 1); u64 val_max_width = val_64 & ((1ull << pmu_gp_counter_width()) - 1); - int nr_gp_counters = pmu_nr_gp_counters(); int i; /* @@ -627,14 +638,14 @@ static void check_gp_counters_write_width(void) static void set_ref_cycle_expectations(void) { pmu_counter_t cnt = { - .ctr = MSR_IA32_PERFCTR0, - .config = EVNTSEL_OS | EVNTSEL_USR | gp_events[2].unit_sel, + .ctr = get_gp_counter_msr(0), + .config = EVNTSEL_OS | EVNTSEL_USR | intel_gp_events[2].unit_sel, }; uint64_t tsc_delta; uint64_t t0, t1, t2, t3; /* Bit 2 enumerates the availability of reference cycles events. */ - if (!pmu_nr_gp_counters() || !pmu_gp_counter_is_available(2)) + if (!nr_gp_counters || !pmu_gp_counter_is_available(2)) return; wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, 0); @@ -663,8 +674,8 @@ static void set_ref_cycle_expectations(void) if (!tsc_delta) return; - gp_events[2].min = (gp_events[2].min * cnt.count) / tsc_delta; - gp_events[2].max = (gp_events[2].max * cnt.count) / tsc_delta; + intel_gp_events[2].min = (intel_gp_events[2].min * cnt.count) / tsc_delta; + intel_gp_events[2].max = (intel_gp_events[2].max * cnt.count) / tsc_delta; } static bool detect_intel_pmu(void) @@ -674,6 +685,12 @@ static bool detect_intel_pmu(void) return false; } + nr_gp_counters = pmu_nr_gp_counters(); + gp_events_size = sizeof(intel_gp_events)/sizeof(intel_gp_events[0]); + gp_events = (PMU_EVENTS_ARRAY_t *)intel_gp_events; + gp_counter_base = MSR_IA32_PERFCTR0; + gp_select_base = MSR_P6_EVNTSEL0; + report_prefix_push("Intel"); return true; } @@ -700,7 +717,7 @@ int main(int ac, char **av) set_ref_cycle_expectations(); printf("PMU version: %d\n", pmu_version()); - printf("GP counters: %d\n", pmu_nr_gp_counters()); + printf("GP counters: %d\n", nr_gp_counters); printf("GP counter width: %d\n", pmu_gp_counter_width()); printf("Mask length: %d\n", pmu_gp_counter_mask_length()); printf("Fixed counters: %d\n", pmu_nr_fixed_counters()); From patchwork Fri Aug 19 11:09:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Like Xu X-Patchwork-Id: 12948727 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 88208C32772 for ; Fri, 19 Aug 2022 11:10:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348743AbiHSLKX (ORCPT ); Fri, 19 Aug 2022 07:10:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34018 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348739AbiHSLKW (ORCPT ); Fri, 19 Aug 2022 07:10:22 -0400 Received: from mail-pj1-x102f.google.com (mail-pj1-x102f.google.com [IPv6:2607:f8b0:4864:20::102f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8596CFBA7C for ; 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All above differences are instantiated at the detection step, and it also covers the K7 PMU registers, which is consistent with bare-metal. Signed-off-by: Like Xu Reviewed-by: Sandipan Das --- lib/x86/msr.h | 17 ++++++++++++ lib/x86/processor.h | 32 ++++++++++++++++++++-- x86/pmu.c | 67 ++++++++++++++++++++++++++++++++++++++++----- 3 files changed, 106 insertions(+), 10 deletions(-) diff --git a/lib/x86/msr.h b/lib/x86/msr.h index 252e041..5f16a58 100644 --- a/lib/x86/msr.h +++ b/lib/x86/msr.h @@ -130,6 +130,23 @@ #define MSR_AMD64_IBSDCPHYSAD 0xc0011039 #define MSR_AMD64_IBSCTL 0xc001103a +/* Fam 15h MSRs */ +#define MSR_F15H_PERF_CTL 0xc0010200 +#define MSR_F15H_PERF_CTL0 MSR_F15H_PERF_CTL +#define MSR_F15H_PERF_CTL1 (MSR_F15H_PERF_CTL + 2) +#define MSR_F15H_PERF_CTL2 (MSR_F15H_PERF_CTL + 4) +#define MSR_F15H_PERF_CTL3 (MSR_F15H_PERF_CTL + 6) +#define MSR_F15H_PERF_CTL4 (MSR_F15H_PERF_CTL + 8) +#define MSR_F15H_PERF_CTL5 (MSR_F15H_PERF_CTL + 10) + +#define MSR_F15H_PERF_CTR 0xc0010201 +#define MSR_F15H_PERF_CTR0 MSR_F15H_PERF_CTR +#define MSR_F15H_PERF_CTR1 (MSR_F15H_PERF_CTR + 2) +#define MSR_F15H_PERF_CTR2 (MSR_F15H_PERF_CTR + 4) +#define MSR_F15H_PERF_CTR3 (MSR_F15H_PERF_CTR + 6) +#define MSR_F15H_PERF_CTR4 (MSR_F15H_PERF_CTR + 8) +#define MSR_F15H_PERF_CTR5 (MSR_F15H_PERF_CTR + 10) + /* Fam 10h MSRs */ #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 #define FAM10H_MMIO_CONF_ENABLE (1<<0) diff --git a/lib/x86/processor.h b/lib/x86/processor.h index 0324220..10bca27 100644 --- a/lib/x86/processor.h +++ b/lib/x86/processor.h @@ -793,6 +793,9 @@ static inline void flush_tlb(void) static inline u8 pmu_version(void) { + if (!is_intel()) + return 0; + return cpuid(10).a & 0xff; } @@ -806,19 +809,39 @@ static inline bool this_cpu_has_perf_global_ctrl(void) return pmu_version() > 1; } +#define AMD64_NUM_COUNTERS 4 +#define AMD64_NUM_COUNTERS_CORE 6 + +static inline bool has_amd_perfctr_core(void) +{ + return cpuid(0x80000001).c & BIT_ULL(23); +} + static inline u8 pmu_nr_gp_counters(void) { - return (cpuid(10).a >> 8) & 0xff; + if (is_intel()) { + return (cpuid(10).a >> 8) & 0xff; + } else if (!has_amd_perfctr_core()) { + return AMD64_NUM_COUNTERS; + } + + return AMD64_NUM_COUNTERS_CORE; } static inline u8 pmu_gp_counter_width(void) { - return (cpuid(10).a >> 16) & 0xff; + if (is_intel()) + return (cpuid(10).a >> 16) & 0xff; + else + return 48; } static inline u8 pmu_gp_counter_mask_length(void) { - return (cpuid(10).a >> 24) & 0xff; + if (is_intel()) + return (cpuid(10).a >> 24) & 0xff; + else + return pmu_nr_gp_counters(); } static inline u8 pmu_nr_fixed_counters(void) @@ -843,6 +866,9 @@ static inline u8 pmu_fixed_counter_width(void) static inline bool pmu_gp_counter_is_available(int i) { + if (!is_intel()) + return i < pmu_nr_gp_counters(); + /* CPUID.0xA.EBX bit is '1 if they counter is NOT available. */ return !(cpuid(10).b & BIT(i)); } diff --git a/x86/pmu.c b/x86/pmu.c index 0706cb1..b6ab10c 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -62,6 +62,11 @@ struct pmu_event { {"fixed 1", MSR_CORE_PERF_FIXED_CTR0, 10*N, 10.2*N}, {"fixed 2", MSR_CORE_PERF_FIXED_CTR0 + 1, 1*N, 30*N}, {"fixed 3", MSR_CORE_PERF_FIXED_CTR0 + 2, 0.1*N, 30*N} +}, amd_gp_events[] = { + {"core cycles", 0x0076, 1*N, 50*N}, + {"instructions", 0x00c0, 10*N, 10.2*N}, + {"branches", 0x00c2, 1*N, 1.1*N}, + {"branch misses", 0x00c3, 0, 0.1*N}, }; #define PMU_CAP_FW_WRITES (1ULL << 13) @@ -105,14 +110,24 @@ static bool check_irq(void) static bool is_gp(pmu_counter_t *evt) { + if (!is_intel()) + return true; + return evt->ctr < MSR_CORE_PERF_FIXED_CTR0 || evt->ctr >= MSR_IA32_PMC0; } static int event_to_global_idx(pmu_counter_t *cnt) { - return cnt->ctr - (is_gp(cnt) ? gp_counter_base : - (MSR_CORE_PERF_FIXED_CTR0 - FIXED_CNT_INDEX)); + if (is_intel()) + return cnt->ctr - (is_gp(cnt) ? gp_counter_base : + (MSR_CORE_PERF_FIXED_CTR0 - FIXED_CNT_INDEX)); + + if (gp_counter_base == MSR_F15H_PERF_CTR0) { + return (cnt->ctr - gp_counter_base) / 2; + } else { + return cnt->ctr - gp_counter_base; + } } static struct pmu_event* get_counter_event(pmu_counter_t *cnt) @@ -150,11 +165,17 @@ static void global_disable(pmu_counter_t *cnt) static inline uint32_t get_gp_counter_msr(unsigned int i) { + if (gp_counter_base == MSR_F15H_PERF_CTR0) + return gp_counter_base + 2 * i; + return gp_counter_base + i; } static inline uint32_t get_gp_select_msr(unsigned int i) { + if (gp_select_base == MSR_F15H_PERF_CTL0) + return gp_select_base + 2 * i; + return gp_select_base + i; } @@ -334,6 +355,9 @@ static void check_counter_overflow(void) cnt.count &= (1ull << pmu_gp_counter_width()) - 1; if (i == nr_gp_counters) { + if (!is_intel()) + break; + cnt.ctr = fixed_events[0].unit_sel; __measure(&cnt, 0); count = cnt.count; @@ -494,7 +518,7 @@ static void check_running_counter_wrmsr(void) static void check_emulated_instr(void) { uint64_t status, instr_start, brnch_start; - unsigned int branch_idx = 5; + unsigned int branch_idx = is_intel() ? 5 : 2; pmu_counter_t brnch_cnt = { .ctr = get_gp_counter_msr(0), /* branch instructions */ @@ -695,13 +719,35 @@ static bool detect_intel_pmu(void) return true; } -static bool pmu_is_detected(void) +static void amd_switch_to_non_perfctr_core(void) { - if (!is_intel()) { - report_skip("AMD PMU is not supported."); + gp_counter_base = MSR_K7_PERFCTR0; + gp_select_base = MSR_K7_EVNTSEL0; + nr_gp_counters = AMD64_NUM_COUNTERS; +} + +static bool detect_amd_pmu(void) +{ + if (!has_amd_perfctr_core()) { + report_skip("Missing perfctr_core, unsupported AMD PMU."); return false; } + nr_gp_counters = pmu_nr_gp_counters(); + gp_events_size = sizeof(amd_gp_events)/sizeof(amd_gp_events[0]); + gp_events = (PMU_EVENTS_ARRAY_t *)amd_gp_events; + gp_counter_base = MSR_F15H_PERF_CTR0; + gp_select_base = MSR_F15H_PERF_CTL0; + + report_prefix_push("AMD"); + return true; +} + +static bool pmu_is_detected(void) +{ + if (!is_intel()) + return detect_amd_pmu(); + return detect_intel_pmu(); } @@ -714,7 +760,8 @@ int main(int ac, char **av) if (!pmu_is_detected()) return report_summary(); - set_ref_cycle_expectations(); + if (is_intel()) + set_ref_cycle_expectations(); printf("PMU version: %d\n", pmu_version()); printf("GP counters: %d\n", nr_gp_counters); @@ -736,5 +783,11 @@ int main(int ac, char **av) report_prefix_pop(); } + if (!is_intel()) { + report_prefix_push("K7"); + amd_switch_to_non_perfctr_core(); + check_counters(); + } + return report_summary(); }