From patchwork Fri Aug 19 19:07:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Apurva Nandan X-Patchwork-Id: 12949108 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5134EC32771 for ; Fri, 19 Aug 2022 19:09:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Fri, 19 Aug 2022 14:07:36 -0500 From: Apurva Nandan To: Nishanth Menon , Tero Kristo , Santosh Shilimkar , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Ulf Hansson , , , , CC: Apurva Nandan , Hari Nagalla Subject: [PATCH 1/3] dt-bindings: irqchip: ti,sci-inta: Fix warning '#interrupt-cells' was unexpected Date: Sat, 20 Aug 2022 00:37:27 +0530 Message-ID: <20220819190729.32358-2-a-nandan@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220819190729.32358-1-a-nandan@ti.com> References: <20220819190729.32358-1-a-nandan@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220819_120756_870878_462C013C X-CRM114-Status: GOOD ( 10.56 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org #interrupt-cells = <0> property is required in device tree for ti,sci-inta nodes, or else we will have following warning when building device tree files with W=2 warning level. arch/arm64/boot/dts/ti/k3-j721e-main.dtsi:147.51-156.5: Warning (interrupt_provider): /bus@100000/main-navss/interrupt-controller@33d00000: Missing #interrupt-cells in interrupt provider And further, #interrupt-cells is required to be in yaml bindings as well to prevent following schema warnings: k3-j721e-common-proc-board.dtb: interrupt-controller@33d00000: Unevaluated properties are not allowed ('#interrupt-cells' was unexpected) From schema: linux/Documentation/devicetree/bindings/interrupt-controller/ti,sci-inta.yaml Add #interrupt-cells property in ti,sci-inta.yaml Signed-off-by: Apurva Nandan Acked-by: Rob Herring --- .../devicetree/bindings/interrupt-controller/ti,sci-inta.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/ti,sci-inta.yaml b/Documentation/devicetree/bindings/interrupt-controller/ti,sci-inta.yaml index 88c46e61732e..1151518859bd 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/ti,sci-inta.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/ti,sci-inta.yaml @@ -59,6 +59,9 @@ properties: interrupt-controller: true + '#interrupt-cells': + const: 0 + msi-controller: true ti,interrupt-ranges: From patchwork Fri Aug 19 19:07:28 2022 Content-Type: text/plain; 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Fri, 19 Aug 2022 14:07:41 -0500 From: Apurva Nandan To: Nishanth Menon , Tero Kristo , Santosh Shilimkar , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Ulf Hansson , , , , CC: Apurva Nandan , Hari Nagalla Subject: [PATCH 2/3] dt-bindings: mmc: Fix 'dma-coherent' was unexpected Date: Sat, 20 Aug 2022 00:37:28 +0530 Message-ID: <20220819190729.32358-3-a-nandan@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220819190729.32358-1-a-nandan@ti.com> References: <20220819190729.32358-1-a-nandan@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220819_120759_895509_33347FDF X-CRM114-Status: GOOD ( 10.25 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org dma-coherent is mentioned in almost all TI K3 platform mmc nodes. Fix warning generated due to its missing match in yaml schema. Signed-off-by: Apurva Nandan Acked-by: Rob Herring --- Documentation/devicetree/bindings/mmc/sdhci-am654.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/sdhci-am654.yaml b/Documentation/devicetree/bindings/mmc/sdhci-am654.yaml index 0ab07759b472..ea9121fb188d 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-am654.yaml +++ b/Documentation/devicetree/bindings/mmc/sdhci-am654.yaml @@ -51,6 +51,9 @@ properties: sdhci-caps-mask: true + dma-coherent: + type: boolean + # PHY output tap delays: # Used to delay the data valid window and align it to the sampling clock. # Binding needs to be provided for each supported speed mode otherwise the From patchwork Fri Aug 19 19:07:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Apurva Nandan X-Patchwork-Id: 12949109 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4239DC32773 for ; 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Fri, 19 Aug 2022 14:07:51 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Fri, 19 Aug 2022 14:07:51 -0500 Received: from LT5CD112GSQZ.ent.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 27JJ7T2v051038; Fri, 19 Aug 2022 14:07:46 -0500 From: Apurva Nandan To: Nishanth Menon , Tero Kristo , Santosh Shilimkar , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Ulf Hansson , , , , CC: Apurva Nandan , Hari Nagalla Subject: [PATCH 3/3] dt-bindings: interrupt-controller: Fix 'reg' was unexpected Date: Sat, 20 Aug 2022 00:37:29 +0530 Message-ID: <20220819190729.32358-4-a-nandan@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220819190729.32358-1-a-nandan@ti.com> References: <20220819190729.32358-1-a-nandan@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220819_120756_872221_A153E151 X-CRM114-Status: GOOD ( 10.19 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Fix the following warning in dtbs_check interrupt-controller@a00000: Unevaluated properties are not allowed ('reg' was unexpected) Add the reg property in the schema. Signed-off-by: Apurva Nandan Acked-by: Rob Herring --- .../devicetree/bindings/interrupt-controller/ti,sci-intr.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.yaml b/Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.yaml index e12aee42b126..c99cc7323c71 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.yaml @@ -58,6 +58,9 @@ properties: 1 = If intr supports edge triggered interrupts. 4 = If intr supports level triggered interrupts. + reg: + maxItems: 1 + interrupt-controller: true '#interrupt-cells':