From patchwork Sat Aug 20 00:58:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Srivatsa, Anusha" X-Patchwork-Id: 12949434 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 87623C28D13 for ; Sat, 20 Aug 2022 00:59:42 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2F5A410E21D; Sat, 20 Aug 2022 00:59:08 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0F36A10E1B4 for ; Sat, 20 Aug 2022 00:58:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660957132; x=1692493132; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=UOl+49n5Qmi8ob24TZ7/DgtBDbGCrStlTFZ7GXWyWZw=; b=QZqOriESy4RujoTmOvFIEHOWJgmxF6wvA6rqbXX3YnqJewB+fdDYIFSQ XSNDXgwU20zUvrekaEZdcj+9V9imnKaXPPo2s7LhThVsX6HKJTFjqJk+M yXa6IORj2BjAkTySpFxRcQld+vVUI5gjPaeWHLhjkgs8tUvTwtVdztSSM YWyRHZ4JcKy0l3IeRj9GQG8c44c+eIyq6n9RcSFosZdy5H6bkKczK0NvK dEns1mt+OKIGIHqcj1CW2Lw3s0V7ddxPzTkZmMaawbyIRCWJ3CT8K8UPO fsUyga4iNaX0tgXhfW5UOY+05UzAJOwZSrDndBaWyRLGcS3+W2mWe7lfu g==; X-IronPort-AV: E=McAfee;i="6500,9779,10444"; a="294411877" X-IronPort-AV: E=Sophos;i="5.93,249,1654585200"; d="scan'208";a="294411877" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Aug 2022 17:58:51 -0700 X-IronPort-AV: E=Sophos;i="5.93,249,1654585200"; d="scan'208";a="676626670" Received: from cdhirema-mobl.amr.corp.intel.com (HELO anushasr-mobl7.intel.com) ([10.212.188.51]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Aug 2022 17:58:50 -0700 From: Anusha Srivatsa To: intel-gfx@lists.freedesktop.org Date: Fri, 19 Aug 2022 17:58:19 -0700 Message-Id: <20220820005822.102716-2-anusha.srivatsa@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220820005822.102716-1-anusha.srivatsa@intel.com> References: <20220820005822.102716-1-anusha.srivatsa@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 1/4] drm/i915/display: Add CDCLK actions to intel_cdclk_state X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" This is a prep patch for what the rest of the series does. Add existing actions that change cdclk - squash, crawl, modeset to intel_cdclk_state so we have access to the cdclk values that are in transition. Cc: Jani Nikula Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/display/intel_cdclk.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h index b535cf6a7d9e..43835688ee02 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.h +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h @@ -15,6 +15,14 @@ struct drm_i915_private; struct intel_atomic_state; struct intel_crtc_state; +enum cdclk_actions { + INTEL_CDCLK_MODESET = 0, + INTEL_CDCLK_SQUASH, + INTEL_CDCLK_CRAWL, + INTEL_CDCLK_NOOP, + MAX_CDCLK_ACTIONS +}; + struct intel_cdclk_config { unsigned int cdclk, vco, ref, bypass; u8 voltage_level; @@ -51,6 +59,11 @@ struct intel_cdclk_state { /* bitmask of active pipes */ u8 active_pipes; + + struct cdclk_step { + enum cdclk_actions action; + u32 cdclk; + } steps[MAX_CDCLK_ACTIONS]; }; int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state); From patchwork Sat Aug 20 00:58:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Srivatsa, Anusha" X-Patchwork-Id: 12949436 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BED13C32792 for ; Sat, 20 Aug 2022 01:00:21 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C9A4310E1E6; Sat, 20 Aug 2022 00:59:06 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id E38DB10E133 for ; Sat, 20 Aug 2022 00:58:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660957132; x=1692493132; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=bIjhQJ4AiVU048aV2nF5bQLq4TudkwoQtvweyz2Zr54=; b=Qt3u9o7ajpQlAz5tMN2ObBAxKr7IW74NKKQq14RvN8zimYqGdG+XqUJF wffa/OaPItsoS0BHo1TEwOrqyMsV9SGmeRnSQPicO0r7JXIGZAVQOJswe tz7WWSbpnZ8fhAgGGr/QSyB1bTGVdIjV9LlTRNmSG2bB5WS+KxY5Xrfqa WPW1iqa45r3cwA9h5cYjEMLuHd1iIMfH+YV3GwEGOEx2YIOHFaS4FS+x/ ScrJbI9svcQZA9vMGQNdMvCps/DrYlVyTUju94+b5lgTtwz9RFYOP8ZSQ v7xCT+VltgdMDxIIYiy+7vrmZDLup/W56/Eduxt6+XH940F/IJdlUG2Ez A==; X-IronPort-AV: E=McAfee;i="6500,9779,10444"; a="294411881" X-IronPort-AV: E=Sophos;i="5.93,249,1654585200"; d="scan'208";a="294411881" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Aug 2022 17:58:52 -0700 X-IronPort-AV: E=Sophos;i="5.93,249,1654585200"; d="scan'208";a="676626678" Received: from cdhirema-mobl.amr.corp.intel.com (HELO anushasr-mobl7.intel.com) ([10.212.188.51]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Aug 2022 17:58:51 -0700 From: Anusha Srivatsa To: intel-gfx@lists.freedesktop.org Date: Fri, 19 Aug 2022 17:58:20 -0700 Message-Id: <20220820005822.102716-3-anusha.srivatsa@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220820005822.102716-1-anusha.srivatsa@intel.com> References: <20220820005822.102716-1-anusha.srivatsa@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 2/4] drm/i915/squash: s/intel_cdclk_can_squash/intel_cdclk_squash X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Apart from checking if squashing can be performed, accommodate accessing in-flight cdclk state for any changes that are needed during commit phase. v2: Move squashing bits to switch case.(Anusha) Cc: Jani Nikula Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/display/intel_cdclk.c | 62 ++++++++++++++-------- 1 file changed, 40 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 86a22c3766e5..f98fd48fe905 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -1693,12 +1693,18 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, const struct intel_cdclk_config *cdclk_config, enum pipe pipe) { + struct intel_cdclk_state *cdclk_state = to_intel_cdclk_state(dev_priv->cdclk.obj.state); + struct intel_atomic_state *state = cdclk_state->base.state; + struct intel_cdclk_state *new_cdclk_state = intel_atomic_get_new_cdclk_state(state); + struct cdclk_step *cdclk_steps = new_cdclk_state->steps; int cdclk = cdclk_config->cdclk; int vco = cdclk_config->vco; + u32 squash_ctl = 0; u32 val; u16 waveform; int clock; int ret; + int i; /* Inform power controller of upcoming frequency change. */ if (DISPLAY_VER(dev_priv) >= 11) @@ -1742,21 +1748,27 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, waveform = cdclk_squash_waveform(dev_priv, cdclk); - if (waveform) + if (waveform && has_cdclk_squasher(dev_priv)) { clock = vco / 2; - else + for (i = 0; i < MAX_CDCLK_ACTIONS; i++) { + switch (cdclk_steps[i].action) { + case INTEL_CDCLK_SQUASH: + waveform = cdclk_squash_waveform(dev_priv, cdclk_steps[i].cdclk); + squash_ctl = CDCLK_SQUASH_ENABLE | + CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform; + intel_de_write(dev_priv, CDCLK_SQUASH_CTL, squash_ctl); + break; + case INTEL_CDCLK_NOOP: + case INTEL_CDCLK_CRAWL: + case INTEL_CDCLK_MODESET: + break; + default: + break; + } + } + } else clock = cdclk; - if (has_cdclk_squasher(dev_priv)) { - u32 squash_ctl = 0; - - if (waveform) - squash_ctl = CDCLK_SQUASH_ENABLE | - CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform; - - intel_de_write(dev_priv, CDCLK_SQUASH_CTL, squash_ctl); - } - val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) | bxt_cdclk_cd2x_pipe(dev_priv, pipe) | skl_cdclk_decimal(cdclk); @@ -1966,10 +1978,11 @@ static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv, a->ref == b->ref; } -static bool intel_cdclk_can_squash(struct drm_i915_private *dev_priv, - const struct intel_cdclk_config *a, - const struct intel_cdclk_config *b) +static bool intel_cdclk_squash(struct drm_i915_private *dev_priv, + const struct intel_cdclk_state *a, + struct intel_cdclk_state *b) { + struct cdclk_step *cdclk_transition = b->steps; /* * FIXME should store a bit more state in intel_cdclk_config * to differentiate squasher vs. cd2x divider properly. For @@ -1978,11 +1991,16 @@ static bool intel_cdclk_can_squash(struct drm_i915_private *dev_priv, */ if (!has_cdclk_squasher(dev_priv)) return false; + + cdclk_transition[0].action = INTEL_CDCLK_SQUASH; + cdclk_transition[0].cdclk = b->actual.cdclk; + cdclk_transition[1].action = INTEL_CDCLK_NOOP; + cdclk_transition[1].cdclk = b->actual.cdclk; - return a->cdclk != b->cdclk && - a->vco != 0 && - a->vco == b->vco && - a->ref == b->ref; + return a->actual.cdclk != b->actual.cdclk && + a->actual.vco != 0 && + a->actual.vco == b->actual.vco && + a->actual.ref == b->actual.ref; } /** @@ -2758,9 +2776,9 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state) pipe = INVALID_PIPE; } - if (intel_cdclk_can_squash(dev_priv, - &old_cdclk_state->actual, - &new_cdclk_state->actual)) { + if (intel_cdclk_squash(dev_priv, + old_cdclk_state, + new_cdclk_state)) { drm_dbg_kms(&dev_priv->drm, "Can change cdclk via squasher\n"); } else if (intel_cdclk_can_crawl(dev_priv, From patchwork Sat Aug 20 00:58:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Srivatsa, Anusha" X-Patchwork-Id: 12949437 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 24C06C28D13 for ; Sat, 20 Aug 2022 01:00:31 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8BB0510E1B6; Sat, 20 Aug 2022 00:59:02 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id A83A410E1B6 for ; Sat, 20 Aug 2022 00:58:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660957133; x=1692493133; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=mqyh4pO45SkTximprPm8fk6cUJa+0pHIMLoEcCC1ev4=; b=GQ9B3RFvXwHqWzVX/N7MTz+z+j6G0JjxS3GZxjnZUzNExcSLg8Z9BBC0 dH7nF4AzTpaFuPkewa4kq8+ldEcXbwtgpdFsebVQH7Beyjavtfln3/J0e z4/mNIkmqxIVPYHZJ1XkOZP1suX7mOhHR7vDUUYy0NM5xgYK1QdEINHQ6 tv0/rxQVtcXBu1dx1f83fPXRxTujYpOXJpQ4xAZjkMroDTZDEg2adwksE aGPhdT+LBgTUtkd07Ak346ySItPPclRA95UHCwBZ6Rzo4Rv4BV4AME8Hk OZG/NFoCSqshjWdn4zpJleL9bS9ipfJcceX8TeXiqhK+DqR5ZTErZjRsh Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10444"; a="294411886" X-IronPort-AV: E=Sophos;i="5.93,249,1654585200"; d="scan'208";a="294411886" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Aug 2022 17:58:53 -0700 X-IronPort-AV: E=Sophos;i="5.93,249,1654585200"; d="scan'208";a="676626681" Received: from cdhirema-mobl.amr.corp.intel.com (HELO anushasr-mobl7.intel.com) ([10.212.188.51]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Aug 2022 17:58:52 -0700 From: Anusha Srivatsa To: intel-gfx@lists.freedesktop.org Date: Fri, 19 Aug 2022 17:58:21 -0700 Message-Id: <20220820005822.102716-4-anusha.srivatsa@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220820005822.102716-1-anusha.srivatsa@intel.com> References: <20220820005822.102716-1-anusha.srivatsa@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 3/4] drm/i915/display: s/intel_cdclk_can_crawl/intel_cdclk_crawl X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Apart from checking if crawling can be performed, accommodate accessing in-flight cdclk state for any changes that are needed during commit phase. v2: Move crawling steps to a switch case (anusha) Cc: Matt Roper Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/display/intel_cdclk.c | 45 +++++++++++++--------- 1 file changed, 26 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index f98fd48fe905..7bba10635c5e 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -38,6 +38,7 @@ #include "intel_psr.h" #include "vlv_sideband.h" +#define ADLP_CDCLK_CRAWL(dev_priv, vco) (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->cdclk.hw.vco > 0 && vco > 0) /** * DOC: CDCLK / RAWCLK * @@ -1727,10 +1728,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, return; } - if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->cdclk.hw.vco > 0 && vco > 0) { - if (dev_priv->cdclk.hw.vco != vco) - adlp_cdclk_pll_crawl(dev_priv, vco); - } else if (DISPLAY_VER(dev_priv) >= 11) { + if (!ADLP_CDCLK_CRAWL(dev_priv, vco) && DISPLAY_VER(dev_priv) >= 11) { if (dev_priv->cdclk.hw.vco != 0 && dev_priv->cdclk.hw.vco != vco) icl_cdclk_pll_disable(dev_priv); @@ -1748,18 +1746,21 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, waveform = cdclk_squash_waveform(dev_priv, cdclk); - if (waveform && has_cdclk_squasher(dev_priv)) { - clock = vco / 2; + if ((waveform && has_cdclk_squasher(dev_priv)) || ADLP_CDCLK_CRAWL(dev_priv, vco)) { for (i = 0; i < MAX_CDCLK_ACTIONS; i++) { switch (cdclk_steps[i].action) { + case INTEL_CDCLK_CRAWL: + adlp_cdclk_pll_crawl(dev_priv, vco); + clock = cdclk; + break; case INTEL_CDCLK_SQUASH: waveform = cdclk_squash_waveform(dev_priv, cdclk_steps[i].cdclk); squash_ctl = CDCLK_SQUASH_ENABLE | CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform; intel_de_write(dev_priv, CDCLK_SQUASH_CTL, squash_ctl); + clock = vco / 2; break; case INTEL_CDCLK_NOOP: - case INTEL_CDCLK_CRAWL: case INTEL_CDCLK_MODESET: break; default: @@ -1956,10 +1957,11 @@ void intel_cdclk_uninit_hw(struct drm_i915_private *i915) skl_cdclk_uninit_hw(i915); } -static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv, - const struct intel_cdclk_config *a, - const struct intel_cdclk_config *b) +static bool intel_cdclk_crawl(struct drm_i915_private *dev_priv, + const struct intel_cdclk_state *a, + struct intel_cdclk_state *b) { + struct cdclk_step *cdclk_transition = b->steps; int a_div, b_div; if (!HAS_CDCLK_CRAWL(dev_priv)) @@ -1969,13 +1971,18 @@ static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv, * The vco and cd2x divider will change independently * from each, so we disallow cd2x change when crawling. */ - a_div = DIV_ROUND_CLOSEST(a->vco, a->cdclk); - b_div = DIV_ROUND_CLOSEST(b->vco, b->cdclk); + a_div = DIV_ROUND_CLOSEST(a->actual.vco, a->actual.cdclk); + b_div = DIV_ROUND_CLOSEST(b->actual.vco, b->actual.cdclk); - return a->vco != 0 && b->vco != 0 && - a->vco != b->vco && - a_div == b_div && - a->ref == b->ref; + cdclk_transition[0].action = INTEL_CDCLK_CRAWL; + cdclk_transition[0].cdclk = b->actual.cdclk; + cdclk_transition[1].action = INTEL_CDCLK_NOOP; + cdclk_transition[1].cdclk = b->actual.cdclk; + + return a->actual.vco != 0 && b->actual.vco != 0 && + a->actual.vco != b->actual.vco && + a_div == b_div && + a->actual.ref == b->actual.ref; } static bool intel_cdclk_squash(struct drm_i915_private *dev_priv, @@ -2781,9 +2788,9 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state) new_cdclk_state)) { drm_dbg_kms(&dev_priv->drm, "Can change cdclk via squasher\n"); - } else if (intel_cdclk_can_crawl(dev_priv, - &old_cdclk_state->actual, - &new_cdclk_state->actual)) { + } else if (intel_cdclk_crawl(dev_priv, + old_cdclk_state, + new_cdclk_state)) { drm_dbg_kms(&dev_priv->drm, "Can change cdclk via crawl\n"); } else if (pipe != INVALID_PIPE) { From patchwork Sat Aug 20 00:58:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Srivatsa, Anusha" X-Patchwork-Id: 12949435 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 121C4C32789 for ; Sat, 20 Aug 2022 01:00:14 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 275DE10E133; Sat, 20 Aug 2022 00:59:04 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 572A110E1D8 for ; Sat, 20 Aug 2022 00:58:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660957134; x=1692493134; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=gAyZhR33hhqQH38dAFykd3GouuCzh88OPCO0t+iTzJs=; b=L8G2u8SMnACGPxGrR0NRrgXVpqbn+nhsNN9lY2tl5QZ+yaBDyskEk/QD D2YFIdz2a3/h2A9zLBCEsdRwG0/+ST3I7cZh/n2n+1OmmtRVw5wgekinM 5t0+AZXb02blI0Lh2nLyJEmm3gskCo3pU52XdAZPR/bW63X61v+LPUkET 87vANye74jnijPwUDbPyGbPcLtGkLj5VxdU1tHIYLR0n+ftFySva0lq73 iK/do3FMJW3vxjXyo+v8lrvzpS3bb1M0OvwAq0aOswmbQlazaC8+8NLSU 0kxfkPPUJ7bj2JQNkM+HaZg9s76yg7lyO+9y4plskexm5YeAYCopFh7BL A==; X-IronPort-AV: E=McAfee;i="6500,9779,10444"; a="294411887" X-IronPort-AV: E=Sophos;i="5.93,249,1654585200"; d="scan'208";a="294411887" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Aug 2022 17:58:54 -0700 X-IronPort-AV: E=Sophos;i="5.93,249,1654585200"; d="scan'208";a="676626682" Received: from cdhirema-mobl.amr.corp.intel.com (HELO anushasr-mobl7.intel.com) ([10.212.188.51]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Aug 2022 17:58:53 -0700 From: Anusha Srivatsa To: intel-gfx@lists.freedesktop.org Date: Fri, 19 Aug 2022 17:58:22 -0700 Message-Id: <20220820005822.102716-5-anusha.srivatsa@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220820005822.102716-1-anusha.srivatsa@intel.com> References: <20220820005822.102716-1-anusha.srivatsa@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 4/4] drm/i915/display: Add cdclk checks to atomic check X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Checking cdclk conditions during atomic check and preparing for commit phase so we can have atomic commit as simple as possible. Add the specific steps to be taken during cdclk changes, prepare for squashing, crawling and modeset scenarios. v2: Add intel_cdclk_modeset() similar to intel_cdclk_squash() and intel_cdclk_crawl(). Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/display/intel_cdclk.c | 61 ++++++++++++++-------- 1 file changed, 38 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 7bba10635c5e..cb58fc857484 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -38,7 +38,6 @@ #include "intel_psr.h" #include "vlv_sideband.h" -#define ADLP_CDCLK_CRAWL(dev_priv, vco) (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->cdclk.hw.vco > 0 && vco > 0) /** * DOC: CDCLK / RAWCLK * @@ -1728,27 +1727,10 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, return; } - if (!ADLP_CDCLK_CRAWL(dev_priv, vco) && DISPLAY_VER(dev_priv) >= 11) { - if (dev_priv->cdclk.hw.vco != 0 && - dev_priv->cdclk.hw.vco != vco) - icl_cdclk_pll_disable(dev_priv); - - if (dev_priv->cdclk.hw.vco != vco) - icl_cdclk_pll_enable(dev_priv, vco); - } else { - if (dev_priv->cdclk.hw.vco != 0 && - dev_priv->cdclk.hw.vco != vco) - bxt_de_pll_disable(dev_priv); - - if (dev_priv->cdclk.hw.vco != vco) - bxt_de_pll_enable(dev_priv, vco); - } - waveform = cdclk_squash_waveform(dev_priv, cdclk); - if ((waveform && has_cdclk_squasher(dev_priv)) || ADLP_CDCLK_CRAWL(dev_priv, vco)) { - for (i = 0; i < MAX_CDCLK_ACTIONS; i++) { - switch (cdclk_steps[i].action) { + for (i = 0; i < MAX_CDCLK_ACTIONS; i++) { + switch (cdclk_steps[i].action) { case INTEL_CDCLK_CRAWL: adlp_cdclk_pll_crawl(dev_priv, vco); clock = cdclk; @@ -1760,15 +1742,28 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, intel_de_write(dev_priv, CDCLK_SQUASH_CTL, squash_ctl); clock = vco / 2; break; - case INTEL_CDCLK_NOOP: case INTEL_CDCLK_MODESET: + if (DISPLAY_VER(dev_priv) >= 11) { + if (dev_priv->cdclk.hw.vco != 0 && + dev_priv->cdclk.hw.vco != vco) + icl_cdclk_pll_disable(dev_priv); + if (dev_priv->cdclk.hw.vco != vco) + icl_cdclk_pll_enable(dev_priv, vco); + } else { + if (dev_priv->cdclk.hw.vco != 0 && + dev_priv->cdclk.hw.vco != vco) + bxt_de_pll_disable(dev_priv); + if (dev_priv->cdclk.hw.vco != vco) + bxt_de_pll_enable(dev_priv, vco); + } + clock = cdclk; + break; + case INTEL_CDCLK_NOOP: break; default: break; } } - } else - clock = cdclk; val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) | bxt_cdclk_cd2x_pipe(dev_priv, pipe) | @@ -2010,6 +2005,24 @@ static bool intel_cdclk_squash(struct drm_i915_private *dev_priv, a->actual.ref == b->actual.ref; } +static void intel_cdclk_modeset(struct drm_i915_private *i915, + const struct intel_cdclk_config *a, + const struct intel_cdclk_config *b) +{ + struct intel_cdclk_state *new_cdclk_state; + struct cdclk_step *cdclk_transition; + struct intel_cdclk_state *cdclk_state = to_intel_cdclk_state(i915->cdclk.obj.state); + struct intel_atomic_state *state = cdclk_state->base.state; + + new_cdclk_state = intel_atomic_get_new_cdclk_state(state); + cdclk_transition = new_cdclk_state->steps; + + cdclk_transition[0].action = INTEL_CDCLK_MODESET; + cdclk_transition[0].cdclk = b->cdclk; + cdclk_transition[1].action = INTEL_CDCLK_NOOP; + cdclk_transition[1].cdclk = b->cdclk; +} + /** * intel_cdclk_needs_modeset - Determine if changong between the CDCLK * configurations requires a modeset on all pipes @@ -2801,6 +2814,8 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state) pipe_name(pipe)); } else if (intel_cdclk_needs_modeset(&old_cdclk_state->actual, &new_cdclk_state->actual)) { + intel_cdclk_modeset(dev_priv, &old_cdclk_state->actual, + &new_cdclk_state->actual); /* All pipes must be switched off while we change the cdclk. */ ret = intel_modeset_all_pipes(state); if (ret)