From patchwork Mon Aug 22 10:54:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 12950496 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BFBC5C28D13 for ; Mon, 22 Aug 2022 10:55:13 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3EEA9112411; Mon, 22 Aug 2022 10:55:09 +0000 (UTC) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id B98591123A0 for ; Mon, 22 Aug 2022 10:54:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1661165694; x=1692701694; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ZgDzaRnqBLrubKzrk+l9vKZDKsYoMNnp3wtwJHmya/g=; b=I2deYOUEH/YtfWehnQ0saaCjiadq7IXaMWIk0CUVeDwnKtwBXXqOnj18 tdsZ0dl0X4+lOyFaJYlsID3OLfD+/opoirvjVAT8eIGl6WPcBjNASz0dL 0xtVLhfqadWLsvKPBg9A167MW78JfFpA8M3d0rbh6KAWCu1O6j5y/3gCC 1GySJo1oz6md7CmE91yrbODWEjMvRoFZVENTOLx7104TeFfDNGPqngv40 6spjuMHCiVkOOnF/xcWwO0OV2yDYLLOAGUtVSW+R1dcqatJpTeRr6tDRS LjlY+bXZXtKThaXW6Yroz7SXmxVvlfhrinRRmIm3WM85F0p+n9MiFFL6K g==; X-IronPort-AV: E=McAfee;i="6500,9779,10446"; a="280353979" X-IronPort-AV: E=Sophos;i="5.93,254,1654585200"; d="scan'208";a="280353979" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Aug 2022 03:54:54 -0700 X-IronPort-AV: E=Sophos;i="5.93,254,1654585200"; d="scan'208";a="585474033" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by orsmga006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Aug 2022 03:54:52 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Date: Mon, 22 Aug 2022 16:24:22 +0530 Message-Id: <20220822105426.3521960-2-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220822105426.3521960-1-ankit.k.nautiyal@intel.com> References: <20220822105426.3521960-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 1/5] drm/i915/dp: Add helper to check DSC1.2 for HDMI2.1 DFP X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add helper function to check if Downstream HDMI 2.1 sink supports DSC1.2. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 32292c0be2bd..fdf82373a22d 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -118,6 +118,15 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp) static void intel_dp_unset_edid(struct intel_dp *intel_dp); static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc); +static bool +is_dfp_hdmi_sink_dsc_1_2(struct intel_dp *intel_dp) +{ + struct intel_connector *intel_connector = intel_dp->attached_connector; + struct drm_connector *connector = &intel_connector->base; + + return connector->display_info.hdmi.dsc_cap.v_1p2; +} + /* Is link rate UHBR and thus 128b/132b? */ bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state) { @@ -2393,7 +2402,7 @@ static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp) rate_per_lane = connector->display_info.hdmi.max_frl_rate_per_lane; max_frl_rate = max_lanes * rate_per_lane; - if (connector->display_info.hdmi.dsc_cap.v_1p2) { + if (is_dfp_hdmi_sink_dsc_1_2(intel_dp)) { max_dsc_lanes = connector->display_info.hdmi.dsc_cap.max_lanes; dsc_rate_per_lane = connector->display_info.hdmi.dsc_cap.max_frl_rate_per_lane; if (max_dsc_lanes && dsc_rate_per_lane) @@ -2605,7 +2614,7 @@ intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp, if (!intel_connector) return; connector = &intel_connector->base; - hdmi_is_dsc_1_2 = connector->display_info.hdmi.dsc_cap.v_1p2; + hdmi_is_dsc_1_2 = is_dfp_hdmi_sink_dsc_1_2(intel_dp); if (!drm_dp_pcon_enc_is_dsc_1_2(intel_dp->pcon_dsc_dpcd) || !hdmi_is_dsc_1_2) From patchwork Mon Aug 22 10:54:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 12950498 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 380AFC28D13 for ; Mon, 22 Aug 2022 10:55:20 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 965E211241D; Mon, 22 Aug 2022 10:55:16 +0000 (UTC) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3420E1123DD for ; Mon, 22 Aug 2022 10:54:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1661165697; x=1692701697; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=TTncIpyDE6o7dPS1aOWZTNew9xusq+ycRV4EU+EuGys=; b=QFz4IMTkJjW9e+i6j7DLJF9DxoKknInF1w3PQzd9LvCuIVJ+2bQy312j ZTHZMTBESr6M+QUmpq76PSekVm1rF28R9BPbcEGuwRo1cX9wR0oDcldT1 G5nJnfzDdkGi1SXrPgwt5DTAgNtkaeD4lcnhuhIKHudG/cvkHRiTg4Yt7 H8F4DgAf1Peh/Lq3/0qBL1DxD8Q1CfINUJC2cQc6LpLqzhB/m0qU+wIrf /zudMWelafXbWdd5KcmsCOUsmBq+cbZcJRNuNgPCcoo+Rb43vf1HVHbA1 cX9FjK3cA4Z9USu3ecqH5JjOGf7VjxoCaJ8RymmHI4iAYvkec9Ply48eH w==; X-IronPort-AV: E=McAfee;i="6500,9779,10446"; a="280353982" X-IronPort-AV: E=Sophos;i="5.93,254,1654585200"; d="scan'208";a="280353982" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Aug 2022 03:54:57 -0700 X-IronPort-AV: E=Sophos;i="5.93,254,1654585200"; d="scan'208";a="585474041" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by orsmga006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Aug 2022 03:54:54 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Date: Mon, 22 Aug 2022 16:24:23 +0530 Message-Id: <20220822105426.3521960-3-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220822105426.3521960-1-ankit.k.nautiyal@intel.com> References: <20220822105426.3521960-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 2/5] drm/i915/dp: Reset frl trained flag before restarting FRL training X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" For cases where DP has HDMI2.1 sink and FRL Link issues are detected, reset the flag to state FRL trained status before restarting FRL training. Fixes: 9488a030ac91 ("drm/i915: Add support for enabling link status and recovery") Cc: Swati Sharma Cc: Ankit Nautiyal Cc: Uma Shankar (v2) Cc: Jani Nikula Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index fdf82373a22d..fc082a933d59 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -3957,6 +3957,8 @@ intel_dp_handle_hdmi_link_status_change(struct intel_dp *intel_dp) drm_dp_pcon_hdmi_frl_link_error_count(&intel_dp->aux, &intel_dp->attached_connector->base); + intel_dp->frl.is_trained = false; + /* Restart FRL training or fall back to TMDS mode */ intel_dp_check_frl_training(intel_dp); } From patchwork Mon Aug 22 10:54:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 12950495 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 55FF0C32772 for ; Mon, 22 Aug 2022 10:55:11 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id EE91E11240C; Mon, 22 Aug 2022 10:55:08 +0000 (UTC) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 936A311237C for ; Mon, 22 Aug 2022 10:54:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1661165699; x=1692701699; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=tcpwgk4lCcX1w5mYm2oHUVmvbr4qEvK1w629PT6QXPk=; b=CO+1jg0zNXwIFQG0e1NZR7oYjtn+6v0eLJ/S0iaOHp3SldLA5ukOTrlz aTyAFeniUvZ3zKxaaF4lLIgErqAXEpvJcFmTCbAhIcKWlWX5npsyLHxS3 WQn7ZATkMW1KNxPoxneFJLbax4AAsIbaK61H3ldESy4j2VY1FlfBCfCGt zZNNsMnalqWFTXoB0yPnkeP9/qTawvHOs7JFF9tJJaEE16zHItxuap6b3 SzgW+oPkLsJ9iH8H4UkQdh/VygU0xxAn86sWr9VCoGWxLAkCTWSQcMxtF InUbmN2q0y12hSYfwoYUA8faTJJpyjg2wItU9mPMnLPlCy8KRb4EWURRq g==; X-IronPort-AV: E=McAfee;i="6500,9779,10446"; a="280353990" X-IronPort-AV: E=Sophos;i="5.93,254,1654585200"; d="scan'208";a="280353990" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Aug 2022 03:54:59 -0700 X-IronPort-AV: E=Sophos;i="5.93,254,1654585200"; d="scan'208";a="585474048" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by orsmga006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Aug 2022 03:54:57 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Date: Mon, 22 Aug 2022 16:24:24 +0530 Message-Id: <20220822105426.3521960-4-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220822105426.3521960-1-ankit.k.nautiyal@intel.com> References: <20220822105426.3521960-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 3/5] drm/i915/dp: Fix DFP RGB->YCBCR conversion X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The decision to use DFP output format conversion capabilities should be during compute_config phase. This patch: -uses the members of intel_dp->dfp to only store the format conversion capabilities of the DP device. -adds new members to crtc_state to help configure the DFP output related conversions. -pulls the decision making to use DFP conversion capabilities for every mode during compute config. Signed-off-by: Ankit Nautiyal --- .../drm/i915/display/intel_display_types.h | 7 ++ drivers/gpu/drm/i915/display/intel_dp.c | 88 +++++++++++-------- 2 files changed, 59 insertions(+), 36 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 0da9b208d56e..065ed19a5dd3 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1311,6 +1311,12 @@ struct intel_crtc_state { /* for loading single buffered registers during vblank */ struct drm_vblank_work vblank_work; + + /* DP DFP color configuration */ + struct { + bool rgb_to_ycbcr; + bool ycbcr_444_to_420; + } dp_dfp_config; }; enum intel_pipe_crc_source { @@ -1704,6 +1710,7 @@ struct intel_dp { int pcon_max_frl_bw; u8 max_bpc; bool ycbcr_444_to_420; + bool ycbcr420_passthrough; bool rgb_to_ycbcr; } dfp; diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index fc082a933d59..8ccbe591b9e2 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1201,19 +1201,21 @@ static bool intel_dp_supports_dsc(struct intel_dp *intel_dp, drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd); } -static bool intel_dp_is_ycbcr420(struct intel_dp *intel_dp, - const struct intel_crtc_state *crtc_state) +static bool intel_dp_is_ycbcr420(const struct intel_crtc_state *crtc_state) { return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 || (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 && - intel_dp->dfp.ycbcr_444_to_420); + crtc_state->dp_dfp_config.ycbcr_444_to_420) || + (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB && + crtc_state->dp_dfp_config.ycbcr_444_to_420 && + crtc_state->dp_dfp_config.rgb_to_ycbcr); } static int intel_dp_hdmi_compute_bpc(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state, int bpc, bool respect_downstream_limits) { - bool ycbcr420_output = intel_dp_is_ycbcr420(intel_dp, crtc_state); + bool ycbcr420_output = intel_dp_is_ycbcr420(crtc_state); int clock = crtc_state->hw.adjusted_mode.crtc_clock; /* @@ -1966,6 +1968,30 @@ static bool intel_dp_has_audio(struct intel_encoder *encoder, return intel_conn_state->force_audio == HDMI_AUDIO_ON; } +static void +intel_dp_compute_dfp_ycbcr420(struct intel_encoder *encoder, + struct intel_crtc_state *crtc_state) +{ + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); + + if (!drm_dp_is_branch(intel_dp->dpcd)) + return; + + /* Mode is YCBCR420, output_format is also YCBCR420: Passthrough */ + if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) + return; + + /* Mode is YCBCR420, output_format is YCBCR444: Downsample */ + if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) { + crtc_state->dp_dfp_config.ycbcr_444_to_420 = true; + return; + } + + /* Mode is YCBCR420, output_format is RGB: Convert to YCBCR444 and Downsample */ + crtc_state->dp_dfp_config.rgb_to_ycbcr = true; + crtc_state->dp_dfp_config.ycbcr_444_to_420 = true; +} + static int intel_dp_compute_output_format(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state, @@ -1984,7 +2010,10 @@ intel_dp_compute_output_format(struct intel_encoder *encoder, crtc_state->output_format = intel_dp_output_format(connector, ycbcr_420_only); - if (ycbcr_420_only && !intel_dp_is_ycbcr420(intel_dp, crtc_state)) { + if (ycbcr_420_only) + intel_dp_compute_dfp_ycbcr420(encoder, crtc_state); + + if (ycbcr_420_only && !intel_dp_is_ycbcr420(crtc_state)) { drm_dbg_kms(&i915->drm, "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n"); crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB; @@ -1993,12 +2022,13 @@ intel_dp_compute_output_format(struct intel_encoder *encoder, ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state, respect_downstream_limits); if (ret) { - if (intel_dp_is_ycbcr420(intel_dp, crtc_state) || + if (intel_dp_is_ycbcr420(crtc_state) || !connector->base.ycbcr_420_allowed || !drm_mode_is_420_also(info, adjusted_mode)) return ret; crtc_state->output_format = intel_dp_output_format(connector, true); + intel_dp_compute_dfp_ycbcr420(encoder, crtc_state); ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state, respect_downstream_limits); } @@ -2668,8 +2698,7 @@ void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp, drm_dbg_kms(&i915->drm, "Failed to %s protocol converter HDMI mode\n", str_enable_disable(intel_dp->has_hdmi_sink)); - tmp = crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 && - intel_dp->dfp.ycbcr_444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0; + tmp = crtc_state->dp_dfp_config.ycbcr_444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0; if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1) @@ -2677,7 +2706,7 @@ void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp, "Failed to %s protocol converter YCbCr 4:2:0 conversion mode\n", str_enable_disable(intel_dp->dfp.ycbcr_444_to_420)); - tmp = intel_dp->dfp.rgb_to_ycbcr ? + tmp = crtc_state->dp_dfp_config.rgb_to_ycbcr ? DP_CONVERSION_BT709_RGB_YCBCR_ENABLE : 0; if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0) @@ -2686,7 +2715,6 @@ void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp, str_enable_disable(tmp)); } - bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp) { u8 dprx = 0; @@ -4534,7 +4562,6 @@ intel_dp_update_420(struct intel_dp *intel_dp) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); struct intel_connector *connector = intel_dp->attached_connector; - bool is_branch, ycbcr_420_passthrough, ycbcr_444_to_420, rgb_to_ycbcr; /* No YCbCr output support on gmch platforms */ if (HAS_GMCH(i915)) @@ -4547,39 +4574,28 @@ intel_dp_update_420(struct intel_dp *intel_dp) if (IS_IRONLAKE(i915)) return; - is_branch = drm_dp_is_branch(intel_dp->dpcd); - ycbcr_420_passthrough = + if (!drm_dp_is_branch(intel_dp->dpcd)) { + connector->base.ycbcr_420_allowed = true; + return; + } + + intel_dp->dfp.ycbcr420_passthrough = drm_dp_downstream_420_passthrough(intel_dp->dpcd, intel_dp->downstream_ports); + /* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */ - ycbcr_444_to_420 = + intel_dp->dfp.ycbcr_444_to_420 = dp_to_dig_port(intel_dp)->lspcon.active || drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd, intel_dp->downstream_ports); - rgb_to_ycbcr = drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd, - intel_dp->downstream_ports, - DP_DS_HDMI_BT709_RGB_YCBCR_CONV); - - if (DISPLAY_VER(i915) >= 11) { - /* Let PCON convert from RGB->YCbCr if possible */ - if (is_branch && rgb_to_ycbcr && ycbcr_444_to_420) { - intel_dp->dfp.rgb_to_ycbcr = true; - intel_dp->dfp.ycbcr_444_to_420 = true; - connector->base.ycbcr_420_allowed = true; - } else { - /* Prefer 4:2:0 passthrough over 4:4:4->4:2:0 conversion */ - intel_dp->dfp.ycbcr_444_to_420 = - ycbcr_444_to_420 && !ycbcr_420_passthrough; - connector->base.ycbcr_420_allowed = - !is_branch || ycbcr_444_to_420 || ycbcr_420_passthrough; - } - } else { - /* 4:4:4->4:2:0 conversion is the only way */ - intel_dp->dfp.ycbcr_444_to_420 = ycbcr_444_to_420; + intel_dp->dfp.rgb_to_ycbcr = + drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd, + intel_dp->downstream_ports, + DP_DS_HDMI_BT709_RGB_YCBCR_CONV); - connector->base.ycbcr_420_allowed = ycbcr_444_to_420; - } + if (intel_dp->dfp.ycbcr420_passthrough || intel_dp->dfp.ycbcr_444_to_420) + connector->base.ycbcr_420_allowed = true; drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] RGB->YcbCr conversion? %s, YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversion? %s\n", From patchwork Mon Aug 22 10:54:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 12950497 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D307EC28D13 for ; Mon, 22 Aug 2022 10:55:16 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B45AE112417; Mon, 22 Aug 2022 10:55:10 +0000 (UTC) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0722011237C for ; Mon, 22 Aug 2022 10:55:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1661165702; x=1692701702; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1HyfYkmuO5+3Xe/OJlp96IIfwmkHxKg0Vliv2pWXfDk=; b=cvw9hpwmBiBwfT0nPCicmh3WYx/rrEwqS/brYUg/R0QzqFzZX0gMvH3p NjiCY+3PXPZae3NNtrIu1y1oDcwCIAh5sgsDPUwPHArUuUf3nLwXCYVp4 NriwGmE67TLpf5NMHFy31lYYdbgTruclqwkqtsyPHdIdaZ8z+C/UPI3zi rxAH1iQeCsHRL3q/19+IjK/H/lY/spqO+/btDHDJo9kzxsZ4OpUrMTVQH d9IReQk/uLWv/GVyZPMrHnI9q5lTxvYDykfZ56yx2usP7wj/jHpbyBl7T GdwPR6/fP6+0UG2cDjl7d/m0EqsWQXBulTgaWkdj7QeDYgOjfRjtlIRd9 w==; X-IronPort-AV: E=McAfee;i="6500,9779,10446"; a="280353995" X-IronPort-AV: E=Sophos;i="5.93,254,1654585200"; d="scan'208";a="280353995" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Aug 2022 03:55:01 -0700 X-IronPort-AV: E=Sophos;i="5.93,254,1654585200"; d="scan'208";a="585474063" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by orsmga006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Aug 2022 03:54:59 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Date: Mon, 22 Aug 2022 16:24:25 +0530 Message-Id: <20220822105426.3521960-5-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220822105426.3521960-1-ankit.k.nautiyal@intel.com> References: <20220822105426.3521960-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 4/5] drm/i915/dp: Handle BPP where HDMI2.1 DFP doesn't support DSC X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Currently we use the highest input BPC supported by DP sink while using DSC.In cases where PCON with HDMI2.1 as branch device, if PCON supports DSC but HDMI2.1 sink does not supports DSC, The PCON tries to use same input BPC that is used between Source and the PCON without DSC, which might not work even with the maximum FRL rate supported by HDMI2.1 sink. This patch calculates the max BPC that can be sufficient with either RGB or YCBCR420 format for the maximum FRL rate supported. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 90 ++++++++++++++++++++++++- 1 file changed, 89 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 8ccbe591b9e2..f0a62f71904e 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -117,6 +117,7 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp) static void intel_dp_unset_edid(struct intel_dp *intel_dp); static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc); +static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp); static bool is_dfp_hdmi_sink_dsc_1_2(struct intel_dp *intel_dp) @@ -1455,6 +1456,74 @@ static int intel_dp_dsc_compute_params(struct intel_encoder *encoder, return drm_dsc_compute_rc_parameters(vdsc_cfg); } +static int +_intel_dp_pcon_hdmi21_get_bpp_nodsc(struct intel_dp *intel_dp, + const struct drm_display_mode *adjusted_mode, + int max_bpc, bool is_ycbcr420) +{ + struct intel_connector *intel_connector = intel_dp->attached_connector; + struct drm_connector *connector = &intel_connector->base; + int i, num_bpc; + u8 dsc_bpc[3] = {0}; + int req_rate_gbps; + int max_frl_rate = connector->display_info.hdmi.max_lanes * + connector->display_info.hdmi.max_frl_rate_per_lane; + + /* + * Currently DSC with Ycbcr420 is not supported. So for modes with Ycbcr420, + * DSC will use RGB and support for RGB->YCBCR444->YCBCR420 conversion is + * required from DP HDMI2.1 PCON. + */ + if (is_ycbcr420 && !(intel_dp->dfp.rgb_to_ycbcr || intel_dp->dfp.ycbcr_444_to_420)) + return 0; + + num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd, + dsc_bpc); + for (i = 0; i < num_bpc; i++) { + if (dsc_bpc[i] > max_bpc) + continue; + + req_rate_gbps = DIV_ROUND_UP(dsc_bpc[i] * 3 * adjusted_mode->clock, 1000000); + + /* YCBCR420 reduces data rate by 2 */ + if (is_ycbcr420) + req_rate_gbps /= 2; + + if (req_rate_gbps < max_frl_rate) + return dsc_bpc[i] * 3; + } + + return 0; +} + +static int +intel_dp_pcon_hdmi21_get_bpp_nodsc(struct intel_dp *intel_dp, + struct intel_crtc_state *pipe_config, + int max_bpc) +{ + const struct drm_display_mode *adjusted_mode = + &pipe_config->hw.adjusted_mode; + struct intel_connector *connector = intel_dp->attached_connector; + const struct drm_display_info *info = &connector->base.display_info; + bool is_ycbcr420 = drm_mode_is_420_only(info, adjusted_mode); + int pipe_bpp; + + pipe_bpp = _intel_dp_pcon_hdmi21_get_bpp_nodsc(intel_dp, adjusted_mode, + max_bpc, is_ycbcr420); + if (!pipe_bpp && !is_ycbcr420 && drm_mode_is_420_also(info, adjusted_mode)) { + is_ycbcr420 = true; + pipe_bpp = _intel_dp_pcon_hdmi21_get_bpp_nodsc(intel_dp, adjusted_mode, + max_bpc, is_ycbcr420); + } + + if (!pipe_bpp && is_ycbcr420) { + pipe_config->dp_dfp_config.rgb_to_ycbcr = true; + pipe_config->dp_dfp_config.ycbcr_444_to_420 = true; + } + + return pipe_bpp; +} + static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state, @@ -1473,7 +1542,26 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, if (!intel_dp_supports_dsc(intel_dp, pipe_config)) return -EINVAL; - pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc); + /* + * In cases where PCON with HDMI2.1 as branch device, if PCON supports + * DSC but HDMI2.1 sink does not supports DSC, The PCON tries to use same + * input DSC bpc that is used between Source and PCON with Ycbcr420 + * format. + * So use the max BPC that will be sufficient to show the mode in YCbcr420 + * without DSC from PCON->HDMI2.1 + */ + if (intel_dp_is_hdmi_2_1_sink(intel_dp) && + !is_dfp_hdmi_sink_dsc_1_2(intel_dp)) { + pipe_bpp = intel_dp_pcon_hdmi21_get_bpp_nodsc(intel_dp, pipe_config, + conn_state->max_requested_bpc); + if (!pipe_bpp) { + drm_dbg_kms(&dev_priv->drm, + "No BPC possible to support the mode without HDMI2.1 DSC\n"); + return -EINVAL; + } + } else { + pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc); + } /* Min Input BPC for ICL+ is 8 */ if (pipe_bpp < 8 * 3) { From patchwork Mon Aug 22 10:54:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 12950499 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D6044C28D13 for ; Mon, 22 Aug 2022 10:55:52 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2AD1D11253D; Mon, 22 Aug 2022 10:55:51 +0000 (UTC) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8B2761123E9 for ; Mon, 22 Aug 2022 10:55:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1661165704; x=1692701704; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=d1slpelmuiY4+m/2nWjsNA2Y9oDcBBwvM5FgZMHhIL4=; b=S/guhRYCwy1J6OWfGLaNVcL2BxZ7KgiQZp+4rs1+3QYi3pOEdppCfG0P j4SM7Bvkgm7WV1iFAA30Souk7uiDliuRaMXNAW7LJcHAmPbn8VmPNr/ZI vMMMQzpaGTzr6coQwYfLxpE9TBWBeWgt+CxL5cTSUnbucQqLMbM3lYUyl RHWxVBj6C+FeNqrPiBG/JxynQHyxPJ9EqIZGwTpjURH/p3Ct1hAizbVSo 8dmQlNaJFT+Hbv+ESN9H6nzpRahg1Ucz99YecmO/d1H9vEdBIhz42/sLv jlk9D2W61Yfm25i9BHL+/jPStoWeIXvw6cntfrBG/MNz3gLv7qXDkogUJ w==; X-IronPort-AV: E=McAfee;i="6500,9779,10446"; a="280354005" X-IronPort-AV: E=Sophos;i="5.93,254,1654585200"; d="scan'208";a="280354005" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Aug 2022 03:55:04 -0700 X-IronPort-AV: E=Sophos;i="5.93,254,1654585200"; d="scan'208";a="585474090" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by orsmga006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Aug 2022 03:55:02 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Date: Mon, 22 Aug 2022 16:24:26 +0530 Message-Id: <20220822105426.3521960-6-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220822105426.3521960-1-ankit.k.nautiyal@intel.com> References: <20220822105426.3521960-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 5/5] drm/i915/dp: Fix FRL BW check for HDMI2.1 DFP X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" During FRL bandwidth check for downstream HDMI2.1 sink, the min BPC supported is incorrectly taken for DP, and the check does not consider ybcr420 only modes. This patch fixes the bandwidth calculation similar to the TMDS case, by taking min 8Bpc and considering Ycbcr420 only modes. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 52 ++++++++++++++++++------- 1 file changed, 39 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index f0a62f71904e..7f24f7633078 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -118,6 +118,7 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp) static void intel_dp_unset_edid(struct intel_dp *intel_dp); static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc); static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp); +static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp); static bool is_dfp_hdmi_sink_dsc_1_2(struct intel_dp *intel_dp) @@ -917,6 +918,32 @@ intel_dp_tmds_clock_valid(struct intel_dp *intel_dp, return MODE_OK; } +static int +intel_dp_frl_bw_valid(struct intel_dp *intel_dp, int target_clock, + int bpc, bool ycbcr_420_only) +{ + int target_bw; + int max_frl_bw; + int bpp = bpc * 3; + + if (ycbcr_420_only) + target_clock /= 2; + + target_bw = bpp * target_clock; + + /* check for MAX FRL BW for both PCON and HDMI2.1 sink */ + max_frl_bw = min(intel_dp->dfp.pcon_max_frl_bw, + intel_dp_hdmi_sink_max_frl(intel_dp)); + + /* converting bw from Gbps to Kbps*/ + max_frl_bw = max_frl_bw * 1000000; + + if (target_bw > max_frl_bw) + return MODE_CLOCK_HIGH; + + return MODE_OK; +} + static enum drm_mode_status intel_dp_mode_valid_downstream(struct intel_connector *connector, const struct drm_display_mode *mode, @@ -925,23 +952,24 @@ intel_dp_mode_valid_downstream(struct intel_connector *connector, struct intel_dp *intel_dp = intel_attached_dp(connector); const struct drm_display_info *info = &connector->base.display_info; enum drm_mode_status status; - bool ycbcr_420_only; + bool ycbcr_420_only = drm_mode_is_420_only(info, mode); /* If PCON supports FRL MODE, check FRL bandwidth constraints */ if (intel_dp->dfp.pcon_max_frl_bw) { - int target_bw; - int max_frl_bw; - int bpp = intel_dp_mode_min_output_bpp(connector, mode); - - target_bw = bpp * target_clock; - max_frl_bw = intel_dp->dfp.pcon_max_frl_bw; + /* Assume 8bpc for the HDMI2.1 FRL BW check */ + status = intel_dp_frl_bw_valid(intel_dp, target_clock, 8, ycbcr_420_only); - /* converting bw from Gbps to Kbps*/ - max_frl_bw = max_frl_bw * 1000000; + if (status != MODE_OK) { + if (ycbcr_420_only || + !connector->base.ycbcr_420_allowed || + !drm_mode_is_420_also(info, mode)) + return status; - if (target_bw > max_frl_bw) - return MODE_CLOCK_HIGH; + status = intel_dp_frl_bw_valid(intel_dp, target_clock, 8, true); + if (status != MODE_OK) + return status; + } return MODE_OK; } @@ -950,8 +978,6 @@ intel_dp_mode_valid_downstream(struct intel_connector *connector, target_clock > intel_dp->dfp.max_dotclock) return MODE_CLOCK_HIGH; - ycbcr_420_only = drm_mode_is_420_only(info, mode); - /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */ status = intel_dp_tmds_clock_valid(intel_dp, target_clock, 8, ycbcr_420_only, true);