From patchwork Thu Aug 25 09:50:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12954449 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AEFE2C64990 for ; Thu, 25 Aug 2022 09:53:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240785AbiHYJxr (ORCPT ); Thu, 25 Aug 2022 05:53:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36218 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240786AbiHYJx0 (ORCPT ); Thu, 25 Aug 2022 05:53:26 -0400 Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D9F17AC24E for ; Thu, 25 Aug 2022 02:51:13 -0700 (PDT) Received: by mail-lf1-x12c.google.com with SMTP id q7so23809559lfu.5 for ; Thu, 25 Aug 2022 02:51:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=zWKtgCgwZZgC5f9GsWm7np14RFmpgHY79lEXnopj1ws=; b=wLASKggMZdRTOZseTW9I9mmBrVGxL/PN9VYLTEaAeSO7iCUhiygwKcY+v5V/FHZDeD tVEq+1GUATi6sNnNjiNCGLT2RuU29qBLZQOfmVEonjNGobctiTkAU93MHbmFbPBNfj1Y 49qaYzC63Mtpru5n1P0GcDnL6Yx204H6pDh319PF0Cw5kjIQz+0DYAKR0BwzEu0tZQXz aQabYYPkPaCc553gWy42OAxU/cVpzLwUAIYneGmWxisHTg46HZKrO/yLYKTpxax/WPBY kBLp4emyKNZM80p9l0mh3UVbAlRynStjZGQqt2e1HouBwjPltshWbPAHZ/rqm0tVATqb eEig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=zWKtgCgwZZgC5f9GsWm7np14RFmpgHY79lEXnopj1ws=; b=r9+gd4R/PD6FXv7PXLlzee1jMRV0d78wE6Jx3PtcAV7XRpEJQJsiQCSdt1sLgzL2LW j55soJsJmXRhFsOy4BeENyEnpmoWe3oxGnIHG9iKCBm8OgIob+XMqRnKP96Ggor4totO IIyM7NBcj7XJbsYEYE0Kxl61Bt0gh8r6f8zMs935jh1Xdzw+NmtogHvGXElcOMQY+i9K hMfdjzv3e+QfhG7UNhpV7LE5ZD5Lpmr5u1RaWwqpgTlMCcCFI+M6AhaGEeZvMR4qPWlu QFTAN7j7Qz669WGPcoN73Xjbn2jFcq1P6aQnt7pJ5hSZHwo0nAnj2N946i8xUMTGj9nA /c6Q== X-Gm-Message-State: ACgBeo2617LuerTfNO3MX7PgvHCvnnkCj56HWTpHJLOyEjKWOIpAtk2f YI9tc22NP/o5WQPAnkkYm/+qUQ== X-Google-Smtp-Source: AA6agR4Ht1JX8SPjimMrPZ1pZRlPJWDsLH31Ole52fwVDxTwYWAWKuLMhzyt3S3uDWMHQJVjpxPkXg== X-Received: by 2002:a05:6512:3984:b0:492:da1b:9683 with SMTP id j4-20020a056512398400b00492da1b9683mr946589lfu.58.1661421065814; Thu, 25 Aug 2022 02:51:05 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id h10-20020a056512220a00b00492cfecf1c0sm398502lfu.245.2022.08.25.02.51.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Aug 2022 02:51:05 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Clark , Sean Paul , Abhinav Kumar , Rob Herring , Krzysztof Kozlowski Cc: Stephen Boyd , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v4 01/10] dt-bindings: display/msm: split qcom,mdss bindings Date: Thu, 25 Aug 2022 12:50:54 +0300 Message-Id: <20220825095103.624891-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220825095103.624891-1-dmitry.baryshkov@linaro.org> References: <20220825095103.624891-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Split Mobile Display SubSystem (MDSS) root node bindings to the separate yaml file. Changes to the existing (txt) schema: - Added optional "vbif_nrt_phys" region used by msm8996 - Made "bus" and "vsync" clocks optional (they are not used by some platforms) - Added (optional) "core" clock added recently to the mdss driver - Added optional resets property referencing MDSS reset - Defined child nodes pointing to corresponding reference schema. - Dropped the "lut" clock. It was added to the schema by mistake (it is a part of mdp4 schema, not the mdss). Signed-off-by: Dmitry Baryshkov Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/display/msm/mdp5.txt | 30 +-- .../devicetree/bindings/display/msm/mdss.yaml | 183 ++++++++++++++++++ 2 files changed, 184 insertions(+), 29 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/msm/mdss.yaml diff --git a/Documentation/devicetree/bindings/display/msm/mdp5.txt b/Documentation/devicetree/bindings/display/msm/mdp5.txt index 43d11279c925..65d03c58dee6 100644 --- a/Documentation/devicetree/bindings/display/msm/mdp5.txt +++ b/Documentation/devicetree/bindings/display/msm/mdp5.txt @@ -2,37 +2,9 @@ Qualcomm adreno/snapdragon MDP5 display controller Description: -This is the bindings documentation for the Mobile Display Subsytem(MDSS) that -encapsulates sub-blocks like MDP5, DSI, HDMI, eDP etc, and the MDP5 display +This is the bindings documentation for the MDP5 display controller found in SoCs like MSM8974, APQ8084, MSM8916, MSM8994 and MSM8996. -MDSS: -Required properties: -- compatible: - * "qcom,mdss" - MDSS -- reg: Physical base address and length of the controller's registers. -- reg-names: The names of register regions. The following regions are required: - * "mdss_phys" - * "vbif_phys" -- interrupts: The interrupt signal from MDSS. -- interrupt-controller: identifies the node as an interrupt controller. -- #interrupt-cells: specifies the number of cells needed to encode an interrupt - source, should be 1. -- power-domains: a power domain consumer specifier according to - Documentation/devicetree/bindings/power/power_domain.txt -- clocks: device clocks. See ../clocks/clock-bindings.txt for details. -- clock-names: the following clocks are required. - * "iface" - * "bus" - * "vsync" -- #address-cells: number of address cells for the MDSS children. Should be 1. -- #size-cells: Should be 1. -- ranges: parent bus address space is the same as the child bus address space. - -Optional properties: -- clock-names: the following clocks are optional: - * "lut" - MDP5: Required properties: - compatible: diff --git a/Documentation/devicetree/bindings/display/msm/mdss.yaml b/Documentation/devicetree/bindings/display/msm/mdss.yaml new file mode 100644 index 000000000000..afc48d2b02f1 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/mdss.yaml @@ -0,0 +1,183 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Mobile Display SubSystem (MDSS) + +maintainers: + - Dmitry Baryshkov + - Rob Clark + +description: + This is the bindings documentation for the Mobile Display Subsytem(MDSS) that + encapsulates sub-blocks like MDP5, DSI, HDMI, eDP, etc. + +properties: + compatible: + enum: + - qcom,mdss + + reg: + minItems: 2 + maxItems: 3 + + reg-names: + minItems: 2 + items: + - const: mdss_phys + - const: vbif_phys + - const: vbif_nrt_phys + + interrupts: + maxItems: 1 + + interrupt-controller: + true + + "#interrupt-cells": + const: 1 + + power-domains: + maxItems: 1 + description: | + The MDSS power domain provided by GCC + + clocks: + minItems: 1 + maxItems: 4 + + clock-names: + minItems: 1 + maxItems: 4 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + ranges: + true + + resets: + items: + - description: MDSS_CORE reset + +oneOf: + - properties: + clocks: + minItems: 3 + maxItems: 4 + + clock-names: + minItems: 3 + items: + - const: iface + - const: bus + - const: vsync + - const: core + - properties: + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + items: + - const: iface + - const: core + +required: + - compatible + - reg + - reg-names + - interrupts + - interrupt-controller + - "#interrupt-cells" + - power-domains + - clocks + - clock-names + - "#address-cells" + - "#size-cells" + - ranges + +patternProperties: + "^mdp@[1-9a-f][0-9a-f]*$": + type: object + properties: + compatible: + const: qcom,mdp5 + + "^dsi@[1-9a-f][0-9a-f]*$": + type: object + properties: + compatible: + const: qcom,mdss-dsi-ctrl + + "^dsi-phy@[1-9a-f][0-9a-f]*$": + type: object + properties: + compatible: + enum: + - qcom,dsi-phy-14nm + - qcom,dsi-phy-20nm + - qcom,dsi-phy-28nm-hpm + - qcom,dsi-phy-28nm-lp + + "^hdmi-phy@[1-9a-f][0-9a-f]*$": + type: object + properties: + compatible: + enum: + - qcom,hdmi-phy-8084 + - qcom,hdmi-phy-8660 + - qcom,hdmi-phy-8960 + - qcom,hdmi-phy-8974 + - qcom,hdmi-phy-8996 + + "^hdmi-tx@[1-9a-f][0-9a-f]*$": + type: object + properties: + compatible: + enum: + - qcom,hdmi-tx-8084 + - qcom,hdmi-tx-8660 + - qcom,hdmi-tx-8960 + - qcom,hdmi-tx-8974 + - qcom,hdmi-tx-8994 + - qcom,hdmi-tx-8996 + +additionalProperties: false + +examples: + - | + #include + #include + mdss@1a00000 { + compatible = "qcom,mdss"; + reg = <0x1a00000 0x1000>, + <0x1ac8000 0x3000>; + reg-names = "mdss_phys", "vbif_phys"; + + power-domains = <&gcc MDSS_GDSC>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>; + clock-names = "iface", + "bus", + "vsync"; + + interrupts = ; + + interrupt-controller; + #interrupt-cells = <1>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + }; +... 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Signed-off-by: Dmitry Baryshkov --- .../bindings/display/msm/dpu-sdm845.yaml | 135 +++------ .../devicetree/bindings/display/msm/mdss.yaml | 265 ++++++++++++++---- 2 files changed, 239 insertions(+), 161 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml b/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml index 2bb8896beffc..2074e954372f 100644 --- a/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml +++ b/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml @@ -10,139 +10,74 @@ maintainers: - Krishna Manikandan description: | - Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates - sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree - bindings of MDSS and DPU are mentioned for SDM845 target. + Device tree bindings for the DPU display controller for SDM845 target. properties: compatible: items: - - const: qcom,sdm845-mdss + - const: qcom,sdm845-dpu reg: - maxItems: 1 + items: + - description: Address offset and size for mdp register set + - description: Address offset and size for vbif register set reg-names: - const: mdss - - power-domains: - maxItems: 1 + items: + - const: mdp + - const: vbif clocks: items: - - description: Display AHB clock from gcc + - description: Display ahb clock + - description: Display axi clock - description: Display core clock + - description: Display vsync clock clock-names: items: - const: iface + - const: bus - const: core + - const: vsync interrupts: maxItems: 1 - interrupt-controller: true - - "#address-cells": true - - "#size-cells": true - - "#interrupt-cells": - const: 1 - - iommus: - items: - - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0 - - description: Phandle to apps_smmu node with SID mask for Hard-Fail port1 - - ranges: true - - resets: - items: - - description: MDSS_CORE reset + power-domains: + maxItems: 1 -patternProperties: - "^display-controller@[0-9a-f]+$": - type: object - description: Node containing the properties of DPU. + operating-points-v2: true + ports: + $ref: /schemas/graph.yaml#/properties/ports + description: | + Contains the list of output ports from DPU device. These ports + connect to interfaces that are external to the DPU hardware, + such as DSI, DP etc. Each output port contains an endpoint that + describes how it is connected to an external interface. properties: - compatible: - items: - - const: qcom,sdm845-dpu - - reg: - items: - - description: Address offset and size for mdp register set - - description: Address offset and size for vbif register set - - reg-names: - items: - - const: mdp - - const: vbif - - clocks: - items: - - description: Display ahb clock - - description: Display axi clock - - description: Display core clock - - description: Display vsync clock - - clock-names: - items: - - const: iface - - const: bus - - const: core - - const: vsync - - interrupts: - maxItems: 1 - - power-domains: - maxItems: 1 - - operating-points-v2: true - ports: - $ref: /schemas/graph.yaml#/properties/ports - description: | - Contains the list of output ports from DPU device. These ports - connect to interfaces that are external to the DPU hardware, - such as DSI, DP etc. Each output port contains an endpoint that - describes how it is connected to an external interface. - - properties: - port@0: - $ref: /schemas/graph.yaml#/properties/port - description: DPU_INTF1 (DSI1) - - port@1: - $ref: /schemas/graph.yaml#/properties/port - description: DPU_INTF2 (DSI2) - - required: - - port@0 - - port@1 + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: DPU_INTF1 (DSI1) + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: DPU_INTF2 (DSI2) required: - - compatible - - reg - - reg-names - - clocks - - interrupts - - power-domains - - operating-points-v2 - - ports + - port@0 + - port@1 required: - compatible - reg - reg-names - - power-domains - clocks - interrupts - - interrupt-controller - - iommus - - ranges + - power-domains + - operating-points-v2 + - ports additionalProperties: false diff --git a/Documentation/devicetree/bindings/display/msm/mdss.yaml b/Documentation/devicetree/bindings/display/msm/mdss.yaml index afc48d2b02f1..ef4709d87004 100644 --- a/Documentation/devicetree/bindings/display/msm/mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/mdss.yaml @@ -18,17 +18,15 @@ properties: compatible: enum: - qcom,mdss + - qcom,sdm845-mdss reg: - minItems: 2 + minItems: 1 maxItems: 3 reg-names: - minItems: 2 - items: - - const: mdss_phys - - const: vbif_phys - - const: vbif_nrt_phys + minItems: 1 + maxItems: 3 interrupts: maxItems: 1 @@ -53,10 +51,10 @@ properties: maxItems: 4 "#address-cells": - const: 1 + enum: [1, 2] "#size-cells": - const: 1 + enum: [1, 2] ranges: true @@ -65,29 +63,178 @@ properties: items: - description: MDSS_CORE reset -oneOf: - - properties: - clocks: - minItems: 3 - maxItems: 4 - - clock-names: - minItems: 3 - items: - - const: iface - - const: bus - - const: vsync - - const: core - - properties: - clocks: - minItems: 1 - maxItems: 2 - - clock-names: - minItems: 1 - items: - - const: iface - - const: core + interconnects: + minItems: 2 + items: + - description: MDP port 0 + - description: MDP port 1 + - description: Rotator + + interconnect-names: + minItems: 2 + items: + - const: mdp0-mem + - const: mdp1-mem + - const: rotator-mem + + iommus: + items: + - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0 + - description: Phandle to apps_smmu node with SID mask for Hard-Fail port1 + +allOf: + - if: + properties: + compatible: + contains: + const: qcom,mdss + then: + properties: + reg-names: + minItems: 2 + items: + - const: mdss_phys + - const: vbif_phys + - const: vbif_nrt_phys + oneOf: + - properties: + clocks: + minItems: 3 + maxItems: 4 + + clock-names: + minItems: 3 + items: + - const: iface + - const: bus + - const: vsync + - const: core + - properties: + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + items: + - const: iface + - const: core + else: + properties: + regs: + maxItems: 1 + + reg-names: + items: + - const: mdss + + interconnects: + maxItems: 2 + + interconnect-names: + maxItems: 2 + + required: + - iommus + + - if: + properties: + compatible: + contains: + const: qcom,sdm845-mdss + then: + properties: + clocks: + items: + - description: Display AHB clock from gcc + - description: Display core clock + + clock-names: + items: + - const: iface + - const: core + + iommus: + minItems: 2 + + - if: + properties: + compatible: + contains: + const: qcom,mdss + then: + patternProperties: + "^mdp@[1-9a-f][0-9a-f]*$": + type: object + properties: + compatible: + const: qcom,mdp5 + + "^dsi@[1-9a-f][0-9a-f]*$": + type: object + properties: + compatible: + const: qcom,mdss-dsi-ctrl + + "^dsi-phy@[1-9a-f][0-9a-f]*$": + type: object + properties: + compatible: + enum: + - qcom,dsi-phy-14nm + - qcom,dsi-phy-14nm-660 + - qcom,dsi-phy-20nm + - qcom,dsi-phy-28nm-hpm + - qcom,dsi-phy-28nm-lp + + "^hdmi-phy@[1-9a-f][0-9a-f]*$": + type: object + properties: + compatible: + enum: + - qcom,hdmi-phy-8084 + - qcom,hdmi-phy-8660 + - qcom,hdmi-phy-8960 + - qcom,hdmi-phy-8974 + - qcom,hdmi-phy-8996 + + "^hdmi-tx@[1-9a-f][0-9a-f]*$": + type: object + properties: + compatible: + enum: + - qcom,hdmi-tx-8084 + - qcom,hdmi-tx-8660 + - qcom,hdmi-tx-8960 + - qcom,hdmi-tx-8974 + - qcom,hdmi-tx-8994 + - qcom,hdmi-tx-8996 + + - if: + properties: + compatible: + contains: + const: qcom,sdm845-mdss + then: + patternProperties: + "^display-controller@[1-9a-f][0-9a-f]*$": + type: object + properties: + compatible: + const: qcom,sdm845-dpu + + "^dsi@[1-9a-f][0-9a-f]*$": + type: object + properties: + compatible: + const: qcom,mdss-dsi-ctrl + + "^dsi-phy@[1-9a-f][0-9a-f]*$": + type: object + properties: + compatible: + enum: + - qcom,dsi-phy-10nm required: - compatible @@ -106,48 +253,21 @@ required: patternProperties: "^mdp@[1-9a-f][0-9a-f]*$": type: object - properties: - compatible: - const: qcom,mdp5 + + "^display-controller@[1-9a-f][0-9a-f]*$": + type: object "^dsi@[1-9a-f][0-9a-f]*$": type: object - properties: - compatible: - const: qcom,mdss-dsi-ctrl "^dsi-phy@[1-9a-f][0-9a-f]*$": type: object - properties: - compatible: - enum: - - qcom,dsi-phy-14nm - - qcom,dsi-phy-20nm - - qcom,dsi-phy-28nm-hpm - - qcom,dsi-phy-28nm-lp "^hdmi-phy@[1-9a-f][0-9a-f]*$": type: object - properties: - compatible: - enum: - - qcom,hdmi-phy-8084 - - qcom,hdmi-phy-8660 - - qcom,hdmi-phy-8960 - - qcom,hdmi-phy-8974 - - qcom,hdmi-phy-8996 "^hdmi-tx@[1-9a-f][0-9a-f]*$": type: object - properties: - compatible: - enum: - - qcom,hdmi-tx-8084 - - qcom,hdmi-tx-8660 - - qcom,hdmi-tx-8960 - - qcom,hdmi-tx-8974 - - qcom,hdmi-tx-8994 - - qcom,hdmi-tx-8996 additionalProperties: false @@ -180,4 +300,27 @@ examples: ranges; }; + - | + #include + #include + display-subsystem@ae00000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,sdm845-mdss"; + reg = <0x0ae00000 0x1000>; + reg-names = "mdss"; + power-domains = <&dispcc MDSS_GDSC>; + + clocks = <&gcc 19>, + <&dispcc 12>; + clock-names = "iface", "core"; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x880 0x8>, + <&apps_smmu 0xc80 0x8>; + ranges; + }; ... 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Signed-off-by: Dmitry Baryshkov --- .../bindings/display/msm/dpu-sc7180.yaml | 149 +++++------------- .../devicetree/bindings/display/msm/mdss.yaml | 66 +++++++- 2 files changed, 102 insertions(+), 113 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml b/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml index d3c3e4b07897..9d4ec0b60c25 100644 --- a/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml +++ b/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml @@ -10,151 +10,78 @@ maintainers: - Krishna Manikandan description: | - Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates - sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree - bindings of MDSS and DPU are mentioned for SC7180 target. + Device tree bindings for the DPU display controller for SC7180 target. properties: compatible: items: - - const: qcom,sc7180-mdss + - const: qcom,sc7180-dpu reg: - maxItems: 1 + items: + - description: Address offset and size for mdp register set + - description: Address offset and size for vbif register set reg-names: - const: mdss - - power-domains: - maxItems: 1 + items: + - const: mdp + - const: vbif clocks: items: - - description: Display AHB clock from gcc - - description: Display AHB clock from dispcc + - description: Display hf axi clock + - description: Display ahb clock + - description: Display rotator clock + - description: Display lut clock - description: Display core clock + - description: Display vsync clock clock-names: items: + - const: bus - const: iface - - const: ahb + - const: rot + - const: lut - const: core + - const: vsync interrupts: maxItems: 1 - interrupt-controller: true - - "#address-cells": true - - "#size-cells": true - - "#interrupt-cells": - const: 1 - - iommus: - items: - - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0 - - ranges: true - - interconnects: - items: - - description: Interconnect path specifying the port ids for data bus - - interconnect-names: - const: mdp0-mem + power-domains: + maxItems: 1 - resets: - items: - - description: MDSS_CORE reset + operating-points-v2: true -patternProperties: - "^display-controller@[0-9a-f]+$": - type: object - description: Node containing the properties of DPU. + ports: + $ref: /schemas/graph.yaml#/properties/ports + description: | + Contains the list of output ports from DPU device. These ports + connect to interfaces that are external to the DPU hardware, + such as DSI, DP etc. Each output port contains an endpoint that + describes how it is connected to an external interface. properties: - compatible: - items: - - const: qcom,sc7180-dpu - - reg: - items: - - description: Address offset and size for mdp register set - - description: Address offset and size for vbif register set - - reg-names: - items: - - const: mdp - - const: vbif - - clocks: - items: - - description: Display hf axi clock - - description: Display ahb clock - - description: Display rotator clock - - description: Display lut clock - - description: Display core clock - - description: Display vsync clock - - clock-names: - items: - - const: bus - - const: iface - - const: rot - - const: lut - - const: core - - const: vsync - - interrupts: - maxItems: 1 - - power-domains: - maxItems: 1 - - operating-points-v2: true - - ports: - $ref: /schemas/graph.yaml#/properties/ports - description: | - Contains the list of output ports from DPU device. These ports - connect to interfaces that are external to the DPU hardware, - such as DSI, DP etc. Each output port contains an endpoint that - describes how it is connected to an external interface. - - properties: - port@0: - $ref: /schemas/graph.yaml#/properties/port - description: DPU_INTF1 (DSI1) - - port@2: - $ref: /schemas/graph.yaml#/properties/port - description: DPU_INTF0 (DP) - - required: - - port@0 + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: DPU_INTF1 (DSI1) + + port@2: + $ref: /schemas/graph.yaml#/properties/port + description: DPU_INTF0 (DP) required: - - compatible - - reg - - reg-names - - clocks - - interrupts - - power-domains - - operating-points-v2 - - ports + - port@0 required: - compatible - reg - reg-names - - power-domains - clocks - interrupts - - interrupt-controller - - iommus - - ranges + - power-domains + - operating-points-v2 + - ports additionalProperties: false diff --git a/Documentation/devicetree/bindings/display/msm/mdss.yaml b/Documentation/devicetree/bindings/display/msm/mdss.yaml index ef4709d87004..f86177bb2e8c 100644 --- a/Documentation/devicetree/bindings/display/msm/mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/mdss.yaml @@ -18,6 +18,7 @@ properties: compatible: enum: - qcom,mdss + - qcom,sc7180-mdss - qcom,sdm845-mdss reg: @@ -64,20 +65,21 @@ properties: - description: MDSS_CORE reset interconnects: - minItems: 2 + minItems: 1 items: - description: MDP port 0 - description: MDP port 1 - description: Rotator interconnect-names: - minItems: 2 + minItems: 1 items: - const: mdp0-mem - const: mdp1-mem - const: rotator-mem iommus: + minItems: 1 items: - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0 - description: Phandle to apps_smmu node with SID mask for Hard-Fail port1 @@ -129,14 +131,39 @@ allOf: - const: mdss interconnects: + minItems: 1 maxItems: 2 interconnect-names: + minItems: 1 maxItems: 2 required: - iommus + - if: + properties: + compatible: + contains: + enum: + - qcom,sc7180-mdss + then: + properties: + clocks: + items: + - description: Display AHB clock from gcc + - description: Display AHB clock from dispcc + - description: Display core clock + + clock-names: + items: + - const: iface + - const: ahb + - const: core + + iommus: + maxItems: 1 + - if: properties: compatible: @@ -210,6 +237,38 @@ allOf: - qcom,hdmi-tx-8994 - qcom,hdmi-tx-8996 + - if: + properties: + compatible: + contains: + const: qcom,sc7180-mdss + then: + patternProperties: + "^display-controller@[1-9a-f][0-9a-f]*$": + type: object + properties: + compatible: + const: qcom,sc7180-dpu + + "^displayport-controller@[1-9a-f][0-9a-f]*$": + type: object + properties: + compatible: + const: qcom,sc7180-dp + + "^dsi@[1-9a-f][0-9a-f]*$": + type: object + properties: + compatible: + const: qcom,mdss-dsi-ctrl + + "^dsi-phy@[1-9a-f][0-9a-f]*$": + type: object + properties: + compatible: + enum: + - qcom,dsi-phy-10nm + - if: properties: compatible: @@ -257,6 +316,9 @@ patternProperties: "^display-controller@[1-9a-f][0-9a-f]*$": type: object + "^displayport-controller@[1-9a-f][0-9a-f]*$": + type: object + "^dsi@[1-9a-f][0-9a-f]*$": type: object From patchwork Thu Aug 25 09:50:57 2022 Content-Type: text/plain; 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Thu, 25 Aug 2022 02:51:08 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id h10-20020a056512220a00b00492cfecf1c0sm398502lfu.245.2022.08.25.02.51.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Aug 2022 02:51:08 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Clark , Sean Paul , Abhinav Kumar , Rob Herring , Krzysztof Kozlowski Cc: Stephen Boyd , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v4 04/10] dt-bindings: display/msm: move qcom,sc7280-mdss schema to mdss.yaml Date: Thu, 25 Aug 2022 12:50:57 +0300 Message-Id: <20220825095103.624891-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220825095103.624891-1-dmitry.baryshkov@linaro.org> References: <20220825095103.624891-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Move schema for qcom,sc7280-mdss from dpu-sc7280.yaml to mdss.yaml so that the dpu file describes only the DPU schema. Signed-off-by: Dmitry Baryshkov --- .../bindings/display/msm/dpu-sc7280.yaml | 148 +++++------------- .../devicetree/bindings/display/msm/mdss.yaml | 54 +++++++ 2 files changed, 92 insertions(+), 110 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml b/Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml index f427eec3d3a4..349a454099ad 100644 --- a/Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml +++ b/Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml @@ -10,149 +10,77 @@ maintainers: - Krishna Manikandan description: | - Device tree bindings for MSM Mobile Display Subsystem (MDSS) that encapsulates - sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree - bindings of MDSS and DPU are mentioned for SC7280. + Device tree bindings for the DPU display controller for SC7280 target. properties: compatible: - const: qcom,sc7280-mdss + const: qcom,sc7280-dpu reg: - maxItems: 1 + items: + - description: Address offset and size for mdp register set + - description: Address offset and size for vbif register set reg-names: - const: mdss - - power-domains: - maxItems: 1 + items: + - const: mdp + - const: vbif clocks: items: - - description: Display AHB clock from gcc - - description: Display AHB clock from dispcc + - description: Display hf axi clock + - description: Display sf axi clock + - description: Display ahb clock + - description: Display lut clock - description: Display core clock + - description: Display vsync clock clock-names: items: + - const: bus + - const: nrt_bus - const: iface - - const: ahb + - const: lut - const: core + - const: vsync interrupts: maxItems: 1 - interrupt-controller: true - - "#address-cells": true - - "#size-cells": true - - "#interrupt-cells": - const: 1 - - iommus: - items: - - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0 - - ranges: true - - interconnects: - items: - - description: Interconnect path specifying the port ids for data bus - - interconnect-names: - const: mdp0-mem + power-domains: + maxItems: 1 - resets: - items: - - description: MDSS_CORE reset + operating-points-v2: true -patternProperties: - "^display-controller@[0-9a-f]+$": - type: object - description: Node containing the properties of DPU. + ports: + $ref: /schemas/graph.yaml#/properties/ports + description: | + Contains the list of output ports from DPU device. These ports + connect to interfaces that are external to the DPU hardware, + such as DSI, DP etc. Each output port contains an endpoint that + describes how it is connected to an external interface. properties: - compatible: - const: qcom,sc7280-dpu - - reg: - items: - - description: Address offset and size for mdp register set - - description: Address offset and size for vbif register set - - reg-names: - items: - - const: mdp - - const: vbif - - clocks: - items: - - description: Display hf axi clock - - description: Display sf axi clock - - description: Display ahb clock - - description: Display lut clock - - description: Display core clock - - description: Display vsync clock - - clock-names: - items: - - const: bus - - const: nrt_bus - - const: iface - - const: lut - - const: core - - const: vsync - - interrupts: - maxItems: 1 - - power-domains: - maxItems: 1 - - operating-points-v2: true - - ports: - $ref: /schemas/graph.yaml#/properties/ports - description: | - Contains the list of output ports from DPU device. These ports - connect to interfaces that are external to the DPU hardware, - such as DSI, DP etc. Each output port contains an endpoint that - describes how it is connected to an external interface. - - properties: - port@0: - $ref: /schemas/graph.yaml#/properties/port - description: DPU_INTF1 (DSI) - - port@1: - $ref: /schemas/graph.yaml#/properties/port - description: DPU_INTF5 (EDP) - - required: - - port@0 + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: DPU_INTF1 (DSI) + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: DPU_INTF5 (EDP) required: - - compatible - - reg - - reg-names - - clocks - - interrupts - - power-domains - - operating-points-v2 - - ports + - port@0 required: - compatible - reg - reg-names - - power-domains - clocks - interrupts - - interrupt-controller - - iommus - - ranges + - power-domains + - operating-points-v2 + - ports additionalProperties: false diff --git a/Documentation/devicetree/bindings/display/msm/mdss.yaml b/Documentation/devicetree/bindings/display/msm/mdss.yaml index f86177bb2e8c..8d748fc5359c 100644 --- a/Documentation/devicetree/bindings/display/msm/mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/mdss.yaml @@ -19,6 +19,7 @@ properties: enum: - qcom,mdss - qcom,sc7180-mdss + - qcom,sc7280-mdss - qcom,sdm845-mdss reg: @@ -147,6 +148,7 @@ allOf: contains: enum: - qcom,sc7180-mdss + - qcom,sc7280-mdss then: properties: clocks: @@ -269,6 +271,52 @@ allOf: enum: - qcom,dsi-phy-10nm + - if: + properties: + compatible: + contains: + const: qcom,sc7280-mdss + then: + patternProperties: + "^display-controller@[1-9a-f][0-9a-f]*$": + type: object + properties: + compatible: + const: qcom,sc7280-dpu + + "^displayport-controller@[1-9a-f][0-9a-f]*$": + type: object + properties: + compatible: + const: qcom,sc7280-dp + + "^dsi@[1-9a-f][0-9a-f]*$": + type: object + properties: + compatible: + const: qcom,mdss-dsi-ctrl + + "^dsi-phy@[1-9a-f][0-9a-f]*$": + type: object + properties: + compatible: + enum: + - qcom,dsi-phy-10nm + + "^edp@[1-9a-f][0-9a-f]*$": + type: object + properties: + compatible: + const: qcom,sc7280-edp + + "^phy@[1-9a-f][0-9a-f]*$": + type: object + properties: + compatible: + enum: + - qcom,sc7280-dsi-phy-7nm + - qcom,sc7280-edp-phy + - if: properties: compatible: @@ -325,12 +373,18 @@ patternProperties: "^dsi-phy@[1-9a-f][0-9a-f]*$": type: object + "^edp@[1-9a-f][0-9a-f]*$": + type: object + "^hdmi-phy@[1-9a-f][0-9a-f]*$": type: object "^hdmi-tx@[1-9a-f][0-9a-f]*$": type: object + "^phy@[1-9a-f][0-9a-f]*$": + type: object + additionalProperties: false examples: From patchwork Thu Aug 25 09:50:58 2022 Content-Type: text/plain; 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Thu, 25 Aug 2022 02:51:09 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id h10-20020a056512220a00b00492cfecf1c0sm398502lfu.245.2022.08.25.02.51.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Aug 2022 02:51:09 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Clark , Sean Paul , Abhinav Kumar , Rob Herring , Krzysztof Kozlowski Cc: Stephen Boyd , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v4 05/10] dt-bindings: display/msm: move qcom,qcm2290-mdss schema to mdss.yaml Date: Thu, 25 Aug 2022 12:50:58 +0300 Message-Id: <20220825095103.624891-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220825095103.624891-1-dmitry.baryshkov@linaro.org> References: <20220825095103.624891-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Move schema for qcom,qcm2290-mdss from dpu-qcm2290.yaml to mdss.yaml so that the dpu file describes only the DPU schema. Signed-off-by: Dmitry Baryshkov --- .../bindings/display/msm/dpu-qcm2290.yaml | 140 +++++------------- .../devicetree/bindings/display/msm/mdss.yaml | 49 ++++++ 2 files changed, 82 insertions(+), 107 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/dpu-qcm2290.yaml b/Documentation/devicetree/bindings/display/msm/dpu-qcm2290.yaml index 734d14de966d..8027319b1aad 100644 --- a/Documentation/devicetree/bindings/display/msm/dpu-qcm2290.yaml +++ b/Documentation/devicetree/bindings/display/msm/dpu-qcm2290.yaml @@ -10,146 +10,72 @@ maintainers: - Loic Poulain description: | - Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates - sub-blocks like DPU display controller and DSI. Device tree bindings of MDSS - and DPU are mentioned for QCM2290 target. + Device tree bindings for the DPU display controller for QCM2290 target. properties: compatible: items: - - const: qcom,qcm2290-mdss + - const: qcom,qcm2290-dpu reg: - maxItems: 1 + items: + - description: Address offset and size for mdp register set + - description: Address offset and size for vbif register set reg-names: - const: mdss - - power-domains: - maxItems: 1 + items: + - const: mdp + - const: vbif clocks: items: - - description: Display AHB clock from gcc - - description: Display AXI clock - - description: Display core clock + - description: Display AXI clock from gcc + - description: Display AHB clock from dispcc + - description: Display core clock from dispcc + - description: Display lut clock from dispcc + - description: Display vsync clock from dispcc clock-names: items: - - const: iface - const: bus + - const: iface - const: core + - const: lut + - const: vsync interrupts: maxItems: 1 - interrupt-controller: true - - "#address-cells": true - - "#size-cells": true - - "#interrupt-cells": - const: 1 - - iommus: - items: - - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0 - - description: Phandle to apps_smmu node with SID mask for Hard-Fail port1 - - ranges: true - - interconnects: - items: - - description: Interconnect path specifying the port ids for data bus - - interconnect-names: - const: mdp0-mem + power-domains: + maxItems: 1 - resets: - items: - - description: MDSS_CORE reset + operating-points-v2: true -patternProperties: - "^display-controller@[0-9a-f]+$": - type: object - description: Node containing the properties of DPU. + ports: + $ref: /schemas/graph.yaml#/properties/ports + description: | + Contains the list of output ports from DPU device. These ports + connect to interfaces that are external to the DPU hardware, + such as DSI. Each output port contains an endpoint that + describes how it is connected to an external interface. properties: - compatible: - items: - - const: qcom,qcm2290-dpu - - reg: - items: - - description: Address offset and size for mdp register set - - description: Address offset and size for vbif register set - - reg-names: - items: - - const: mdp - - const: vbif - - clocks: - items: - - description: Display AXI clock from gcc - - description: Display AHB clock from dispcc - - description: Display core clock from dispcc - - description: Display lut clock from dispcc - - description: Display vsync clock from dispcc - - clock-names: - items: - - const: bus - - const: iface - - const: core - - const: lut - - const: vsync - - interrupts: - maxItems: 1 - - power-domains: - maxItems: 1 - - operating-points-v2: true - - ports: - $ref: /schemas/graph.yaml#/properties/ports - description: | - Contains the list of output ports from DPU device. These ports - connect to interfaces that are external to the DPU hardware, - such as DSI. Each output port contains an endpoint that - describes how it is connected to an external interface. - - properties: - port@0: - $ref: /schemas/graph.yaml#/properties/port - description: DPU_INTF1 (DSI1) - - required: - - port@0 + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: DPU_INTF1 (DSI1) required: - - compatible - - reg - - reg-names - - clocks - - interrupts - - power-domains - - operating-points-v2 - - ports + - port@0 required: - compatible - reg - reg-names - - power-domains - clocks - interrupts - - interrupt-controller - - iommus - - ranges + - power-domains + - operating-points-v2 + - ports additionalProperties: false diff --git a/Documentation/devicetree/bindings/display/msm/mdss.yaml b/Documentation/devicetree/bindings/display/msm/mdss.yaml index 8d748fc5359c..0c6d68f2a450 100644 --- a/Documentation/devicetree/bindings/display/msm/mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/mdss.yaml @@ -18,6 +18,7 @@ properties: compatible: enum: - qcom,mdss + - qcom,qcm2290-mdss - qcom,sc7180-mdss - qcom,sc7280-mdss - qcom,sdm845-mdss @@ -142,6 +143,28 @@ allOf: required: - iommus + - if: + properties: + compatible: + contains: + const: qcom,qcm2290-mdss + then: + properties: + clocks: + items: + - description: Display AHB clock from gcc + - description: Display AXI clock + - description: Display core clock + + clock-names: + items: + - const: iface + - const: bus + - const: core + + iommus: + minItems: 2 + - if: properties: compatible: @@ -239,6 +262,32 @@ allOf: - qcom,hdmi-tx-8994 - qcom,hdmi-tx-8996 + - if: + properties: + compatible: + contains: + const: qcom,qcm2290-mdss + then: + patternProperties: + "^display-controller@[1-9a-f][0-9a-f]*$": + type: object + properties: + compatible: + const: qcom,qcm2290-dpu + + "^dsi@[1-9a-f][0-9a-f]*$": + type: object + properties: + compatible: + const: qcom,dsi-ctrl-6g-qcm2290 + + "^phy@[1-9a-f][0-9a-f]*$": + type: object + properties: + compatible: + enum: + - qcom,dsi-phy-14nm + - if: properties: compatible: From patchwork Thu Aug 25 09:50:59 2022 Content-Type: text/plain; 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Thu, 25 Aug 2022 02:51:10 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id h10-20020a056512220a00b00492cfecf1c0sm398502lfu.245.2022.08.25.02.51.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Aug 2022 02:51:10 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Clark , Sean Paul , Abhinav Kumar , Rob Herring , Krzysztof Kozlowski Cc: Stephen Boyd , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Rob Herring Subject: [PATCH v4 06/10] dt-bindings: display/msm: move qcom,msm8998-mdss schema to mdss.yaml Date: Thu, 25 Aug 2022 12:50:59 +0300 Message-Id: <20220825095103.624891-7-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220825095103.624891-1-dmitry.baryshkov@linaro.org> References: <20220825095103.624891-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Move schema for qcom,msm8998-mdss from dpu-msm8998.yaml to mdss.yaml so that the dpu file describes only the DPU schema. Reviewed-by: Rob Herring Signed-off-by: Dmitry Baryshkov --- .../bindings/display/msm/dpu-msm8998.yaml | 142 +++++------------- .../devicetree/bindings/display/msm/mdss.yaml | 49 ++++++ 2 files changed, 89 insertions(+), 102 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml b/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml index 2df64afb76e6..5caf46a1dd88 100644 --- a/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml +++ b/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml @@ -10,142 +10,80 @@ maintainers: - AngeloGioacchino Del Regno description: | - Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates - sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree - bindings of MDSS and DPU are mentioned for MSM8998 target. + Device tree bindings for the DPU display controller for MSM8998 target. properties: compatible: items: - - const: qcom,msm8998-mdss + - const: qcom,msm8998-dpu reg: - maxItems: 1 + items: + - description: Address offset and size for mdp register set + - description: Address offset and size for regdma register set + - description: Address offset and size for vbif register set + - description: Address offset and size for non-realtime vbif register set reg-names: - const: mdss - - power-domains: - maxItems: 1 + items: + - const: mdp + - const: regdma + - const: vbif + - const: vbif_nrt clocks: items: - - description: Display AHB clock - - description: Display AXI clock + - description: Display ahb clock + - description: Display axi clock + - description: Display mem-noc clock - description: Display core clock + - description: Display vsync clock clock-names: items: - const: iface - const: bus + - const: mnoc - const: core + - const: vsync interrupts: maxItems: 1 - interrupt-controller: true - - "#address-cells": true - - "#size-cells": true - - "#interrupt-cells": - const: 1 - - iommus: - items: - - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0 - - ranges: true + power-domains: + maxItems: 1 -patternProperties: - "^display-controller@[0-9a-f]+$": - type: object - description: Node containing the properties of DPU. + operating-points-v2: true + ports: + $ref: /schemas/graph.yaml#/properties/ports + description: | + Contains the list of output ports from DPU device. These ports + connect to interfaces that are external to the DPU hardware, + such as DSI, DP etc. Each output port contains an endpoint that + describes how it is connected to an external interface. properties: - compatible: - items: - - const: qcom,msm8998-dpu - - reg: - items: - - description: Address offset and size for mdp register set - - description: Address offset and size for regdma register set - - description: Address offset and size for vbif register set - - description: Address offset and size for non-realtime vbif register set - - reg-names: - items: - - const: mdp - - const: regdma - - const: vbif - - const: vbif_nrt - - clocks: - items: - - description: Display ahb clock - - description: Display axi clock - - description: Display mem-noc clock - - description: Display core clock - - description: Display vsync clock - - clock-names: - items: - - const: iface - - const: bus - - const: mnoc - - const: core - - const: vsync - - interrupts: - maxItems: 1 - - power-domains: - maxItems: 1 - - operating-points-v2: true - ports: - $ref: /schemas/graph.yaml#/properties/ports - description: | - Contains the list of output ports from DPU device. These ports - connect to interfaces that are external to the DPU hardware, - such as DSI, DP etc. Each output port contains an endpoint that - describes how it is connected to an external interface. - - properties: - port@0: - $ref: /schemas/graph.yaml#/properties/port - description: DPU_INTF1 (DSI1) - - port@1: - $ref: /schemas/graph.yaml#/properties/port - description: DPU_INTF2 (DSI2) - - required: - - port@0 - - port@1 + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: DPU_INTF1 (DSI1) + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: DPU_INTF2 (DSI2) required: - - compatible - - reg - - reg-names - - clocks - - interrupts - - power-domains - - operating-points-v2 - - ports + - port@0 + - port@1 required: - compatible - reg - reg-names - - power-domains - clocks - interrupts - - interrupt-controller - - iommus - - ranges + - power-domains + - operating-points-v2 + - ports additionalProperties: false diff --git a/Documentation/devicetree/bindings/display/msm/mdss.yaml b/Documentation/devicetree/bindings/display/msm/mdss.yaml index 0c6d68f2a450..1b469893732a 100644 --- a/Documentation/devicetree/bindings/display/msm/mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/mdss.yaml @@ -18,6 +18,7 @@ properties: compatible: enum: - qcom,mdss + - qcom,msm8998-mdss - qcom,qcm2290-mdss - qcom,sc7180-mdss - qcom,sc7280-mdss @@ -143,6 +144,28 @@ allOf: required: - iommus + - if: + properties: + compatible: + contains: + const: qcom,msm8998-mdss + then: + properties: + clocks: + items: + - description: Display AHB clock + - description: Display AXI clock + - description: Display core clock + + clock-names: + items: + - const: iface + - const: bus + - const: core + + iommus: + maxItems: 1 + - if: properties: compatible: @@ -262,6 +285,32 @@ allOf: - qcom,hdmi-tx-8994 - qcom,hdmi-tx-8996 + - if: + properties: + compatible: + contains: + const: qcom,msm8998-mdss + then: + patternProperties: + "^display-controller@[1-9a-f][0-9a-f]*$": + type: object + properties: + compatible: + const: qcom,msm8998-dpu + + "^dsi@[1-9a-f][0-9a-f]*$": + type: object + properties: + compatible: + const: qcom,mdss-dsi-ctrl + + "^phy@[1-9a-f][0-9a-f]*$": + type: object + properties: + compatible: + enum: + - qcom,dsi-phy-14nm + - if: properties: compatible: From patchwork Thu Aug 25 09:51:00 2022 Content-Type: text/plain; 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Thu, 25 Aug 2022 02:51:11 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id h10-20020a056512220a00b00492cfecf1c0sm398502lfu.245.2022.08.25.02.51.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Aug 2022 02:51:11 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Clark , Sean Paul , Abhinav Kumar , Rob Herring , Krzysztof Kozlowski Cc: Stephen Boyd , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Rob Herring Subject: [PATCH v4 07/10] dt-bindings: display/mdm: add gcc-bus clock to dpu-smd845 Date: Thu, 25 Aug 2022 12:51:00 +0300 Message-Id: <20220825095103.624891-8-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220825095103.624891-1-dmitry.baryshkov@linaro.org> References: <20220825095103.624891-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add gcc-bus clock required for the SDM845 DPU device tree node. This change was made in the commit 111c52854102 ("arm64: dts: qcom: sdm845: move bus clock to mdp node for sdm845 target"), but was not reflected in the schema. Reviewed-by: Rob Herring Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/display/msm/dpu-sdm845.yaml | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml b/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml index 2074e954372f..42ff85e80f45 100644 --- a/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml +++ b/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml @@ -29,6 +29,7 @@ properties: clocks: items: + - description: Display GCC bus clock - description: Display ahb clock - description: Display axi clock - description: Display core clock @@ -36,6 +37,7 @@ properties: clock-names: items: + - const: gcc-bus - const: iface - const: bus - const: core @@ -114,11 +116,12 @@ examples: <0x0aeb0000 0x2008>; reg-names = "mdp", "vbif"; - clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + clocks = <&gcc GCC_DISP_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, <&dispcc DISP_CC_MDSS_AXI_CLK>, <&dispcc DISP_CC_MDSS_MDP_CLK>, <&dispcc DISP_CC_MDSS_VSYNC_CLK>; - clock-names = "iface", "bus", "core", "vsync"; + clock-names = "gcc-bus", "iface", "bus", "core", "vsync"; interrupt-parent = <&mdss>; interrupts = <0>; From patchwork Thu Aug 25 09:51:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12954455 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 86576C3F6B0 for ; Thu, 25 Aug 2022 09:54:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240729AbiHYJyF (ORCPT ); Thu, 25 Aug 2022 05:54:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36144 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240706AbiHYJxm (ORCPT ); Thu, 25 Aug 2022 05:53:42 -0400 Received: from mail-lf1-x12d.google.com (mail-lf1-x12d.google.com [IPv6:2a00:1450:4864:20::12d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5281BAE23F for ; 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Note, this removes description of individual DPU port@ nodes. However such definitions add no additional value. The reg values do not correspond to hardware INTF indices. The driver discovers and binds these ports not paying any care for the order of these items. Thus just leave the reference to graph.yaml#/properties/ports and the description. Signed-off-by: Dmitry Baryshkov --- .../bindings/display/msm/dpu-common.yaml | 42 ++++++++++++++++++ .../bindings/display/msm/dpu-msm8998.yaml | 43 ++----------------- .../bindings/display/msm/dpu-qcm2290.yaml | 39 ++--------------- .../bindings/display/msm/dpu-sc7180.yaml | 43 ++----------------- .../bindings/display/msm/dpu-sc7280.yaml | 43 ++----------------- .../bindings/display/msm/dpu-sdm845.yaml | 43 ++----------------- 6 files changed, 62 insertions(+), 191 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/msm/dpu-common.yaml diff --git a/Documentation/devicetree/bindings/display/msm/dpu-common.yaml b/Documentation/devicetree/bindings/display/msm/dpu-common.yaml new file mode 100644 index 000000000000..14eda883e149 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/dpu-common.yaml @@ -0,0 +1,42 @@ +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/dpu-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display DPU dt properties (common properties) + +maintainers: + - Dmitry Baryshkov + - Krishna Manikandan + - Rob Clark + +description: | + Common properties for QCom DPU display controller. + +properties: + interrupts: + maxItems: 1 + + power-domains: + maxItems: 1 + + operating-points-v2: true + + ports: + $ref: /schemas/graph.yaml#/properties/ports + description: | + Contains the list of output ports from DPU device. These ports + connect to interfaces that are external to the DPU hardware, + such as DSI, DP etc. + +required: + - compatible + - reg + - reg-names + - clocks + - interrupts + - power-domains + - operating-points-v2 + - ports + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml b/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml index 5caf46a1dd88..158bd93a157f 100644 --- a/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml +++ b/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml @@ -47,45 +47,10 @@ properties: - const: core - const: vsync - interrupts: - maxItems: 1 - - power-domains: - maxItems: 1 - - operating-points-v2: true - ports: - $ref: /schemas/graph.yaml#/properties/ports - description: | - Contains the list of output ports from DPU device. These ports - connect to interfaces that are external to the DPU hardware, - such as DSI, DP etc. Each output port contains an endpoint that - describes how it is connected to an external interface. - - properties: - port@0: - $ref: /schemas/graph.yaml#/properties/port - description: DPU_INTF1 (DSI1) - - port@1: - $ref: /schemas/graph.yaml#/properties/port - description: DPU_INTF2 (DSI2) - - required: - - port@0 - - port@1 - -required: - - compatible - - reg - - reg-names - - clocks - - interrupts - - power-domains - - operating-points-v2 - - ports - -additionalProperties: false +allOf: + - $ref: "/schemas/display/msm/dpu-common.yaml#" + +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/display/msm/dpu-qcm2290.yaml b/Documentation/devicetree/bindings/display/msm/dpu-qcm2290.yaml index 8027319b1aad..0364261bf3d2 100644 --- a/Documentation/devicetree/bindings/display/msm/dpu-qcm2290.yaml +++ b/Documentation/devicetree/bindings/display/msm/dpu-qcm2290.yaml @@ -43,41 +43,10 @@ properties: - const: lut - const: vsync - interrupts: - maxItems: 1 - - power-domains: - maxItems: 1 - - operating-points-v2: true - - ports: - $ref: /schemas/graph.yaml#/properties/ports - description: | - Contains the list of output ports from DPU device. These ports - connect to interfaces that are external to the DPU hardware, - such as DSI. Each output port contains an endpoint that - describes how it is connected to an external interface. - - properties: - port@0: - $ref: /schemas/graph.yaml#/properties/port - description: DPU_INTF1 (DSI1) - - required: - - port@0 - -required: - - compatible - - reg - - reg-names - - clocks - - interrupts - - power-domains - - operating-points-v2 - - ports - -additionalProperties: false +allOf: + - $ref: "/schemas/display/msm/dpu-common.yaml#" + +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml b/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml index 9d4ec0b60c25..5df1f2d987c9 100644 --- a/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml +++ b/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml @@ -45,45 +45,10 @@ properties: - const: core - const: vsync - interrupts: - maxItems: 1 - - power-domains: - maxItems: 1 - - operating-points-v2: true - - ports: - $ref: /schemas/graph.yaml#/properties/ports - description: | - Contains the list of output ports from DPU device. These ports - connect to interfaces that are external to the DPU hardware, - such as DSI, DP etc. Each output port contains an endpoint that - describes how it is connected to an external interface. - - properties: - port@0: - $ref: /schemas/graph.yaml#/properties/port - description: DPU_INTF1 (DSI1) - - port@2: - $ref: /schemas/graph.yaml#/properties/port - description: DPU_INTF0 (DP) - - required: - - port@0 - -required: - - compatible - - reg - - reg-names - - clocks - - interrupts - - power-domains - - operating-points-v2 - - ports - -additionalProperties: false +allOf: + - $ref: "/schemas/display/msm/dpu-common.yaml#" + +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml b/Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml index 349a454099ad..c822da588de0 100644 --- a/Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml +++ b/Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml @@ -44,45 +44,10 @@ properties: - const: core - const: vsync - interrupts: - maxItems: 1 - - power-domains: - maxItems: 1 - - operating-points-v2: true - - ports: - $ref: /schemas/graph.yaml#/properties/ports - description: | - Contains the list of output ports from DPU device. These ports - connect to interfaces that are external to the DPU hardware, - such as DSI, DP etc. Each output port contains an endpoint that - describes how it is connected to an external interface. - - properties: - port@0: - $ref: /schemas/graph.yaml#/properties/port - description: DPU_INTF1 (DSI) - - port@1: - $ref: /schemas/graph.yaml#/properties/port - description: DPU_INTF5 (EDP) - - required: - - port@0 - -required: - - compatible - - reg - - reg-names - - clocks - - interrupts - - power-domains - - operating-points-v2 - - ports - -additionalProperties: false +allOf: + - $ref: "/schemas/display/msm/dpu-common.yaml#" + +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml b/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml index 42ff85e80f45..218c9d0f3fed 100644 --- a/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml +++ b/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml @@ -43,45 +43,10 @@ properties: - const: core - const: vsync - interrupts: - maxItems: 1 - - power-domains: - maxItems: 1 - - operating-points-v2: true - ports: - $ref: /schemas/graph.yaml#/properties/ports - description: | - Contains the list of output ports from DPU device. These ports - connect to interfaces that are external to the DPU hardware, - such as DSI, DP etc. Each output port contains an endpoint that - describes how it is connected to an external interface. - - properties: - port@0: - $ref: /schemas/graph.yaml#/properties/port - description: DPU_INTF1 (DSI1) - - port@1: - $ref: /schemas/graph.yaml#/properties/port - description: DPU_INTF2 (DSI2) - - required: - - port@0 - - port@1 - -required: - - compatible - - reg - - reg-names - - clocks - - interrupts - - power-domains - - operating-points-v2 - - ports - -additionalProperties: false +allOf: + - $ref: "/schemas/display/msm/dpu-common.yaml#" + +unevaluatedProperties: false examples: - | From patchwork Thu Aug 25 09:51:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12954456 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 12C40C64991 for ; Thu, 25 Aug 2022 09:54:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240771AbiHYJyH (ORCPT ); Thu, 25 Aug 2022 05:54:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35262 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240976AbiHYJxp (ORCPT ); Thu, 25 Aug 2022 05:53:45 -0400 Received: from mail-lj1-x232.google.com (mail-lj1-x232.google.com [IPv6:2a00:1450:4864:20::232]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8C8D5AE845 for ; Thu, 25 Aug 2022 02:51:44 -0700 (PDT) Received: by mail-lj1-x232.google.com with SMTP id d9so2818682ljl.8 for ; Thu, 25 Aug 2022 02:51:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=DmWp0uy89TPiPu8UitGlfJ4fqSkdwaIvyUKOGTjMH64=; b=F+XB9cd63aY9IouNoB5Mm0wxVzYEXXc//IevbAgG1v+ccxUbKvSfYbaM2+KG2wZhJP EA+ttydRKnlkqqNLTFaw+PXRZzuN0yn/1ivj0iJzfUVsdFlwkVmHvnD3/pmet6tcv7Vu VUAHdrYgi5HlPYnI19akMIX86ty09/ZCe3Mh8S6dhHcvtBCOpkST6qpTqZFCWXBo38vl gJR85LSm5HsGL4KnYGiD2/SMxm7qNsawswh8etaTtJNaANp7RAk9zrcEm5oXMdKxTXEt fj4On0YzP1rgRVfV3uzwDdT3VAwbzEryzc5RvRjJJJzBudLcB69C8ts9r1Uig4cawZAO j6og== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=DmWp0uy89TPiPu8UitGlfJ4fqSkdwaIvyUKOGTjMH64=; b=tUTZz/JiLgmRPP0JfdCzi15xOeODa82w4vA3duuEsjDPTCrwwa2c0CtSJRLSzML/Nr EDufJgpnpOnuI0CCHRPOKRxVtBW54FPWEh2QRHvR/dw7PuYBHUrHa7Txx7Bm1OlGj1qF PxbNxiHR1dC56wM9orVJOoiOVNd8iEGp+aq9iG38P1UZE5ZdjaJW3InjRYHMqhnko23u UmWt4CCY33bsw8hkKd4OE8CeZ655PKyCFt92WX3rJwKrbXdfav1tHzpzkCNjB4E/00gw kHecidl8uaPtYMnSVXTbSejU/z8E5GWkcZzu5x2oAVjJLiZJaLT3y92giBeLKjNzWc/s Eh5Q== X-Gm-Message-State: ACgBeo3nsi4D1D330l0hB56ijuoPY8dwBgk3lBHa5K9hhkNWpJ3sOnYH lZq+DEvRL61qjfYTI2OWz6BGZA== X-Google-Smtp-Source: AA6agR6hyi4jQGGTPThz5bMq67PFnK9qnxRl0rMJwYMP8RA5+UGh7yGLAWfRmT/+N66e4+Li5MG7xA== X-Received: by 2002:a2e:9e56:0:b0:261:7544:d79d with SMTP id g22-20020a2e9e56000000b002617544d79dmr917898ljk.296.1661421073687; Thu, 25 Aug 2022 02:51:13 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id h10-20020a056512220a00b00492cfecf1c0sm398502lfu.245.2022.08.25.02.51.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Aug 2022 02:51:12 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Clark , Sean Paul , Abhinav Kumar , Rob Herring , Krzysztof Kozlowski Cc: Stephen Boyd , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v4 09/10] dt-bindings: display/msm/dpu-common: add opp-table property Date: Thu, 25 Aug 2022 12:51:02 +0300 Message-Id: <20220825095103.624891-10-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220825095103.624891-1-dmitry.baryshkov@linaro.org> References: <20220825095103.624891-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The display controller node can contain the opp-table describing its frequencies and OPP levels. Allow specifying the opp-table in the DPU devices. Signed-off-by: Dmitry Baryshkov --- Documentation/devicetree/bindings/display/msm/dpu-common.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/dpu-common.yaml b/Documentation/devicetree/bindings/display/msm/dpu-common.yaml index 14eda883e149..42e1616a5670 100644 --- a/Documentation/devicetree/bindings/display/msm/dpu-common.yaml +++ b/Documentation/devicetree/bindings/display/msm/dpu-common.yaml @@ -22,6 +22,9 @@ properties: operating-points-v2: true + opp-table: + type: object + ports: $ref: /schemas/graph.yaml#/properties/ports description: | From patchwork Thu Aug 25 09:51:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12954457 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BD89EC04AA5 for ; Thu, 25 Aug 2022 09:54:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240939AbiHYJyI (ORCPT ); Thu, 25 Aug 2022 05:54:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36240 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240986AbiHYJxp (ORCPT ); Thu, 25 Aug 2022 05:53:45 -0400 Received: from mail-lj1-x229.google.com (mail-lj1-x229.google.com [IPv6:2a00:1450:4864:20::229]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5AD7CAE84F for ; Thu, 25 Aug 2022 02:51:46 -0700 (PDT) Received: by mail-lj1-x229.google.com with SMTP id bx38so18866863ljb.10 for ; Thu, 25 Aug 2022 02:51:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=DvaJK17gV4B+bl1ZbEWU+oqW67fAbVfCADxcKfyU+fo=; b=jrMX2sKeb7fmWWgdwU0PRGp30JE12BX2p6j9usPnDrXjswJ4bzVW1QN3IlrPHB62Bi +EFnKvG7IvmbLuwH4GiwE2lrxqWAUCT6nk1vVWJlPSGkwMh+CqVpZwkOw9MGxIyghOWG c6I7mhb7EPuxMwtG2InqAxOCsfKCjOUpJ5v8uBazJEdiDtbVyrc22rrbpbVVazy1e9Pn 8RWOnSABSUWvSzKr8KqT/gD5zeUgri2Fx4v6K0YE7yrk3ICuVMgfSsMuCE23gku0kQWQ HC6R1yJRJdZDWFOE49kEHMX+aI0ArOyaY0j+ucltO6vQjFr81G+RRj4zgJDJxc2othN1 48Lg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=DvaJK17gV4B+bl1ZbEWU+oqW67fAbVfCADxcKfyU+fo=; b=Alzotd/XySzDvLPTi1LvGc9lyx9y3y188tpm++N0756B1tp8/wxUfr5P/OR4mFQwAC RVqJ6qczjbRHb+SlzMDkFqxA0chN0eKYRSWyNOsD4Ag0pRy2G/0JBPlA5R5sfVk3vcvz cyTOtxP3M1syDS1nBjqz29RpY/HP2aWuulfohWG6N4fiWaIBeJKee59WHbkv4Ek8qLff XQjd+kHQ6PBKP6xlYQ5Hr3YbjL3pB0bY5GRGbG5NEeNl25uwcV/2CDAHWiXpXwDHsBPk BDZSvPyQlUUPv6yzBgk3Zjin36L7Nn/s4L3VH/IRQpxNxWJ7Is5bmNvWr/wq82r9iYPg Qe6Q== X-Gm-Message-State: ACgBeo1KTIywGX+3JwwT+C+y5NTZreK6IwC/mzjlBMSuu7KTqP6TputA EWTKgRfDzs8R+/scFqWL/x4qlw== X-Google-Smtp-Source: AA6agR6YfoBwsTqR20ybFZO3sNncqpFoke6wtT679ceGxCwxo1h5VJwbmkf3yMwRokjXS5wG7ZrvsA== X-Received: by 2002:a2e:84d7:0:b0:261:e692:511a with SMTP id q23-20020a2e84d7000000b00261e692511amr847690ljh.32.1661421074575; Thu, 25 Aug 2022 02:51:14 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id h10-20020a056512220a00b00492cfecf1c0sm398502lfu.245.2022.08.25.02.51.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Aug 2022 02:51:14 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Clark , Sean Paul , Abhinav Kumar , Rob Herring , Krzysztof Kozlowski Cc: Stephen Boyd , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v4 10/10] dt-bindings: display/msm: add support for the display on SM8250 Date: Thu, 25 Aug 2022 12:51:03 +0300 Message-Id: <20220825095103.624891-11-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220825095103.624891-1-dmitry.baryshkov@linaro.org> References: <20220825095103.624891-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add DPU schema and extend MDSS schema to describe MDSS and DPU blocks on Qualcomm SM8250 platform. Signed-off-by: Dmitry Baryshkov --- .../bindings/display/msm/dpu-sm8250.yaml | 123 ++++++++++++++++++ .../devicetree/bindings/display/msm/mdss.yaml | 51 ++++++++ 2 files changed, 174 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/msm/dpu-sm8250.yaml diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sm8250.yaml b/Documentation/devicetree/bindings/display/msm/dpu-sm8250.yaml new file mode 100644 index 000000000000..26e71a0feb96 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/dpu-sm8250.yaml @@ -0,0 +1,123 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/dpu-sm8250.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display DPU dt properties for SM8250 + +maintainers: + - Dmitry Baryshkov + +description: | + Device tree bindings for the DPU display controller for SM8250 target. + +properties: + compatible: + const: qcom,sm8250-dpu + + reg: + items: + - description: Address offset and size for mdp register set + - description: Address offset and size for vbif register set + + reg-names: + items: + - const: mdp + - const: vbif + + clocks: + items: + - description: Display ahb clock + - description: Display hf axi clock + - description: Display core clock + - description: Display vsync clock + + clock-names: + items: + - const: iface + - const: bus + - const: core + - const: vsync + +allOf: + - $ref: "/schemas/display/msm/dpu-common.yaml#" + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + mdss@ae00000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,sm8250-mdss"; + reg = <0x0ae00000 0x1000>; + reg-names = "mdss"; + + interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>, + <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>; + interconnect-names = "mdp0-mem", "mdp1-mem"; + + power-domains = <&dispcc MDSS_GDSC>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "bus", "nrt_bus", "core"; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x820 0x402>; + ranges; + + display-controller@ae01000 { + compatible = "qcom,sm8250-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "iface", "bus", "core", "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd SM8250_MMCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/display/msm/mdss.yaml b/Documentation/devicetree/bindings/display/msm/mdss.yaml index 1b469893732a..57fa8dedc82b 100644 --- a/Documentation/devicetree/bindings/display/msm/mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/mdss.yaml @@ -23,6 +23,7 @@ properties: - qcom,sc7180-mdss - qcom,sc7280-mdss - qcom,sdm845-mdss + - qcom,sm8250-mdss reg: minItems: 1 @@ -232,6 +233,30 @@ allOf: iommus: minItems: 2 + - if: + properties: + compatible: + contains: + const: qcom,sm8250-mdss + then: + properties: + clocks: + items: + - description: Display AHB clock + - description: Display hf axi clock + - description: Display sf axi clock + - description: Display core clock + + clock-names: + items: + - const: iface + - const: bus + - const: nrt_bus + - const: core + + iommus: + minItems: 1 + - if: properties: compatible: @@ -441,6 +466,32 @@ allOf: enum: - qcom,dsi-phy-10nm + - if: + properties: + compatible: + contains: + const: qcom,sm8250-mdss + then: + patternProperties: + "^display-controller@[1-9a-f][0-9a-f]*$": + type: object + properties: + compatible: + const: qcom,sm8250-dpu + + "^dsi@[1-9a-f][0-9a-f]*$": + type: object + properties: + compatible: + const: qcom,mdss-dsi-ctrl + + "^dsi-phy@[1-9a-f][0-9a-f]*$": + type: object + properties: + compatible: + enum: + - qcom,dsi-phy-7nm + required: - compatible - reg