From patchwork Thu Aug 25 16:07:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Jiang X-Patchwork-Id: 12955034 X-Patchwork-Delegate: dan.j.williams@gmail.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BEAC3ECAA24 for ; Thu, 25 Aug 2022 16:09:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237841AbiHYQJM (ORCPT ); Thu, 25 Aug 2022 12:09:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50864 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242947AbiHYQJI (ORCPT ); Thu, 25 Aug 2022 12:09:08 -0400 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0B211B941B for ; Thu, 25 Aug 2022 09:09:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1661443748; x=1692979748; h=subject:from:to:cc:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=DXPAPk5sgimghpSz3bZw0wPQ8/s6bGtqJP4TlhHMeEo=; b=AhaZroBNmcdBq2PdHV0JnrIhL+PG9kIuD3zRmck00BBcy+7txKLFBsLO CpGSFUpGepQwIjDXFqj5TD+vQ10FoLTG4yooTYG7C0chtTqAqeoc2pnUK YVgJF3CyhdOjSXoS4sz0ZHfb1dcRLFQy+3vLJISbfedHRs7kJbe3aNi6v TBo5Xr8h9pKd/+W0rpU66ZLTTqh44FjWjESP9deZdahAVveLm/jYKjgeM CbX2ddnJdhOifaRlatf+FAuuzjApAXHT0gzHsdOQGpLMsUsoPbKZMZ8Ei WMYgfBDgMBH0/Em0MBV8cIjO/WauCph0OtMCcI7LgUMbwVDe/f7bBN2bS A==; X-IronPort-AV: E=McAfee;i="6500,9779,10450"; a="274034747" X-IronPort-AV: E=Sophos;i="5.93,263,1654585200"; d="scan'208";a="274034747" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Aug 2022 09:07:41 -0700 X-IronPort-AV: E=Sophos;i="5.93,263,1654585200"; d="scan'208";a="586932563" Received: from djiang5-desk3.ch.intel.com ([143.182.136.137]) by orsmga006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Aug 2022 09:07:40 -0700 Subject: [PATCH v5 1/6] cxl: Add check for result of interleave ways plus granularity combo From: Dave Jiang To: linux-cxl@vger.kernel.org Cc: dan.j.williams@intel.com, vishal.l.verma@intel.com, ira.weiny@intel.com, alison.schofield@intel.com, Jonathan.Cameron@huawei.com Date: Thu, 25 Aug 2022 09:07:40 -0700 Message-ID: <166144366038.745916.13425367025352369885.stgit@djiang5-desk3.ch.intel.com> In-Reply-To: <166144343809.745916.16054560464363829844.stgit@djiang5-desk3.ch.intel.com> References: <166144343809.745916.16054560464363829844.stgit@djiang5-desk3.ch.intel.com> User-Agent: StGit/1.4 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org Add a helper function to check the combination of interleave ways and interleave granularity together is sane against the interleave mask from the HDM decoder. Add the check to cxl_region_attach() to make sure the region config is sane. Add the check to cxl_port_setup_targets() to make sure the port setup config is also sane. Calculation refers to CXL spec rev3.0 8.2.4.19.13 implementation note #3. Reviewed-by: Dan Williams Signed-off-by: Dave Jiang Reviewed-by: Jonathan Cameron --- drivers/cxl/core/region.c | 47 +++++++++++++++++++++++++++++++++++++++++- tools/testing/cxl/test/cxl.c | 1 + 2 files changed, 47 insertions(+), 1 deletion(-) diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c index 401148016978..28272b0196e6 100644 --- a/drivers/cxl/core/region.c +++ b/drivers/cxl/core/region.c @@ -940,6 +940,42 @@ static int check_last_peer(struct cxl_endpoint_decoder *cxled, return 0; } +static int cxl_interleave_capable(struct cxl_port *port, struct device *dev, + int ways, int granularity) +{ + struct cxl_hdm *cxlhdm = dev_get_drvdata(&port->dev); + unsigned int addr_mask; + u16 eig; + u8 eiw; + int rc; + + rc = granularity_to_cxl(granularity, &eig); + if (rc) + return rc; + + rc = ways_to_cxl(ways, &eiw); + if (rc) + return rc; + + if (eiw == 0) + return 0; + + if (is_power_of_2(eiw)) + addr_mask = GENMASK(eig + 8 + eiw - 1, eig + 8); + else + addr_mask = GENMASK((eig + eiw) / 3 - 1, eig + 8); + + if (~cxlhdm->interleave_mask & addr_mask) { + dev_dbg(dev, + "%s:%s interleave (eig: %d eiw: %d mask: %#x) exceed cap (mask: %#x)\n", + dev_name(port->uport), dev_name(&port->dev), eig, eiw, + cxlhdm->interleave_mask, addr_mask); + return -EINVAL; + } + + return 0; +} + static int cxl_port_setup_targets(struct cxl_port *port, struct cxl_region *cxlr, struct cxl_endpoint_decoder *cxled) @@ -1047,6 +1083,10 @@ static int cxl_port_setup_targets(struct cxl_port *port, return rc; } + rc = cxl_interleave_capable(port, &cxlr->dev, iw, ig); + if (rc) + return rc; + cxld->interleave_ways = iw; cxld->interleave_granularity = ig; cxld->hpa_range = (struct range) { @@ -1196,6 +1236,12 @@ static int cxl_region_attach(struct cxl_region *cxlr, return -EBUSY; } + ep_port = cxled_to_port(cxled); + rc = cxl_interleave_capable(ep_port, &cxlr->dev, p->interleave_ways, + p->interleave_granularity); + if (rc) + return rc; + for (i = 0; i < p->interleave_ways; i++) { struct cxl_endpoint_decoder *cxled_target; struct cxl_memdev *cxlmd_target; @@ -1214,7 +1260,6 @@ static int cxl_region_attach(struct cxl_region *cxlr, } } - ep_port = cxled_to_port(cxled); root_port = cxlrd_to_port(cxlrd); dport = cxl_find_dport_by_dev(root_port, ep_port->host_bridge); if (!dport) { diff --git a/tools/testing/cxl/test/cxl.c b/tools/testing/cxl/test/cxl.c index a072b2d3e726..4b361ed63333 100644 --- a/tools/testing/cxl/test/cxl.c +++ b/tools/testing/cxl/test/cxl.c @@ -398,6 +398,7 @@ static struct cxl_hdm *mock_cxl_setup_hdm(struct cxl_port *port) return ERR_PTR(-ENOMEM); cxlhdm->port = port; + dev_set_drvdata(&port->dev, cxlhdm); return cxlhdm; } From patchwork Thu Aug 25 16:07:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Jiang X-Patchwork-Id: 12955037 X-Patchwork-Delegate: dan.j.williams@gmail.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 31E4BECAA24 for ; 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X-IronPort-AV: E=McAfee;i="6500,9779,10450"; a="320362968" X-IronPort-AV: E=Sophos;i="5.93,263,1654585200"; d="scan'208";a="320362968" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Aug 2022 09:07:47 -0700 X-IronPort-AV: E=Sophos;i="5.93,263,1654585200"; d="scan'208";a="678517822" Received: from djiang5-desk3.ch.intel.com ([143.182.136.137]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Aug 2022 09:07:46 -0700 Subject: [PATCH v5 2/6] cxl: Add CXL spec v3.0 interleave support From: Dave Jiang To: linux-cxl@vger.kernel.org Cc: dan.j.williams@intel.com, vishal.l.verma@intel.com, ira.weiny@intel.com, alison.schofield@intel.com, Jonathan.Cameron@huawei.com Date: Thu, 25 Aug 2022 09:07:46 -0700 Message-ID: <166144366619.745916.10798926478044975266.stgit@djiang5-desk3.ch.intel.com> In-Reply-To: <166144343809.745916.16054560464363829844.stgit@djiang5-desk3.ch.intel.com> References: <166144343809.745916.16054560464363829844.stgit@djiang5-desk3.ch.intel.com> User-Agent: StGit/1.4 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org CXL spec rev3.0 added 2 CAP bits to the CXL HDM Decoder Capability Register. CXL spec rev3.0 8.2.4.19.1. Bit 11 indicates that 3, 6, and 12 way interleave is capable. Bit 12 indicates that 16 way interleave is capable. Add code to parse_hdm_decoder_caps() to cache those new bits. Add check in cxl_interleave_capable() call to make sure those CAP bits matches the passed in interleave value. Reviewed-by: Dan Williams Reviewed-by: Jonathan Cameron Signed-off-by: Dave Jiang --- drivers/cxl/core/hdm.c | 6 ++++++ drivers/cxl/core/region.c | 3 +++ drivers/cxl/cxl.h | 2 ++ drivers/cxl/cxlmem.h | 5 +++++ 4 files changed, 16 insertions(+) diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c index d1d2caea5c62..51d8cbcdace1 100644 --- a/drivers/cxl/core/hdm.c +++ b/drivers/cxl/core/hdm.c @@ -80,6 +80,12 @@ static void parse_hdm_decoder_caps(struct cxl_hdm *cxlhdm) cxlhdm->interleave_mask |= GENMASK(11, 8); if (FIELD_GET(CXL_HDM_DECODER_INTERLEAVE_14_12, hdm_cap)) cxlhdm->interleave_mask |= GENMASK(14, 12); + + cxlhdm->interleave_cap = CXL_HDM_INTERLEAVE_CAP_BASELINE; + if (FIELD_GET(CXL_HDM_DECODER_INTERLEAVE_3_6_12_WAY, hdm_cap)) + cxlhdm->interleave_cap |= CXL_HDM_INTERLEAVE_CAP_3_6_12; + if (FIELD_GET(CXL_HDM_DECODER_INTERLEAVE_16_WAY, hdm_cap)) + cxlhdm->interleave_cap |= CXL_HDM_INTERLEAVE_CAP_16; } static void __iomem *map_hdm_decoder_regs(struct cxl_port *port, diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c index 28272b0196e6..9851ab2782f2 100644 --- a/drivers/cxl/core/region.c +++ b/drivers/cxl/core/region.c @@ -960,6 +960,9 @@ static int cxl_interleave_capable(struct cxl_port *port, struct device *dev, if (eiw == 0) return 0; + if (!test_bit(ways, &cxlhdm->interleave_cap)) + return -EINVAL; + if (is_power_of_2(eiw)) addr_mask = GENMASK(eig + 8 + eiw - 1, eig + 8); else diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index f680450f0b16..11f2a14f42eb 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -42,6 +42,8 @@ #define CXL_HDM_DECODER_TARGET_COUNT_MASK GENMASK(7, 4) #define CXL_HDM_DECODER_INTERLEAVE_11_8 BIT(8) #define CXL_HDM_DECODER_INTERLEAVE_14_12 BIT(9) +#define CXL_HDM_DECODER_INTERLEAVE_3_6_12_WAY BIT(11) +#define CXL_HDM_DECODER_INTERLEAVE_16_WAY BIT(12) #define CXL_HDM_DECODER_CTRL_OFFSET 0x4 #define CXL_HDM_DECODER_ENABLE BIT(1) #define CXL_HDM_DECODER0_BASE_LOW_OFFSET(i) (0x20 * (i) + 0x10) diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h index 88e3a8e54b6a..5a147ce70f4c 100644 --- a/drivers/cxl/cxlmem.h +++ b/drivers/cxl/cxlmem.h @@ -393,11 +393,16 @@ static inline void cxl_mem_active_dec(void) } #endif +#define CXL_HDM_INTERLEAVE_CAP_BASELINE BIT(1) | BIT(2) | BIT(4) | BIT(8) +#define CXL_HDM_INTERLEAVE_CAP_3_6_12 BIT(3) | BIT(6) | BIT(12) +#define CXL_HDM_INTERLEAVE_CAP_16 BIT(16) + struct cxl_hdm { struct cxl_component_regs regs; unsigned int decoder_count; unsigned int target_count; unsigned int interleave_mask; + unsigned long interleave_cap; struct cxl_port *port; }; From patchwork Thu Aug 25 16:07:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Jiang X-Patchwork-Id: 12955035 X-Patchwork-Delegate: dan.j.williams@gmail.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 943F7ECAA24 for ; Thu, 25 Aug 2022 16:09:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236857AbiHYQJS (ORCPT ); Thu, 25 Aug 2022 12:09:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51194 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242959AbiHYQJP (ORCPT ); Thu, 25 Aug 2022 12:09:15 -0400 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3B518B943D for ; Thu, 25 Aug 2022 09:09:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1661443755; x=1692979755; h=subject:from:to:cc:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=iojtyF3+UVw9VQBCGoZrJ+6EfM3nRg8+vvuPRr7Cafk=; b=KD5pjAyywxc4R534S19jtTJ34AnlecevR+euxB4/0amWTRYU/5olIiEV +rvM7d7vVugMixLw+/bUh+oSo59LbOMv64zLCN14BTctRUkHBNprUmwf2 8QbfVtLut+ffcGpqGpQCQNTgiMjfAcAXjk9tiZ+aDTIcTZFSm5isSTLVL bjeAOSlQZMY3QOR7mG/WjZM4KR2Efrw8u6rCNiAzOgEUY5bOKDPpMm5E+ KYur24MTUrbO1EyMX7HEBn9K9TNTy40+4TVdy50VYvrHCOCjgLlSbF2Gq jMIlM19u+AIGTf5TCNS2BxuLY0Jb29u0R4w0BwxBB+8sfL3bUVZbNGvpo A==; X-IronPort-AV: E=McAfee;i="6500,9779,10450"; a="274034821" X-IronPort-AV: E=Sophos;i="5.93,263,1654585200"; d="scan'208";a="274034821" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Aug 2022 09:07:53 -0700 X-IronPort-AV: E=Sophos;i="5.93,263,1654585200"; d="scan'208";a="639661045" Received: from djiang5-desk3.ch.intel.com ([143.182.136.137]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Aug 2022 09:07:52 -0700 Subject: [PATCH v5 3/6] tools/testing/cxl: Add interleave check support to mock cxl port device From: Dave Jiang To: linux-cxl@vger.kernel.org Cc: dan.j.williams@intel.com, vishal.l.verma@intel.com, ira.weiny@intel.com, alison.schofield@intel.com, Jonathan.Cameron@huawei.com Date: Thu, 25 Aug 2022 09:07:51 -0700 Message-ID: <166144367188.745916.2815396662040037518.stgit@djiang5-desk3.ch.intel.com> In-Reply-To: <166144343809.745916.16054560464363829844.stgit@djiang5-desk3.ch.intel.com> References: <166144343809.745916.16054560464363829844.stgit@djiang5-desk3.ch.intel.com> User-Agent: StGit/1.4 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org Attach the cxl mock hdm to the port device to allow cxl_interleave_capable() to check the interleave configuration. Set the interleave_mask as well to support the new verification code. Reviewed-by: Dan Williams Signed-off-by: Dave Jiang Reviewed-by: Jonathan Cameron --- tools/testing/cxl/test/cxl.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tools/testing/cxl/test/cxl.c b/tools/testing/cxl/test/cxl.c index 4b361ed63333..85000d1b5812 100644 --- a/tools/testing/cxl/test/cxl.c +++ b/tools/testing/cxl/test/cxl.c @@ -398,6 +398,8 @@ static struct cxl_hdm *mock_cxl_setup_hdm(struct cxl_port *port) return ERR_PTR(-ENOMEM); cxlhdm->port = port; + cxlhdm->interleave_mask = GENMASK(14, 8); + cxlhdm->interleave_cap = CXL_HDM_INTERLEAVE_CAP_BASELINE; dev_set_drvdata(&port->dev, cxlhdm); return cxlhdm; } From patchwork Thu Aug 25 16:07:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Jiang X-Patchwork-Id: 12955038 X-Patchwork-Delegate: dan.j.williams@gmail.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 806C0ECAA24 for ; Thu, 25 Aug 2022 16:10:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242760AbiHYQKO (ORCPT ); Thu, 25 Aug 2022 12:10:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52720 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241072AbiHYQKN (ORCPT ); Thu, 25 Aug 2022 12:10:13 -0400 Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3A9C3CE11 for ; Thu, 25 Aug 2022 09:10:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1661443812; x=1692979812; h=subject:from:to:cc:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=n7s4QvRWLEp7QXMJUGXcz/kCCPoUkloZTOlE+KDhw9U=; b=BtuthD4dviIJmWINlt+qRflN552rK3ZfAcogJ1uZCI7dT+2fwxEm+6wA OKlDHBdVAsQyGk4+IzqD68vCAU3azspTHCSCR9YU6c8GO5eZ4wDF/LcaM BKHZ9cv1riov1rMYU68ln/uMo/TKT9SUeQX7AoEEC8UJsdyn2fdJJx8HD JCuQHqt8421bQ5toPEevmkeeSuwKkoYy+MKTR8sy+tAdCUWeo1cuCwcGC qRjWrHZkVHh/yzJNIgz9XtekBQJ5H4KdT0U21oY5dWdqapKIxb7e14cWb UiGD3LhXFGgHJSSd9ISI5gXhkULuvSlLSci0S3hGIxdmoOkOjRd/62K0r g==; X-IronPort-AV: E=McAfee;i="6500,9779,10450"; a="320363062" X-IronPort-AV: E=Sophos;i="5.93,263,1654585200"; d="scan'208";a="320363062" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Aug 2022 09:07:59 -0700 X-IronPort-AV: E=Sophos;i="5.93,263,1654585200"; d="scan'208";a="713555716" Received: from djiang5-desk3.ch.intel.com ([143.182.136.137]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Aug 2022 09:07:58 -0700 Subject: [PATCH v5 4/6] cxl: change cxl_port_attribute_groups naming to avoid confusion From: Dave Jiang To: linux-cxl@vger.kernel.org Cc: dan.j.williams@intel.com, vishal.l.verma@intel.com, ira.weiny@intel.com, alison.schofield@intel.com, Jonathan.Cameron@huawei.com Date: Thu, 25 Aug 2022 09:07:58 -0700 Message-ID: <166144367858.745916.5617777347082312832.stgit@djiang5-desk3.ch.intel.com> In-Reply-To: <166144343809.745916.16054560464363829844.stgit@djiang5-desk3.ch.intel.com> References: <166144343809.745916.16054560464363829844.stgit@djiang5-desk3.ch.intel.com> User-Agent: StGit/1.4 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org Both cxl/port.c and cxl/core/port.c have cxl_port_attribute_groups. Change cxl_port_attribute_groups in cxl/port.c to cxl_port_dynamic_attr_groups in order to avoid confusion. Suggested-by: Dan Williams Reviewed-by: Jonathan Cameron Signed-off-by: Dave Jiang --- drivers/cxl/port.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c index 5453771bf330..c4aa073b7e31 100644 --- a/drivers/cxl/port.c +++ b/drivers/cxl/port.c @@ -123,7 +123,7 @@ static struct attribute_group cxl_cdat_attribute_group = { .is_bin_visible = cxl_port_bin_attr_is_visible, }; -static const struct attribute_group *cxl_port_attribute_groups[] = { +static const struct attribute_group *cxl_port_dynamic_attr_groups[] = { &cxl_cdat_attribute_group, NULL, }; @@ -133,7 +133,7 @@ static struct cxl_driver cxl_port_driver = { .probe = cxl_port_probe, .id = CXL_DEVICE_PORT, .drv = { - .dev_groups = cxl_port_attribute_groups, + .dev_groups = cxl_port_dynamic_attr_groups, }, }; From patchwork Thu Aug 25 16:08:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Jiang X-Patchwork-Id: 12955036 X-Patchwork-Delegate: dan.j.williams@gmail.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9D854ECAA27 for ; Thu, 25 Aug 2022 16:09:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240732AbiHYQJs (ORCPT ); Thu, 25 Aug 2022 12:09:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51684 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242641AbiHYQJr (ORCPT ); Thu, 25 Aug 2022 12:09:47 -0400 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 965563A0 for ; Thu, 25 Aug 2022 09:09:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1661443785; x=1692979785; h=subject:from:to:cc:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=M73zOZ/B+AB8d/4ltG96fC8ys7EpI+MwPP16HFR4vTQ=; b=bkFOQDEssBEWeQJGcTdnZCfmMFGKMzxnGoMjIz42kwo4vWWwLac4Qn3Y 4qe/noThOSjKQwP/e7wKtfCHc+iItSUtKQduTRKP1RFNnC806OL+/Uis7 jtKNQAk3jAr25uaKauN+sFKoMybVFgPhUmkRRiLBrA8/MpHP5X8zFeEqn t0e5m3wYcU6/+P639FO2dCfZjtFqO7rAqrnRclVKwEefqX9zTIfoZrEyT GumQNyDaMt5jDkuLaGqVtnFCkS7v207HdOsOz/+FPbeUDJSjP2Fos0ZkM RkY4HESyTU1i+FTUWQUG+qhZAKBveHy0LDiK6/fFm/XbC2tK0RRCJ+KuM w==; X-IronPort-AV: E=McAfee;i="6500,9779,10450"; a="380574934" X-IronPort-AV: E=Sophos;i="5.93,263,1654585200"; d="scan'208";a="380574934" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Aug 2022 09:08:04 -0700 X-IronPort-AV: E=Sophos;i="5.93,263,1654585200"; d="scan'208";a="938386808" Received: from djiang5-desk3.ch.intel.com ([143.182.136.137]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Aug 2022 09:08:04 -0700 Subject: [PATCH v5 5/6] cxl: export interleave address mask as port sysfs attribute From: Dave Jiang To: linux-cxl@vger.kernel.org Cc: dan.j.williams@intel.com, vishal.l.verma@intel.com, ira.weiny@intel.com, alison.schofield@intel.com, Jonathan.Cameron@huawei.com Date: Thu, 25 Aug 2022 09:08:04 -0700 Message-ID: <166144368419.745916.8544064496236189589.stgit@djiang5-desk3.ch.intel.com> In-Reply-To: <166144343809.745916.16054560464363829844.stgit@djiang5-desk3.ch.intel.com> References: <166144343809.745916.16054560464363829844.stgit@djiang5-desk3.ch.intel.com> User-Agent: StGit/1.4 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org Export the interleave address mask as a sysfs attribute for a port. The interleave address mask is created based off the CXL HDM Decoder Capability Register (CXL spec rev3.0 8.2.4.19.1) and sets the bits indicated by the "A11to8 Interleave Capable" bit and the "A14to12 Interleave Capable" bit. It indicates the decoder supports interleaving based on those address bits. The exported sysfs attribute will help user region creation to do more valid configuration checking. Suggested-by: Dan Williams Reviewed-by: Jonathan Cameron Signed-off-by: Dave Jiang --- Documentation/ABI/testing/sysfs-bus-cxl | 11 +++++++++++ drivers/cxl/port.c | 19 +++++++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-cxl b/Documentation/ABI/testing/sysfs-bus-cxl index 8494ef27e8d2..96becbf4f7c5 100644 --- a/Documentation/ABI/testing/sysfs-bus-cxl +++ b/Documentation/ABI/testing/sysfs-bus-cxl @@ -191,6 +191,17 @@ Description: the data is 0 reading the CDAT data failed. Otherwise the CDAT data is reported. +What: /sys/bus/cxl/devices/endpointX/interleave_mask + /sys/bus/cxl/devices/portX/interleave_mask +Date: Aug, 2020 +KernelVersion: v6.1 +Contact: linux-cxl@vger.kernel.org +Description: + (RO) Interleave address mask from the HDM decoder attached to the + port. The address bits are set depending on the CXL HDM Decoder + Capability Register (CXL spec rev3.0 8.2.4.19.1) where the "A11to8 + Interleave Capable" bit and the "AA14to12 Interleave Capable" bits + are set. What: /sys/bus/cxl/devices/decoderX.Y/mode Date: May, 2022 diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c index c4aa073b7e31..0ca81f94b267 100644 --- a/drivers/cxl/port.c +++ b/drivers/cxl/port.c @@ -123,8 +123,27 @@ static struct attribute_group cxl_cdat_attribute_group = { .is_bin_visible = cxl_port_bin_attr_is_visible, }; +static ssize_t interleave_mask_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct cxl_hdm *cxlhdm = dev_get_drvdata(dev); + + return sysfs_emit(buf, "%#x\n", cxlhdm->interleave_mask); +} +static DEVICE_ATTR_RO(interleave_mask); + +static struct attribute *cxl_port_info_attributes[] = { + &dev_attr_interleave_mask.attr, + NULL +}; + +static struct attribute_group cxl_port_info_attribute_group = { + .attrs = cxl_port_info_attributes, +}; + static const struct attribute_group *cxl_port_dynamic_attr_groups[] = { &cxl_cdat_attribute_group, + &cxl_port_info_attribute_group, NULL, }; From patchwork Thu Aug 25 16:08:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Jiang X-Patchwork-Id: 12955033 X-Patchwork-Delegate: dan.j.williams@gmail.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BA8DCECAA25 for ; Thu, 25 Aug 2022 16:08:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239640AbiHYQIl (ORCPT ); Thu, 25 Aug 2022 12:08:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50424 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237841AbiHYQIl (ORCPT ); Thu, 25 Aug 2022 12:08:41 -0400 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 27CB7B2CE3 for ; Thu, 25 Aug 2022 09:08:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1661443720; x=1692979720; h=subject:from:to:cc:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=xkfCp7LYmNdkgX5sp6jWftzcjyUMKzlNCZ99re74Wq8=; b=YjzlCvMp9cQ49QwDV8t5YlCCqRBH80Hd2K/kJU89wgJcfOxlgWmqs3WJ /22JOhIeyTiu7PQPV2OGiZP7z8CvcTbta3zarti8YnbZkSKvOln3y1f7z q9Z2LoDBHLCg5ld5qqop1omSj9PCUb6C44nZqBr2ohugOQ4f8Px22tnBO vWr8ajNHzLugdN+H6/YUjhFcbkTB/HiGNPe24dpceFxxYEuletJmR9Adm sGvBD1MQ8xQNnYRyXdlXxbmN9GSdZzBkkAilrz7Zu9M729P0nfAq7u65I uq8V7WJYXT78qk+djTcdDduHEVDhPj685cGU9ZX485q6lVPdiClQ0ze6i g==; X-IronPort-AV: E=McAfee;i="6500,9779,10450"; a="295061488" X-IronPort-AV: E=Sophos;i="5.93,263,1654585200"; d="scan'208";a="295061488" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Aug 2022 09:08:11 -0700 X-IronPort-AV: E=Sophos;i="5.93,263,1654585200"; d="scan'208";a="786058040" Received: from djiang5-desk3.ch.intel.com ([143.182.136.137]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Aug 2022 09:08:11 -0700 Subject: [PATCH v5 6/6] cxl: export intereleave capability as port sysfs attribute From: Dave Jiang To: linux-cxl@vger.kernel.org Cc: dan.j.williams@intel.com, vishal.l.verma@intel.com, ira.weiny@intel.com, alison.schofield@intel.com, Jonathan.Cameron@huawei.com Date: Thu, 25 Aug 2022 09:08:09 -0700 Message-ID: <166144368990.745916.1792181347596381868.stgit@djiang5-desk3.ch.intel.com> In-Reply-To: <166144343809.745916.16054560464363829844.stgit@djiang5-desk3.ch.intel.com> References: <166144343809.745916.16054560464363829844.stgit@djiang5-desk3.ch.intel.com> User-Agent: StGit/1.4 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org Export the interleave capability as a sysfs attribute for a port. The exported mask is interpreted from the CXL HDM Decoder Capability Register (CXL spec rev3.0 8.2.4.19.1). Each bit in the mask represents the number of interleave ways the decoder supports. For example, CXL devices designed from CXL spec v2.0 supports 1, 2, 4, and 8 interleave ways. The exported mask would show 0x116. The exported sysfs attribute will help user region creation to do more valid configuration checking. Suggested-by: Dan Williams Reviewed-by: Jonathan Cameron Signed-off-by: Dave Jiang --- Documentation/ABI/testing/sysfs-bus-cxl | 13 +++++++++++++ drivers/cxl/port.c | 10 ++++++++++ 2 files changed, 23 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-cxl b/Documentation/ABI/testing/sysfs-bus-cxl index 96becbf4f7c5..0fce54d962bd 100644 --- a/Documentation/ABI/testing/sysfs-bus-cxl +++ b/Documentation/ABI/testing/sysfs-bus-cxl @@ -203,6 +203,19 @@ Description: Interleave Capable" bit and the "AA14to12 Interleave Capable" bits are set. +What: /sys/bus/cxl/devices/endpointX/interleave_cap + /sys/bus/cxl/devices/portX/interleave_cap +Date: Aug, 2020 +KernelVersion: v6.1 +Contact: linux-cxl@vger.kernel.org +Description: + (RO) Interleave capability mask from the HDM decoder attached to the + port. Each bit in the mask represents the number of interleave ways + the decoder supports. For CXL devices designed from CXL spec rev2.0 or + earlier, 1, 2, 4, and 8 interleave ways are supported. With CXL spec + v3.0 or later, the capability register (CXL spec rev3 8.2.4.19.1) + indicates 3, 6, and 12 ways supported or 16 ways supported. + What: /sys/bus/cxl/devices/decoderX.Y/mode Date: May, 2022 KernelVersion: v5.20 diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c index 0ca81f94b267..4dee8b8c416f 100644 --- a/drivers/cxl/port.c +++ b/drivers/cxl/port.c @@ -132,8 +132,18 @@ static ssize_t interleave_mask_show(struct device *dev, } static DEVICE_ATTR_RO(interleave_mask); +static ssize_t interleave_cap_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct cxl_hdm *cxlhdm = dev_get_drvdata(dev); + + return sysfs_emit(buf, "%#lx\n", cxlhdm->interleave_cap); +} +static DEVICE_ATTR_RO(interleave_cap); + static struct attribute *cxl_port_info_attributes[] = { &dev_attr_interleave_mask.attr, + &dev_attr_interleave_cap.attr, NULL };