From patchwork Tue Aug 30 03:33:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abhinav Kumar X-Patchwork-Id: 12958680 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0CFEFECAAD1 for ; Tue, 30 Aug 2022 03:33:46 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DBDA710E9E0; Tue, 30 Aug 2022 03:33:39 +0000 (UTC) Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1C2E410E8A2; Tue, 30 Aug 2022 03:33:25 +0000 (UTC) Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 27TMnxwN008240; Tue, 30 Aug 2022 03:33:22 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=hGeZiiTOxpovkxzOnTmMUzW9RuF+eLieMkrJVYCT+Ao=; b=TzN7aTlkW23wP+F56gMxDSnok3Aay1g7GmB+nTYaV/On2lD3mbC8e6jjsf+PtbmgZo8J eNYwdbYVoiMeErCs5A2rMA504dRykoiLGzndgKbQ3qUA92kCtcb3AfVsCRoKzxe+41qx tmUxcfCX/gF5g5u0V3O++kyqX/zOQOCHmqhJu8GBbpZUpMd5RFFk8ZVLu4zlh6WPglgW aJ/vdfIRJ/C/r0U2bFqKB1XdLkvVatvq7uzUN1C4gynqeFhHdnoP6uW8lIEc8WiNwfsB lUR1doY1okxURlrxhegs6O5V1+KJjKvX+SOo8vJ+xZexzViKuYdhWQYTjcF+vE5r+nRR dg== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3j8x1j1yph-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 30 Aug 2022 03:33:22 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 27U3XKs0016704 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 30 Aug 2022 03:33:20 GMT Received: from abhinavk-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Mon, 29 Aug 2022 20:33:20 -0700 From: Abhinav Kumar To: Subject: [RFC PATCH 1/3] drm/msm/dpu: add max external pixel clock for all targets Date: Mon, 29 Aug 2022 20:33:07 -0700 Message-ID: <1661830389-22439-2-git-send-email-quic_abhinavk@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1661830389-22439-1-git-send-email-quic_abhinavk@quicinc.com> References: <1661830389-22439-1-git-send-email-quic_abhinavk@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: HQnPkLU-qvWGMwzs6BousUWp6FKtAdb_ X-Proofpoint-ORIG-GUID: HQnPkLU-qvWGMwzs6BousUWp6FKtAdb_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-29_13,2022-08-25_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 clxscore=1015 bulkscore=0 mlxscore=0 mlxlogscore=999 lowpriorityscore=0 adultscore=0 impostorscore=0 suspectscore=0 priorityscore=1501 malwarescore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2207270000 definitions=main-2208300015 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dianders@chromium.org, Abhinav Kumar , dri-devel@lists.freedesktop.org, swboyd@chromium.org, seanpaul@chromium.org, dmitry.baryshkov@linaro.org, quic_jesszhan@quicinc.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add maximum external pixel clock for all targets based on the advertised limits for each of them. The pixel clock has been calculated from the timings mentioned in the CEA specification for CEA modes and according to the VESA CVT standard for the others. Signed-off-by: Abhinav Kumar --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 8 ++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 ++ 2 files changed, 10 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 27f029fdc682..b04d219ac380 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -277,6 +277,7 @@ static const struct dpu_caps msm8998_dpu_caps = { .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, .max_hdeci_exp = MAX_HORZ_DECIMATION, .max_vdeci_exp = MAX_VERT_DECIMATION, + .max_ext_pclk = 594000, }; static const struct dpu_caps qcm2290_dpu_caps = { @@ -288,6 +289,7 @@ static const struct dpu_caps qcm2290_dpu_caps = { .has_idle_pc = true, .max_linewidth = 2160, .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, + .max_ext_pclk = 101250, }; static const struct dpu_caps sdm845_dpu_caps = { @@ -304,6 +306,7 @@ static const struct dpu_caps sdm845_dpu_caps = { .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, .max_hdeci_exp = MAX_HORZ_DECIMATION, .max_vdeci_exp = MAX_VERT_DECIMATION, + .max_ext_pclk = 594000, }; static const struct dpu_caps sc7180_dpu_caps = { @@ -316,6 +319,7 @@ static const struct dpu_caps sc7180_dpu_caps = { .has_idle_pc = true, .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, + .max_ext_pclk = 312250, }; static const struct dpu_caps sm8150_dpu_caps = { @@ -332,6 +336,7 @@ static const struct dpu_caps sm8150_dpu_caps = { .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, .max_hdeci_exp = MAX_HORZ_DECIMATION, .max_vdeci_exp = MAX_VERT_DECIMATION, + .max_ext_pclk = 594000, }; static const struct dpu_caps sc8180x_dpu_caps = { @@ -348,6 +353,7 @@ static const struct dpu_caps sc8180x_dpu_caps = { .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, .max_hdeci_exp = MAX_HORZ_DECIMATION, .max_vdeci_exp = MAX_VERT_DECIMATION, + .max_ext_pclk = 594000, }; static const struct dpu_caps sm8250_dpu_caps = { @@ -362,6 +368,7 @@ static const struct dpu_caps sm8250_dpu_caps = { .has_3d_merge = true, .max_linewidth = 4096, .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, + .max_ext_pclk = 594000, }; static const struct dpu_caps sc7280_dpu_caps = { @@ -374,6 +381,7 @@ static const struct dpu_caps sc7280_dpu_caps = { .has_idle_pc = true, .max_linewidth = 2400, .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, + .max_ext_pclk = 312250, }; static const struct dpu_mdp_cfg msm8998_mdp[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index 38aa38ab1568..35cab76d9530 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -370,6 +370,7 @@ struct dpu_rotation_cfg { /** * struct dpu_caps - define DPU capabilities + * @max_ext_pclk max pixel clock of the external display * @max_mixer_width max layer mixer line width support. * @max_mixer_blendstages max layer mixer blend stages or * supported z order @@ -386,6 +387,7 @@ struct dpu_rotation_cfg { * @max_vdeci_exp max vertical decimation supported (max is 2^value) */ struct dpu_caps { + int max_ext_pclk; u32 max_mixer_width; u32 max_mixer_blendstages; u32 qseed_type; From patchwork Tue Aug 30 03:33:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abhinav Kumar X-Patchwork-Id: 12958681 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5DA9AECAAD1 for ; Tue, 30 Aug 2022 03:33:51 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0D32F10E9E1; Tue, 30 Aug 2022 03:33:42 +0000 (UTC) Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0390B10E9CB; Tue, 30 Aug 2022 03:33:25 +0000 (UTC) Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 27U3F73t028677; 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Tue, 30 Aug 2022 03:33:22 GMT Received: from abhinavk-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Mon, 29 Aug 2022 20:33:21 -0700 From: Abhinav Kumar To: Subject: [RFC PATCH 2/3] drm/msm: filter out modes for DSI bridge having unsupported clock Date: Mon, 29 Aug 2022 20:33:08 -0700 Message-ID: <1661830389-22439-3-git-send-email-quic_abhinavk@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1661830389-22439-1-git-send-email-quic_abhinavk@quicinc.com> References: <1661830389-22439-1-git-send-email-quic_abhinavk@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: w28MbedrUCnN6Ag5qNbKCoWgg-BCyAWm X-Proofpoint-ORIG-GUID: w28MbedrUCnN6Ag5qNbKCoWgg-BCyAWm X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-29_13,2022-08-25_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 clxscore=1015 bulkscore=0 mlxscore=0 mlxlogscore=999 lowpriorityscore=0 adultscore=0 impostorscore=0 suspectscore=0 priorityscore=1501 malwarescore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2207270000 definitions=main-2208300015 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dianders@chromium.org, Abhinav Kumar , dri-devel@lists.freedesktop.org, swboyd@chromium.org, seanpaul@chromium.org, dmitry.baryshkov@linaro.org, quic_jesszhan@quicinc.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" DSI interface used with a bridge chip connected to an external display is subject to the same pixel clock limits as one which is natively pluggable like DisplayPort. Hence filter out DSI modes having an unsupported pixel clock if its connected to a bridge which is pluggable. Ideally, this can be accommodated into msm_dsi_modeset_init() by passing an extra parameter but this will also affect non-dpu targets. Till we add the same logic for non-dpu chipsets, lets have this as a separate call. Signed-off-by: Abhinav Kumar --- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 11 +++++++-- drivers/gpu/drm/msm/dsi/dsi.c | 5 +++++ drivers/gpu/drm/msm/dsi/dsi.h | 6 +++-- drivers/gpu/drm/msm/dsi/dsi_host.c | 40 ++++++++++++++++++++++++++++----- drivers/gpu/drm/msm/dsi/dsi_manager.c | 2 +- drivers/gpu/drm/msm/msm_drv.h | 4 ++++ 6 files changed, 58 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index 7a5fabc0fd4f..e6f7e07fd2a6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -539,7 +539,8 @@ static void dpu_kms_wait_flush(struct msm_kms *kms, unsigned crtc_mask) static int _dpu_kms_initialize_dsi(struct drm_device *dev, struct msm_drm_private *priv, - struct dpu_kms *dpu_kms) + struct dpu_kms *dpu_kms, + int max_ext_pclk) { struct drm_encoder *encoder = NULL; struct msm_display_info info; @@ -582,6 +583,8 @@ static int _dpu_kms_initialize_dsi(struct drm_device *dev, break; } + msm_dsi_set_max_extpclk(priv->dsi[i], max_ext_pclk); + info.h_tile_instance[info.num_of_h_tiles++] = i; info.is_cmd_mode = msm_dsi_is_cmd_mode(priv->dsi[i]); @@ -595,6 +598,8 @@ static int _dpu_kms_initialize_dsi(struct drm_device *dev, break; } + msm_dsi_set_max_extpclk(priv->dsi[i], max_ext_pclk); + info.h_tile_instance[info.num_of_h_tiles++] = other; } @@ -702,7 +707,9 @@ static int _dpu_kms_setup_displays(struct drm_device *dev, int rc = 0; int i; - rc = _dpu_kms_initialize_dsi(dev, priv, dpu_kms); + int max_ext_pclk = dpu_kms->catalog->caps->max_ext_pclk; + + rc = _dpu_kms_initialize_dsi(dev, priv, dpu_kms, max_ext_pclk); if (rc) { DPU_ERROR("initialize_dsi failed, rc = %d\n", rc); return rc; diff --git a/drivers/gpu/drm/msm/dsi/dsi.c b/drivers/gpu/drm/msm/dsi/dsi.c index 39bbabb5daf6..3a06a157d1b1 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.c +++ b/drivers/gpu/drm/msm/dsi/dsi.c @@ -265,6 +265,11 @@ int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev, return ret; } +void msm_dsi_set_max_extpclk(struct msm_dsi *msm_dsi, int max_ext_pclk) +{ + msm_dsi_host_set_max_extpclk(msm_dsi->host, max_ext_pclk); +} + void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi) { msm_dsi_host_snapshot(disp_state, msm_dsi->host); diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h index 2a96b4fe7839..1be4ebb0f9c8 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.h +++ b/drivers/gpu/drm/msm/dsi/dsi.h @@ -93,8 +93,9 @@ int msm_dsi_host_power_on(struct mipi_dsi_host *host, int msm_dsi_host_power_off(struct mipi_dsi_host *host); int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host, const struct drm_display_mode *mode); -enum drm_mode_status msm_dsi_host_check_dsc(struct mipi_dsi_host *host, - const struct drm_display_mode *mode); +enum drm_mode_status msm_dsi_host_mode_valid(struct mipi_dsi_host *host, + const struct drm_display_mode *mode, + struct drm_bridge *ext_bridge); unsigned long msm_dsi_host_get_mode_flags(struct mipi_dsi_host *host); int msm_dsi_host_register(struct mipi_dsi_host *host); void msm_dsi_host_unregister(struct mipi_dsi_host *host); @@ -109,6 +110,7 @@ void msm_dsi_host_get_phy_clk_req(struct mipi_dsi_host *host, void msm_dsi_host_destroy(struct mipi_dsi_host *host); int msm_dsi_host_modeset_init(struct mipi_dsi_host *host, struct drm_device *dev); +void msm_dsi_host_set_max_extpclk(struct mipi_dsi_host *host, int max_ext_pclk); int msm_dsi_host_init(struct msm_dsi *msm_dsi); int msm_dsi_runtime_suspend(struct device *dev); int msm_dsi_runtime_resume(struct device *dev); diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 57a4c0fa614b..4428a6a66ee1 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -172,6 +172,9 @@ struct msm_dsi_host { int dlane_swap; int num_data_lanes; + /* max pixel clock when used with a bridge chip */ + int max_ext_pclk; + /* from phy DT */ bool cphy_mode; @@ -2076,6 +2079,13 @@ int msm_dsi_host_modeset_init(struct mipi_dsi_host *host, return 0; } +void msm_dsi_host_set_max_extpclk(struct mipi_dsi_host *host, int max_ext_pclk) +{ + struct msm_dsi_host *msm_host = to_msm_dsi_host(host); + + msm_host->max_ext_pclk = max_ext_pclk; +} + int msm_dsi_host_register(struct mipi_dsi_host *host) { struct msm_dsi_host *msm_host = to_msm_dsi_host(host); @@ -2548,17 +2558,14 @@ int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host, return 0; } -enum drm_mode_status msm_dsi_host_check_dsc(struct mipi_dsi_host *host, - const struct drm_display_mode *mode) +static enum drm_mode_status msm_dsi_host_check_dsc(struct mipi_dsi_host *host, + const struct drm_display_mode *mode) { struct msm_dsi_host *msm_host = to_msm_dsi_host(host); struct drm_dsc_config *dsc = msm_host->dsc; int pic_width = mode->hdisplay; int pic_height = mode->vdisplay; - if (!msm_host->dsc) - return MODE_OK; - if (pic_width % dsc->slice_width) { pr_err("DSI: pic_width %d has to be multiple of slice %d\n", pic_width, dsc->slice_width); @@ -2574,6 +2581,29 @@ enum drm_mode_status msm_dsi_host_check_dsc(struct mipi_dsi_host *host, return MODE_OK; } +enum drm_mode_status msm_dsi_host_mode_valid(struct mipi_dsi_host *host, + const struct drm_display_mode *mode, + struct drm_bridge *ext_bridge) +{ + struct msm_dsi_host *msm_host = to_msm_dsi_host(host); + + /* TODO: external bridge chip with DSI having DSC */ + if (msm_host->dsc) + return msm_dsi_host_check_dsc(host, mode); + + /* TODO: add same logic for non-dpu targets */ + if (!msm_host->max_ext_pclk) + return MODE_OK; + + if (ext_bridge) { + if (ext_bridge->ops & DRM_BRIDGE_OP_HPD) + if (mode->clock > msm_host->max_ext_pclk) + return MODE_CLOCK_HIGH; + } + + return MODE_OK; +} + unsigned long msm_dsi_host_get_mode_flags(struct mipi_dsi_host *host) { return to_msm_dsi_host(host)->mode_flags; diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c b/drivers/gpu/drm/msm/dsi/dsi_manager.c index 3a1417397283..1543a0e07d5a 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_manager.c +++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c @@ -451,7 +451,7 @@ static enum drm_mode_status dsi_mgr_bridge_mode_valid(struct drm_bridge *bridge, struct msm_dsi *msm_dsi = dsi_mgr_get_dsi(id); struct mipi_dsi_host *host = msm_dsi->host; - return msm_dsi_host_check_dsc(host, mode); + return msm_dsi_host_mode_valid(host, mode, msm_dsi->external_bridge); } static const struct drm_bridge_funcs dsi_mgr_bridge_funcs = { diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index ea80846e7ac3..44d882b04327 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -281,6 +281,7 @@ void __init msm_dsi_register(void); void __exit msm_dsi_unregister(void); int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev, struct drm_encoder *encoder); +void msm_dsi_set_max_extpclk(struct msm_dsi *msm_dsi, int max_ext_pclk); void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi); bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi); bool msm_dsi_is_bonded_dsi(struct msm_dsi *msm_dsi); @@ -299,6 +300,9 @@ static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, { return -EINVAL; } +static inline void msm_dsi_set_max_extpclk(struct msm_dsi *msm_dsi, int max_ext_pclk) +{ +} static inline void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi) { } From patchwork Tue Aug 30 03:33:09 2022 Content-Type: text/plain; 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Tue, 30 Aug 2022 03:33:22 GMT Received: from abhinavk-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Mon, 29 Aug 2022 20:33:23 -0700 From: Abhinav Kumar To: Subject: [RFC PATCH 3/3] drm/msm: filter out modes for DP/eDP bridge having unsupported clock Date: Mon, 29 Aug 2022 20:33:09 -0700 Message-ID: <1661830389-22439-4-git-send-email-quic_abhinavk@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1661830389-22439-1-git-send-email-quic_abhinavk@quicinc.com> References: <1661830389-22439-1-git-send-email-quic_abhinavk@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: ZfRuI8pI0BWZ4RaHVlRvughh-m_QBed5 X-Proofpoint-ORIG-GUID: ZfRuI8pI0BWZ4RaHVlRvughh-m_QBed5 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-29_13,2022-08-25_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 clxscore=1015 bulkscore=0 mlxscore=0 mlxlogscore=999 lowpriorityscore=0 adultscore=0 impostorscore=0 suspectscore=0 priorityscore=1501 malwarescore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2207270000 definitions=main-2208300015 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dianders@chromium.org, Abhinav Kumar , dri-devel@lists.freedesktop.org, swboyd@chromium.org, seanpaul@chromium.org, dmitry.baryshkov@linaro.org, quic_jesszhan@quicinc.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Filter out DP/eDP modes having an unsupported pixel clock by replacing the current hard-coded limit with the per chipset advertised value. Signed-off-by: Abhinav Kumar --- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 7 ++++--- drivers/gpu/drm/msm/dp/dp_display.c | 16 +++++++++++++--- drivers/gpu/drm/msm/dp/dp_parser.h | 1 - drivers/gpu/drm/msm/msm_drv.h | 5 +++-- 4 files changed, 20 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index e6f7e07fd2a6..7857ce58b615 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -614,7 +614,8 @@ static int _dpu_kms_initialize_dsi(struct drm_device *dev, static int _dpu_kms_initialize_displayport(struct drm_device *dev, struct msm_drm_private *priv, - struct dpu_kms *dpu_kms) + struct dpu_kms *dpu_kms, + int max_ext_pclk) { struct drm_encoder *encoder = NULL; struct msm_display_info info; @@ -632,7 +633,7 @@ static int _dpu_kms_initialize_displayport(struct drm_device *dev, } memset(&info, 0, sizeof(info)); - rc = msm_dp_modeset_init(priv->dp[i], dev, encoder); + rc = msm_dp_modeset_init(priv->dp[i], dev, encoder, max_ext_pclk); if (rc) { DPU_ERROR("modeset_init failed for DP, rc = %d\n", rc); drm_encoder_cleanup(encoder); @@ -715,7 +716,7 @@ static int _dpu_kms_setup_displays(struct drm_device *dev, return rc; } - rc = _dpu_kms_initialize_displayport(dev, priv, dpu_kms); + rc = _dpu_kms_initialize_displayport(dev, priv, dpu_kms, max_ext_pclk); if (rc) { DPU_ERROR("initialize_DP failed, rc = %d\n", rc); return rc; diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index bfd0aeff3f0d..8b91d8adf921 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -117,6 +117,7 @@ struct dp_display_private { bool wide_bus_en; + int max_ext_pclk; struct dp_audio *audio; }; @@ -986,8 +987,15 @@ enum drm_mode_status dp_bridge_mode_valid(struct drm_bridge *bridge, if (dp->is_edp) return MODE_OK; - if (mode->clock > DP_MAX_PIXEL_CLK_KHZ) - return MODE_CLOCK_HIGH; + /* + * If DP/eDP supports HPD natively or through a bridge, need to make + * sure that we filter out the modes with pixel clock higher than the + * chipset capabilities + */ + if ((bridge->ops & DRM_BRIDGE_OP_HPD) || + (dp->next_bridge && (dp->next_bridge->ops & DRM_BRIDGE_OP_HPD))) + if (mode->clock > dp_display->max_ext_pclk) + return MODE_CLOCK_HIGH; dp_display = container_of(dp, struct dp_display_private, dp_display); link_info = &dp_display->panel->link_info; @@ -1587,7 +1595,7 @@ static int dp_display_get_next_bridge(struct msm_dp *dp) } int msm_dp_modeset_init(struct msm_dp *dp_display, struct drm_device *dev, - struct drm_encoder *encoder) + struct drm_encoder *encoder, int max_ext_pclk) { struct msm_drm_private *priv; struct dp_display_private *dp_priv; @@ -1599,6 +1607,8 @@ int msm_dp_modeset_init(struct msm_dp *dp_display, struct drm_device *dev, priv = dev->dev_private; dp_display->drm_dev = dev; + dp_priv->max_ext_pclk = max_ext_pclk; + dp_priv = container_of(dp_display, struct dp_display_private, dp_display); ret = dp_display_request_irq(dp_display); diff --git a/drivers/gpu/drm/msm/dp/dp_parser.h b/drivers/gpu/drm/msm/dp/dp_parser.h index 866c1a82bf1a..c94b793027a2 100644 --- a/drivers/gpu/drm/msm/dp/dp_parser.h +++ b/drivers/gpu/drm/msm/dp/dp_parser.h @@ -13,7 +13,6 @@ #include "msm_drv.h" #define DP_LABEL "MDSS DP DISPLAY" -#define DP_MAX_PIXEL_CLK_KHZ 675000 #define DP_MAX_NUM_DP_LANES 4 enum dp_pm_type { diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index 44d882b04327..39e8cdde6152 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -329,7 +329,7 @@ static inline struct drm_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_ int __init msm_dp_register(void); void __exit msm_dp_unregister(void); int msm_dp_modeset_init(struct msm_dp *dp_display, struct drm_device *dev, - struct drm_encoder *encoder); + struct drm_encoder *encoder, int max_ext_pclk); void msm_dp_irq_postinstall(struct msm_dp *dp_display); void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display); @@ -346,7 +346,8 @@ static inline void __exit msm_dp_unregister(void) } static inline int msm_dp_modeset_init(struct msm_dp *dp_display, struct drm_device *dev, - struct drm_encoder *encoder) + struct drm_encoder *encoder, + int max_ext_pclk) { return -EINVAL; }