From patchwork Wed Aug 31 05:18:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil P Oommen X-Patchwork-Id: 12960402 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2D09FC64991 for ; Wed, 31 Aug 2022 05:19:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231934AbiHaFT3 (ORCPT ); Wed, 31 Aug 2022 01:19:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54358 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230510AbiHaFT0 (ORCPT ); Wed, 31 Aug 2022 01:19:26 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5ADE2B5E66; Tue, 30 Aug 2022 22:19:25 -0700 (PDT) Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 27V1FugI002336; Wed, 31 Aug 2022 05:19:07 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=y5Wja1p/9P93G5DwYgWzDk04yKR4AAF3vxxCF5pAYHk=; b=SQYIBfIN+DbKxp4XCbcMYuxr+PrmsvAFidS0p3A9pQGPh3q1Dq7U3dz9gXPeGI6L4UO0 gn0wGAy+6xFnm7NZPE6AcWUD116Na5KNZegWStoQ79a9D3QoCq6PHCK01R8lP3C4N+nO vVil4H7N+hUIA+hzgkFNXMNQHVmTgQtnL5wMBv/SyaZy1OmaMEFOkF/YLH489sdfC4Qk qt7wA/x+r6CxFHMJKQIu5GX2D3x3/iFX5AyuBixq0bPfD2G9fl14/lERf4pO/ORw7Gy+ F0mphYDOrZwU+o/VOMfjc/zBibeyW46PJMT1q1ZAGCHxcIAvi3B1YxVwK5S8giUtLQWy tg== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3j9n862eay-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 31 Aug 2022 05:19:07 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 27V5J6tW029268 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 31 Aug 2022 05:19:06 GMT Received: from hyd-lnxbld559.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Tue, 30 Aug 2022 22:19:00 -0700 From: Akhil P Oommen To: freedreno , , , Rob Clark , Bjorn Andersson , "Stephen Boyd" , Dmitry Baryshkov , Philipp Zabel CC: Douglas Anderson , , Akhil P Oommen , Andy Gross , Konrad Dybcio , Krzysztof Kozlowski , Michael Turquette , Rob Herring , Stephen Boyd , , , Subject: [PATCH v6 1/6] dt-bindings: clk: qcom: Support gpu cx gdsc reset Date: Wed, 31 Aug 2022 10:48:22 +0530 Message-ID: <20220831104741.v6.1.I68b749219741db01356a42d782f74265d29a2ac3@changeid> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1661923108-789-1-git-send-email-quic_akhilpo@quicinc.com> References: <1661923108-789-1-git-send-email-quic_akhilpo@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: z7t5iSuY-9gZpeBEK57muvso-hJ2-br3 X-Proofpoint-ORIG-GUID: z7t5iSuY-9gZpeBEK57muvso-hJ2-br3 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-31_03,2022-08-30_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 suspectscore=0 impostorscore=0 adultscore=0 mlxlogscore=999 spamscore=0 clxscore=1015 phishscore=0 bulkscore=0 priorityscore=1501 mlxscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2207270000 definitions=main-2208310025 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add necessary definitions in gpucc bindings to ensure gpu cx gdsc collapse through 'reset' framework for SC7280. Signed-off-by: Akhil P Oommen Acked-by: Krzysztof Kozlowski --- (no changes since v1) include/dt-bindings/clock/qcom,gpucc-sc7280.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/dt-bindings/clock/qcom,gpucc-sc7280.h b/include/dt-bindings/clock/qcom,gpucc-sc7280.h index 669b23b..843a31b 100644 --- a/include/dt-bindings/clock/qcom,gpucc-sc7280.h +++ b/include/dt-bindings/clock/qcom,gpucc-sc7280.h @@ -32,4 +32,7 @@ #define GPU_CC_CX_GDSC 0 #define GPU_CC_GX_GDSC 1 +/* GPU_CC reset IDs */ +#define GPU_CX_COLLAPSE 0 + #endif From patchwork Wed Aug 31 05:18:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil P Oommen X-Patchwork-Id: 12960400 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DDA9DECAAD8 for ; Wed, 31 Aug 2022 05:19:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231829AbiHaFT0 (ORCPT ); Wed, 31 Aug 2022 01:19:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54352 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229449AbiHaFT0 (ORCPT ); Wed, 31 Aug 2022 01:19:26 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 58517B14D8; Tue, 30 Aug 2022 22:19:25 -0700 (PDT) Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 27V4DYPX020411; Wed, 31 Aug 2022 05:19:13 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=NN0hANgOTosS67AZM7qStNdWjz7PM0mNu/rAh+RRKaQ=; b=nof6eVgQdjqi+tUoGHd0jgiqo/B9MR+GTqEdp0PbaKtltafb2AN6UbfW0AtXmctJsPwA StKylhXquPllJwkb5tr7kJ3B5R0dT08Vqx+v6G37mmUt4ftxWPHSR2greKDo/gBY0Sm7 uxwje5Uv5arFHRgU4w5eiQ7dfiCfb2KdJ0/bfQqY/+XV+m0OXVs+W9lz94mO46B9wZUm VBUvgwriA88o4d2hUdnSIb3NXTPUB+JscY3wJ0munyVAscoqmMYza7+tCQjaNHP/HVdU 2ctkeLO027iTQgntvs9leTFa9qrPWgx8sZ9llJr3aePL6kQCRcnG14Ozx0pofZ7WhuI3 GA== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3j9m2t2jnq-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 31 Aug 2022 05:19:13 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 27V5JCtc013996 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 31 Aug 2022 05:19:12 GMT Received: from hyd-lnxbld559.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Tue, 30 Aug 2022 22:19:07 -0700 From: Akhil P Oommen To: freedreno , , , Rob Clark , Bjorn Andersson , "Stephen Boyd" , Dmitry Baryshkov , Philipp Zabel CC: Douglas Anderson , , Akhil P Oommen , Andy Gross , Konrad Dybcio , Michael Turquette , Stephen Boyd , , Subject: [PATCH v6 2/6] clk: qcom: Allow custom reset ops Date: Wed, 31 Aug 2022 10:48:23 +0530 Message-ID: <20220831104741.v6.2.I75baff799a363bbb960376539e3a0f737377c3f1@changeid> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1661923108-789-1-git-send-email-quic_akhilpo@quicinc.com> References: <1661923108-789-1-git-send-email-quic_akhilpo@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: D6OrqctB7GR9Grklm_IuDSXrkz2tB1AB X-Proofpoint-ORIG-GUID: D6OrqctB7GR9Grklm_IuDSXrkz2tB1AB X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-31_03,2022-08-30_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 phishscore=0 adultscore=0 mlxlogscore=999 bulkscore=0 suspectscore=0 mlxscore=0 clxscore=1015 spamscore=0 malwarescore=0 impostorscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2207270000 definitions=main-2208310025 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Allow soc specific clk drivers to specify a custom reset operation. We will use this in an upcoming patch to allow gpucc driver to specify a differet reset operation for cx_gdsc. Signed-off-by: Akhil P Oommen Reviewed-by: Dmitry Baryshkov --- (no changes since v3) Changes in v3: - Use pointer to const for "struct qcom_reset_ops" in qcom_reset_map (Krzysztof) Changes in v2: - Return error when a particular custom reset op is not implemented. (Dmitry) drivers/clk/qcom/reset.c | 27 +++++++++++++++++++++++++++ drivers/clk/qcom/reset.h | 8 ++++++++ 2 files changed, 35 insertions(+) diff --git a/drivers/clk/qcom/reset.c b/drivers/clk/qcom/reset.c index 819d194..b7ae4a3 100644 --- a/drivers/clk/qcom/reset.c +++ b/drivers/clk/qcom/reset.c @@ -13,6 +13,21 @@ static int qcom_reset(struct reset_controller_dev *rcdev, unsigned long id) { + struct qcom_reset_controller *rst; + const struct qcom_reset_map *map; + + rst = to_qcom_reset_controller(rcdev); + map = &rst->reset_map[id]; + + if (map->ops && map->ops->reset) + return map->ops->reset(map->priv); + /* + * If custom ops is implemented but just not this callback, return + * error + */ + else if (map->ops) + return -EOPNOTSUPP; + rcdev->ops->assert(rcdev, id); udelay(1); rcdev->ops->deassert(rcdev, id); @@ -28,6 +43,12 @@ qcom_reset_assert(struct reset_controller_dev *rcdev, unsigned long id) rst = to_qcom_reset_controller(rcdev); map = &rst->reset_map[id]; + + if (map->ops && map->ops->assert) + return map->ops->assert(map->priv); + else if (map->ops) + return -EOPNOTSUPP; + mask = BIT(map->bit); return regmap_update_bits(rst->regmap, map->reg, mask, mask); @@ -42,6 +63,12 @@ qcom_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id) rst = to_qcom_reset_controller(rcdev); map = &rst->reset_map[id]; + + if (map->ops && map->ops->deassert) + return map->ops->deassert(map->priv); + else if (map->ops) + return -EOPNOTSUPP; + mask = BIT(map->bit); return regmap_update_bits(rst->regmap, map->reg, mask, 0); diff --git a/drivers/clk/qcom/reset.h b/drivers/clk/qcom/reset.h index 2a08b5e..f3147eb 100644 --- a/drivers/clk/qcom/reset.h +++ b/drivers/clk/qcom/reset.h @@ -8,9 +8,17 @@ #include +struct qcom_reset_ops { + int (*reset)(void *priv); + int (*assert)(void *priv); + int (*deassert)(void *priv); +}; + struct qcom_reset_map { unsigned int reg; u8 bit; + const struct qcom_reset_ops *ops; + void *priv; }; struct regmap; From patchwork Wed Aug 31 05:18:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil P Oommen X-Patchwork-Id: 12960403 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 97DBBECAAD8 for ; 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Wed, 31 Aug 2022 05:19:19 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 27V5JIgY022403 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 31 Aug 2022 05:19:18 GMT Received: from hyd-lnxbld559.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Tue, 30 Aug 2022 22:19:12 -0700 From: Akhil P Oommen To: freedreno , , , Rob Clark , Bjorn Andersson , "Stephen Boyd" , Dmitry Baryshkov , Philipp Zabel CC: Douglas Anderson , , Akhil P Oommen , Andy Gross , Konrad Dybcio , Michael Turquette , Stephen Boyd , , Subject: [PATCH v6 3/6] clk: qcom: gdsc: Add a reset op to poll gdsc collapse Date: Wed, 31 Aug 2022 10:48:24 +0530 Message-ID: <20220831104741.v6.3.I162c4be55f230cd439f0643f1624527bdc8a9831@changeid> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1661923108-789-1-git-send-email-quic_akhilpo@quicinc.com> References: <1661923108-789-1-git-send-email-quic_akhilpo@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: hAzWmiUmRMqxGHlpU1qYtoImThH6zp03 X-Proofpoint-ORIG-GUID: hAzWmiUmRMqxGHlpU1qYtoImThH6zp03 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-31_03,2022-08-30_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 bulkscore=0 mlxscore=0 clxscore=1015 adultscore=0 phishscore=0 malwarescore=0 spamscore=0 priorityscore=1501 suspectscore=0 lowpriorityscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2207270000 definitions=main-2208310025 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add a reset op compatible function to poll for gdsc collapse. Signed-off-by: Akhil P Oommen Reviewed-by: Dmitry Baryshkov --- (no changes since v2) Changes in v2: - Minor update to function prototype drivers/clk/qcom/gdsc.c | 23 +++++++++++++++++++---- drivers/clk/qcom/gdsc.h | 7 +++++++ 2 files changed, 26 insertions(+), 4 deletions(-) diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c index 44520ef..2d0f1d1 100644 --- a/drivers/clk/qcom/gdsc.c +++ b/drivers/clk/qcom/gdsc.c @@ -17,6 +17,7 @@ #include #include #include "gdsc.h" +#include "reset.h" #define PWR_ON_MASK BIT(31) #define EN_REST_WAIT_MASK GENMASK_ULL(23, 20) @@ -116,7 +117,8 @@ static int gdsc_hwctrl(struct gdsc *sc, bool en) return regmap_update_bits(sc->regmap, sc->gdscr, HW_CONTROL_MASK, val); } -static int gdsc_poll_status(struct gdsc *sc, enum gdsc_status status) +static int gdsc_poll_status(struct gdsc *sc, enum gdsc_status status, + s64 timeout_us, unsigned int interval_ms) { ktime_t start; @@ -124,7 +126,9 @@ static int gdsc_poll_status(struct gdsc *sc, enum gdsc_status status) do { if (gdsc_check_status(sc, status)) return 0; - } while (ktime_us_delta(ktime_get(), start) < TIMEOUT_US); + if (interval_ms) + msleep(interval_ms); + } while (ktime_us_delta(ktime_get(), start) < timeout_us); if (gdsc_check_status(sc, status)) return 0; @@ -172,7 +176,7 @@ static int gdsc_toggle_logic(struct gdsc *sc, enum gdsc_status status) udelay(1); } - ret = gdsc_poll_status(sc, status); + ret = gdsc_poll_status(sc, status, TIMEOUT_US, 0); WARN(ret, "%s status stuck at 'o%s'", sc->pd.name, status ? "ff" : "n"); if (!ret && status == GDSC_OFF && sc->rsupply) { @@ -343,7 +347,7 @@ static int _gdsc_disable(struct gdsc *sc) */ udelay(1); - ret = gdsc_poll_status(sc, GDSC_ON); + ret = gdsc_poll_status(sc, GDSC_ON, TIMEOUT_US, 0); if (ret) return ret; } @@ -565,3 +569,14 @@ int gdsc_gx_do_nothing_enable(struct generic_pm_domain *domain) return 0; } EXPORT_SYMBOL_GPL(gdsc_gx_do_nothing_enable); + +int gdsc_wait_for_collapse(void *priv) +{ + struct gdsc *sc = priv; + int ret; + + ret = gdsc_poll_status(sc, GDSC_OFF, 500000, 5); + WARN(ret, "%s status stuck at 'on'", sc->pd.name); + return ret; +} +EXPORT_SYMBOL_GPL(gdsc_wait_for_collapse); diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h index ad313d7..d484bdb 100644 --- a/drivers/clk/qcom/gdsc.h +++ b/drivers/clk/qcom/gdsc.h @@ -12,6 +12,7 @@ struct regmap; struct regulator; struct reset_controller_dev; +struct qcom_reset_map; /** * struct gdsc - Globally Distributed Switch Controller @@ -79,6 +80,7 @@ int gdsc_register(struct gdsc_desc *desc, struct reset_controller_dev *, struct regmap *); void gdsc_unregister(struct gdsc_desc *desc); int gdsc_gx_do_nothing_enable(struct generic_pm_domain *domain); +int gdsc_wait_for_collapse(void *priv); #else static inline int gdsc_register(struct gdsc_desc *desc, struct reset_controller_dev *rcdev, @@ -88,5 +90,10 @@ static inline int gdsc_register(struct gdsc_desc *desc, } static inline void gdsc_unregister(struct gdsc_desc *desc) {}; + +static int gdsc_wait_for_collapse(void *priv) +{ + return -ENOSYS; +} #endif /* CONFIG_QCOM_GDSC */ #endif /* __QCOM_GDSC_H__ */ From patchwork Wed Aug 31 05:18:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil P Oommen X-Patchwork-Id: 12960404 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D6698C0502A for ; Wed, 31 Aug 2022 05:19:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232157AbiHaFTv (ORCPT ); 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Signed-off-by: Akhil P Oommen Reviewed-by: Dmitry Baryshkov --- (no changes since v3) Changes in v3: - Convert 'struct qcom_reset_ops cx_gdsc_reset' to 'static const' (Krzysztof) Changes in v2: - Minor update to use the updated custom reset ops implementation drivers/clk/qcom/gpucc-sc7280.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/clk/qcom/gpucc-sc7280.c b/drivers/clk/qcom/gpucc-sc7280.c index 9a832f2..fece3f4 100644 --- a/drivers/clk/qcom/gpucc-sc7280.c +++ b/drivers/clk/qcom/gpucc-sc7280.c @@ -433,12 +433,22 @@ static const struct regmap_config gpu_cc_sc7280_regmap_config = { .fast_io = true, }; +static const struct qcom_reset_ops cx_gdsc_reset = { + .reset = gdsc_wait_for_collapse, +}; + +static const struct qcom_reset_map gpucc_sc7280_resets[] = { + [GPU_CX_COLLAPSE] = { .ops = &cx_gdsc_reset, .priv = &cx_gdsc }, +}; + static const struct qcom_cc_desc gpu_cc_sc7280_desc = { .config = &gpu_cc_sc7280_regmap_config, .clks = gpu_cc_sc7280_clocks, .num_clks = ARRAY_SIZE(gpu_cc_sc7280_clocks), .gdscs = gpu_cc_sc7180_gdscs, .num_gdscs = ARRAY_SIZE(gpu_cc_sc7180_gdscs), + .resets = gpucc_sc7280_resets, + .num_resets = ARRAY_SIZE(gpucc_sc7280_resets), }; static const struct of_device_id gpu_cc_sc7280_match_table[] = {