From patchwork Wed Aug 31 17:24:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jones X-Patchwork-Id: 12961150 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3CB60ECAAD1 for ; Wed, 31 Aug 2022 17:25:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=iCjnBdswg8H3DtIl/ZtdBemF/bISAkqiKl+jctuQRb8=; b=ivQw4Af4CWN9BF l6d5NNfLVNx/riNuk4qDsguAZs4c35ILZhCE/3kvI5EoRGgEyhw3us0uiqxPAefPyh8USrGIuHWu9 xlzPtKdxt97RXRmWt1koxrrjrM6G9wAAkIGcbIAg+svLnUaUv92r1U+FTRmAHO6JkTBU407WIOo5j HLrgfVLIZ10vVPyATA9yoOhmFp/YQio9ICCb+vu2dpTuUukIgw74P8csGXb8sxJvVcDzpxvTXH2s5 q1l6CtWZ7SLH7bzZtF1+G7YNz0QWACyi+niw89OYWebCIGH+jIzECK2x/I2dQdFx71XK7Dl1Yvd5V GJ9M+vipLVHJ9zqobvKg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oTRSi-007Ol9-H7; Wed, 31 Aug 2022 17:25:12 +0000 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oTRSd-007OhG-Sx for linux-riscv@lists.infradead.org; Wed, 31 Aug 2022 17:25:09 +0000 Received: by mail-wr1-x434.google.com with SMTP id bu22so18835143wrb.3 for ; Wed, 31 Aug 2022 10:25:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=DdNOmnay44tpamKMrs1LwErqXxNdYL1hnnIQ+CjZ7QA=; b=MG0rBr2wWp2+FARb5OnChcQ4x0S23ZL60h95CnzB7VjDZ/H2HzOa4qhBqJfaUhg+bl HH5NMuPrPw4BBMJ3GKz++cbp+aJPSUUdP776VpS+lgLuEgUKtZt18gnVv3ooY7nKDzxl vwmrQATtXcj1hDSk4rrVBtBx0sqkrypO3+3VGt8gksRuuwORrUdhboPgeoODeKhpbVqp W4+J069NjrhutbCY/qVWI0Pk5r3H8/XFTGFFdVfn7/SHsW0aszphuwKoa5PaZPpGYZQM WiwK8bGL1chbaM/cM+VZ5grJrVGRBHGb/OYSZDQwgm1s2MBXHEJqrvVJx8SRmoWWtlrg bViA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=DdNOmnay44tpamKMrs1LwErqXxNdYL1hnnIQ+CjZ7QA=; b=pZ2sFMgDAIgy1duonv0RdloAgRH2DSppMytS5zqgH0wwAdmQvNV2mwrmMznqTTKoLN px4X9ZBQIhSul2X1bhvFqrvtfCNhzwKy34O8cZiqMncKiQ7YPdBcxh30LlWxYYtQO8o/ UzTnqsvFR9Es5Tp4tot7/CDk06ci1wOo0uhFEzUIe21J+bauKn27yGHy7ZQTEqe6ggIx rzvI5JVwf1do6Zcwa1WhWPiw95Bm6xhTBSfkvfyVm/Dx0kRhCD/iLjGC8d56kE6Bw82q 6S9fhhK6lcNj81lK+mTA9+/xh+DjFYDoZrXOdVY6pc1pxXAVXDZAOr6vNaiffJd7yLuq FFFA== X-Gm-Message-State: ACgBeo3FhxLFdUAIALmtszwOEaKyZ56FS66k16fPVv6v+FL2jyCltk5+ JqfUx3BCRfujAK9RchYW/egYu5FoqA9jGw== X-Google-Smtp-Source: AA6agR4D9tdHfJxgAr4odD2uA9lewMl1R3XYhjjgYG/X1gSRjA2gExwl6O2ex2Vl5wzSh024Cw+XvQ== X-Received: by 2002:adf:d1c5:0:b0:222:cbe8:f9fa with SMTP id b5-20020adfd1c5000000b00222cbe8f9famr12286408wrd.383.1661966703923; Wed, 31 Aug 2022 10:25:03 -0700 (PDT) Received: from localhost (cst2-173-67.cust.vodafone.cz. [31.30.173.67]) by smtp.gmail.com with ESMTPSA id u18-20020a05600c19d200b003a5a5069107sm2618214wmq.24.2022.08.31.10.25.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Aug 2022 10:25:03 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org Cc: linux-kernel@vger.kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, anup@brainfault.org, mchitale@ventanamicro.com, heiko@sntech.de Subject: [PATCH v2 1/4] riscv: Add X register names to gpr-nums Date: Wed, 31 Aug 2022 19:24:57 +0200 Message-Id: <20220831172500.752195-2-ajones@ventanamicro.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220831172500.752195-1-ajones@ventanamicro.com> References: <20220831172500.752195-1-ajones@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220831_102507_938636_83172548 X-CRM114-Status: UNSURE ( 9.35 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org When encoding instructions it's sometimes necessary to set a register field to a precise number. This is easiest to do using the x naming. Signed-off-by: Andrew Jones Reviewed-by: Anup Patel --- arch/riscv/include/asm/gpr-num.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/riscv/include/asm/gpr-num.h b/arch/riscv/include/asm/gpr-num.h index dfee2829fc7c..efeb5edf8a3a 100644 --- a/arch/riscv/include/asm/gpr-num.h +++ b/arch/riscv/include/asm/gpr-num.h @@ -3,6 +3,11 @@ #define __ASM_GPR_NUM_H #ifdef __ASSEMBLY__ + + .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 + .equ .L__gpr_num_x\num, \num + .endr + .equ .L__gpr_num_zero, 0 .equ .L__gpr_num_ra, 1 .equ .L__gpr_num_sp, 2 @@ -39,6 +44,9 @@ #else /* __ASSEMBLY__ */ #define __DEFINE_ASM_GPR_NUMS \ +" .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31\n" \ +" .equ .L__gpr_num_x\\num, \\num\n" \ +" .endr\n" \ " .equ .L__gpr_num_zero, 0\n" \ " .equ .L__gpr_num_ra, 1\n" \ " .equ .L__gpr_num_sp, 2\n" \ From patchwork Wed Aug 31 17:24:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jones X-Patchwork-Id: 12961151 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7D053ECAAD3 for ; Wed, 31 Aug 2022 17:25:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=7p3of/McULJ3HiaPBUq10292cAJc9T88MXnW4TntPFM=; b=tEJ5TJ0H4euThw 5t95YJ/0Tkye4Ocu0rQPTHhNJ92TDg3FHXCVcSU3HoZj6kOgK+aZKzK0gH0MqIiHkfkfoDQkKCrjk k8HG/H4d96Ara39+K3v/yTzXlH2/UNUNljmJuZNF7G0h+BM9NqMd2XjccnVDg89C6tEddyOruOu7y ysOP+bTXlR39ajdklxziyOKx4ohcE9juBLBo2rNVgqtxEmYMCqYKMAI8F5QhhN9JAVkdAfUNB4aDU 06tdQsil89uvcdSU0O4lZTq8zmSocJfpuYSx+LyhGHEjXzIhHn+cLvry9sfmyo5rN6jhEbDCaByz3 GUYea71sqcKWnrSNNj3w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oTRSl-007Omm-4O; Wed, 31 Aug 2022 17:25:15 +0000 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oTRSe-007OhS-4M for linux-riscv@lists.infradead.org; Wed, 31 Aug 2022 17:25:09 +0000 Received: by mail-wm1-x32f.google.com with SMTP id ay39-20020a05600c1e2700b003a5503a80cfso8407951wmb.2 for ; Wed, 31 Aug 2022 10:25:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=5h3L3YOiG9CNXYHQtw/et5Sc+1r6Zl/xaASBla9taYA=; b=G5vxTVeX8UktfzniDjTnkLblMXMKWgBYh+R/zA8MObo5kCtHE/4HRGHqvkVm3dHKIn Su2cvs50mNGPLJI790jlw1So7LyZSsduFO1NSGToSMmBvB5ocNz2Ox5thy9u2n1xK65e DMewhEiPnTmFiGgwHol01Lc/Pi/tFjdFNeximileSt63NdPSFbfx3L218VWWD6NkQkXg cmMZ66qsLRAc6JeYpVXYLdeg8a4BjRWRYCyRLxKEIUwjNZjmKEM+ZAOVL0GHRLJrA8vK D5LM1fvMywqOpH19URp0URi/B9NDOa2UzrJyHUyu98dzsr7lbej+ThgqjmEQCuDFKa0q 1tLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=5h3L3YOiG9CNXYHQtw/et5Sc+1r6Zl/xaASBla9taYA=; b=U/o+038g1W7hCqBSMVmfBmcKg7hU/in8LwplNs/07lq5za/V+78eu+w9G3N+Jo34G0 mYMGrf0jHi4BsJvMDo9QxSMsHKUMyKHh+0G9lohx2KxHszukCeiu66MPxjCFBToAngaX Kt3yoyV193p4zGZ4PJYSB+nau8d6zXWYFWSysWbCaol73FEwDr2OonSwxywGtqwm+El6 f266QIPHK2G9nJ4WSK2bjc/ulZ1i2az/sCjDhrZ81uD4aTva3CbVV1SEQr2HLBhgU/+e a0ItfFV7SuYYZnbqBiSZT8jQG8M8zwwxTbvaJrqfhVR7m+V4aEzGIKbatF/gwsng0BF4 RsWw== X-Gm-Message-State: ACgBeo3k1r0z2nOokofyQhlHrdH7ttSe8/j574x425Df8bd4i9IXMovJ MTxU186x03nsmkqS/7NAWBewrZIk/6cTSQ== X-Google-Smtp-Source: AA6agR7lpMuqSCKxNT4vSMdBVaSEyRIEQ+Pl2du5hdijO1YQun6REosptUuvlx9D3nXsoLSdQpx6uQ== X-Received: by 2002:a1c:4b01:0:b0:3a5:94e8:948e with SMTP id y1-20020a1c4b01000000b003a594e8948emr2653368wma.197.1661966705440; Wed, 31 Aug 2022 10:25:05 -0700 (PDT) Received: from localhost (cst2-173-67.cust.vodafone.cz. [31.30.173.67]) by smtp.gmail.com with ESMTPSA id k34-20020a05600c1ca200b003a62400724bsm3419320wms.0.2022.08.31.10.25.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Aug 2022 10:25:04 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org Cc: linux-kernel@vger.kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, anup@brainfault.org, mchitale@ventanamicro.com, heiko@sntech.de Subject: [PATCH v2 2/4] riscv: Introduce support for defining instructions Date: Wed, 31 Aug 2022 19:24:58 +0200 Message-Id: <20220831172500.752195-3-ajones@ventanamicro.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220831172500.752195-1-ajones@ventanamicro.com> References: <20220831172500.752195-1-ajones@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220831_102508_204433_6B9CB030 X-CRM114-Status: GOOD ( 16.23 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org When compiling with toolchains that haven't yet been taught about new instructions we need to encode them ourselves. Create a new file where support for instruction definitions will evolve. We initiate the file with a macro called INSN_R(), which implements the R-type instruction encoding. INSN_R() will use the assembler's .insn directive when available, which should give the assembler a chance to do some validation. When .insn is not available we fall back to manual encoding. Not only should using instruction encoding macros improve readability and maintainability of code over the alternative of inserting instructions directly (e.g. '.word 0xc0de'), but we should also gain potential for more optimized code after compilation because the compiler will have control over the input and output registers used. Signed-off-by: Andrew Jones Reviewed-by: Anup Patel --- arch/riscv/Kconfig | 3 ++ arch/riscv/include/asm/insn-def.h | 86 +++++++++++++++++++++++++++++++ 2 files changed, 89 insertions(+) create mode 100644 arch/riscv/include/asm/insn-def.h diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index ed66c31e4655..f8f3b316b838 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -227,6 +227,9 @@ config RISCV_DMA_NONCOHERENT select ARCH_HAS_SETUP_DMA_OPS select DMA_DIRECT_REMAP +config AS_HAS_INSN + def_bool $(as-instr,.insn r 51$(comma) 0$(comma) 0$(comma) t0$(comma) t0$(comma) zero) + source "arch/riscv/Kconfig.socs" source "arch/riscv/Kconfig.erratas" diff --git a/arch/riscv/include/asm/insn-def.h b/arch/riscv/include/asm/insn-def.h new file mode 100644 index 000000000000..2dcd1d4781bf --- /dev/null +++ b/arch/riscv/include/asm/insn-def.h @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __ASM_INSN_DEF_H +#define __ASM_INSN_DEF_H + +#include + +#define INSN_R_FUNC7_SHIFT 25 +#define INSN_R_RS2_SHIFT 20 +#define INSN_R_RS1_SHIFT 15 +#define INSN_R_FUNC3_SHIFT 12 +#define INSN_R_RD_SHIFT 7 +#define INSN_R_OPCODE_SHIFT 0 + +#ifdef __ASSEMBLY__ + +#ifdef CONFIG_AS_HAS_INSN + + .macro insn_r, opcode, func3, func7, rd, rs1, rs2 + .insn r \opcode, \func3, \func7, \rd, \rs1, \rs2 + .endm + +#else + +#include + + .macro insn_r, opcode, func3, func7, rd, rs1, rs2 + .4byte ((\opcode << INSN_R_OPCODE_SHIFT) | \ + (\func3 << INSN_R_FUNC3_SHIFT) | \ + (\func7 << INSN_R_FUNC7_SHIFT) | \ + (.L__gpr_num_\rd << INSN_R_RD_SHIFT) | \ + (.L__gpr_num_\rs1 << INSN_R_RS1_SHIFT) | \ + (.L__gpr_num_\rs2 << INSN_R_RS2_SHIFT)) + .endm + +#endif + +#define INSN_R(...) insn_r __VA_ARGS__ + +#else /* ! __ASSEMBLY__ */ + +#ifdef CONFIG_AS_HAS_INSN + +#define INSN_R(opcode, func3, func7, rd, rs1, rs2) \ + ".insn r " opcode ", " func3 ", " func7 ", " rd ", " rs1 ", " rs2 "\n" + +#else + +#include +#include + +#define DEFINE_INSN_R \ + __DEFINE_ASM_GPR_NUMS \ +" .macro insn_r, opcode, func3, func7, rd, rs1, rs2\n" \ +" .4byte ((\\opcode << " __stringify(INSN_R_OPCODE_SHIFT) ") |" \ +" (\\func3 << " __stringify(INSN_R_FUNC3_SHIFT) ") |" \ +" (\\func7 << " __stringify(INSN_R_FUNC7_SHIFT) ") |" \ +" (.L__gpr_num_\\rd << " __stringify(INSN_R_RD_SHIFT) ") |" \ +" (.L__gpr_num_\\rs1 << " __stringify(INSN_R_RS1_SHIFT) ") |" \ +" (.L__gpr_num_\\rs2 << " __stringify(INSN_R_RS2_SHIFT) "))\n" \ +" .endm\n" + +#define UNDEFINE_INSN_R \ +" .purgem insn_r\n" + +#define INSN_R(opcode, func3, func7, rd, rs1, rs2) \ + DEFINE_INSN_R \ + "insn_r " opcode ", " func3 ", " func7 ", " rd ", " rs1 ", " rs2 "\n" \ + UNDEFINE_INSN_R + +#endif + +#endif /* ! __ASSEMBLY__ */ + +#define OPCODE(v) __ASM_STR(v) +#define FUNC3(v) __ASM_STR(v) +#define FUNC7(v) __ASM_STR(v) +#define RD(v) __ASM_STR(v) +#define RS1(v) __ASM_STR(v) +#define RS2(v) __ASM_STR(v) +#define __REG(v) __ASM_STR(x ## v) +#define __RD(v) __REG(v) +#define __RS1(v) __REG(v) +#define __RS2(v) __REG(v) + +#endif /* __ASM_INSN_DEF_H */ From patchwork Wed Aug 31 17:24:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jones X-Patchwork-Id: 12961153 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 85749C0502A for ; Wed, 31 Aug 2022 17:25:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=YsU14v/Dv4Z0UrFGlVv6PI2oCBGe1uvNsff5aNlUUDk=; b=XsICbwqJYTFUOh 2xnhAZh+mG34iOuZ18HuE1WyxGrLLPcrYdgG1hzt3S3WySLXOD7fvgJia2zZepA6S8/7vdtyQ45yW whdNzfgblh9TwwhePZXiREGG5EAfzssSwCXZFrx3J0jgZA8yK6CiZBKV9vrWTG1MZnhGgR2/QZfjk tWn8OVoG2C2083VvGv+zoPbK/d9ZauTa4LDm276RZzfIpW3zAzR+Ig8TXP/yFp6DJOLKumL9ry9Bx x0k81K6bB9ZwkI3x2PrSOnEzQlHlJBx0tce7ufcVRoTQVghmUkn2NDX0qMk7zAqXjyk6gPkWH9Qe7 YjLvE4yhtzNyAuGMrWpA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oTRSm-007Opj-Rn; Wed, 31 Aug 2022 17:25:16 +0000 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oTRSg-007OiV-3c for linux-riscv@lists.infradead.org; Wed, 31 Aug 2022 17:25:11 +0000 Received: by mail-wm1-x32b.google.com with SMTP id n17-20020a05600c501100b003a84bf9b68bso3450469wmr.3 for ; Wed, 31 Aug 2022 10:25:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=fizBC8NpPcL0RO1q/LLq/Re49C8DURQi6bNhDvOLByc=; b=Thjp/7LoSdR+BA8d4yQIMpuR3obWObcLBIt6v4+66n8/RxuUlNGmfr8JsCtgZr3Qkf 6SwmSnpvcy5sXxN29DLz7+SYjrCRgF8X7up11Jis86GrFvuAe/fMDfgBCrxha2l3dsj1 U5auAhYkh7aZK6d6iRezooRAPPqNdUH6xaYsfCskyMW4OV4kkhiTwucnFEc/Aa2eFrlq mFjo1g4k5Dgk27rwbVrIGryJd7B3RNrvTw4LI05x7s6O37XTLXwlSo5C+NR1rOV5O406 WajxWdao5ciVkP/uSbxsp+5D/6TcoXgYBUJMx4CLVyJMh8eMQr9sIv5EItpjBTdZmddB 8VGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=fizBC8NpPcL0RO1q/LLq/Re49C8DURQi6bNhDvOLByc=; b=ce/1dcJ7ntjXz9ij3LnhO/peDtmzsiCazoaL+RRnhM29hRjXqhheATPO+f6ObVnG1F moxGlkFgAKHTfodhj5DIpVTrgQO1at5dMjuZdXybkxFbBSnixyNP1WqStJitFyGVSCPu CWjCJCIKnWzld/6LRsCOpb0CSYjGqGm8mtXxTYMBXVL6jFxar5H2alXWLaYlWMIU1kdo mIDTtSuuKZkX0FId7uL/N0wYe4bs2Qshwp2I3Olpq/u0zdE0ePsXXMI+Z4PMXK9cL0G5 nRDeak3RromSNeOmuT09me8bBZwCy8gm1zUEUINnq1huFq869QAZPLzUeAyPGQxr/mIf pdcw== X-Gm-Message-State: ACgBeo0yZFj41oy1GdGloq+o6Bnzb/hBJMVS3snQSt7Zx0gPbsc9U7zQ ENjFm1s2nkkpB4vJsyXhG7nZ6bqVdvih0Q== X-Google-Smtp-Source: AA6agR5wAvxqhLqol7jiXr6Zv4bFSqdk46xUnBeQG+Zqq51F5hJLLyZGiw6lcSeEZ7PZ2SDRjRt8hw== X-Received: by 2002:a05:600c:28cd:b0:3a5:4f45:b927 with SMTP id h13-20020a05600c28cd00b003a54f45b927mr2728838wmd.90.1661966707060; Wed, 31 Aug 2022 10:25:07 -0700 (PDT) Received: from localhost (cst2-173-67.cust.vodafone.cz. [31.30.173.67]) by smtp.gmail.com with ESMTPSA id a11-20020a5d456b000000b0021f15514e7fsm14899052wrc.0.2022.08.31.10.25.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Aug 2022 10:25:06 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org Cc: linux-kernel@vger.kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, anup@brainfault.org, mchitale@ventanamicro.com, heiko@sntech.de Subject: [PATCH v2 3/4] riscv: KVM: Apply insn-def to hfence encodings Date: Wed, 31 Aug 2022 19:24:59 +0200 Message-Id: <20220831172500.752195-4-ajones@ventanamicro.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220831172500.752195-1-ajones@ventanamicro.com> References: <20220831172500.752195-1-ajones@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220831_102510_182745_636474C9 X-CRM114-Status: GOOD ( 10.02 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Introduce hfence instruction encodings and apply them to KVM's use. With the self-documenting nature of the instruction encoding macros, and a spec always within arm's reach, it's safe to remove the comments, so we do that too. Signed-off-by: Andrew Jones Reviewed-by: Anup Patel --- arch/riscv/include/asm/insn-def.h | 10 +++ arch/riscv/kvm/tlb.c | 129 ++++-------------------------- 2 files changed, 27 insertions(+), 112 deletions(-) diff --git a/arch/riscv/include/asm/insn-def.h b/arch/riscv/include/asm/insn-def.h index 2dcd1d4781bf..86c1f602413b 100644 --- a/arch/riscv/include/asm/insn-def.h +++ b/arch/riscv/include/asm/insn-def.h @@ -83,4 +83,14 @@ #define __RS1(v) __REG(v) #define __RS2(v) __REG(v) +#define OPCODE_SYSTEM OPCODE(115) + +#define HFENCE_VVMA(vaddr, asid) \ + INSN_R(OPCODE_SYSTEM, FUNC3(0), FUNC7(17), \ + __RD(0), RS1(vaddr), RS2(asid)) + +#define HFENCE_GVMA(gaddr, vmid) \ + INSN_R(OPCODE_SYSTEM, FUNC3(0), FUNC7(49), \ + __RD(0), RS1(gaddr), RS2(vmid)) + #endif /* __ASM_INSN_DEF_H */ diff --git a/arch/riscv/kvm/tlb.c b/arch/riscv/kvm/tlb.c index 1a76d0b1907d..1ce3394b3acf 100644 --- a/arch/riscv/kvm/tlb.c +++ b/arch/riscv/kvm/tlb.c @@ -12,22 +12,7 @@ #include #include #include - -/* - * Instruction encoding of hfence.gvma is: - * HFENCE.GVMA rs1, rs2 - * HFENCE.GVMA zero, rs2 - * HFENCE.GVMA rs1 - * HFENCE.GVMA - * - * rs1!=zero and rs2!=zero ==> HFENCE.GVMA rs1, rs2 - * rs1==zero and rs2!=zero ==> HFENCE.GVMA zero, rs2 - * rs1!=zero and rs2==zero ==> HFENCE.GVMA rs1 - * rs1==zero and rs2==zero ==> HFENCE.GVMA - * - * Instruction encoding of HFENCE.GVMA is: - * 0110001 rs2(5) rs1(5) 000 00000 1110011 - */ +#include void kvm_riscv_local_hfence_gvma_vmid_gpa(unsigned long vmid, gpa_t gpa, gpa_t gpsz, @@ -40,32 +25,14 @@ void kvm_riscv_local_hfence_gvma_vmid_gpa(unsigned long vmid, return; } - for (pos = gpa; pos < (gpa + gpsz); pos += BIT(order)) { - /* - * rs1 = a0 (GPA >> 2) - * rs2 = a1 (VMID) - * HFENCE.GVMA a0, a1 - * 0110001 01011 01010 000 00000 1110011 - */ - asm volatile ("srli a0, %0, 2\n" - "add a1, %1, zero\n" - ".word 0x62b50073\n" - :: "r" (pos), "r" (vmid) - : "a0", "a1", "memory"); - } + for (pos = gpa; pos < (gpa + gpsz); pos += BIT(order)) + asm volatile (HFENCE_GVMA(%0, %1) + : : "r" (pos >> 2), "r" (vmid) : "memory"); } void kvm_riscv_local_hfence_gvma_vmid_all(unsigned long vmid) { - /* - * rs1 = zero - * rs2 = a0 (VMID) - * HFENCE.GVMA zero, a0 - * 0110001 01010 00000 000 00000 1110011 - */ - asm volatile ("add a0, %0, zero\n" - ".word 0x62a00073\n" - :: "r" (vmid) : "a0", "memory"); + asm volatile(HFENCE_GVMA(zero, %0) : : "r" (vmid) : "memory"); } void kvm_riscv_local_hfence_gvma_gpa(gpa_t gpa, gpa_t gpsz, @@ -78,46 +45,16 @@ void kvm_riscv_local_hfence_gvma_gpa(gpa_t gpa, gpa_t gpsz, return; } - for (pos = gpa; pos < (gpa + gpsz); pos += BIT(order)) { - /* - * rs1 = a0 (GPA >> 2) - * rs2 = zero - * HFENCE.GVMA a0 - * 0110001 00000 01010 000 00000 1110011 - */ - asm volatile ("srli a0, %0, 2\n" - ".word 0x62050073\n" - :: "r" (pos) : "a0", "memory"); - } + for (pos = gpa; pos < (gpa + gpsz); pos += BIT(order)) + asm volatile(HFENCE_GVMA(%0, zero) + : : "r" (pos >> 2) : "memory"); } void kvm_riscv_local_hfence_gvma_all(void) { - /* - * rs1 = zero - * rs2 = zero - * HFENCE.GVMA - * 0110001 00000 00000 000 00000 1110011 - */ - asm volatile (".word 0x62000073" ::: "memory"); + asm volatile(HFENCE_GVMA(zero, zero) : : : "memory"); } -/* - * Instruction encoding of hfence.gvma is: - * HFENCE.VVMA rs1, rs2 - * HFENCE.VVMA zero, rs2 - * HFENCE.VVMA rs1 - * HFENCE.VVMA - * - * rs1!=zero and rs2!=zero ==> HFENCE.VVMA rs1, rs2 - * rs1==zero and rs2!=zero ==> HFENCE.VVMA zero, rs2 - * rs1!=zero and rs2==zero ==> HFENCE.VVMA rs1 - * rs1==zero and rs2==zero ==> HFENCE.VVMA - * - * Instruction encoding of HFENCE.VVMA is: - * 0010001 rs2(5) rs1(5) 000 00000 1110011 - */ - void kvm_riscv_local_hfence_vvma_asid_gva(unsigned long vmid, unsigned long asid, unsigned long gva, @@ -133,19 +70,9 @@ void kvm_riscv_local_hfence_vvma_asid_gva(unsigned long vmid, hgatp = csr_swap(CSR_HGATP, vmid << HGATP_VMID_SHIFT); - for (pos = gva; pos < (gva + gvsz); pos += BIT(order)) { - /* - * rs1 = a0 (GVA) - * rs2 = a1 (ASID) - * HFENCE.VVMA a0, a1 - * 0010001 01011 01010 000 00000 1110011 - */ - asm volatile ("add a0, %0, zero\n" - "add a1, %1, zero\n" - ".word 0x22b50073\n" - :: "r" (pos), "r" (asid) - : "a0", "a1", "memory"); - } + for (pos = gva; pos < (gva + gvsz); pos += BIT(order)) + asm volatile(HFENCE_VVMA(%0, %1) + : : "r" (pos), "r" (asid) : "memory"); csr_write(CSR_HGATP, hgatp); } @@ -157,15 +84,7 @@ void kvm_riscv_local_hfence_vvma_asid_all(unsigned long vmid, hgatp = csr_swap(CSR_HGATP, vmid << HGATP_VMID_SHIFT); - /* - * rs1 = zero - * rs2 = a0 (ASID) - * HFENCE.VVMA zero, a0 - * 0010001 01010 00000 000 00000 1110011 - */ - asm volatile ("add a0, %0, zero\n" - ".word 0x22a00073\n" - :: "r" (asid) : "a0", "memory"); + asm volatile(HFENCE_VVMA(zero, %0) : : "r" (asid) : "memory"); csr_write(CSR_HGATP, hgatp); } @@ -183,17 +102,9 @@ void kvm_riscv_local_hfence_vvma_gva(unsigned long vmid, hgatp = csr_swap(CSR_HGATP, vmid << HGATP_VMID_SHIFT); - for (pos = gva; pos < (gva + gvsz); pos += BIT(order)) { - /* - * rs1 = a0 (GVA) - * rs2 = zero - * HFENCE.VVMA a0 - * 0010001 00000 01010 000 00000 1110011 - */ - asm volatile ("add a0, %0, zero\n" - ".word 0x22050073\n" - :: "r" (pos) : "a0", "memory"); - } + for (pos = gva; pos < (gva + gvsz); pos += BIT(order)) + asm volatile(HFENCE_VVMA(%0, zero) + : : "r" (pos) : "memory"); csr_write(CSR_HGATP, hgatp); } @@ -204,13 +115,7 @@ void kvm_riscv_local_hfence_vvma_all(unsigned long vmid) hgatp = csr_swap(CSR_HGATP, vmid << HGATP_VMID_SHIFT); - /* - * rs1 = zero - * rs2 = zero - * HFENCE.VVMA - * 0010001 00000 00000 000 00000 1110011 - */ - asm volatile (".word 0x22000073" ::: "memory"); + asm volatile(HFENCE_VVMA(zero, zero) : : : "memory"); csr_write(CSR_HGATP, hgatp); } From patchwork Wed Aug 31 17:25:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jones X-Patchwork-Id: 12961152 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 77071ECAAD3 for ; Wed, 31 Aug 2022 17:25:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ZdhZs1G64IV2QHTWS4mBblGDBxcUChFt+SuaVbqoxwg=; b=Jl1LhTRjMdPk+A PavCsXFqxsEfNOjTsUgBUrBDS8Ng1B57uuB5ILxIRs0VE3cI9OvhHrnU7yz5olJHqyYkuz+Tk2wZw XZma2D2Io2VIl8UzqG9L5H+6nDRsbPfpA0tclvU5JG7LODjLOo9FfvGbGxKKQaFwAEnWj5FLj4d6R NBSYc66i85/rUsIx9CTcZLESevnGTcjC9pw07SsxuT47QGKRn+qc8Z2nGJJCPPJaw7LwJ/Xw0ZZxA UjWFOiiykOk5ltpJquhGjR8Jq01NhZsvjED0eE1h0W0i8qWbzMC+ZpCYCVXzP1OcBJ/uDladbSCa+ 4vwSH2bdWw8VGytMSr3A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oTRSq-007OtC-JB; Wed, 31 Aug 2022 17:25:20 +0000 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oTRSi-007OjJ-FS for linux-riscv@lists.infradead.org; Wed, 31 Aug 2022 17:25:14 +0000 Received: by mail-wr1-x42a.google.com with SMTP id b16so11551987wru.7 for ; Wed, 31 Aug 2022 10:25:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=j/4NmJqDbu56RZTur3QY16Eac2cEYz1FtNauBSCWCWQ=; b=Gctht5Adjh+JJvvaLgnzQD96KymRBCoBtTYden65aDTuXUNcFIftMzaaVSVgOk89Pt 22s4yl//k+NA19/+1YDYlCoHsrexoj1YEfPZX0DeRQJbWRmmQBfNDg4hVwxfbLK6hcgJ OMHE+huBXyktCnI7fGjm509OYEZDKqxtmo17IC57fGzapx6OZiXEgXGy6kYCF/wgwhjE X+4VF0eHw9NiCuB/uXmrZl5t7qvakCQ1wABEikeyRBVGOBzMrLCzm2JN2b/VfUaFTQLn J+4Ncgj/w3zBgGdeSz9X9/gMCZulUlCXxryClGDTzn8UGmGxeS767ad2OuaUw0j1ByLu Ms5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=j/4NmJqDbu56RZTur3QY16Eac2cEYz1FtNauBSCWCWQ=; b=DfMOLpkIbyXce8r0mk+hrXPPoT3HaaHjA/Dp5btAN6WuEBhpcCjpj0+Wo36n8MAd1V yaNqsbL0MbPzHr7H5I1aTcfq6HtmzOv/OjuLc1LNjSj9dnHXKLbBfY5mej/MFttwrwTV U7mSOR01TWGIS/KgAk9oHHfCIGGVQm3YDYMSnZdo0njXivAnD8e5Lziiy95d20KNfpZL GPdcTKnrI7Oga6XtcNmv/pGntddAMkvhgTWingGIox3kWJODZHaCBSVRrih9grYXpUMs sH/yb0WvIgVVIK1G3e2MWYM+wkHaFwuxYFmrWiP8DyBzvq0DjqBEo1MyW1K8hfcnlDM2 D8xw== X-Gm-Message-State: ACgBeo1nE/7euxBOR3aBGeIgw6FEzVr1wBEvjJruBGsakarV7kLziU9s ra9GkJo6f1k+ACflkHvLHCbdlY+x4NfhyQ== X-Google-Smtp-Source: AA6agR6cPZwhir1oSL4FH+tlBFkccGiF2un2JQUTMvARQ3UEhDSAxmKc+ttgXP2sV/U7RLNiu1ekrg== X-Received: by 2002:a5d:5941:0:b0:225:3fc3:d923 with SMTP id e1-20020a5d5941000000b002253fc3d923mr12309606wri.522.1661966708622; Wed, 31 Aug 2022 10:25:08 -0700 (PDT) Received: from localhost (cst2-173-67.cust.vodafone.cz. [31.30.173.67]) by smtp.gmail.com with ESMTPSA id ay21-20020a05600c1e1500b003a536d5aa2esm2838222wmb.11.2022.08.31.10.25.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Aug 2022 10:25:08 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org Cc: linux-kernel@vger.kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, anup@brainfault.org, mchitale@ventanamicro.com, heiko@sntech.de Subject: [PATCH v2 4/4] riscv: KVM: Apply insn-def to hlv encodings Date: Wed, 31 Aug 2022 19:25:00 +0200 Message-Id: <20220831172500.752195-5-ajones@ventanamicro.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220831172500.752195-1-ajones@ventanamicro.com> References: <20220831172500.752195-1-ajones@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220831_102512_542915_070FA671 X-CRM114-Status: UNSURE ( 8.60 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Introduce hlv instruction encodings and apply them to KVM's use. We're careful not to introduce hlv.d to 32-bit builds. Indeed, we ensure the build fails if someone tries to use it. Signed-off-by: Andrew Jones Reviewed-by: Anup Patel --- arch/riscv/include/asm/insn-def.h | 17 +++++++++++++++++ arch/riscv/kvm/vcpu_exit.c | 29 +++++------------------------ 2 files changed, 22 insertions(+), 24 deletions(-) diff --git a/arch/riscv/include/asm/insn-def.h b/arch/riscv/include/asm/insn-def.h index 86c1f602413b..8fe9036efb68 100644 --- a/arch/riscv/include/asm/insn-def.h +++ b/arch/riscv/include/asm/insn-def.h @@ -93,4 +93,21 @@ INSN_R(OPCODE_SYSTEM, FUNC3(0), FUNC7(49), \ __RD(0), RS1(gaddr), RS2(vmid)) +#define HLVX_HU(dest, addr) \ + INSN_R(OPCODE_SYSTEM, FUNC3(4), FUNC7(50), \ + RD(dest), RS1(addr), __RS2(3)) + +#define HLV_W(dest, addr) \ + INSN_R(OPCODE_SYSTEM, FUNC3(4), FUNC7(52), \ + RD(dest), RS1(addr), __RS2(0)) + +#ifdef CONFIG_64BIT +#define HLV_D(dest, addr) \ + INSN_R(OPCODE_SYSTEM, FUNC3(4), FUNC7(54), \ + RD(dest), RS1(addr), __RS2(0)) +#else +#define HLV_D(dest, addr) \ + __ASM_STR(.error "hlv.d requires 64-bit support") +#endif + #endif /* __ASM_INSN_DEF_H */ diff --git a/arch/riscv/kvm/vcpu_exit.c b/arch/riscv/kvm/vcpu_exit.c index d5c36386878a..da793f113a72 100644 --- a/arch/riscv/kvm/vcpu_exit.c +++ b/arch/riscv/kvm/vcpu_exit.c @@ -8,6 +8,7 @@ #include #include +#include static int gstage_page_fault(struct kvm_vcpu *vcpu, struct kvm_run *run, struct kvm_cpu_trap *trap) @@ -82,22 +83,12 @@ unsigned long kvm_riscv_vcpu_unpriv_read(struct kvm_vcpu *vcpu, ".option push\n" ".option norvc\n" "add %[ttmp], %[taddr], 0\n" - /* - * HLVX.HU %[val], (%[addr]) - * HLVX.HU t0, (t2) - * 0110010 00011 00111 100 00101 1110011 - */ - ".word 0x6433c2f3\n" + HLVX_HU(%[val], %[addr]) "andi %[tmp], %[val], 3\n" "addi %[tmp], %[tmp], -3\n" "bne %[tmp], zero, 2f\n" "addi %[addr], %[addr], 2\n" - /* - * HLVX.HU %[tmp], (%[addr]) - * HLVX.HU t1, (t2) - * 0110010 00011 00111 100 00110 1110011 - */ - ".word 0x6433c373\n" + HLVX_HU(%[tmp], %[addr]) "sll %[tmp], %[tmp], 16\n" "add %[val], %[val], %[tmp]\n" "2:\n" @@ -121,19 +112,9 @@ unsigned long kvm_riscv_vcpu_unpriv_read(struct kvm_vcpu *vcpu, ".option norvc\n" "add %[ttmp], %[taddr], 0\n" #ifdef CONFIG_64BIT - /* - * HLV.D %[val], (%[addr]) - * HLV.D t0, (t2) - * 0110110 00000 00111 100 00101 1110011 - */ - ".word 0x6c03c2f3\n" + HLV_D(%[val], %[addr]) #else - /* - * HLV.W %[val], (%[addr]) - * HLV.W t0, (t2) - * 0110100 00000 00111 100 00101 1110011 - */ - ".word 0x6803c2f3\n" + HLV_W(%[val], %[addr]) #endif ".option pop" : [val] "=&r" (val),