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Wed, 31 Aug 2022 17:13:25 -0500 From: Fangzhi Zuo To: Daniel Vetter , Ville Syrjala , David Airlie , Lyude Paul , Alex Deucher , Harry Wentland , Leo Li , Rodrigo Siqueira Subject: [PATCH] drm/dp: Avoid Reading DPCD_REV Before Native Aux Read Date: Wed, 31 Aug 2022 18:13:21 -0400 Message-ID: <20220831221321.748264-1-Jerry.Zuo@amd.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f1e7292a-321e-471d-8fb5-08da8b9e070b X-MS-TrafficTypeDiagnostic: DM6PR12MB4435:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Chv8vuVurB7zFIcxMSjNKs62m0IBGSe4vAA/hLqXdRRxV8//Sdj7lqe1U3EFnjl5pBHCgRjCrwr7lNxVb5wo9rU+fTlOA5SPHx9aMskVDO2SdkLyZ0fRpMlQD6AwBOzp6g6mT2UzUcXwB06h41uABBi7VpdqfDmG08ohP+MCwupUqRgkaFZtPtOh2+Jou9ZSEaOVBGevsw/xMEMPjMeP9vKmS2Nv5O84sCRtBPlnXNALyZF3QqjJ63XxJ4pautQ3R+q0s4uf/GwBAr5viZzKn5CKytIDD+jehZu1CSbKV4Nr30QNFphsHE8RjLxxJyqt6fB6KoYAyDmbCjZz7fNB6gZhp7yLQHsADWOZww800QLTV4MCcnwsH72JnbJMLkrZURgq44t+oHWK5pKqc8EeFjY5QKG0PIhvd3JpRFgiliuP473BItETL9WSd4VA72IyuzF6NjO3nAHmiOKpv3Sp7hXQixNFckYd1ELS/YYJ1AloAsnrR7vCCYhyexJpyAWmtmnSBW60tNXHBXwFMRzRNNgGL9eeSsxQLzOSD88MK8Fsa7sKQm5HM0VTmtKuTcoYoEXcTkfhPYY3hlD/m8RU4vPgrA0GDyDtV8xC9zCiV24Z4XZw+w6frSOcrgUZOLEz+AevYeOXWXV+/G6zclfJli9CYvyhUFxgdCiI60fk6L/Ohd15ie4WJGYvLw8Hq1b0kVU/6SkXUJsGf5ZD9JHu4N37eTBDzz3s4m8WT3VJi1XB+pJddIn581SFZ9b01q+h4KuvyGErA4z+Wg/mzRaWarwcRda+nN1171xCzwtcn6f0I30h1sSB6vRTR6YTrvF5 X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB03.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230016)(4636009)(376002)(136003)(39860400002)(346002)(396003)(40470700004)(36840700001)(46966006)(186003)(2616005)(1076003)(36860700001)(83380400001)(336012)(426003)(47076005)(81166007)(86362001)(356005)(70586007)(82740400003)(40460700003)(8936002)(40480700001)(5660300002)(2906002)(70206006)(4326008)(8676002)(7696005)(6666004)(478600001)(54906003)(110136005)(26005)(6636002)(36756003)(316002)(41300700001)(82310400005)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Aug 2022 22:13:26.4700 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f1e7292a-321e-471d-8fb5-08da8b9e070b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT080.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4435 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fangzhi Zuo , amd-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The attempt to read DPCD_REV before any native aux read breaks majority of DP2 compliance. The spec. requires DP_SINK_STATUS to be polled for the reset status DP_INTRA_HOP_AUX_REPLY_INDICATION during the clear training stage. Polling DP_SINK_STATUS each time gets DPCD_REV read first that makes non link training regsiter DPCD_REV get read during UHBR link training. It violates DP2 compliance. Cc: Ville Syrjala Cc: Lyude Paul Signed-off-by: Fangzhi Zuo Reviewed-by: Lyude Paul --- drivers/gpu/drm/display/drm_dp_helper.c | 18 ------------------ 1 file changed, 18 deletions(-) diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c index e7c22c2ca90c..c7aa5bafa667 100644 --- a/drivers/gpu/drm/display/drm_dp_helper.c +++ b/drivers/gpu/drm/display/drm_dp_helper.c @@ -571,24 +571,6 @@ ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset, { int ret; - /* - * HP ZR24w corrupts the first DPCD access after entering power save - * mode. Eg. on a read, the entire buffer will be filled with the same - * byte. Do a throw away read to avoid corrupting anything we care - * about. Afterwards things will work correctly until the monitor - * gets woken up and subsequently re-enters power save mode. - * - * The user pressing any button on the monitor is enough to wake it - * up, so there is no particularly good place to do the workaround. - * We just have to do it before any DPCD access and hope that the - * monitor doesn't power down exactly after the throw away read. - */ - if (!aux->is_remote) { - ret = drm_dp_dpcd_probe(aux, DP_DPCD_REV); - if (ret < 0) - return ret; - } - if (aux->is_remote) ret = drm_dp_mst_dpcd_read(aux, offset, buffer, size); else