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Thu, 1 Sep 2022 01:58:01 +0000 From: Joy Zou To: krzysztof.kozlowski@linaro.org Cc: shengjiu.wang@nxp.com, vkoul@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH V4 1/4] dt-bindings: fsl-imx-sdma: Convert imx sdma to DT schema Date: Thu, 1 Sep 2022 09:59:26 +0800 Message-Id: <20220901015926.50082-1-joy.zou@nxp.com> X-Mailer: git-send-email 2.37.1 X-ClientProxiedBy: SG2PR02CA0072.apcprd02.prod.outlook.com (2603:1096:4:54::36) To AM6PR04MB5925.eurprd04.prod.outlook.com (2603:10a6:20b:ab::19) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: b92df860-aef9-4e82-7551-08da8bbd666b X-MS-TrafficTypeDiagnostic: VI1PR04MB6159:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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The compatibles fsl,imx31-to1-sdma, fsl,imx31-to2-sdma, fsl,imx35-to1-sdma and fsl,imx35-to2-sdma are not used. So need to delete it. The compatibles fsl,imx50-sdma,fsl,imx6sll-sdma and fsl,imx6sl-sdma are added. The original binding don't list all compatible used. In addition, add new peripheral types HDMI Audio. Signed-off-by: Joy Zou --- Changes since (implicit) v3: modify the commit message in patch v4. delete the quotes in patch v4. modify the compatible in patch v4. delete maxitems and add items for clock-names property in patch v4. add iram property in patch v4. --- .../devicetree/bindings/dma/fsl,imx-sdma.yaml | 143 ++++++++++++++++++ .../devicetree/bindings/dma/fsl-imx-sdma.txt | 118 --------------- 2 files changed, 143 insertions(+), 118 deletions(-) create mode 100644 Documentation/devicetree/bindings/dma/fsl,imx-sdma.yaml delete mode 100644 Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt diff --git a/Documentation/devicetree/bindings/dma/fsl,imx-sdma.yaml b/Documentation/devicetree/bindings/dma/fsl,imx-sdma.yaml new file mode 100644 index 000000000000..18b31758cc67 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/fsl,imx-sdma.yaml @@ -0,0 +1,143 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/fsl,imx-sdma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale Smart Direct Memory Access (SDMA) Controller for i.MX + +maintainers: + - Joy Zou + +properties: + compatible: + oneOf: + - items: + - enum: + - fsl,imx50-sdma + - fsl,imx51-sdma + - fsl,imx53-sdma + - fsl,imx6q-sdma + - fsl,imx7d-sdma + - const: fsl,imx35-sdma + - items: + - enum: + - fsl,imx6sx-sdma + - fsl,imx6sl-sdma + - const: fsl,imx6q-sdma + - items: + - const: fsl,imx6ul-sdma + - const: fsl,imx6q-sdma + - const: fsl,imx35-sdma + - items: + - const: fsl,imx6sll-sdma + - const: fsl,imx6ul-sdma + - items: + - const: fsl,imx8mq-sdma + - const: fsl,imx7d-sdma + - items: + - enum: + - fsl,imx8mp-sdma + - fsl,imx8mn-sdma + - fsl,imx8mm-sdma + - const: fsl,imx8mq-sdma + - items: + - enum: + - fsl,imx25-sdma + - fsl,imx31-sdma + - fsl,imx35-sdma + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + fsl,sdma-ram-script-name: + $ref: /schemas/types.yaml#/definitions/string + description: Should contain the full path of SDMA RAM scripts firmware. + + "#dma-cells": + const: 3 + description: | + The first cell: request/event ID + + The second cell: peripheral types ID + enum: + - MCU domain SSI: 0 + - Shared SSI: 1 + - MMC: 2 + - SDHC: 3 + - MCU domain UART: 4 + - Shared UART: 5 + - FIRI: 6 + - MCU domain CSPI: 7 + - Shared CSPI: 8 + - SIM: 9 + - ATA: 10 + - CCM: 11 + - External peripheral: 12 + - Memory Stick Host Controller: 13 + - Shared Memory Stick Host Controller: 14 + - DSP: 15 + - Memory: 16 + - FIFO type Memory: 17 + - SPDIF: 18 + - IPU Memory: 19 + - ASRC: 20 + - ESAI: 21 + - SSI Dual FIFO: 22 + description: needs firmware more than ver 2 + - Shared ASRC: 23 + - SAI: 24 + - HDMI Audio: 25 + + The third cell: transfer priority ID + enum: + - High: 0 + - Medium: 1 + - Low: 2 + + gpr: + $ref: /schemas/types.yaml#/definitions/phandle + description: The phandle to the General Purpose Register (GPR) node + + fsl,sdma-event-remap: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + items: + - description: The GPR register offset, shift and value for RX + - description: The GPR register offset, shift and value for TX + description: | + Register bits of sdma event remap, the format is . + + clocks: + maxItems: 2 + + clock-names: + items: + - const: ipg + - const: ahb + + iram: + $ref: /schemas/types.yaml#/definitions/phandle + description: The phandle to the On-chip RAM (OCRAM) node. + +required: + - compatible + - reg + - interrupts + - fsl,sdma-ram-script-name + - "#dma-cells" + +unevaluatedProperties: false + +examples: + - | + sdma: dma-controller@83fb0000 { + compatible = "fsl,imx51-sdma", "fsl,imx35-sdma"; + reg = <0x83fb0000 0x4000>; + interrupts = <6>; + #dma-cells = <3>; + fsl,sdma-ram-script-name = "sdma-imx51.bin"; + }; + +... diff --git a/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt b/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt deleted file mode 100644 index 12c316ff4834..000000000000 --- a/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt +++ /dev/null @@ -1,118 +0,0 @@ -* Freescale Smart Direct Memory Access (SDMA) Controller for i.MX - -Required properties: -- compatible : Should be one of - "fsl,imx25-sdma" - "fsl,imx31-sdma", "fsl,imx31-to1-sdma", "fsl,imx31-to2-sdma" - "fsl,imx35-sdma", "fsl,imx35-to1-sdma", "fsl,imx35-to2-sdma" - "fsl,imx51-sdma" - "fsl,imx53-sdma" - "fsl,imx6q-sdma" - "fsl,imx7d-sdma" - "fsl,imx6ul-sdma" - "fsl,imx8mq-sdma" - "fsl,imx8mm-sdma" - "fsl,imx8mn-sdma" - "fsl,imx8mp-sdma" - The -to variants should be preferred since they allow to determine the - correct ROM script addresses needed for the driver to work without additional - firmware. -- reg : Should contain SDMA registers location and length -- interrupts : Should contain SDMA interrupt -- #dma-cells : Must be <3>. - The first cell specifies the DMA request/event ID. See details below - about the second and third cell. -- fsl,sdma-ram-script-name : Should contain the full path of SDMA RAM - scripts firmware - -The second cell of dma phandle specifies the peripheral type of DMA transfer. -The full ID of peripheral types can be found below. - - ID transfer type - --------------------- - 0 MCU domain SSI - 1 Shared SSI - 2 MMC - 3 SDHC - 4 MCU domain UART - 5 Shared UART - 6 FIRI - 7 MCU domain CSPI - 8 Shared CSPI - 9 SIM - 10 ATA - 11 CCM - 12 External peripheral - 13 Memory Stick Host Controller - 14 Shared Memory Stick Host Controller - 15 DSP - 16 Memory - 17 FIFO type Memory - 18 SPDIF - 19 IPU Memory - 20 ASRC - 21 ESAI - 22 SSI Dual FIFO (needs firmware ver >= 2) - 23 Shared ASRC - 24 SAI - -The third cell specifies the transfer priority as below. - - ID transfer priority - ------------------------- - 0 High - 1 Medium - 2 Low - -Optional properties: - -- gpr : The phandle to the General Purpose Register (GPR) node. -- fsl,sdma-event-remap : Register bits of sdma event remap, the format is - . - reg is the GPR register offset. - shift is the bit position inside the GPR register. - val is the value of the bit (0 or 1). - -Examples: - -sdma@83fb0000 { - compatible = "fsl,imx51-sdma", "fsl,imx35-sdma"; - reg = <0x83fb0000 0x4000>; - interrupts = <6>; - #dma-cells = <3>; - fsl,sdma-ram-script-name = "sdma-imx51.bin"; -}; - -DMA clients connected to the i.MX SDMA controller must use the format -described in the dma.txt file. - -Examples: - -ssi2: ssi@70014000 { - compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; - reg = <0x70014000 0x4000>; - interrupts = <30>; - clocks = <&clks 49>; - dmas = <&sdma 24 1 0>, - <&sdma 25 1 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; -}; - -Using the fsl,sdma-event-remap property: - -If we want to use SDMA on the SAI1 port on a MX6SX: - -&sdma { - gpr = <&gpr>; - /* SDMA events remap for SAI1_RX and SAI1_TX */ - fsl,sdma-event-remap = <0 15 1>, <0 16 1>; -}; - -The fsl,sdma-event-remap property in this case has two values: -- <0 15 1> means that the offset is 0, so GPR0 is the register of the -SDMA remap. Bit 15 of GPR0 selects between UART4_RX and SAI1_RX. -Setting bit 15 to 1 selects SAI1_RX. -- <0 16 1> means that the offset is 0, so GPR0 is the register of the -SDMA remap. Bit 16 of GPR0 selects between UART4_TX and SAI1_TX. -Setting bit 16 to 1 selects SAI1_TX. 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Thu, 1 Sep 2022 01:59:36 +0000 From: Joy Zou To: krzysztof.kozlowski@linaro.org, vkoul@kernel.org Cc: shengjiu.wang@nxp.com, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH V4 2/4] dmaengine: imx-sdma: support hdmi audio Date: Thu, 1 Sep 2022 10:00:59 +0800 Message-Id: <20220901020059.50099-1-joy.zou@nxp.com> X-Mailer: git-send-email 2.37.1 X-ClientProxiedBy: SG2PR02CA0034.apcprd02.prod.outlook.com (2603:1096:3:18::22) To AM6PR04MB5925.eurprd04.prod.outlook.com (2603:10a6:20b:ab::19) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 5abd72d5-4998-4dd7-66fe-08da8bbd9f30 X-MS-TrafficTypeDiagnostic: AS8PR04MB8724:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: pnEB2zwbi94ibr1AAKo87IhxxMd+M4JGO57bSzM1PFCIpqt14/fQGmpOSDU63eHj6eddPla0HkjKICmu6h4Z7LA9ARAq2PeCWUULIgequKLu8v1BTQNB6BmHqC7xjYDGVXa6pR1H5e5h+Jjf1bwHKn8zhEjCCinDHWEtcu+fwaqBh6ryjjB4VLtOyt/1BQw70Em9hzp5ZvdQpUCQcl5sfaSsG8L3J1XVyfjTkhAwiQ3taeQLgdQyTQIuvmksYGCMLGfVQ83qka3PtYJO3+8ZNVhACWhlMXNcB1GNH9AKtdoYxPj255IBSiMSnteWfV0ONFRYSObtfpmbmUYCJ072FSD2N37EGF9FEIDHGPQ6/isA+br7c0/O+c5jvyrvOcK69ooWEERFkODNlYpI8r2rhaBniSxee1xOLZ3ENT1c59e+39irfDNa7thAjiDQ33RQXqboTv2+9cCg4TVfervZ0m9mL8I7FUKx6iz1pamt/DDhjUo7np8CQNxQOsf2a08fuizLYPYzlcdH+2aKcK0R7zhfGv5+fxc4Nm3xUR7c5ScJX6E1W1/8blB1sqTLkwcxrodAqN5sZWhs/DAAulQFMDUwBgBvmWoAzhwaFU0rb7/CtDNTetZMN6WsiG4GMGMHJibj54GsD6aJZtp20RZ1NPS7L3vRtMRYtsFjjO08hdjUWdo3Zls/Xvd6ETu6XWIINeGesb63bft8WltGjAaVbOE+dPB7sJNX1UQ1YL9CvbAXuhJA0oOIBgZB+USlINP8fGW0P4upk/DC8iDGlKH40Q== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:AM6PR04MB5925.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230016)(4636009)(136003)(39860400002)(366004)(396003)(376002)(346002)(8936002)(4326008)(8676002)(66476007)(66556008)(66946007)(6486002)(478600001)(26005)(6512007)(2616005)(1076003)(83380400001)(186003)(6666004)(44832011)(5660300002)(86362001)(52116002)(2906002)(41300700001)(316002)(6506007)(36756003)(38100700002)(38350700002);DIR:OUT;SFP:1101; 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Signed-off-by: Joy Zou --- drivers/dma/imx-sdma.c | 38 +++++++++++++++++++++++++++++-------- include/linux/dma/imx-dma.h | 1 + 2 files changed, 31 insertions(+), 8 deletions(-) diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c index fbea5f62dd98..ab877ceeac3f 100644 --- a/drivers/dma/imx-sdma.c +++ b/drivers/dma/imx-sdma.c @@ -954,7 +954,10 @@ static irqreturn_t sdma_int_handler(int irq, void *dev_id) desc = sdmac->desc; if (desc) { if (sdmac->flags & IMX_DMA_SG_LOOP) { - sdma_update_channel_loop(sdmac); + if (sdmac->peripheral_type != IMX_DMATYPE_HDMI) + sdma_update_channel_loop(sdmac); + else + vchan_cyclic_callback(&desc->vd); } else { mxc_sdma_handle_channel_normal(sdmac); vchan_cookie_complete(&desc->vd); @@ -1074,6 +1077,10 @@ static int sdma_get_pc(struct sdma_channel *sdmac, per_2_emi = sdma->script_addrs->sai_2_mcu_addr; emi_2_per = sdma->script_addrs->mcu_2_sai_addr; break; + case IMX_DMATYPE_HDMI: + emi_2_per = sdma->script_addrs->hdmi_dma_addr; + sdmac->is_ram_script = true; + break; default: dev_err(sdma->dev, "Unsupported transfer type %d\n", peripheral_type); @@ -1125,11 +1132,16 @@ static int sdma_load_context(struct sdma_channel *sdmac) /* Send by context the event mask,base address for peripheral * and watermark level */ - context->gReg[0] = sdmac->event_mask[1]; - context->gReg[1] = sdmac->event_mask[0]; - context->gReg[2] = sdmac->per_addr; - context->gReg[6] = sdmac->shp_addr; - context->gReg[7] = sdmac->watermark_level; + if (sdmac->peripheral_type == IMX_DMATYPE_HDMI) { + context->gReg[4] = sdmac->per_addr; + context->gReg[6] = sdmac->shp_addr; + } else { + context->gReg[0] = sdmac->event_mask[1]; + context->gReg[1] = sdmac->event_mask[0]; + context->gReg[2] = sdmac->per_addr; + context->gReg[6] = sdmac->shp_addr; + context->gReg[7] = sdmac->watermark_level; + } bd0->mode.command = C0_SETDM; bd0->mode.status = BD_DONE | BD_WRAP | BD_EXTD; @@ -1513,7 +1525,7 @@ static struct sdma_desc *sdma_transfer_init(struct sdma_channel *sdmac, desc->sdmac = sdmac; desc->num_bd = bds; - if (sdma_alloc_bd(desc)) + if (bds && sdma_alloc_bd(desc)) goto err_desc_out; /* No slave_config called in MEMCPY case, so do here */ @@ -1678,13 +1690,16 @@ static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic( { struct sdma_channel *sdmac = to_sdma_chan(chan); struct sdma_engine *sdma = sdmac->sdma; - int num_periods = buf_len / period_len; + int num_periods = 0; int channel = sdmac->channel; int i = 0, buf = 0; struct sdma_desc *desc; dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel); + if (sdmac->peripheral_type != IMX_DMATYPE_HDMI) + num_periods = buf_len / period_len; + sdma_config_write(chan, &sdmac->slave_config, direction); desc = sdma_transfer_init(sdmac, direction, num_periods); @@ -1701,6 +1716,9 @@ static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic( goto err_bd_out; } + if (sdmac->peripheral_type == IMX_DMATYPE_HDMI) + return vchan_tx_prep(&sdmac->vc, &desc->vd, flags); + while (buf < buf_len) { struct sdma_buffer_descriptor *bd = &desc->bd[i]; int param; @@ -1761,6 +1779,10 @@ static int sdma_config_write(struct dma_chan *chan, sdmac->watermark_level |= (dmaengine_cfg->dst_maxburst << 16) & SDMA_WATERMARK_LEVEL_HWML; sdmac->word_size = dmaengine_cfg->dst_addr_width; + } else if (sdmac->peripheral_type == IMX_DMATYPE_HDMI) { + sdmac->per_address = dmaengine_cfg->dst_addr; + sdmac->per_address2 = dmaengine_cfg->src_addr; + sdmac->watermark_level = 0; } else { sdmac->per_address = dmaengine_cfg->dst_addr; sdmac->watermark_level = dmaengine_cfg->dst_maxburst * diff --git a/include/linux/dma/imx-dma.h b/include/linux/dma/imx-dma.h index f487a4fa103a..cfec5f946e23 100644 --- a/include/linux/dma/imx-dma.h +++ b/include/linux/dma/imx-dma.h @@ -40,6 +40,7 @@ enum sdma_peripheral_type { IMX_DMATYPE_ASRC_SP, /* Shared ASRC */ IMX_DMATYPE_SAI, /* SAI */ IMX_DMATYPE_MULTI_SAI, /* MULTI FIFOs For Audio */ + IMX_DMATYPE_HDMI, /* HDMI Audio */ }; enum imx_dma_prio {