From patchwork Thu Sep 1 06:00:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 12961854 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A9BBEECAAD2 for ; Thu, 1 Sep 2022 06:01:28 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3408810E59C; Thu, 1 Sep 2022 06:01:24 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id B9FFE10E54F for ; Thu, 1 Sep 2022 06:01:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1662012080; x=1693548080; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=uCGcg6O5+qGQDYYxwQ/y0/rs66x+CfgKY7ZqbC8RvqM=; b=QnKxv3ZpQVY9d7gbzbECtqi2xyWkt/8WI1qvFMoeqEILhCd2x85vqKBd UyRWS+0yNJhsJt4ZuS93uUC9uEVW/j1RRmcRR3koPTOS9Jlf9Jt2maxB1 YXM58sENT335DUCqMCZB4ZFUkHDXLTiXKCG6uuI98dEEbRO+sTYr94tBF nE8VRps8AEYQj3haChmr7Pnw68u/uB06WPhxP760zFkdWmnjMJu4xtmyA qVsHur5+iU7/rIY3jY9Gge2YzIdEphlFhGwzwBaQOUGFg0ScQSp1V4SzE vkjnZUVO3vIjDO+XiiwKCI69kNy9LiYIa0018FCuar1rUmT4DReUw95EK g==; X-IronPort-AV: E=McAfee;i="6500,9779,10456"; a="381920220" X-IronPort-AV: E=Sophos;i="5.93,280,1654585200"; d="scan'208";a="381920220" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Aug 2022 23:01:20 -0700 X-IronPort-AV: E=Sophos;i="5.93,280,1654585200"; d="scan'208";a="754685612" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Aug 2022 23:01:18 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Date: Thu, 1 Sep 2022 11:30:53 +0530 Message-Id: <20220901060101.1000290-2-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220901060101.1000290-1-ankit.k.nautiyal@intel.com> References: <20220901060101.1000290-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 1/9] drm/i915/dp: Reset frl trained flag before restarting FRL training X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" For cases where DP has HDMI2.1 sink and FRL Link issues are detected, reset the flag to state FRL trained status before restarting FRL training. Fixes: 9488a030ac91 ("drm/i915: Add support for enabling link status and recovery") Cc: Swati Sharma Cc: Ankit Nautiyal Cc: Uma Shankar (v2) Cc: Jani Nikula Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index d4e037450ac5..e9e5e4606d9c 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -3958,6 +3958,8 @@ intel_dp_handle_hdmi_link_status_change(struct intel_dp *intel_dp) drm_dp_pcon_hdmi_frl_link_error_count(&intel_dp->aux, &intel_dp->attached_connector->base); + intel_dp->frl.is_trained = false; + /* Restart FRL training or fall back to TMDS mode */ intel_dp_check_frl_training(intel_dp); } From patchwork Thu Sep 1 06:00:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 12961855 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E38EBECAAD2 for ; Thu, 1 Sep 2022 06:01:32 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1CED010E5A5; Thu, 1 Sep 2022 06:01:27 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id E3B0310E59C for ; Thu, 1 Sep 2022 06:01:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1662012082; x=1693548082; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=M+iNAiSHD0jFR5WGKnWiyzl6kewUQK5M50bkGdQdXuw=; b=iZIanXNXctMesCWA+hFMJQXCoNUHQiylB5AHm081f9h4EEdM2AVUnhoj kMWE3P/H1i0VTq6gz9ldDPZ4IxkcZSPrnID4x9ZrXOv3ZWlzuDVLSwzti WK5zaqRpK17q60DWa10I0LQUCBejbLHn4JmKIp6DOrGOip6860k84WDk0 2zTr7I6iDi7SPYNwhuujldmp+MxLv0dA6MtKqOjbV46FskgIcKbA/jpfq eT5KZixLWTVXPjfrRfdqkJFcVd9KRom3KXIAs2APVvUzMzQP4B95vTd0P dFccxUUXBwwnZaTg37RQnMDHFjatxciMtD+k/SeAyQ8HvHo503W9WR79W A==; X-IronPort-AV: E=McAfee;i="6500,9779,10456"; a="381920229" X-IronPort-AV: E=Sophos;i="5.93,280,1654585200"; d="scan'208";a="381920229" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Aug 2022 23:01:22 -0700 X-IronPort-AV: E=Sophos;i="5.93,280,1654585200"; d="scan'208";a="754685631" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Aug 2022 23:01:20 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Date: Thu, 1 Sep 2022 11:30:54 +0530 Message-Id: <20220901060101.1000290-3-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220901060101.1000290-1-ankit.k.nautiyal@intel.com> References: <20220901060101.1000290-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 2/9] drm/i915/dp: Add RGB to YCBCR conversion case in is_dp_ycbcr420 helper X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add the case for RGB444 to YCBCR444 conversion required by the DFP in the helper to check if output format is YCBCR420. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index e9e5e4606d9c..a05b8b86e5c8 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1197,6 +1197,9 @@ static bool intel_dp_is_ycbcr420(struct intel_dp *intel_dp, { return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 || (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 && + intel_dp->dfp.ycbcr_444_to_420) || + (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB && + intel_dp->dfp.rgb_to_ycbcr && intel_dp->dfp.ycbcr_444_to_420); } From patchwork Thu Sep 1 06:00:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 12961857 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 23683ECAAD1 for ; Thu, 1 Sep 2022 06:01:36 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E095F10E5A6; Thu, 1 Sep 2022 06:01:30 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 19D5610E5A5 for ; Thu, 1 Sep 2022 06:01:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1662012085; x=1693548085; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=k4N/YrjsB2EMTKQlgIulEL4noVYSnkMu1CkwCnxtrD0=; b=F80wSwiGt8klvmUZTXgCgfziBHXmRKXBFbLpTHTw5iwYlknnfQ8kvNnF c6lp8wdeL4pZqXwkX2YtWo3Xv/ZJn2tbJkTg6aSu3WL/+LkkcgjxJe+HD RUoRpDnS44cAro81KDFOgyts/IbzGTTY86rdOBeKblmSfwFilinFW43rt xnmEIo73kfcsD4WJ3ix5NHymCkfzJbifswY0lz3pRaAOhI9eUts6DoSzv fWWazlolRR4gDlssf9WtgyZ9H+HQXH9S9MF4MEsoHeNQ6PPIUfQBV/2Aq 6AHSewoR+RCPo+drEaezAAou1Q6nqN7vEGfndyghzNJjVZE7O3CgVZ1O7 Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10456"; a="381920234" X-IronPort-AV: E=Sophos;i="5.93,280,1654585200"; d="scan'208";a="381920234" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Aug 2022 23:01:24 -0700 X-IronPort-AV: E=Sophos;i="5.93,280,1654585200"; d="scan'208";a="754685657" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Aug 2022 23:01:23 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Date: Thu, 1 Sep 2022 11:30:55 +0530 Message-Id: <20220901060101.1000290-4-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220901060101.1000290-1-ankit.k.nautiyal@intel.com> References: <20220901060101.1000290-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 3/9] drm/i915/dp: Remove whitespace at the end of function. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Remove extraline left after intel_dp_configure_protocol_converter. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index a05b8b86e5c8..b6f62444b589 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2690,7 +2690,6 @@ void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp, str_enable_disable(tmp)); } - bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp) { u8 dprx = 0; From patchwork Thu Sep 1 06:00:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 12961856 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 45452ECAAD2 for ; Thu, 1 Sep 2022 06:01:39 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B24BB10E5AB; Thu, 1 Sep 2022 06:01:34 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 492D710E5A6 for ; Thu, 1 Sep 2022 06:01:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1662012087; x=1693548087; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=AQ8fRJYCGfwdCQMd91PKti8jEIMCfNXdBLP0SpF3tVo=; b=W8/qK+ZB7x6gKb7zzv8rhLIHeZku24Yp+PGAR32JpKizmV9Kl/aIk9lF u2AXRUrfzkG1KKPjsPAKpbuqv/sNlE02CZnlBJo2kqWO60Z2Jr7UIauKb COJGNsZfq7t5psPvdTKRq/YaHuh0ecvlN5D7FznbNZcVGD4RAIsFvvR/b 06kzDDVDCHnf1HU7G0CgC2WxycDpwnNraCzeLYzb2e4N2Um/NbD9MV/q8 V7MtoyuLJ25iQQezJ/N+1H9ENWjNNRaOTz6oDjILSNRV2Vv2PB0E74AAK aqMYS8bcQWf3Yicrdzr/GHVf1+PBwVKX1Q2CDPiC3PVBedNL+udPKB5Re w==; X-IronPort-AV: E=McAfee;i="6500,9779,10456"; a="381920240" X-IronPort-AV: E=Sophos;i="5.93,280,1654585200"; d="scan'208";a="381920240" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Aug 2022 23:01:27 -0700 X-IronPort-AV: E=Sophos;i="5.93,280,1654585200"; d="scan'208";a="754685681" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Aug 2022 23:01:25 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Date: Thu, 1 Sep 2022 11:30:56 +0530 Message-Id: <20220901060101.1000290-5-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220901060101.1000290-1-ankit.k.nautiyal@intel.com> References: <20220901060101.1000290-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 4/9] drm/i915/display: Add new members to configure PCON color conversion X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The decision to use DFP output format conversion capabilities should be during compute_config phase. This patch adds new members to crtc_state to help configure the DFP output related conversions. Also adds a member to intel_dp to store ycbcr420 pass through capability. This will help to store only the format conversion capabilities of the DP device in intel_dp->dfp, and use crtc_state to compute and store the configuration for color/format conversion for a given mode. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_display_types.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 0da9b208d56e..065ed19a5dd3 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1311,6 +1311,12 @@ struct intel_crtc_state { /* for loading single buffered registers during vblank */ struct drm_vblank_work vblank_work; + + /* DP DFP color configuration */ + struct { + bool rgb_to_ycbcr; + bool ycbcr_444_to_420; + } dp_dfp_config; }; enum intel_pipe_crc_source { @@ -1704,6 +1710,7 @@ struct intel_dp { int pcon_max_frl_bw; u8 max_bpc; bool ycbcr_444_to_420; + bool ycbcr420_passthrough; bool rgb_to_ycbcr; } dfp; From patchwork Thu Sep 1 06:00:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 12961860 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 77C94ECAAD1 for ; Thu, 1 Sep 2022 06:01:47 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 290C610E5B4; Thu, 1 Sep 2022 06:01:39 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id ECB8010E5A6 for ; Thu, 1 Sep 2022 06:01:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1662012089; x=1693548089; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=48fvnGmwuKwtMyoLkXN59oWM6NQpbtY+cpaXo4jfK+U=; b=GV1TLUtMUmjoAw5H1NiCW4LcBif9nsIaBqwlAaNG5XVxoqTxb9s1+29J IHAcobFsNJAcY4UGSggKHElNfWy/iXWMF36AkH7r0JqZcx/pXZdJ8Hit4 e8BqQXvPqK8Nqo9bms6ytNTtO+gRzW8ztMnQvqb8++/lldhlsIwiPpNAn 5HZARTe3pNApR2pkSO/0Iau/HPvqzTdciU/Th1z0p7CfAtrqFlWPap/v6 RrYGxbxG/9vWLHpGwOlgSEt3nEspknjYYJKbyxVu3i+cR1LjVioQym7Pl olIGUl0b/TCM5QwCQqyalKaVsdH9t4z1SiDFwTf8Blzl1CkqM9yiDWbhj w==; X-IronPort-AV: E=McAfee;i="6500,9779,10456"; a="381920247" X-IronPort-AV: E=Sophos;i="5.93,280,1654585200"; d="scan'208";a="381920247" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Aug 2022 23:01:29 -0700 X-IronPort-AV: E=Sophos;i="5.93,280,1654585200"; d="scan'208";a="754685706" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Aug 2022 23:01:27 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Date: Thu, 1 Sep 2022 11:30:57 +0530 Message-Id: <20220901060101.1000290-6-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220901060101.1000290-1-ankit.k.nautiyal@intel.com> References: <20220901060101.1000290-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 5/9] drm/i915/dp: Compute configuration for using PCON's color/format conversion X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Fill the crtc_state members to store the configuration required by PCONs for color/format conversion for a YCBCR420 mode and the computed output format. This will be later used during protocol_converter_config to program the PCON to use appropriate color/format conversion. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 27 +++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index b6f62444b589..4c1a0d9f750c 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1970,6 +1970,30 @@ static bool intel_dp_has_audio(struct intel_encoder *encoder, return intel_conn_state->force_audio == HDMI_AUDIO_ON; } +static void +intel_dp_compute_dfp_ycbcr420(struct intel_encoder *encoder, + struct intel_crtc_state *crtc_state) +{ + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); + + if (!drm_dp_is_branch(intel_dp->dpcd)) + return; + + /* Mode is YCBCR420, output_format is also YCBCR420: Passthrough */ + if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) + return; + + /* Mode is YCBCR420, output_format is YCBCR444: Downsample */ + if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) { + crtc_state->dp_dfp_config.ycbcr_444_to_420 = true; + return; + } + + /* Mode is YCBCR420, output_format is RGB: Convert to YCBCR444 and Downsample */ + crtc_state->dp_dfp_config.rgb_to_ycbcr = true; + crtc_state->dp_dfp_config.ycbcr_444_to_420 = true; +} + static int intel_dp_compute_output_format(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state, @@ -1987,6 +2011,8 @@ intel_dp_compute_output_format(struct intel_encoder *encoder, ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode); crtc_state->output_format = intel_dp_output_format(connector, ycbcr_420_only); + if (ycbcr_420_only) + intel_dp_compute_dfp_ycbcr420(encoder, crtc_state); if (ycbcr_420_only && !intel_dp_is_ycbcr420(intel_dp, crtc_state)) { drm_dbg_kms(&i915->drm, @@ -2003,6 +2029,7 @@ intel_dp_compute_output_format(struct intel_encoder *encoder, return ret; crtc_state->output_format = intel_dp_output_format(connector, true); + intel_dp_compute_dfp_ycbcr420(encoder, crtc_state); ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state, respect_downstream_limits); } From patchwork Thu Sep 1 06:00:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 12961859 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E50C1ECAAD8 for ; Thu, 1 Sep 2022 06:01:44 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A745B10E5AC; Thu, 1 Sep 2022 06:01:37 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id D58FC10E5AB for ; Thu, 1 Sep 2022 06:01:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1662012091; x=1693548091; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2540V2KVCW+5+o4xnuXt7tt7eZ+D5Sal3LyfsekSN14=; b=VV8n2ydCK20irdsIdoOFOxPHMsBohwjz58Ot2bxRaCzmJviMfrjlDRu1 zMXlKoqPnY1rEt2MvG0wIQfMRaPyqiA8Ir5VcY4GgCyRoivmwIKHBEdi6 J72wBE/VQKhU0fv79As0r1bZjQElM8ZWRZVLr3Qv3SO7qhD0Cz3PCujT+ Gdseibq2wn411r4X45OyuNGAAjnooUOtTD8aBNRf7k+4bjpaaYa7OvpG+ c/MrGGjdtL15WwRx957Q06ThfGlGpW26wtOKHldnJfYYysqioa7QC4Mtr 27n9b/RkD6d+g4+jeFtVS1hUDnjEQBLwOsY3P1JE3WvsdoJ2HFvDNVtum w==; X-IronPort-AV: E=McAfee;i="6500,9779,10456"; a="381920252" X-IronPort-AV: E=Sophos;i="5.93,280,1654585200"; d="scan'208";a="381920252" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Aug 2022 23:01:31 -0700 X-IronPort-AV: E=Sophos;i="5.93,280,1654585200"; d="scan'208";a="754685715" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Aug 2022 23:01:29 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Date: Thu, 1 Sep 2022 11:30:58 +0530 Message-Id: <20220901060101.1000290-7-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220901060101.1000290-1-ankit.k.nautiyal@intel.com> References: <20220901060101.1000290-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 6/9] drm/i915/dp: Use crtc_state members in dp_is_ycbcr420 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Use the new crtc_state members to check if DP DFP will use YCBCR420. The earlier intel_dp->dfp members are not required as decision to use color format conversion by the PCON is computed and stored in crtc_state. Also drop the intel_dp argument in the helper function. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 4c1a0d9f750c..f3c2aeda0c1d 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1192,22 +1192,21 @@ static bool intel_dp_supports_dsc(struct intel_dp *intel_dp, drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd); } -static bool intel_dp_is_ycbcr420(struct intel_dp *intel_dp, - const struct intel_crtc_state *crtc_state) +static bool intel_dp_is_ycbcr420(const struct intel_crtc_state *crtc_state) { return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 || (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 && - intel_dp->dfp.ycbcr_444_to_420) || + crtc_state->dp_dfp_config.ycbcr_444_to_420) || (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB && - intel_dp->dfp.rgb_to_ycbcr && - intel_dp->dfp.ycbcr_444_to_420); + crtc_state->dp_dfp_config.rgb_to_ycbcr && + crtc_state->dp_dfp_config.ycbcr_444_to_420); } static int intel_dp_hdmi_compute_bpc(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state, int bpc, bool respect_downstream_limits) { - bool ycbcr420_output = intel_dp_is_ycbcr420(intel_dp, crtc_state); + bool ycbcr420_output = intel_dp_is_ycbcr420(crtc_state); int clock = crtc_state->hw.adjusted_mode.crtc_clock; /* @@ -2014,7 +2013,7 @@ intel_dp_compute_output_format(struct intel_encoder *encoder, if (ycbcr_420_only) intel_dp_compute_dfp_ycbcr420(encoder, crtc_state); - if (ycbcr_420_only && !intel_dp_is_ycbcr420(intel_dp, crtc_state)) { + if (ycbcr_420_only && !intel_dp_is_ycbcr420(crtc_state)) { drm_dbg_kms(&i915->drm, "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n"); crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB; @@ -2023,7 +2022,7 @@ intel_dp_compute_output_format(struct intel_encoder *encoder, ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state, respect_downstream_limits); if (ret) { - if (intel_dp_is_ycbcr420(intel_dp, crtc_state) || + if (intel_dp_is_ycbcr420(crtc_state) || !connector->base.ycbcr_420_allowed || !drm_mode_is_420_also(info, adjusted_mode)) return ret; From patchwork Thu Sep 1 06:00:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 12961858 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0A81AECAAD2 for ; Thu, 1 Sep 2022 06:01:42 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 97B0F10E5AE; Thu, 1 Sep 2022 06:01:36 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 11F8810E5AB for ; Thu, 1 Sep 2022 06:01:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1662012094; x=1693548094; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=JCekVWjOTmkA+7q/V9YoB1gnGzNe42JEQizr1QEpJnQ=; b=k4wzkP/DJABHf7HBrkyJQGzNRzkq7dgTxxkxDnwzvLnhYqmyK5mVtMcz JSz9tH+paJSOgqM//DhHFtzumOGd9rsI0yHKN8A7lBF7VgImHMlnsVVEY QgsD5xl9+55I78nzIZJbegeXMy+bIfo/wNiHik6QNKlOqfgJmgKFZONbI uvA0hsNy3QlohWOxD3H0ZGbd3llwC4Sc/pwXnGNcFWyaOdpj/yiE2OzZL CrQT0rsDsYzLQs9ZVX/cGuGw3h6B3iOO3QZAT5C72jKR7U+a90epbI6n5 PySh1+rABNlaKDZDdQiM8NYS1nPHsBJVYLt4LKaOglaXurOv9Q0ajOVJ7 w==; X-IronPort-AV: E=McAfee;i="6500,9779,10456"; a="381920256" X-IronPort-AV: E=Sophos;i="5.93,280,1654585200"; d="scan'208";a="381920256" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Aug 2022 23:01:33 -0700 X-IronPort-AV: E=Sophos;i="5.93,280,1654585200"; d="scan'208";a="754685727" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Aug 2022 23:01:31 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Date: Thu, 1 Sep 2022 11:30:59 +0530 Message-Id: <20220901060101.1000290-8-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220901060101.1000290-1-ankit.k.nautiyal@intel.com> References: <20220901060101.1000290-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 7/9] drm/i915/dp: Replace intel_dp.dfp members with the new crtc_state dp_dfp members X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The decision to use DFP output format conversion capabilities should be during compute_config phase. This patch uses the members of intel_dp->dfp to only store the format conversion capabilities of the DP device and uses the crtc_state dp_dfp members that are computed earlier, to program the protocol-converter for colorspace/format conversion. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 46 +++++++++---------------- 1 file changed, 17 insertions(+), 29 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index f3c2aeda0c1d..409bd9cdf450 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -805,6 +805,7 @@ intel_dp_output_format(struct intel_connector *connector, bool ycbcr_420_output) { struct intel_dp *intel_dp = intel_attached_dp(connector); + struct drm_i915_private *i915 = dp_to_i915(intel_dp); if (!connector->base.ycbcr_420_allowed || !ycbcr_420_output) return INTEL_OUTPUT_FORMAT_RGB; @@ -813,6 +814,10 @@ intel_dp_output_format(struct intel_connector *connector, intel_dp->dfp.ycbcr_444_to_420) return INTEL_OUTPUT_FORMAT_RGB; + /* Prefer 4:2:0 passthrough over 4:4:4->4:2:0 conversion */ + if (DISPLAY_VER(i915) >= 11 && intel_dp->dfp.ycbcr420_passthrough) + return INTEL_OUTPUT_FORMAT_YCBCR420; + if (intel_dp->dfp.ycbcr_444_to_420) return INTEL_OUTPUT_FORMAT_YCBCR444; else @@ -2698,8 +2703,8 @@ void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp, drm_dbg_kms(&i915->drm, "Failed to %s protocol converter HDMI mode\n", str_enable_disable(intel_dp->has_hdmi_sink)); - tmp = crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 && - intel_dp->dfp.ycbcr_444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0; + tmp = crtc_state->dp_dfp_config.ycbcr_444_to_420 ? + DP_CONVERSION_TO_YCBCR420_ENABLE : 0; if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1) @@ -2707,7 +2712,7 @@ void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp, "Failed to %s protocol converter YCbCr 4:2:0 conversion mode\n", str_enable_disable(intel_dp->dfp.ycbcr_444_to_420)); - tmp = intel_dp->dfp.rgb_to_ycbcr ? + tmp = crtc_state->dp_dfp_config.rgb_to_ycbcr ? DP_CONVERSION_BT709_RGB_YCBCR_ENABLE : 0; if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0) @@ -4563,7 +4568,7 @@ intel_dp_update_420(struct intel_dp *intel_dp) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); struct intel_connector *connector = intel_dp->attached_connector; - bool is_branch, ycbcr_420_passthrough, ycbcr_444_to_420, rgb_to_ycbcr; + bool is_branch; /* No YCbCr output support on gmch platforms */ if (HAS_GMCH(i915)) @@ -4577,38 +4582,21 @@ intel_dp_update_420(struct intel_dp *intel_dp) return; is_branch = drm_dp_is_branch(intel_dp->dpcd); - ycbcr_420_passthrough = + intel_dp->dfp.ycbcr420_passthrough = drm_dp_downstream_420_passthrough(intel_dp->dpcd, intel_dp->downstream_ports); /* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */ - ycbcr_444_to_420 = + intel_dp->dfp.ycbcr_444_to_420 = dp_to_dig_port(intel_dp)->lspcon.active || drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd, intel_dp->downstream_ports); - rgb_to_ycbcr = drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd, - intel_dp->downstream_ports, - DP_DS_HDMI_BT709_RGB_YCBCR_CONV); - - if (DISPLAY_VER(i915) >= 11) { - /* Let PCON convert from RGB->YCbCr if possible */ - if (is_branch && rgb_to_ycbcr && ycbcr_444_to_420) { - intel_dp->dfp.rgb_to_ycbcr = true; - intel_dp->dfp.ycbcr_444_to_420 = true; - connector->base.ycbcr_420_allowed = true; - } else { - /* Prefer 4:2:0 passthrough over 4:4:4->4:2:0 conversion */ - intel_dp->dfp.ycbcr_444_to_420 = - ycbcr_444_to_420 && !ycbcr_420_passthrough; + intel_dp->dfp.rgb_to_ycbcr = + drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd, + intel_dp->downstream_ports, + DP_DS_HDMI_BT709_RGB_YCBCR_CONV); - connector->base.ycbcr_420_allowed = - !is_branch || ycbcr_444_to_420 || ycbcr_420_passthrough; - } - } else { - /* 4:4:4->4:2:0 conversion is the only way */ - intel_dp->dfp.ycbcr_444_to_420 = ycbcr_444_to_420; - - connector->base.ycbcr_420_allowed = ycbcr_444_to_420; - } + if (!is_branch || intel_dp->dfp.ycbcr420_passthrough || intel_dp->dfp.ycbcr_444_to_420) + connector->base.ycbcr_420_allowed = true; drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] RGB->YcbCr conversion? %s, YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversion? %s\n", From patchwork Thu Sep 1 06:01:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 12961861 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 92EF3ECAAD1 for ; Thu, 1 Sep 2022 06:01:49 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0DE8B10E5B9; Thu, 1 Sep 2022 06:01:45 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 489A310E5AC for ; Thu, 1 Sep 2022 06:01:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1662012096; x=1693548096; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=yeMQr6PnecT2Fnj4vk2w4T3MJ9fgSNuGrbqwfgO6k+w=; b=eJB9ADNis+d19bISsptLlCF0RyhTGdiKM1g/NIihuGqgDcqzY/tzTH63 Mm1Ws5iSisg0qzUz8G354biNh3wvrReVA/Zo6LG3ODjOo29mPfWAFH3aH JvGPBgx6pnarvi1YxAUsqacSPK2tYzgIoDYWUc5BfaTBowj5qrX03pzyP PaHDFS9M1DFwfJuRExG7+jvWs5g3vlMVBp41XS/Uncunq/ebtIifo1Nzz GoYC3sadravRqwyxBaLhSqm3BKM3i9oIRwWs5t2fe7J/V50VzO8LYQWTP nH4DDS80f0hllmUORnTzMwnn4eyFGYrPrEzdb9ICWdTylQwAx8ojezKfF g==; X-IronPort-AV: E=McAfee;i="6500,9779,10456"; a="381920264" X-IronPort-AV: E=Sophos;i="5.93,280,1654585200"; d="scan'208";a="381920264" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Aug 2022 23:01:36 -0700 X-IronPort-AV: E=Sophos;i="5.93,280,1654585200"; d="scan'208";a="754685736" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Aug 2022 23:01:34 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Date: Thu, 1 Sep 2022 11:31:00 +0530 Message-Id: <20220901060101.1000290-9-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220901060101.1000290-1-ankit.k.nautiyal@intel.com> References: <20220901060101.1000290-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 8/9] drm/i915/dp: Handle BPP where HDMI2.1 DFP doesn't support DSC X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Currently we use the highest input BPC supported by DP sink while using DSC.In cases where PCON with HDMI2.1 as branch device, if PCON supports DSC but HDMI2.1 sink does not supports DSC, The PCON tries to use same input BPC that is used between Source and the PCON without DSC, which might not work even with the maximum FRL rate supported by HDMI2.1 sink. This patch calculates the max BPC that can be sufficient with either RGB or YCBCR420 format for the maximum FRL rate supported. v2: Rebase Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 92 ++++++++++++++++++++++++- 1 file changed, 91 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 409bd9cdf450..7c5843f6608d 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -117,6 +117,7 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp) static void intel_dp_unset_edid(struct intel_dp *intel_dp); static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc); +static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp); /* Is link rate UHBR and thus 128b/132b? */ bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state) @@ -1461,12 +1462,82 @@ static int intel_dp_dsc_compute_params(struct intel_encoder *encoder, return drm_dsc_compute_rc_parameters(vdsc_cfg); } +static int +_intel_dp_pcon_hdmi21_get_bpp_nodsc(struct intel_dp *intel_dp, + const struct drm_display_mode *adjusted_mode, + int max_bpc, bool is_ycbcr420) +{ + struct intel_connector *intel_connector = intel_dp->attached_connector; + struct drm_connector *connector = &intel_connector->base; + int i, num_bpc; + u8 dsc_bpc[3] = {0}; + int req_rate_gbps; + int max_frl_rate = connector->display_info.hdmi.max_lanes * + connector->display_info.hdmi.max_frl_rate_per_lane; + + /* + * Currently DSC with Ycbcr420 is not supported. So for modes with Ycbcr420, + * DSC will use RGB and support for RGB->YCBCR444->YCBCR420 conversion is + * required from DP HDMI2.1 PCON. + */ + if (is_ycbcr420 && !(intel_dp->dfp.rgb_to_ycbcr || intel_dp->dfp.ycbcr_444_to_420)) + return 0; + + num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd, + dsc_bpc); + for (i = 0; i < num_bpc; i++) { + if (dsc_bpc[i] > max_bpc) + continue; + + req_rate_gbps = DIV_ROUND_UP(dsc_bpc[i] * 3 * adjusted_mode->clock, 1000000); + + /* YCBCR420 reduces data rate by 2 */ + if (is_ycbcr420) + req_rate_gbps /= 2; + + if (req_rate_gbps < max_frl_rate) + return dsc_bpc[i] * 3; + } + + return 0; +} + +static int +intel_dp_pcon_hdmi21_get_bpp_nodsc(struct intel_dp *intel_dp, + struct intel_crtc_state *pipe_config, + int max_bpc) +{ + const struct drm_display_mode *adjusted_mode = + &pipe_config->hw.adjusted_mode; + struct intel_connector *connector = intel_dp->attached_connector; + const struct drm_display_info *info = &connector->base.display_info; + bool is_ycbcr420 = drm_mode_is_420_only(info, adjusted_mode); + int pipe_bpp; + + pipe_bpp = _intel_dp_pcon_hdmi21_get_bpp_nodsc(intel_dp, adjusted_mode, + max_bpc, is_ycbcr420); + if (!pipe_bpp && !is_ycbcr420 && drm_mode_is_420_also(info, adjusted_mode)) { + is_ycbcr420 = true; + pipe_bpp = _intel_dp_pcon_hdmi21_get_bpp_nodsc(intel_dp, adjusted_mode, + max_bpc, is_ycbcr420); + } + + if (!pipe_bpp && is_ycbcr420) { + pipe_config->dp_dfp_config.rgb_to_ycbcr = true; + pipe_config->dp_dfp_config.ycbcr_444_to_420 = true; + } + + return pipe_bpp; +} + static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state, struct link_config_limits *limits) { struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); + struct intel_connector *intel_connector = intel_dp->attached_connector; + struct drm_connector *connector = &intel_connector->base; struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; @@ -1479,7 +1550,26 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, if (!intel_dp_supports_dsc(intel_dp, pipe_config)) return -EINVAL; - pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc); + /* + * In cases where PCON with HDMI2.1 as branch device, if PCON supports + * DSC but HDMI2.1 sink does not supports DSC, The PCON tries to use same + * input DSC bpc that is used between Source and PCON with Ycbcr420 + * format. + * So use the max BPC that will be sufficient to show the mode in YCbcr420 + * without DSC from PCON->HDMI2.1 + */ + if (intel_dp_is_hdmi_2_1_sink(intel_dp) && + !connector->display_info.hdmi.dsc_cap.v_1p2) { + pipe_bpp = intel_dp_pcon_hdmi21_get_bpp_nodsc(intel_dp, pipe_config, + conn_state->max_requested_bpc); + if (!pipe_bpp) { + drm_dbg_kms(&dev_priv->drm, + "No BPC possible to support the mode without HDMI2.1 DSC\n"); + return -EINVAL; + } + } else { + pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc); + } /* Min Input BPC for ICL+ is 8 */ if (pipe_bpp < 8 * 3) { From patchwork Thu Sep 1 06:01:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 12961862 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8D00CECAAD2 for ; Thu, 1 Sep 2022 06:01:51 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8803810E5B5; Thu, 1 Sep 2022 06:01:44 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 76AB510E5B0 for ; Thu, 1 Sep 2022 06:01:38 +0000 (UTC) DKIM-Signature: v=1; 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31 Aug 2022 23:01:36 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Date: Thu, 1 Sep 2022 11:31:01 +0530 Message-Id: <20220901060101.1000290-10-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220901060101.1000290-1-ankit.k.nautiyal@intel.com> References: <20220901060101.1000290-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 9/9] drm/i915/dp: Fix FRL BW check for HDMI2.1 DFP X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" During FRL bandwidth check for downstream HDMI2.1 sink, the min BPC supported is incorrectly taken for DP, and the check does not consider ybcr420 only modes. This patch fixes the bandwidth calculation similar to the TMDS case, by taking min 8Bpc and considering Ycbcr420 only modes. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 52 ++++++++++++++++++------- 1 file changed, 39 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 7c5843f6608d..5f5cf38d2c84 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -118,6 +118,7 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp) static void intel_dp_unset_edid(struct intel_dp *intel_dp); static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc); static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp); +static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp); /* Is link rate UHBR and thus 128b/132b? */ bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state) @@ -913,6 +914,32 @@ intel_dp_tmds_clock_valid(struct intel_dp *intel_dp, return MODE_OK; } +static int +intel_dp_frl_bw_valid(struct intel_dp *intel_dp, int target_clock, + int bpc, bool ycbcr_420_only) +{ + int target_bw; + int max_frl_bw; + int bpp = bpc * 3; + + if (ycbcr_420_only) + target_clock /= 2; + + target_bw = bpp * target_clock; + + /* check for MAX FRL BW for both PCON and HDMI2.1 sink */ + max_frl_bw = min(intel_dp->dfp.pcon_max_frl_bw, + intel_dp_hdmi_sink_max_frl(intel_dp)); + + /* converting bw from Gbps to Kbps*/ + max_frl_bw = max_frl_bw * 1000000; + + if (target_bw > max_frl_bw) + return MODE_CLOCK_HIGH; + + return MODE_OK; +} + static enum drm_mode_status intel_dp_mode_valid_downstream(struct intel_connector *connector, const struct drm_display_mode *mode, @@ -921,23 +948,24 @@ intel_dp_mode_valid_downstream(struct intel_connector *connector, struct intel_dp *intel_dp = intel_attached_dp(connector); const struct drm_display_info *info = &connector->base.display_info; enum drm_mode_status status; - bool ycbcr_420_only; + bool ycbcr_420_only = drm_mode_is_420_only(info, mode); /* If PCON supports FRL MODE, check FRL bandwidth constraints */ if (intel_dp->dfp.pcon_max_frl_bw) { - int target_bw; - int max_frl_bw; - int bpp = intel_dp_mode_min_output_bpp(connector, mode); - - target_bw = bpp * target_clock; - max_frl_bw = intel_dp->dfp.pcon_max_frl_bw; + /* Assume 8bpc for the HDMI2.1 FRL BW check */ + status = intel_dp_frl_bw_valid(intel_dp, target_clock, 8, ycbcr_420_only); - /* converting bw from Gbps to Kbps*/ - max_frl_bw = max_frl_bw * 1000000; + if (status != MODE_OK) { + if (ycbcr_420_only || + !connector->base.ycbcr_420_allowed || + !drm_mode_is_420_also(info, mode)) + return status; - if (target_bw > max_frl_bw) - return MODE_CLOCK_HIGH; + status = intel_dp_frl_bw_valid(intel_dp, target_clock, 8, true); + if (status != MODE_OK) + return status; + } return MODE_OK; } @@ -946,8 +974,6 @@ intel_dp_mode_valid_downstream(struct intel_connector *connector, target_clock > intel_dp->dfp.max_dotclock) return MODE_CLOCK_HIGH; - ycbcr_420_only = drm_mode_is_420_only(info, mode); - /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */ status = intel_dp_tmds_clock_valid(intel_dp, target_clock, 8, ycbcr_420_only, true);