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[109.15.145.210]) by smtp.googlemail.com with ESMTPSA id e3-20020adfe383000000b0021ef34124ebsm15399016wrm.11.2022.09.01.06.40.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Sep 2022 06:40:02 -0700 (PDT) From: Amjad Ouled-Ameur To: matthias.bgg@gmail.com Cc: Fabien Parent , rafael@kernel.org, amitk@kernel.org, daniel.lezcano@linaro.org, devicetree@vger.kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-pm@vger.kernel.org, robh+dt@kernel.org, rui.zhang@intel.com, Amjad Ouled-Ameur , AngeloGioacchino Del Regno Subject: [PATCH v3 1/4] dt-bindings: thermal: mediatek: add binding documentation for MT8365 SoC Date: Thu, 1 Sep 2022 15:39:47 +0200 Message-Id: <20220901133950.115122-2-aouledameur@baylibre.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220901133950.115122-1-aouledameur@baylibre.com> References: <20220901133950.115122-1-aouledameur@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Fabien Parent Add the binding documentation for the thermal support on MT8365 SoC. Signed-off-by: Fabien Parent Signed-off-by: Amjad Ouled-Ameur Reviewed-by: Matthias Brugger Reviewed-by: AngeloGioacchino Del Regno Acked-by: Rob Herring --- Documentation/devicetree/bindings/thermal/mediatek-thermal.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt b/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt index 5c7e7bdd029a..ba4ebffeade4 100644 --- a/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt +++ b/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt @@ -14,6 +14,7 @@ Required properties: - "mediatek,mt2712-thermal" : For MT2712 family of SoCs - "mediatek,mt7622-thermal" : For MT7622 SoC - "mediatek,mt8183-thermal" : For MT8183 family of SoCs + - "mediatek,mt8365-thermal" : For MT8365 family of SoCs - "mediatek,mt8516-thermal", "mediatek,mt2701-thermal : For MT8516 family of SoCs - reg: Address range of the thermal controller - interrupts: IRQ for the thermal controller From patchwork Thu Sep 1 13:39:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amjad Ouled-Ameur X-Patchwork-Id: 12962686 X-Patchwork-Delegate: daniel.lezcano@linaro.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 46006ECAAD3 for ; Thu, 1 Sep 2022 13:41:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233396AbiIANlv (ORCPT ); Thu, 1 Sep 2022 09:41:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42192 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233366AbiIANlY (ORCPT ); Thu, 1 Sep 2022 09:41:24 -0400 Received: from mail-wr1-x435.google.com (mail-wr1-x435.google.com [IPv6:2a00:1450:4864:20::435]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C4F8630F5A for ; Thu, 1 Sep 2022 06:40:08 -0700 (PDT) Received: by mail-wr1-x435.google.com with SMTP id u17so3150646wrp.3 for ; Thu, 01 Sep 2022 06:40:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=stpnIznClyFbSSAZ9XIBAQVJVqGJPgWnuEIsfvw/Kgw=; b=SgocxATs9nG+dO5eC5Ry/p9RAchwAh7Dpb52+4CBAMfh5whV5zASWzF3gBuq1hnzwp M+7JtEjt88ret/I+CXbQ/8eC7JhJZZYpUMr9LIXHTG//b8nmupFzHkcA4LJTWam7pZbN QBEVv+DsJY1rMjqi9UwKNxes6DzYt2FsHkrUVjyhamtSGhaNqs25BKDjTXNKk09vaU3e 5Yey/AIv9z1PeDrbwbxvkjhbGh/JUK1k7rdBskyuIVcMMC9wZb8GxUwSHKfubs+QiSld cv+od58WOfHDtJuJll+69LK2+7eNURITPegLYKastnotHmlVwhKrU1nx5L/e+r0bg/SB S5Yg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=stpnIznClyFbSSAZ9XIBAQVJVqGJPgWnuEIsfvw/Kgw=; b=5oj3fYVi8f3XoqDRdZfUm+sSjChIP4tX52hdUkzZ90oXmazAcSDbXb0o0906r3u1ao Jzk/a01EwNvXaE2yZVjYydswycQQYql9XgrE0IEwwGyGj0aeHhU4lJZhk64POo1xl5zp sSWiA0MEPUmLxujYcqqr++Wka77Pkm8856Nc4uwo/faWETtbd0/yoWhjuionFchrZmt6 MIyxUyK9CeaBNzQ617gBKMe1JpwHVxy5ut6jtCZ8jfe/Mbb1q+JDlaaRE7xMvN/upNic 8F2lYSdTqVAnNYKdsnNL8eBrxc9/OwPrXdDTpjcVKsBxwEVNlPCyEPBhpPTEVOYHu+Qu DXZg== X-Gm-Message-State: ACgBeo2GFdQnXaZsx4CKtQjzGXDDj7o7f1l0OxjI6htwvtCkl/PsCFel i/p+NAzbc1grot574PG0hnm5cQ== X-Google-Smtp-Source: AA6agR63Bzb51JkQHDsQML106QA1SRbThkvFgEfcZxG1oTuPekWXu06XLjwe2W8lGlgpYHROZLAeqg== X-Received: by 2002:adf:a702:0:b0:226:e205:fa56 with SMTP id c2-20020adfa702000000b00226e205fa56mr7815687wrd.637.1662039604363; Thu, 01 Sep 2022 06:40:04 -0700 (PDT) Received: from localhost.localdomain (210.145.15.109.rev.sfr.net. [109.15.145.210]) by smtp.googlemail.com with ESMTPSA id e3-20020adfe383000000b0021ef34124ebsm15399016wrm.11.2022.09.01.06.40.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Sep 2022 06:40:03 -0700 (PDT) From: Amjad Ouled-Ameur To: matthias.bgg@gmail.com Cc: Markus Schneider-Pargmann , rafael@kernel.org, fparent@baylibre.com, amitk@kernel.org, daniel.lezcano@linaro.org, devicetree@vger.kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-pm@vger.kernel.org, robh+dt@kernel.org, rui.zhang@intel.com, Amjad Ouled-Ameur Subject: [PATCH v3 2/4] thermal: mediatek: control buffer enablement tweaks Date: Thu, 1 Sep 2022 15:39:48 +0200 Message-Id: <20220901133950.115122-3-aouledameur@baylibre.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220901133950.115122-1-aouledameur@baylibre.com> References: <20220901133950.115122-1-aouledameur@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Markus Schneider-Pargmann Add logic in order to be able to turn on the control buffer on MT8365. This change now allows to have control buffer support for MTK_THERMAL_V1, and it allows to define the register offset, and mask used to enable it. Signed-off-by: Markus Schneider-Pargmann Signed-off-by: Fabien Parent Signed-off-by: Amjad Ouled-Ameur --- Changes in V3: - Use GENMASK() and BIT() instead of hardcoded data. - Use u32 instead of int for "tmp" var in mtk_thermal_turn_on_buffer() drivers/thermal/mtk_thermal.c | 25 ++++++++++++++++++------- 1 file changed, 18 insertions(+), 7 deletions(-) diff --git a/drivers/thermal/mtk_thermal.c b/drivers/thermal/mtk_thermal.c index ede94eadddda..b5b4401249e8 100644 --- a/drivers/thermal/mtk_thermal.c +++ b/drivers/thermal/mtk_thermal.c @@ -271,6 +271,9 @@ struct mtk_thermal_data { bool need_switch_bank; struct thermal_bank_cfg bank_data[MAX_NUM_ZONES]; enum mtk_thermal_version version; + u32 apmixed_buffer_ctl_reg; + u32 apmixed_buffer_ctl_mask; + u32 apmixed_buffer_ctl_set; }; struct mtk_thermal { @@ -514,6 +517,9 @@ static const struct mtk_thermal_data mt7622_thermal_data = { .adcpnp = mt7622_adcpnp, .sensor_mux_values = mt7622_mux_values, .version = MTK_THERMAL_V2, + .apmixed_buffer_ctl_reg = APMIXED_SYS_TS_CON1, + .apmixed_buffer_ctl_mask = GENMASK(31, 6) | BIT(3), + .apmixed_buffer_ctl_set = BIT(0), }; /* @@ -963,14 +969,18 @@ static const struct of_device_id mtk_thermal_of_match[] = { }; MODULE_DEVICE_TABLE(of, mtk_thermal_of_match); -static void mtk_thermal_turn_on_buffer(void __iomem *apmixed_base) +static void mtk_thermal_turn_on_buffer(struct mtk_thermal *mt, + void __iomem *apmixed_base) { - int tmp; + u32 tmp; + + if (!mt->conf->apmixed_buffer_ctl_reg) + return; - tmp = readl(apmixed_base + APMIXED_SYS_TS_CON1); - tmp &= ~(0x37); - tmp |= 0x1; - writel(tmp, apmixed_base + APMIXED_SYS_TS_CON1); + tmp = readl(apmixed_base + mt->conf->apmixed_buffer_ctl_reg); + tmp &= mt->conf->apmixed_buffer_ctl_mask; + tmp |= mt->conf->apmixed_buffer_ctl_set; + writel(tmp, apmixed_base + mt->conf->apmixed_buffer_ctl_reg); udelay(200); } @@ -1070,8 +1080,9 @@ static int mtk_thermal_probe(struct platform_device *pdev) goto err_disable_clk_auxadc; } + mtk_thermal_turn_on_buffer(mt, apmixed_base); + if (mt->conf->version == MTK_THERMAL_V2) { - mtk_thermal_turn_on_buffer(apmixed_base); mtk_thermal_release_periodic_ts(mt, auxadc_base); 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[109.15.145.210]) by smtp.googlemail.com with ESMTPSA id e3-20020adfe383000000b0021ef34124ebsm15399016wrm.11.2022.09.01.06.40.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Sep 2022 06:40:05 -0700 (PDT) From: Amjad Ouled-Ameur To: matthias.bgg@gmail.com Cc: Fabien Parent , rafael@kernel.org, amitk@kernel.org, daniel.lezcano@linaro.org, devicetree@vger.kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-pm@vger.kernel.org, robh+dt@kernel.org, rui.zhang@intel.com, Markus Schneider-Pargmann , Amjad Ouled-Ameur Subject: [PATCH v3 3/4] thermal: mediatek: add support for MT8365 SoC Date: Thu, 1 Sep 2022 15:39:49 +0200 Message-Id: <20220901133950.115122-4-aouledameur@baylibre.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220901133950.115122-1-aouledameur@baylibre.com> References: <20220901133950.115122-1-aouledameur@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Fabien Parent MT8365 is similar to the other SoCs supported by the driver. It has only one bank and 3 actual sensors that can be multiplexed. There is another one sensor that does not have usable data. Signed-off-by: Fabien Parent Signed-off-by: Amjad Ouled-Ameur --- drivers/thermal/mtk_thermal.c | 68 +++++++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/drivers/thermal/mtk_thermal.c b/drivers/thermal/mtk_thermal.c index b5b4401249e8..088c388da241 100644 --- a/drivers/thermal/mtk_thermal.c +++ b/drivers/thermal/mtk_thermal.c @@ -31,6 +31,7 @@ #define AUXADC_CON2_V 0x010 #define AUXADC_DATA(channel) (0x14 + (channel) * 4) +#define APMIXED_SYS_TS_CON0 0x600 #define APMIXED_SYS_TS_CON1 0x604 /* Thermal Controller Registers */ @@ -245,6 +246,17 @@ enum mtk_thermal_version { /* The calibration coefficient of sensor */ #define MT8183_CALIBRATION 153 +/* MT8365 */ +#define MT8365_TEMP_AUXADC_CHANNEL 11 +#define MT8365_CALIBRATION 164 +#define MT8365_NUM_CONTROLLER 1 +#define MT8365_NUM_BANKS 1 +#define MT8365_NUM_SENSORS 3 +#define MT8365_NUM_SENSORS_PER_ZONE 3 +#define MT8365_TS1 0 +#define MT8365_TS2 1 +#define MT8365_TS3 2 + struct mtk_thermal; struct thermal_bank_cfg { @@ -389,6 +401,24 @@ static const int mt7622_mux_values[MT7622_NUM_SENSORS] = { 0, }; static const int mt7622_vts_index[MT7622_NUM_SENSORS] = { VTS1 }; static const int mt7622_tc_offset[MT7622_NUM_CONTROLLER] = { 0x0, }; +/* MT8365 thermal sensor data */ +static const int mt8365_bank_data[MT8365_NUM_SENSORS] = { + MT8365_TS1, MT8365_TS2, MT8365_TS3 +}; + +static const int mt8365_msr[MT8365_NUM_SENSORS_PER_ZONE] = { + TEMP_MSR0, TEMP_MSR1, TEMP_MSR2 +}; + +static const int mt8365_adcpnp[MT8365_NUM_SENSORS_PER_ZONE] = { + TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2 +}; + +static const int mt8365_mux_values[MT8365_NUM_SENSORS] = { 0, 1, 2 }; +static const int mt8365_tc_offset[MT8365_NUM_CONTROLLER] = { 0 }; + +static const int mt8365_vts_index[MT8365_NUM_SENSORS] = { VTS1, VTS2, VTS3 }; + /* * The MT8173 thermal controller has four banks. Each bank can read up to * four temperature sensors simultaneously. The MT8173 has a total of 5 @@ -463,6 +493,40 @@ static const struct mtk_thermal_data mt2701_thermal_data = { .version = MTK_THERMAL_V1, }; +/* + * The MT8365 thermal controller has one bank, which can read up to + * four temperature sensors simultaneously. The MT8365 has a total of 3 + * temperature sensors. + * + * The thermal core only gets the maximum temperature of this one bank, + * so the bank concept wouldn't be necessary here. However, the SVS (Smart + * Voltage Scaling) unit makes its decisions based on the same bank + * data. + */ +static const struct mtk_thermal_data mt8365_thermal_data = { + .auxadc_channel = MT8365_TEMP_AUXADC_CHANNEL, + .num_banks = MT8365_NUM_BANKS, + .num_sensors = MT8365_NUM_SENSORS, + .vts_index = mt8365_vts_index, + .cali_val = MT8365_CALIBRATION, + .num_controller = MT8365_NUM_CONTROLLER, + .controller_offset = mt8365_tc_offset, + .need_switch_bank = false, + .bank_data = { + { + .num_sensors = MT8365_NUM_SENSORS, + .sensors = mt8365_bank_data + }, + }, + .msr = mt8365_msr, + .adcpnp = mt8365_adcpnp, + .sensor_mux_values = mt8365_mux_values, + .version = MTK_THERMAL_V1, + .apmixed_buffer_ctl_reg = APMIXED_SYS_TS_CON0, + .apmixed_buffer_ctl_mask = (u32) ~GENMASK(29, 28), + .apmixed_buffer_ctl_set = 0, +}; + /* * The MT2712 thermal controller has one bank, which can read up to * four temperature sensors simultaneously. The MT2712 has a total of 4 @@ -964,6 +1028,10 @@ static const struct of_device_id mtk_thermal_of_match[] = { { .compatible = "mediatek,mt8183-thermal", .data = (void *)&mt8183_thermal_data, + }, + { + .compatible = "mediatek,mt8365-thermal", + .data = (void *)&mt8365_thermal_data, }, { }, }; From patchwork Thu Sep 1 13:39:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amjad Ouled-Ameur X-Patchwork-Id: 12962689 X-Patchwork-Delegate: daniel.lezcano@linaro.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 36195ECAAD1 for ; Thu, 1 Sep 2022 13:42:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233526AbiIANl7 (ORCPT ); Thu, 1 Sep 2022 09:41:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38984 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233557AbiIANl0 (ORCPT ); Thu, 1 Sep 2022 09:41:26 -0400 Received: from mail-wm1-x329.google.com (mail-wm1-x329.google.com [IPv6:2a00:1450:4864:20::329]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 48ABA32B9B for ; Thu, 1 Sep 2022 06:40:10 -0700 (PDT) Received: by mail-wm1-x329.google.com with SMTP id h1so9040063wmd.3 for ; Thu, 01 Sep 2022 06:40:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=PXZk2g+XOqGMjXGT66nViEOp7155I8tzUe2hmezbk9c=; b=17fsFK3ztgm/SVq5u0ayzndJktrteVKsCKcEqAK3Qn//5L3IkRaOUCawLwShBDJFtl euAItBnkxj6Kr+gObW2PdMQJyW+JNckoeeEdJcOyJ8odVyjv9qwSo+Aa+Agrw1D7uadm NjFL4ytCQsfAsiYRX2ZCnWbkqyjhSvU2ArcGakqT0/pe/tzKAGY5ANhWjbKSskm01+SV e08NiN7JfQwTyq8kqygPzg04A3j1sVIHbYcg2+MQmLJ0G2Z5+pbYD3vww9tiFNQdTwNx Wb/b6iHsoxdWnVPAvK6uJ58Bt5C5ENxo+MtunbH7ABwWaEcZ0kMUtDms8wCLcCUx5Vlk EiCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=PXZk2g+XOqGMjXGT66nViEOp7155I8tzUe2hmezbk9c=; b=FpnGS7SOqo8DR+QetokkJt5hALmEt8TDNuhGoEHAUSTlUDZKeTwyd0aJGSQDzl8GFp vDMeqlBqdiq9slhqBU0KVG0YwAU2CmKJmrVhdlEfUVroBF3zKLD99NFILKePvCAnNg6e QdRqNZ5WztVLuKOq3L2RV4aY5adah7sDoOwVfsIqmbJlWQK8xYDwi62P5i2c2AwZW4k7 APoYcW241l7yW1wLWvys/s6g/KdlsDg/WuDEBpsjWOvj0lQ9ASI8k+EKKgkKru0VFsF2 0glbACJB5Tt/n8AKYZH5XHiY3G56OVDh2Emr2QuZvJau48ZOEU3yzfaB6Wbj4Eeb7+IA COIA== X-Gm-Message-State: ACgBeo37FGgHnHvXv8ig+u8JBTN376C1YR1YEEKR5Yd1FZK3xp4+VbsM CsQtfYyFGcUHb/3oS6N+LQvJnA== X-Google-Smtp-Source: AA6agR42cS6iV9udNENWfEp+1c99N36znNphQvHct12z9G9cTwZBqzId0Md8KfkxH6g9DJOJUI8Dcw== X-Received: by 2002:a05:600c:4148:b0:3a5:4f94:577b with SMTP id h8-20020a05600c414800b003a54f94577bmr5357868wmm.167.1662039606770; Thu, 01 Sep 2022 06:40:06 -0700 (PDT) Received: from localhost.localdomain (210.145.15.109.rev.sfr.net. [109.15.145.210]) by smtp.googlemail.com with ESMTPSA id e3-20020adfe383000000b0021ef34124ebsm15399016wrm.11.2022.09.01.06.40.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Sep 2022 06:40:06 -0700 (PDT) From: Amjad Ouled-Ameur To: matthias.bgg@gmail.com Cc: Amjad Ouled-Ameur , rafael@kernel.org, fparent@baylibre.com, amitk@kernel.org, daniel.lezcano@linaro.org, devicetree@vger.kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-pm@vger.kernel.org, robh+dt@kernel.org, rui.zhang@intel.com, Michael Kao , Hsin-Yi Wang Subject: [PATCH v3 4/4] thermal: mediatek: add another get_temp ops for thermal sensors Date: Thu, 1 Sep 2022 15:39:50 +0200 Message-Id: <20220901133950.115122-5-aouledameur@baylibre.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220901133950.115122-1-aouledameur@baylibre.com> References: <20220901133950.115122-1-aouledameur@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Provide thermal zone to read thermal sensor in the SoC. We can read all the thermal sensors value in the SoC by the node /sys/class/thermal/ In mtk_thermal_bank_temperature, return -EAGAIN instead of -EACCESS on the first read of sensor that often are bogus values. This can avoid following warning on boot: thermal thermal_zone6: failed to read out thermal zone (-13) Signed-off-by: Michael Kao Signed-off-by: Hsin-Yi Wang Signed-off-by: Amjad Ouled-Ameur --- Changes in V3: - Use proper types. - Use devm_kmalloc() instead of kmalloc(). - Fix tabs and spaces. drivers/thermal/mtk_thermal.c | 100 ++++++++++++++++++++++++++-------- 1 file changed, 76 insertions(+), 24 deletions(-) diff --git a/drivers/thermal/mtk_thermal.c b/drivers/thermal/mtk_thermal.c index 088c388da241..5901787c57f5 100644 --- a/drivers/thermal/mtk_thermal.c +++ b/drivers/thermal/mtk_thermal.c @@ -259,6 +259,11 @@ enum mtk_thermal_version { struct mtk_thermal; +struct mtk_thermal_zone { + struct mtk_thermal *mt; + int id; +}; + struct thermal_bank_cfg { unsigned int num_sensors; const int *sensors; @@ -709,6 +714,32 @@ static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank) mutex_unlock(&mt->lock); } +static int _get_sensor_temp(struct mtk_thermal *mt, int id) +{ + u32 raw; + int temp; + + const struct mtk_thermal_data *conf = mt->conf; + + raw = readl(mt->thermal_base + conf->msr[id]); + + if (mt->conf->version == MTK_THERMAL_V1) + temp = raw_to_mcelsius_v1(mt, id, raw); + else + temp = raw_to_mcelsius_v2(mt, id, raw); + + /* + * The first read of a sensor often contains very high bogus + * temperature value. Filter these out so that the system does + * not immediately shut down. + */ + + if (temp > 200000) + return -EAGAIN; + else + return temp; +} + /** * mtk_thermal_bank_temperature - get the temperature of a bank * @bank: The bank @@ -721,26 +752,9 @@ static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank) struct mtk_thermal *mt = bank->mt; const struct mtk_thermal_data *conf = mt->conf; int i, temp = INT_MIN, max = INT_MIN; - u32 raw; for (i = 0; i < conf->bank_data[bank->id].num_sensors; i++) { - raw = readl(mt->thermal_base + conf->msr[i]); - - if (mt->conf->version == MTK_THERMAL_V1) { - temp = raw_to_mcelsius_v1( - mt, conf->bank_data[bank->id].sensors[i], raw); - } else { - temp = raw_to_mcelsius_v2( - mt, conf->bank_data[bank->id].sensors[i], raw); - } - - /* - * The first read of a sensor often contains very high bogus - * temperature value. Filter these out so that the system does - * not immediately shut down. - */ - if (temp > 200000) - temp = 0; + temp = _get_sensor_temp(mt, i); if (temp > max) max = temp; @@ -751,7 +765,8 @@ static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank) static int mtk_read_temp(void *data, int *temperature) { - struct mtk_thermal *mt = data; + struct mtk_thermal_zone *tz = data; + struct mtk_thermal *mt = tz->mt; int i; int tempmax = INT_MIN; @@ -770,10 +785,28 @@ static int mtk_read_temp(void *data, int *temperature) return 0; } +static int mtk_read_sensor_temp(void *data, int *temperature) +{ + struct mtk_thermal_zone *tz = data; + struct mtk_thermal *mt = tz->mt; + int id = tz->id - 1; + + if (id < 0) + return -EACCES; + + *temperature = _get_sensor_temp(mt, id); + + return 0; +} + static const struct thermal_zone_of_device_ops mtk_thermal_ops = { .get_temp = mtk_read_temp, }; +static const struct thermal_zone_of_device_ops mtk_thermal_sensor_ops = { + .get_temp = mtk_read_sensor_temp, +}; + static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num, u32 apmixed_phys_base, u32 auxadc_phys_base, int ctrl_id) @@ -1072,6 +1105,7 @@ static int mtk_thermal_probe(struct platform_device *pdev) u64 auxadc_phys_base, apmixed_phys_base; struct thermal_zone_device *tzdev; void __iomem *apmixed_base, *auxadc_base; + struct mtk_thermal_zone *tz; mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL); if (!mt) @@ -1161,11 +1195,29 @@ static int mtk_thermal_probe(struct platform_device *pdev) platform_set_drvdata(pdev, mt); - tzdev = devm_thermal_zone_of_sensor_register(&pdev->dev, 0, mt, - &mtk_thermal_ops); - if (IS_ERR(tzdev)) { - ret = PTR_ERR(tzdev); - goto err_disable_clk_peri_therm; + for (i = 0; i < mt->conf->num_sensors + 1; i++) { + tz = devm_kmalloc(&pdev->dev, sizeof(*tz), GFP_KERNEL); + if (!tz) + return -ENOMEM; + + tz->mt = mt; + tz->id = i; + + tzdev = devm_thermal_zone_of_sensor_register(&pdev->dev, i, tz, (i == 0) ? + &mtk_thermal_ops : + &mtk_thermal_sensor_ops); + + if (IS_ERR(tzdev)) { + if (PTR_ERR(tzdev) == -ENODEV) { + dev_warn(&pdev->dev, + "sensor %d not registered in thermal zone in dt\n", i); + continue; + } + if (PTR_ERR(tzdev) == -EACCES) { + ret = PTR_ERR(tzdev); + goto err_disable_clk_peri_therm; + } + } } ret = devm_thermal_add_hwmon_sysfs(tzdev);