From patchwork Thu Sep 1 16:25:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 12962903 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2A406ECAAD8 for ; Thu, 1 Sep 2022 16:29:49 +0000 (UTC) Received: from localhost ([::1]:54708 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oTn4e-0004c8-0e for qemu-devel@archiver.kernel.org; Thu, 01 Sep 2022 12:29:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35132) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oTn1n-0001bZ-Pu for qemu-devel@nongnu.org; Thu, 01 Sep 2022 12:26:53 -0400 Received: from mail-ej1-x629.google.com ([2a00:1450:4864:20::629]:34582) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oTn1m-0001Sk-19 for qemu-devel@nongnu.org; Thu, 01 Sep 2022 12:26:51 -0400 Received: by mail-ej1-x629.google.com with SMTP id y3so35859311ejc.1 for ; Thu, 01 Sep 2022 09:26:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=PUf0smrU1Uq6DvRuukc2bu0xLP9NOz9TADXgYciMGNM=; b=ievEE0soa7hr/JK30VaW+VgUpdzh4ptpoScvf60ix+ImhmpkczszBnUSFZyBjfQRcK IJhdomJ5kTVBo2idEPIy9tJcPa6eH3qrDU/YM5KMgJFgY57ttNOyJuGllWAgcuJsCdJx d/AqSx+rSOMJXsD+7HO6jX4adMDGM8xLJm9Bnf1aEbOVXzRr/pWmEL5LJEBf35K2vH+Z kpYXxfhRRwjUgr0LWiBcqJEzaccrlwMqFrEPTNCju7iZizyFZT3UmhpDvzExOy+YoBow 8rwZR8jprPqQAG5OcF9aJaxixOUam9tZLVcN4G8AoaOi6axIgUYy+TV7/OIq3YH3esls 52vA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=PUf0smrU1Uq6DvRuukc2bu0xLP9NOz9TADXgYciMGNM=; b=Gv8GijyB/PMmZqojEhuQvwyd6DUJAtcXEoVYKLQgbdKzFXd19qrfEwGaQ2TEHI5xe4 62hka06eOm1Rauz0YuQ8L3NCrJe6vja/I/jIeWBsPTpt8b9XxtrxhzpEn+3jgbevgObQ 8Vh9TYi/Ml/YcSaYj4dCf7XkkBpe1Jtbaja62fRdaFPcz3FcoCF+0xtAyG1pzhZYU/fp jEBcZjClntDBp3VdL7znvr8RwjNDkUXaaqRDTMkKsWeutjQj4LPMISXDdzkgY4vEMkSU 3BVf1x2Qv0HVcVfGBklGclQSYnOLmE9D/TXSFF24xrux45WcPd8YppFGclpYoua3yX/5 a6Dw== X-Gm-Message-State: ACgBeo0nCvbo61LVye2CLepEhFnAsfLl1v92oTfph3/HEp2VF+n5b6kJ o6rHGcwdJ2+mkosSe2tqXVV8Bmbujzc= X-Google-Smtp-Source: AA6agR64ueiEbgZDkDUoGD1ci+9btR9E4r71Tl1n+fJcUBKBv/ZBcMUdQmx7SUBl413k2mcdjokAUQ== X-Received: by 2002:a17:907:6d05:b0:73d:8092:91ea with SMTP id sa5-20020a1709076d0500b0073d809291eamr23950221ejc.280.1662049608282; Thu, 01 Sep 2022 09:26:48 -0700 (PDT) Received: from osoxes.fritz.box (p200300faaf0bb2009c4947838afc41b6.dip0.t-ipconnect.de. [2003:fa:af0b:b200:9c49:4783:8afc:41b6]) by smtp.gmail.com with ESMTPSA id p6-20020aa7d306000000b00447c0dcbb99sm1587672edq.83.2022.09.01.09.26.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Sep 2022 09:26:48 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Her?= =?utf-8?q?v=C3=A9_Poussineau?= , Aurelien Jarno , Paolo Bonzini , Eduardo Habkost , Richard Henderson , Jiaxun Yang , Ani Sinha , Igor Mammedov , Marcel Apfelbaum , "Michael S. Tsirkin" , Bernhard Beschow Subject: [PATCH 01/42] hw/i386/pc: Create DMA controllers in south bridges Date: Thu, 1 Sep 2022 18:25:32 +0200 Message-Id: <20220901162613.6939-2-shentey@gmail.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220901162613.6939-1-shentey@gmail.com> References: <20220901162613.6939-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::629; envelope-from=shentey@gmail.com; helo=mail-ej1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Just like in the real hardware (and in PIIX4), create the DMA controllers in the south bridges. Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daudé --- hw/i386/pc.c | 3 --- hw/i386/pc_piix.c | 2 ++ hw/isa/Kconfig | 2 ++ hw/isa/lpc_ich9.c | 3 +++ hw/isa/piix3.c | 9 +++++++-- 5 files changed, 14 insertions(+), 5 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 566accf7e6..174b6c2ace 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -47,7 +47,6 @@ #include "multiboot.h" #include "hw/rtc/mc146818rtc.h" #include "hw/intc/i8259.h" -#include "hw/dma/i8257.h" #include "hw/timer/i8254.h" #include "hw/input/i8042.h" #include "hw/irq.h" @@ -1319,8 +1318,6 @@ void pc_basic_device_init(struct PCMachineState *pcms, pcspk_init(pcms->pcspk, isa_bus, pit); } - i8257_dma_init(isa_bus, 0); - /* Super I/O */ pc_superio_init(isa_bus, create_fdctrl, pcms->i8042_enabled, pcms->vmport != ON_OFF_AUTO_ON); diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 8043a250ad..fc70a1abc2 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -26,6 +26,7 @@ #include CONFIG_DEVICES #include "qemu/units.h" +#include "hw/dma/i8257.h" #include "hw/loader.h" #include "hw/i386/x86.h" #include "hw/i386/pc.h" @@ -225,6 +226,7 @@ static void pc_init1(MachineState *machine, pci_bus = NULL; isa_bus = isa_bus_new(NULL, get_system_memory(), system_io, &error_abort); + i8257_dma_init(isa_bus, 0); pcms->hpet_enabled = false; } isa_bus_irqs(isa_bus, x86ms->gsi); diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig index d42143a991..c65d2d2666 100644 --- a/hw/isa/Kconfig +++ b/hw/isa/Kconfig @@ -33,6 +33,7 @@ config PC87312 config PIIX3 bool + select I8257 select ISA_BUS config PIIX4 @@ -67,6 +68,7 @@ config LPC_ICH9 bool # For historical reasons, SuperIO devices are created in the board # for ICH9. + select I8257 select ISA_BUS select ACPI_SMBUS select ACPI_X86_ICH diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c index 4553b5925b..8694e58b21 100644 --- a/hw/isa/lpc_ich9.c +++ b/hw/isa/lpc_ich9.c @@ -34,6 +34,7 @@ #include "qapi/error.h" #include "qapi/visitor.h" #include "qemu/range.h" +#include "hw/dma/i8257.h" #include "hw/isa/isa.h" #include "migration/vmstate.h" #include "hw/irq.h" @@ -722,6 +723,8 @@ static void ich9_lpc_realize(PCIDevice *d, Error **errp) qdev_init_gpio_out_named(dev, lpc->gsi, ICH9_GPIO_GSI, GSI_NUM_PINS); isa_bus_irqs(isa_bus, lpc->gsi); + + i8257_dma_init(isa_bus, 0); } static bool ich9_rst_cnt_needed(void *opaque) diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index 48f9ab1096..44a9998752 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -25,6 +25,7 @@ #include "qemu/osdep.h" #include "qemu/range.h" #include "qapi/error.h" +#include "hw/dma/i8257.h" #include "hw/southbridge/piix.h" #include "hw/irq.h" #include "hw/isa/isa.h" @@ -295,9 +296,11 @@ static const MemoryRegionOps rcr_ops = { static void pci_piix3_realize(PCIDevice *dev, Error **errp) { PIIX3State *d = PIIX3_PCI_DEVICE(dev); + ISABus *isa_bus; - if (!isa_bus_new(DEVICE(d), get_system_memory(), - pci_address_space_io(dev), errp)) { + isa_bus = isa_bus_new(DEVICE(d), get_system_memory(), + pci_address_space_io(dev), errp); + if (!isa_bus) { return; } @@ -307,6 +310,8 @@ static void pci_piix3_realize(PCIDevice *dev, Error **errp) PIIX_RCR_IOPORT, &d->rcr_mem, 1); qemu_register_reset(piix3_reset, d); + + i8257_dma_init(isa_bus, 0); } static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope) From patchwork Thu Sep 1 16:25:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 12962904 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 276CCECAAD3 for ; Thu, 1 Sep 2022 16:29:49 +0000 (UTC) Received: from localhost ([::1]:54704 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oTn4d-0004Ye-Qe for qemu-devel@archiver.kernel.org; Thu, 01 Sep 2022 12:29:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35134) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oTn1q-0001bd-0b for qemu-devel@nongnu.org; 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[2003:fa:af0b:b200:9c49:4783:8afc:41b6]) by smtp.gmail.com with ESMTPSA id p6-20020aa7d306000000b00447c0dcbb99sm1587672edq.83.2022.09.01.09.26.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Sep 2022 09:26:48 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Her?= =?utf-8?q?v=C3=A9_Poussineau?= , Aurelien Jarno , Paolo Bonzini , Eduardo Habkost , Richard Henderson , Jiaxun Yang , Ani Sinha , Igor Mammedov , Marcel Apfelbaum , "Michael S. Tsirkin" , Bernhard Beschow Subject: [PATCH 02/42] hw/i386/pc: Create RTC controllers in south bridges Date: Thu, 1 Sep 2022 18:25:33 +0200 Message-Id: <20220901162613.6939-3-shentey@gmail.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220901162613.6939-1-shentey@gmail.com> References: <20220901162613.6939-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::630; envelope-from=shentey@gmail.com; helo=mail-ej1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Just like in the real hardware (and in PIIX4), create the RTC controllers in the south bridges. Signed-off-by: Bernhard Beschow --- hw/i386/pc.c | 12 +++++++++++- hw/i386/pc_piix.c | 8 ++++++++ hw/i386/pc_q35.c | 1 + hw/isa/Kconfig | 2 ++ hw/isa/lpc_ich9.c | 8 ++++++++ hw/isa/piix3.c | 15 +++++++++++++++ include/hw/i386/ich9.h | 2 ++ include/hw/southbridge/piix.h | 3 +++ 8 files changed, 50 insertions(+), 1 deletion(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 174b6c2ace..05d8b0b3d1 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1300,7 +1300,17 @@ void pc_basic_device_init(struct PCMachineState *pcms, pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); } - *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq); + + if (rtc_irq) { + qdev_connect_gpio_out(DEVICE(*rtc_state), 0, rtc_irq); + } else { + uint32_t irq = object_property_get_uint(OBJECT(*rtc_state), + "irq", + &error_fatal); + isa_connect_gpio_out(*rtc_state, 0, irq); + } + object_property_add_alias(OBJECT(pcms), "rtc-time", OBJECT(*rtc_state), + "date"); qemu_register_boot_set(pc_boot_set, *rtc_state); diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index fc70a1abc2..5f282ff8ad 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -32,6 +32,7 @@ #include "hw/i386/pc.h" #include "hw/i386/apic.h" #include "hw/pci-host/i440fx.h" +#include "hw/rtc/mc146818rtc.h" #include "hw/southbridge/piix.h" #include "hw/display/ramfb.h" #include "hw/firmware/smbios.h" @@ -222,10 +223,17 @@ static void pc_init1(MachineState *machine, piix3->pic = x86ms->gsi; piix3_devfn = piix3->dev.devfn; isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0")); + rtc_state = ISA_DEVICE(object_resolve_path_component(OBJECT(pci_dev), + "rtc")); } else { pci_bus = NULL; isa_bus = isa_bus_new(NULL, get_system_memory(), system_io, &error_abort); + + rtc_state = isa_new(TYPE_MC146818_RTC); + qdev_prop_set_int32(DEVICE(rtc_state), "base_year", 2000); + isa_realize_and_unref(rtc_state, isa_bus, &error_fatal); + i8257_dma_init(isa_bus, 0); pcms->hpet_enabled = false; } diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 53eda50e81..2eaeab7902 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -238,6 +238,7 @@ static void pc_q35_init(MachineState *machine) lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC), true, TYPE_ICH9_LPC_DEVICE); + rtc_state = ISA_DEVICE(object_resolve_path_component(OBJECT(lpc), "rtc")); object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP, TYPE_HOTPLUG_HANDLER, diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig index c65d2d2666..6e8f9cac54 100644 --- a/hw/isa/Kconfig +++ b/hw/isa/Kconfig @@ -35,6 +35,7 @@ config PIIX3 bool select I8257 select ISA_BUS + select MC146818RTC config PIIX4 bool @@ -72,3 +73,4 @@ config LPC_ICH9 select ISA_BUS select ACPI_SMBUS select ACPI_X86_ICH + select MC146818RTC diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c index 8694e58b21..0051fa66ab 100644 --- a/hw/isa/lpc_ich9.c +++ b/hw/isa/lpc_ich9.c @@ -660,6 +660,8 @@ static void ich9_lpc_initfn(Object *obj) static const uint8_t acpi_enable_cmd = ICH9_APM_ACPI_ENABLE; static const uint8_t acpi_disable_cmd = ICH9_APM_ACPI_DISABLE; + object_initialize_child(obj, "rtc", &lpc->rtc, TYPE_MC146818_RTC); + object_property_add_uint8_ptr(obj, ACPI_PM_PROP_SCI_INT, &lpc->sci_gsi, OBJ_PROP_FLAG_READ); object_property_add_uint8_ptr(OBJECT(lpc), ACPI_PM_PROP_ACPI_ENABLE_CMD, @@ -725,6 +727,12 @@ static void ich9_lpc_realize(PCIDevice *d, Error **errp) isa_bus_irqs(isa_bus, lpc->gsi); i8257_dma_init(isa_bus, 0); + + /* RTC */ + qdev_prop_set_int32(DEVICE(&lpc->rtc), "base_year", 2000); + if (!qdev_realize(DEVICE(&lpc->rtc), BUS(isa_bus), errp)) { + return; + } } static bool ich9_rst_cnt_needed(void *opaque) diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index 44a9998752..96ab7107e2 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -28,6 +28,7 @@ #include "hw/dma/i8257.h" #include "hw/southbridge/piix.h" #include "hw/irq.h" +#include "hw/qdev-properties.h" #include "hw/isa/isa.h" #include "hw/xen/xen.h" #include "sysemu/xen.h" @@ -312,6 +313,12 @@ static void pci_piix3_realize(PCIDevice *dev, Error **errp) qemu_register_reset(piix3_reset, d); i8257_dma_init(isa_bus, 0); + + /* RTC */ + qdev_prop_set_int32(DEVICE(&d->rtc), "base_year", 2000); + if (!qdev_realize(DEVICE(&d->rtc), BUS(isa_bus), errp)) { + return; + } } static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope) @@ -327,6 +334,13 @@ static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope) } } +static void pci_piix3_init(Object *obj) +{ + PIIX3State *d = PIIX3_PCI_DEVICE(obj); + + object_initialize_child(obj, "rtc", &d->rtc, TYPE_MC146818_RTC); +} + static void pci_piix3_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -352,6 +366,7 @@ static const TypeInfo piix3_pci_type_info = { .name = TYPE_PIIX3_PCI_DEVICE, .parent = TYPE_PCI_DEVICE, .instance_size = sizeof(PIIX3State), + .instance_init = pci_piix3_init, .abstract = true, .class_init = pci_piix3_class_init, .interfaces = (InterfaceInfo[]) { diff --git a/include/hw/i386/ich9.h b/include/hw/i386/ich9.h index 23ee8e371b..672efc6bce 100644 --- a/include/hw/i386/ich9.h +++ b/include/hw/i386/ich9.h @@ -11,6 +11,7 @@ #include "hw/acpi/acpi.h" #include "hw/acpi/ich9.h" #include "hw/pci/pci_bus.h" +#include "hw/rtc/mc146818rtc.h" #include "qom/object.h" void ich9_lpc_set_irq(void *opaque, int irq_num, int level); @@ -39,6 +40,7 @@ struct ICH9LPCState { */ uint8_t irr[PCI_SLOT_MAX][PCI_NUM_PINS]; + RTCState rtc; APMState apm; ICH9LPCPMRegs pm; uint32_t sci_level; /* track sci level */ diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index 2693778b23..b1fa08dd2b 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -14,6 +14,7 @@ #include "hw/pci/pci.h" #include "qom/object.h" +#include "hw/rtc/mc146818rtc.h" /* PIRQRC[A:D]: PIRQx Route Control Registers */ #define PIIX_PIRQCA 0x60 @@ -52,6 +53,8 @@ struct PIIXState { /* This member isn't used. Just for save/load compatibility */ int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS]; + RTCState rtc; + /* Reset Control Register contents */ uint8_t rcr; From patchwork Thu Sep 1 16:25:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 12962909 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A48FAECAAD1 for ; Thu, 1 Sep 2022 16:36:12 +0000 (UTC) Received: from localhost ([::1]:41312 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oTnAp-0002SM-FN for qemu-devel@archiver.kernel.org; Thu, 01 Sep 2022 12:36:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35136) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oTn1q-0001be-1j for qemu-devel@nongnu.org; Thu, 01 Sep 2022 12:26:54 -0400 Received: from mail-ej1-x630.google.com ([2a00:1450:4864:20::630]:33454) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oTn1n-0001T5-KZ for qemu-devel@nongnu.org; Thu, 01 Sep 2022 12:26:53 -0400 Received: by mail-ej1-x630.google.com with SMTP id cu2so35918557ejb.0 for ; Thu, 01 Sep 2022 09:26:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=mGiH/gTsOZjirvxbc9dQFTtmFJYuQJULrmW8EcJwagc=; b=nP/tqX2o0YbI7R7R9Dn1okUd8wpUwDBvyE+5XgbqUbKE1h+Sc2LtqgGdB64hC9fb3r vfddIylw73kMufkSx8C3pnBJqrS/lkmTCFxOVQqwkVJfebdwAeBcSPxXiIaTTKQxVK1i orEfagOBsKWfvEsJaR+QioW8GufPUXfghfOwmdvzX1wMcAVv08k6rETD1iuC01wH154W 0WW5TMBin+tOvK93rSG2jBP72VMuxlQ8xnhymQ2r/f9YyepD+pXHkumYaRJBV5EANo7A /tlMXIPrYQOkaKAoxkQrEXICbh/KXQirQkmfIQLVi2gZ6PCWCNj5+gSBjBEk92q0gaz1 KCmw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=mGiH/gTsOZjirvxbc9dQFTtmFJYuQJULrmW8EcJwagc=; b=h24ZGfwTbapzn6KCiKv2SDBsFqr+knQdjd4T1RnL3F0NZaPIROB4jdZxCm9QDKHUJF +5t7chSv0RZZI20JDhrCZ1thsXvKEflujfm3aNuPDHhRB6diWnAVBCc/4n8SNE4b8iEa J2+cfMdEHzQtYSqt3xWk5ZJzlsXig6dptQDHXx21q/qYx/ScwTt/rLPH+EMKLDP8f9HG gfZdhpyxZ0eILX0+jjcEq0a7eSiozzfE2tRd+00i1EZfVFNZilywbOKx6nwfl13mKj0X SbL8dVmIbxttEv+snzAbDjqoKiXU67gaDVXrscXgMaFofRR9rCKdUPKjSY+5yilxVswj eEVA== X-Gm-Message-State: ACgBeo0dOedkKl1vMKZmgGifFeX1QAwawz0w5bNQJa10GoSL4T/Om/vH qTUlzfvA9+9otifoSM9thcQ4h3kfoJU= X-Google-Smtp-Source: AA6agR6xiwswoS1BXhN4Zd8hmTJ5sN2eTd/oiKJvq0kGkom3voP6YZX9qitCaczS5O5YjxoOiWaOEw== X-Received: by 2002:a17:907:3f0c:b0:73d:60fc:6594 with SMTP id hq12-20020a1709073f0c00b0073d60fc6594mr25142432ejc.669.1662049610120; Thu, 01 Sep 2022 09:26:50 -0700 (PDT) Received: from osoxes.fritz.box (p200300faaf0bb2009c4947838afc41b6.dip0.t-ipconnect.de. [2003:fa:af0b:b200:9c49:4783:8afc:41b6]) by smtp.gmail.com with ESMTPSA id p6-20020aa7d306000000b00447c0dcbb99sm1587672edq.83.2022.09.01.09.26.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Sep 2022 09:26:49 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Her?= =?utf-8?q?v=C3=A9_Poussineau?= , Aurelien Jarno , Paolo Bonzini , Eduardo Habkost , Richard Henderson , Jiaxun Yang , Ani Sinha , Igor Mammedov , Marcel Apfelbaum , "Michael S. Tsirkin" , Bernhard Beschow , Peter Maydell Subject: [PATCH 03/42] hw/i386/pc: No need for rtc_state to be an out-parameter Date: Thu, 1 Sep 2022 18:25:34 +0200 Message-Id: <20220901162613.6939-4-shentey@gmail.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220901162613.6939-1-shentey@gmail.com> References: <20220901162613.6939-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::630; envelope-from=shentey@gmail.com; helo=mail-ej1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Now that the RTC is created as part of the southbridges it doesn't need to be an out-parameter any longer. Signed-off-by: Bernhard Beschow Reviewed-by: Peter Maydell --- hw/i386/pc.c | 12 ++++++------ hw/i386/pc_piix.c | 2 +- hw/i386/pc_q35.c | 2 +- include/hw/i386/pc.h | 2 +- 4 files changed, 9 insertions(+), 9 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 05d8b0b3d1..b3a61f5ef2 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1247,7 +1247,7 @@ static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, void pc_basic_device_init(struct PCMachineState *pcms, ISABus *isa_bus, qemu_irq *gsi, - ISADevice **rtc_state, + ISADevice *rtc_state, bool create_fdctrl, uint32_t hpet_irqs) { @@ -1302,17 +1302,17 @@ void pc_basic_device_init(struct PCMachineState *pcms, } if (rtc_irq) { - qdev_connect_gpio_out(DEVICE(*rtc_state), 0, rtc_irq); + qdev_connect_gpio_out(DEVICE(rtc_state), 0, rtc_irq); } else { - uint32_t irq = object_property_get_uint(OBJECT(*rtc_state), + uint32_t irq = object_property_get_uint(OBJECT(rtc_state), "irq", &error_fatal); - isa_connect_gpio_out(*rtc_state, 0, irq); + isa_connect_gpio_out(rtc_state, 0, irq); } - object_property_add_alias(OBJECT(pcms), "rtc-time", OBJECT(*rtc_state), + object_property_add_alias(OBJECT(pcms), "rtc-time", OBJECT(rtc_state), "date"); - qemu_register_boot_set(pc_boot_set, *rtc_state); + qemu_register_boot_set(pc_boot_set, rtc_state); if (!xen_enabled() && (x86ms->pit == ON_OFF_AUTO_AUTO || x86ms->pit == ON_OFF_AUTO_ON)) { diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 5f282ff8ad..bdad3b6795 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -259,7 +259,7 @@ static void pc_init1(MachineState *machine, } /* init basic PC hardware */ - pc_basic_device_init(pcms, isa_bus, x86ms->gsi, &rtc_state, true, + pc_basic_device_init(pcms, isa_bus, x86ms->gsi, rtc_state, true, 0x4); pc_nic_init(pcmc, isa_bus, pci_bus); diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 2eaeab7902..ca10fa37c6 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -292,7 +292,7 @@ static void pc_q35_init(MachineState *machine) } /* init basic PC hardware */ - pc_basic_device_init(pcms, isa_bus, x86ms->gsi, &rtc_state, !mc->no_floppy, + pc_basic_device_init(pcms, isa_bus, x86ms->gsi, rtc_state, !mc->no_floppy, 0xff0104); /* connect pm stuff to lpc */ diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index c95333514e..0cf3ccdf0d 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -169,7 +169,7 @@ uint64_t pc_pci_hole64_start(void); DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus); void pc_basic_device_init(struct PCMachineState *pcms, ISABus *isa_bus, qemu_irq *gsi, - ISADevice **rtc_state, + ISADevice *rtc_state, bool create_fdctrl, uint32_t hpet_irqs); void pc_cmos_init(PCMachineState *pcms, From patchwork Thu Sep 1 16:25:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 12962905 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DBF52C64991 for ; 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[2003:fa:af0b:b200:9c49:4783:8afc:41b6]) by smtp.gmail.com with ESMTPSA id p6-20020aa7d306000000b00447c0dcbb99sm1587672edq.83.2022.09.01.09.26.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Sep 2022 09:26:50 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Her?= =?utf-8?q?v=C3=A9_Poussineau?= , Aurelien Jarno , Paolo Bonzini , Eduardo Habkost , Richard Henderson , Jiaxun Yang , Ani Sinha , Igor Mammedov , Marcel Apfelbaum , "Michael S. Tsirkin" , Bernhard Beschow , Peter Maydell Subject: [PATCH 04/42] hw/i386/pc_piix: Allow for setting properties before realizing PIIX3 south bridge Date: Thu, 1 Sep 2022 18:25:35 +0200 Message-Id: <20220901162613.6939-5-shentey@gmail.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220901162613.6939-1-shentey@gmail.com> References: <20220901162613.6939-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::633; envelope-from=shentey@gmail.com; helo=mail-ej1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The next patches will need to take advantage of it. Signed-off-by: Bernhard Beschow Reviewed-by: Peter Maydell --- hw/i386/pc_piix.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index bdad3b6795..b08d946992 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -218,7 +218,8 @@ static void pc_init1(MachineState *machine, pci_memory, ram_memory); pcms->bus = pci_bus; - pci_dev = pci_create_simple_multifunction(pci_bus, -1, true, type); + pci_dev = pci_new_multifunction(-1, true, type); + pci_realize_and_unref(pci_dev, pci_bus, &error_fatal); piix3 = PIIX3_PCI_DEVICE(pci_dev); piix3->pic = x86ms->gsi; piix3_devfn = piix3->dev.devfn; From patchwork Thu Sep 1 16:25:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 12962911 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D3B28ECAAD3 for ; Thu, 1 Sep 2022 16:36:18 +0000 (UTC) Received: from localhost ([::1]:35010 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oTnAv-0002hd-Na for qemu-devel@archiver.kernel.org; Thu, 01 Sep 2022 12:36:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53510) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oTn1s-0001cX-N9 for qemu-devel@nongnu.org; Thu, 01 Sep 2022 12:26:56 -0400 Received: from mail-ej1-x62b.google.com ([2a00:1450:4864:20::62b]:46747) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oTn1p-0001TY-Q1 for qemu-devel@nongnu.org; Thu, 01 Sep 2022 12:26:56 -0400 Received: by mail-ej1-x62b.google.com with SMTP id bj12so35783176ejb.13 for ; Thu, 01 Sep 2022 09:26:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=E8CdrfDzNOCCHxJsZeXx/7U1h4ccAVACKCfHIdwwrww=; b=eNWXWBT9k61wDTAq9YS9IWiA9ljDsk9chfV48TH++0KPLi3xa1uhBojj3K3cQ1sl6X JeNMKBNFgSSYLFJh/hC4Cq1AcN5AtY8MLHa3GF9dW89TeCzS8FaaoVXlgeKjwC4LcZUX DT5Cci9APwkAQj3rp+ysQdht/5KQW1zH9SvO1tlrvLZjiz1sxTnL1H6zwJk5urAkz7iF GvAMSMRg+80gUJbFrAz3Cjo4y4PfCYZ39HVnKKdys6kKtVX7D15k0NA455QVGcaS2EgX KQeqm0wpdrl41c1zCGwTYPDywWPmx1HLJigjDe5L7L78L4HvI54KufoVjvKev6rKMaKT YXEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=E8CdrfDzNOCCHxJsZeXx/7U1h4ccAVACKCfHIdwwrww=; b=S/Rd2LTVPdPK8lAXEPtt6mdtjxeafQjnribeFf3HMzSiLSl/aoN7iYa210XhELmTru 49S9xBq5l3GU7CQDtugO8q1uFTU6pJf5TlVsOlHTqj5a2kzVuFFtkw0AqjgKcMa16B09 BQ9yblpXvhweeAipPw0Mk03iNNCTZlA1nnnPrlshjHJ9O++QSl+ACCwy+fHBVtXhKTQF IOAYWwid9vKBsam8jiEdid79iw61eI3nE9wD7efRdi/86eUb+BKtS6+JagSE0qRCwL9e 3OPOmHCC/PIPLxfSZjAwnZQFCRmZoaf4xsNNreOQYulztoyInlgUA+z4UF3lJGo/1Xgi C0Mw== X-Gm-Message-State: ACgBeo3isi9aHRJRLGqztU1ZZ4jHzThpEtbNTwpuo1qVqbrEn25oaS1q 06NGPfjMGPaaqVBftC2gxsGf9pLSTCA= X-Google-Smtp-Source: AA6agR5Rr3oRXbOzvRovbQV1aiuTe00PRSi/eAehrBZkf62yoIGXRcSyYD0iEujLLQU6kIImFo7img== X-Received: by 2002:a17:907:7215:b0:741:416f:fb59 with SMTP id dr21-20020a170907721500b00741416ffb59mr18594301ejc.150.1662049611881; Thu, 01 Sep 2022 09:26:51 -0700 (PDT) Received: from osoxes.fritz.box (p200300faaf0bb2009c4947838afc41b6.dip0.t-ipconnect.de. [2003:fa:af0b:b200:9c49:4783:8afc:41b6]) by smtp.gmail.com with ESMTPSA id p6-20020aa7d306000000b00447c0dcbb99sm1587672edq.83.2022.09.01.09.26.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Sep 2022 09:26:51 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Her?= =?utf-8?q?v=C3=A9_Poussineau?= , Aurelien Jarno , Paolo Bonzini , Eduardo Habkost , Richard Henderson , Jiaxun Yang , Ani Sinha , Igor Mammedov , Marcel Apfelbaum , "Michael S. Tsirkin" , Bernhard Beschow Subject: [PATCH 05/42] hw/isa/piix3: Create USB controller in host device Date: Thu, 1 Sep 2022 18:25:36 +0200 Message-Id: <20220901162613.6939-6-shentey@gmail.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220901162613.6939-1-shentey@gmail.com> References: <20220901162613.6939-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62b; envelope-from=shentey@gmail.com; helo=mail-ej1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The USB controller is an integral part of PIIX3 (function 2). So create it as part of the south bridge. Note that the USB function is optional in QEMU. This is why it gets object_initialize_child()'ed in realize rather than in instance_init. Signed-off-by: Bernhard Beschow --- hw/i386/pc_piix.c | 6 ++---- hw/isa/Kconfig | 1 + hw/isa/piix3.c | 17 +++++++++++++++++ include/hw/southbridge/piix.h | 4 ++++ 4 files changed, 24 insertions(+), 4 deletions(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index b08d946992..76ac8b2035 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -219,6 +219,8 @@ static void pc_init1(MachineState *machine, pcms->bus = pci_bus; pci_dev = pci_new_multifunction(-1, true, type); + object_property_set_bool(OBJECT(pci_dev), "has-usb", + machine_usb(machine), &error_abort); pci_realize_and_unref(pci_dev, pci_bus, &error_fatal); piix3 = PIIX3_PCI_DEVICE(pci_dev); piix3->pic = x86ms->gsi; @@ -297,10 +299,6 @@ static void pc_init1(MachineState *machine, } #endif - if (pcmc->pci_enabled && machine_usb(machine)) { - pci_create_simple(pci_bus, piix3_devfn + 2, "piix3-usb-uhci"); - } - if (pcmc->pci_enabled && x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) { PCIDevice *piix4_pm; diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig index 6e8f9cac54..f02eca3c3e 100644 --- a/hw/isa/Kconfig +++ b/hw/isa/Kconfig @@ -36,6 +36,7 @@ config PIIX3 select I8257 select ISA_BUS select MC146818RTC + select USB_UHCI config PIIX4 bool diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index 96ab7107e2..27052a5546 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -297,6 +297,7 @@ static const MemoryRegionOps rcr_ops = { static void pci_piix3_realize(PCIDevice *dev, Error **errp) { PIIX3State *d = PIIX3_PCI_DEVICE(dev); + PCIBus *pci_bus = pci_get_bus(dev); ISABus *isa_bus; isa_bus = isa_bus_new(DEVICE(d), get_system_memory(), @@ -319,6 +320,16 @@ static void pci_piix3_realize(PCIDevice *dev, Error **errp) if (!qdev_realize(DEVICE(&d->rtc), BUS(isa_bus), errp)) { return; } + + /* USB */ + if (d->has_usb) { + object_initialize_child(OBJECT(dev), "uhci", &d->uhci, + "piix3-usb-uhci"); + qdev_prop_set_int32(DEVICE(&d->uhci), "addr", dev->devfn + 2); + if (!qdev_realize(DEVICE(&d->uhci), BUS(pci_bus), errp)) { + return; + } + } } static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope) @@ -341,6 +352,11 @@ static void pci_piix3_init(Object *obj) object_initialize_child(obj, "rtc", &d->rtc, TYPE_MC146818_RTC); } +static Property pci_piix3_props[] = { + DEFINE_PROP_BOOL("has-usb", PIIX3State, has_usb, true), + DEFINE_PROP_END_OF_LIST(), +}; + static void pci_piix3_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -359,6 +375,7 @@ static void pci_piix3_class_init(ObjectClass *klass, void *data) * pc_piix.c's pc_init1() */ dc->user_creatable = false; + device_class_set_props(dc, pci_piix3_props); adevc->build_dev_aml = build_pci_isa_aml; } diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index b1fa08dd2b..5367917182 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -15,6 +15,7 @@ #include "hw/pci/pci.h" #include "qom/object.h" #include "hw/rtc/mc146818rtc.h" +#include "hw/usb/hcd-uhci.h" /* PIRQRC[A:D]: PIRQx Route Control Registers */ #define PIIX_PIRQCA 0x60 @@ -54,12 +55,15 @@ struct PIIXState { int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS]; RTCState rtc; + UHCIState uhci; /* Reset Control Register contents */ uint8_t rcr; /* IO memory region for Reset Control Register (PIIX_RCR_IOPORT) */ MemoryRegion rcr_mem; + + bool has_usb; }; typedef struct PIIXState PIIX3State; From patchwork Thu Sep 1 16:25:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 12962910 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 90C6BECAAD8 for ; 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[2003:fa:af0b:b200:9c49:4783:8afc:41b6]) by smtp.gmail.com with ESMTPSA id p6-20020aa7d306000000b00447c0dcbb99sm1587672edq.83.2022.09.01.09.26.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Sep 2022 09:26:52 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Her?= =?utf-8?q?v=C3=A9_Poussineau?= , Aurelien Jarno , Paolo Bonzini , Eduardo Habkost , Richard Henderson , Jiaxun Yang , Ani Sinha , Igor Mammedov , Marcel Apfelbaum , "Michael S. Tsirkin" , Bernhard Beschow Subject: [PATCH 06/42] hw/isa/piix3: Create power management controller in host device Date: Thu, 1 Sep 2022 18:25:37 +0200 Message-Id: <20220901162613.6939-7-shentey@gmail.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220901162613.6939-1-shentey@gmail.com> References: <20220901162613.6939-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62b; envelope-from=shentey@gmail.com; helo=mail-ej1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The power management controller is an integral part of PIIX3 (function 3). So create it as part of the south bridge. Note that the ACPI function is optional in QEMU. This is why it gets object_initialize_child()'ed in realize rather than in instance_init. Signed-off-by: Bernhard Beschow --- hw/i386/pc_piix.c | 23 +++++++++++++---------- hw/isa/Kconfig | 1 + hw/isa/piix3.c | 14 ++++++++++++++ include/hw/southbridge/piix.h | 6 ++++++ 4 files changed, 34 insertions(+), 10 deletions(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 76ac8b2035..7efef4f364 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -45,11 +45,11 @@ #include "sysemu/kvm.h" #include "hw/kvm/clock.h" #include "hw/sysbus.h" +#include "hw/i2c/i2c.h" #include "hw/i2c/smbus_eeprom.h" #include "hw/xen/xen-x86.h" #include "exec/memory.h" #include "hw/acpi/acpi.h" -#include "hw/acpi/piix4.h" #include "qapi/error.h" #include "qemu/error-report.h" #include "sysemu/xen.h" @@ -84,6 +84,7 @@ static void pc_init1(MachineState *machine, MemoryRegion *system_io = get_system_io(); PCIBus *pci_bus; ISABus *isa_bus; + Object *piix4_pm; int piix3_devfn = -1; qemu_irq smi_irq; GSIState *gsi_state; @@ -221,6 +222,13 @@ static void pc_init1(MachineState *machine, pci_dev = pci_new_multifunction(-1, true, type); object_property_set_bool(OBJECT(pci_dev), "has-usb", machine_usb(machine), &error_abort); + object_property_set_bool(OBJECT(pci_dev), "has-acpi", + x86_machine_is_acpi_enabled(x86ms), + &error_abort); + qdev_prop_set_uint32(DEVICE(pci_dev), "smb_io_base", 0xb100); + object_property_set_bool(OBJECT(pci_dev), "smm-enabled", + x86_machine_is_smm_enabled(x86ms), + &error_abort); pci_realize_and_unref(pci_dev, pci_bus, &error_fatal); piix3 = PIIX3_PCI_DEVICE(pci_dev); piix3->pic = x86ms->gsi; @@ -228,8 +236,10 @@ static void pc_init1(MachineState *machine, isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0")); rtc_state = ISA_DEVICE(object_resolve_path_component(OBJECT(pci_dev), "rtc")); + piix4_pm = object_resolve_path_component(OBJECT(pci_dev), "pm"); } else { pci_bus = NULL; + piix4_pm = NULL; isa_bus = isa_bus_new(NULL, get_system_memory(), system_io, &error_abort); @@ -299,15 +309,8 @@ static void pc_init1(MachineState *machine, } #endif - if (pcmc->pci_enabled && x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) { - PCIDevice *piix4_pm; - + if (piix4_pm) { smi_irq = qemu_allocate_irq(pc_acpi_smi_interrupt, first_cpu, 0); - piix4_pm = pci_new(piix3_devfn + 3, TYPE_PIIX4_PM); - qdev_prop_set_uint32(DEVICE(piix4_pm), "smb_io_base", 0xb100); - qdev_prop_set_bit(DEVICE(piix4_pm), "smm-enabled", - x86_machine_is_smm_enabled(x86ms)); - pci_realize_and_unref(piix4_pm, pci_bus, &error_fatal); qdev_connect_gpio_out(DEVICE(piix4_pm), 0, x86ms->gsi[9]); qdev_connect_gpio_out_named(DEVICE(piix4_pm), "smi-irq", 0, smi_irq); @@ -321,7 +324,7 @@ static void pc_init1(MachineState *machine, object_property_allow_set_link, OBJ_PROP_LINK_STRONG); object_property_set_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP, - OBJECT(piix4_pm), &error_abort); + piix4_pm, &error_abort); } if (machine->nvdimms_state->is_enabled) { diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig index f02eca3c3e..f10daa26bc 100644 --- a/hw/isa/Kconfig +++ b/hw/isa/Kconfig @@ -33,6 +33,7 @@ config PC87312 config PIIX3 bool + select ACPI_PIIX4 select I8257 select ISA_BUS select MC146818RTC diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index 27052a5546..3bd25013ee 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -330,6 +330,17 @@ static void pci_piix3_realize(PCIDevice *dev, Error **errp) return; } } + + /* Power Management */ + if (d->has_acpi) { + object_initialize_child(OBJECT(d), "pm", &d->pm, TYPE_PIIX4_PM); + qdev_prop_set_int32(DEVICE(&d->pm), "addr", dev->devfn + 3); + qdev_prop_set_uint32(DEVICE(&d->pm), "smb_io_base", d->smb_io_base); + qdev_prop_set_bit(DEVICE(&d->pm), "smm-enabled", d->smm_enabled); + if (!qdev_realize(DEVICE(&d->pm), BUS(pci_bus), errp)) { + return; + } + } } static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope) @@ -353,7 +364,10 @@ static void pci_piix3_init(Object *obj) } static Property pci_piix3_props[] = { + DEFINE_PROP_UINT32("smb_io_base", PIIX3State, smb_io_base, 0), + DEFINE_PROP_BOOL("has-acpi", PIIX3State, has_acpi, true), DEFINE_PROP_BOOL("has-usb", PIIX3State, has_usb, true), + DEFINE_PROP_BOOL("smm-enabled", PIIX3State, smm_enabled, false), DEFINE_PROP_END_OF_LIST(), }; diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index 5367917182..1c291cc954 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -14,6 +14,7 @@ #include "hw/pci/pci.h" #include "qom/object.h" +#include "hw/acpi/piix4.h" #include "hw/rtc/mc146818rtc.h" #include "hw/usb/hcd-uhci.h" @@ -56,6 +57,9 @@ struct PIIXState { RTCState rtc; UHCIState uhci; + PIIX4PMState pm; + + uint32_t smb_io_base; /* Reset Control Register contents */ uint8_t rcr; @@ -63,7 +67,9 @@ struct PIIXState { /* IO memory region for Reset Control Register (PIIX_RCR_IOPORT) */ MemoryRegion rcr_mem; + bool has_acpi; bool has_usb; + bool smm_enabled; }; typedef struct PIIXState PIIX3State; From patchwork Thu Sep 1 16:25:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 12962913 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AC63AECAAD1 for ; Thu, 1 Sep 2022 16:39:43 +0000 (UTC) Received: from localhost ([::1]:59698 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oTnEE-00007R-Op for qemu-devel@archiver.kernel.org; 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[2003:fa:af0b:b200:9c49:4783:8afc:41b6]) by smtp.gmail.com with ESMTPSA id p6-20020aa7d306000000b00447c0dcbb99sm1587672edq.83.2022.09.01.09.26.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Sep 2022 09:26:53 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Her?= =?utf-8?q?v=C3=A9_Poussineau?= , Aurelien Jarno , Paolo Bonzini , Eduardo Habkost , Richard Henderson , Jiaxun Yang , Ani Sinha , Igor Mammedov , Marcel Apfelbaum , "Michael S. Tsirkin" , Bernhard Beschow Subject: [PATCH 07/42] hw/intc/i8259: Introduce i8259 proxy "isa-pic" Date: Thu, 1 Sep 2022 18:25:38 +0200 Message-Id: <20220901162613.6939-8-shentey@gmail.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220901162613.6939-1-shentey@gmail.com> References: <20220901162613.6939-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::536; envelope-from=shentey@gmail.com; helo=mail-ed1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Having an i8259 proxy allows for ISA PICs to be created and wired up in southbridges. This is especially interesting for PIIX3 for two reasons: First, the southbridge doesn't need to care about the virtualization technology used (KVM, TCG, Xen) due to in-IRQs (where devices get attached) and out-IRQs (which will trigger the IRQs of the respective virtzalization technology) are separated. Second, since the in-IRQs are populated with fully initialized qemu_irq's, they can already be wired up inside PIIX3. Signed-off-by: Bernhard Beschow --- hw/intc/i8259.c | 27 +++++++++++++++++++++++++++ include/hw/intc/i8259.h | 14 ++++++++++++++ 2 files changed, 41 insertions(+) diff --git a/hw/intc/i8259.c b/hw/intc/i8259.c index cc4e21ffec..531f6cca53 100644 --- a/hw/intc/i8259.c +++ b/hw/intc/i8259.c @@ -458,9 +458,36 @@ static const TypeInfo i8259_info = { .class_size = sizeof(PICClass), }; +static void isapic_set_irq(void *opaque, int irq, int level) +{ + ISAPICState *s = opaque; + + qemu_set_irq(s->out_irqs[irq], level); +} + +static void isapic_init(Object *obj) +{ + ISAPICState *s = ISA_PIC(obj); + + qdev_init_gpio_in(DEVICE(s), isapic_set_irq, ISA_NUM_IRQS); + qdev_init_gpio_out(DEVICE(s), s->out_irqs, ISA_NUM_IRQS); + + for (int i = 0; i < ISA_NUM_IRQS; ++i) { + s->in_irqs[i] = qdev_get_gpio_in(DEVICE(s), i); + } +} + +static const TypeInfo isapic_info = { + .name = TYPE_ISA_PIC, + .parent = TYPE_ISA_DEVICE, + .instance_size = sizeof(ISAPICState), + .instance_init = isapic_init, +}; + static void pic_register_types(void) { type_register_static(&i8259_info); + type_register_static(&isapic_info); } type_init(pic_register_types) diff --git a/include/hw/intc/i8259.h b/include/hw/intc/i8259.h index e2b1e8c59a..0246ab6ac6 100644 --- a/include/hw/intc/i8259.h +++ b/include/hw/intc/i8259.h @@ -1,6 +1,20 @@ #ifndef HW_I8259_H #define HW_I8259_H +#include "qom/object.h" +#include "hw/isa/isa.h" +#include "qemu/typedefs.h" + +#define TYPE_ISA_PIC "isa-pic" +OBJECT_DECLARE_SIMPLE_TYPE(ISAPICState, ISA_PIC) + +struct ISAPICState { + ISADevice parent_obj; + + qemu_irq in_irqs[ISA_NUM_IRQS]; + qemu_irq out_irqs[ISA_NUM_IRQS]; +}; + /* i8259.c */ extern DeviceState *isa_pic; From patchwork Thu Sep 1 16:25:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 12962915 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6B214ECAAD3 for ; Thu, 1 Sep 2022 16:39:51 +0000 (UTC) Received: from localhost ([::1]:46042 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oTnEM-0000N3-GT for qemu-devel@archiver.kernel.org; Thu, 01 Sep 2022 12:39:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53516) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oTn1u-0001f6-Du for qemu-devel@nongnu.org; Thu, 01 Sep 2022 12:26:58 -0400 Received: from mail-ej1-x62b.google.com ([2a00:1450:4864:20::62b]:38534) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oTn1s-0001UW-J9 for qemu-devel@nongnu.org; Thu, 01 Sep 2022 12:26:58 -0400 Received: by mail-ej1-x62b.google.com with SMTP id u9so35837892ejy.5 for ; Thu, 01 Sep 2022 09:26:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=2JQF2PriVkCcCHZKUuvvLMa6gjcPvEwC17Lqi8O9ljE=; b=hYplaFoInKnVZycPeCUOMuIVY5z7H7RtGwySsoJ4eWbXbwirHo+KuwU8Tf9Ou/rgzR qjTLw3LbewWPtp96sV+8oRkVKnyHpS+Gb0YSpC/9kPwYS8e6v13nx77oHRymRg8FSjxv 5+RD3bvA0t0bZ/f2po7Ka8xoTo9FJ9aKU4SjI8NIAsylukD5wCu//BNXblCPfIMgn11h 2VdZ+LKhpkirwwiv/9fENwTzNvhrMNwZO7q6F8s2V9u6FYqUYkr5K3AE9OFBMbjPG+nd a/7kGxzvI/WPATdv7JAfpWD64nzT1Hf+NMUtxPDJiiBkIM+vu6CNYQxNXTldODJPIK+b vEnA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=2JQF2PriVkCcCHZKUuvvLMa6gjcPvEwC17Lqi8O9ljE=; b=criUn2dInGDvXp81ue7t7+NSpTIuo4iwOlNXPLsGCCDagmWhT1cy1LHSg37Lcy8TZ/ bb4RySBOoD/CxcfMbmzZEonAikv3n7uKfQjlDd/sMCicRMz0rEDgX5Qr+hIXSz++gx1f ABoay0DFMu6if8voA8OutkNR6liVxQZRPuEelvEF2t+nRsPzFIDHkqtBZchAHXQg6X3A CqSChDBEr9dN8QuZtlOrHOUqGQ3rW0t4Zp9M1bs/mk2/HXiaVcVaBqhUzkIXepwq9Kpt ijHwrBzGbvXWIO5K9OvPOZVm6Kg/zzzMTXeQueqTDJeI4bfwZyXXnLoPcwrN/lE+fb8H 8doA== X-Gm-Message-State: ACgBeo2GAeTQiZYlGpwolb1suhwupAbT/iG8lGf7Jy8Pc/7D4QbH+jkS +KlISTW/56HINq1zQZTNjtZul03HuXQ= X-Google-Smtp-Source: AA6agR4esty8JI7kWpLbFDWcUllyX5AmnD/4YNE4AtuQbPTpn81LR2GQTXz76vTFdlKStrm5G4yK1A== X-Received: by 2002:a17:907:7dac:b0:739:8df9:3c16 with SMTP id oz44-20020a1709077dac00b007398df93c16mr23970005ejc.9.1662049615085; Thu, 01 Sep 2022 09:26:55 -0700 (PDT) Received: from osoxes.fritz.box (p200300faaf0bb2009c4947838afc41b6.dip0.t-ipconnect.de. [2003:fa:af0b:b200:9c49:4783:8afc:41b6]) by smtp.gmail.com with ESMTPSA id p6-20020aa7d306000000b00447c0dcbb99sm1587672edq.83.2022.09.01.09.26.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Sep 2022 09:26:54 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Her?= =?utf-8?q?v=C3=A9_Poussineau?= , Aurelien Jarno , Paolo Bonzini , Eduardo Habkost , Richard Henderson , Jiaxun Yang , Ani Sinha , Igor Mammedov , Marcel Apfelbaum , "Michael S. Tsirkin" , Bernhard Beschow Subject: [PATCH 08/42] hw/isa/piix3: Create ISA PIC in host device Date: Thu, 1 Sep 2022 18:25:39 +0200 Message-Id: <20220901162613.6939-9-shentey@gmail.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220901162613.6939-1-shentey@gmail.com> References: <20220901162613.6939-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62b; envelope-from=shentey@gmail.com; helo=mail-ej1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Use the newly introduced i8259 proxy "isa-pic" which allows for wiring up devices in the southbridge where the virtualization technology used (KVM, TCG, Xen) is not yet known. Signed-off-by: Bernhard Beschow --- hw/i386/pc_piix.c | 15 +++++++++------ hw/isa/Kconfig | 1 + hw/isa/piix3.c | 10 +++++++++- include/hw/southbridge/piix.h | 4 ++-- 4 files changed, 21 insertions(+), 9 deletions(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 7efef4f364..b7fcafb77e 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -206,10 +206,11 @@ static void pc_init1(MachineState *machine, gsi_state = pc_gsi_create(&x86ms->gsi, pcmc->pci_enabled); if (pcmc->pci_enabled) { - PIIX3State *piix3; + DeviceState *dev; PCIDevice *pci_dev; const char *type = xen_enabled() ? TYPE_PIIX3_XEN_DEVICE : TYPE_PIIX3_DEVICE; + int i; pci_bus = i440fx_init(pci_type, i440fx_host, @@ -230,10 +231,12 @@ static void pc_init1(MachineState *machine, x86_machine_is_smm_enabled(x86ms), &error_abort); pci_realize_and_unref(pci_dev, pci_bus, &error_fatal); - piix3 = PIIX3_PCI_DEVICE(pci_dev); - piix3->pic = x86ms->gsi; - piix3_devfn = piix3->dev.devfn; - isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0")); + dev = DEVICE(object_resolve_path_component(OBJECT(pci_dev), "pic")); + for (i = 0; i < ISA_NUM_IRQS; i++) { + qdev_connect_gpio_out(dev, i, x86ms->gsi[i]); + } + piix3_devfn = pci_dev->devfn; + isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(pci_dev), "isa.0")); rtc_state = ISA_DEVICE(object_resolve_path_component(OBJECT(pci_dev), "rtc")); piix4_pm = object_resolve_path_component(OBJECT(pci_dev), "pm"); @@ -242,6 +245,7 @@ static void pc_init1(MachineState *machine, piix4_pm = NULL; isa_bus = isa_bus_new(NULL, get_system_memory(), system_io, &error_abort); + isa_bus_irqs(isa_bus, x86ms->gsi); rtc_state = isa_new(TYPE_MC146818_RTC); qdev_prop_set_int32(DEVICE(rtc_state), "base_year", 2000); @@ -250,7 +254,6 @@ static void pc_init1(MachineState *machine, i8257_dma_init(isa_bus, 0); pcms->hpet_enabled = false; } - isa_bus_irqs(isa_bus, x86ms->gsi); if (x86ms->pic == ON_OFF_AUTO_ON || x86ms->pic == ON_OFF_AUTO_AUTO) { pc_i8259_create(isa_bus, gsi_state->i8259_irq); diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig index f10daa26bc..24e79a9a41 100644 --- a/hw/isa/Kconfig +++ b/hw/isa/Kconfig @@ -35,6 +35,7 @@ config PIIX3 bool select ACPI_PIIX4 select I8257 + select I8259 select ISA_BUS select MC146818RTC select USB_UHCI diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index 3bd25013ee..39d8cb787f 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -41,7 +41,7 @@ static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq) { - qemu_set_irq(piix3->pic[pic_irq], + qemu_set_irq(piix3->pic.in_irqs[pic_irq], !!(piix3->pic_levels & (((1ULL << PIIX_NUM_PIRQS) - 1) << (pic_irq * PIIX_NUM_PIRQS)))); @@ -306,6 +306,13 @@ static void pci_piix3_realize(PCIDevice *dev, Error **errp) return; } + /* PIC */ + if (!qdev_realize(DEVICE(&d->pic), BUS(isa_bus), errp)) { + return; + } + + isa_bus_irqs(isa_bus, d->pic.in_irqs); + memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d, "piix3-reset-control", 1); memory_region_add_subregion_overlap(pci_address_space_io(dev), @@ -360,6 +367,7 @@ static void pci_piix3_init(Object *obj) { PIIX3State *d = PIIX3_PCI_DEVICE(obj); + object_initialize_child(obj, "pic", &d->pic, TYPE_ISA_PIC); object_initialize_child(obj, "rtc", &d->rtc, TYPE_MC146818_RTC); } diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index 1c291cc954..7178147b75 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -15,6 +15,7 @@ #include "hw/pci/pci.h" #include "qom/object.h" #include "hw/acpi/piix4.h" +#include "hw/intc/i8259.h" #include "hw/rtc/mc146818rtc.h" #include "hw/usb/hcd-uhci.h" @@ -50,11 +51,10 @@ struct PIIXState { #endif uint64_t pic_levels; - qemu_irq *pic; - /* This member isn't used. Just for save/load compatibility */ int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS]; + ISAPICState pic; RTCState rtc; UHCIState uhci; PIIX4PMState pm; From patchwork Thu Sep 1 16:25:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 12962908 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 74AFBECAAD3 for ; Thu, 1 Sep 2022 16:36:11 +0000 (UTC) Received: from localhost ([::1]:41314 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oTnAo-0002Uj-9S for qemu-devel@archiver.kernel.org; Thu, 01 Sep 2022 12:36:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53518) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oTn1v-0001ii-TU for qemu-devel@nongnu.org; Thu, 01 Sep 2022 12:26:59 -0400 Received: from mail-ed1-x535.google.com ([2a00:1450:4864:20::535]:40941) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oTn1t-0001Um-Ss for qemu-devel@nongnu.org; Thu, 01 Sep 2022 12:26:59 -0400 Received: by mail-ed1-x535.google.com with SMTP id m1so23309209edb.7 for ; Thu, 01 Sep 2022 09:26:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=EoxlkUwz75TMtGKP4zRxpf2YwPH7PAH4alIR4dYwMwU=; b=NLKBrok271LuJfG05MN0z5/F1m0dUEidl5qm5YcltZq/7lLQVNBAvJ3dqtNqWL7Q7T 5+fFj/2nj/POcrGrh0PFHfZyzvJw3cej74ZBq/DTBq/t3axBwMub9Qodnd+EeloAsT5l VOeMkpn+2v0x6GtGCeW5wJtYfv9VQnQX14v/4Qfg4uXBh6F9pJMRoxgwohY+1VetiEPA On7ibvOIFdCGVhM2yXJNCIZVnXKmlgXC75mVNIlGv3d6etA6mRh6uXygvD/viq+vA1sc Wom3leRbQOiyxGn/+le4Mq9aUKrF7vPmI/0FtgCT+6caOP6PkZvS2XFSiofGor5h5zZt Mliw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=EoxlkUwz75TMtGKP4zRxpf2YwPH7PAH4alIR4dYwMwU=; b=CVHv5CwX+92rSpwgqKQ3hbhLhOL3Z2nHGUVPx2ALjLrPJL5/mD1GKgxtYaAdY7TVdM iKjCUVUnXEDlihgExGztkG8Akp5DPsSGyIIYyB4XRw2WZ11nsuQ5NaKSR/Ql1Fy/cmeQ w7qfB+0yShxqghzDt/xIlYxx7vImNLxEK7T8rwTszG3k0ZnnIMCTG8+e8gwJr2treRiD pqB8JoKMZ3O9XFqegeOwno6IFATaXrmHAFsVshn7UW+sjY88BVlBkOXUMCEmBX5FlS61 Whyr3ivjEQFqANUKTyWFpYK7TU0ISDQRqOITQ9lE1T46EoY2StQ8aNSTblIP6ryXJtKw FAhg== X-Gm-Message-State: ACgBeo0MHEkZln7R8zXGM9b+CxiD4W5fcNY0c5gelEqP4bgb/T+Zpj4I NatqiUNgEL8KFjUclbP32vKLp0I6/30= X-Google-Smtp-Source: AA6agR6Jja6DDS5WoRHVx/swNWQbVS28RSnScsPPxFZO/VHOtqhuqUu9miJzL5zmgEOqGSlP38XlMQ== X-Received: by 2002:a05:6402:1c8f:b0:447:8124:abd with SMTP id cy15-20020a0564021c8f00b0044781240abdmr29348426edb.223.1662049616252; Thu, 01 Sep 2022 09:26:56 -0700 (PDT) Received: from osoxes.fritz.box (p200300faaf0bb2009c4947838afc41b6.dip0.t-ipconnect.de. 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Tsirkin" , Bernhard Beschow Subject: [PATCH 09/42] hw/isa/piix3: Create IDE controller in host device Date: Thu, 1 Sep 2022 18:25:40 +0200 Message-Id: <20220901162613.6939-10-shentey@gmail.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220901162613.6939-1-shentey@gmail.com> References: <20220901162613.6939-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::535; envelope-from=shentey@gmail.com; helo=mail-ed1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Now that PIIX3 contains the new isa-pic, it is possible to instantiate PIIX3 IDE in the PIIX3 southbridge. PIIX3 IDE wires up its interrupts to the ISA bus in its realize method which requires the interrupt controller to provide fully populated qemu_irqs. This is the case for isa-pic even though the virtualization technology not known yet. Signed-off-by: Bernhard Beschow --- hw/i386/Kconfig | 1 - hw/i386/pc_piix.c | 14 ++++++-------- hw/isa/Kconfig | 1 + hw/isa/piix3.c | 7 +++++++ include/hw/southbridge/piix.h | 2 ++ 5 files changed, 16 insertions(+), 9 deletions(-) diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig index d22ac4a4b9..dd247f215c 100644 --- a/hw/i386/Kconfig +++ b/hw/i386/Kconfig @@ -74,7 +74,6 @@ config I440FX select ACPI_SMBUS select PCI_I440FX select PIIX3 - select IDE_PIIX select DIMM select SMBIOS select FW_CFG_DMA diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index b7fcafb77e..c76afbc7e3 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -85,7 +85,6 @@ static void pc_init1(MachineState *machine, PCIBus *pci_bus; ISABus *isa_bus; Object *piix4_pm; - int piix3_devfn = -1; qemu_irq smi_irq; GSIState *gsi_state; BusState *idebus[MAX_IDE_BUS]; @@ -235,11 +234,14 @@ static void pc_init1(MachineState *machine, for (i = 0; i < ISA_NUM_IRQS; i++) { qdev_connect_gpio_out(dev, i, x86ms->gsi[i]); } - piix3_devfn = pci_dev->devfn; isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(pci_dev), "isa.0")); rtc_state = ISA_DEVICE(object_resolve_path_component(OBJECT(pci_dev), "rtc")); piix4_pm = object_resolve_path_component(OBJECT(pci_dev), "pm"); + dev = DEVICE(object_resolve_path_component(OBJECT(pci_dev), "ide")); + pci_ide_create_devs(PCI_DEVICE(dev)); + idebus[0] = qdev_get_child_bus(dev, "ide.0"); + idebus[1] = qdev_get_child_bus(dev, "ide.1"); } else { pci_bus = NULL; piix4_pm = NULL; @@ -253,6 +255,8 @@ static void pc_init1(MachineState *machine, i8257_dma_init(isa_bus, 0); pcms->hpet_enabled = false; + idebus[0] = NULL; + idebus[1] = NULL; } if (x86ms->pic == ON_OFF_AUTO_ON || x86ms->pic == ON_OFF_AUTO_AUTO) { @@ -281,12 +285,6 @@ static void pc_init1(MachineState *machine, pc_nic_init(pcmc, isa_bus, pci_bus); if (pcmc->pci_enabled) { - PCIDevice *dev; - - dev = pci_create_simple(pci_bus, piix3_devfn + 1, "piix3-ide"); - pci_ide_create_devs(dev); - idebus[0] = qdev_get_child_bus(&dev->qdev, "ide.0"); - idebus[1] = qdev_get_child_bus(&dev->qdev, "ide.1"); pc_cmos_init(pcms, idebus[0], idebus[1], rtc_state); } #ifdef CONFIG_IDE_ISA diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig index 24e79a9a41..a021e1cbfc 100644 --- a/hw/isa/Kconfig +++ b/hw/isa/Kconfig @@ -36,6 +36,7 @@ config PIIX3 select ACPI_PIIX4 select I8257 select I8259 + select IDE_PIIX select ISA_BUS select MC146818RTC select USB_UHCI diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index 39d8cb787f..0e86a9a3cb 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -328,6 +328,12 @@ static void pci_piix3_realize(PCIDevice *dev, Error **errp) return; } + /* IDE */ + qdev_prop_set_int32(DEVICE(&d->ide), "addr", dev->devfn + 1); + if (!qdev_realize(DEVICE(&d->ide), BUS(pci_bus), errp)) { + return; + } + /* USB */ if (d->has_usb) { object_initialize_child(OBJECT(dev), "uhci", &d->uhci, @@ -369,6 +375,7 @@ static void pci_piix3_init(Object *obj) object_initialize_child(obj, "pic", &d->pic, TYPE_ISA_PIC); object_initialize_child(obj, "rtc", &d->rtc, TYPE_MC146818_RTC); + object_initialize_child(obj, "ide", &d->ide, "piix3-ide"); } static Property pci_piix3_props[] = { diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index 7178147b75..1f22eb1444 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -15,6 +15,7 @@ #include "hw/pci/pci.h" #include "qom/object.h" #include "hw/acpi/piix4.h" +#include "hw/ide/pci.h" #include "hw/intc/i8259.h" #include "hw/rtc/mc146818rtc.h" #include "hw/usb/hcd-uhci.h" @@ -56,6 +57,7 @@ struct PIIXState { ISAPICState pic; RTCState rtc; + PCIIDEState ide; UHCIState uhci; PIIX4PMState pm; From patchwork Thu Sep 1 16:25:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 12962914 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 18440ECAAD1 for ; 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[2003:fa:af0b:b200:9c49:4783:8afc:41b6]) by smtp.gmail.com with ESMTPSA id p6-20020aa7d306000000b00447c0dcbb99sm1587672edq.83.2022.09.01.09.26.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Sep 2022 09:26:56 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Her?= =?utf-8?q?v=C3=A9_Poussineau?= , Aurelien Jarno , Paolo Bonzini , Eduardo Habkost , Richard Henderson , Jiaxun Yang , Ani Sinha , Igor Mammedov , Marcel Apfelbaum , "Michael S. Tsirkin" , Bernhard Beschow Subject: [PATCH 10/42] hw/isa/piix3: Wire up ACPI interrupt internally Date: Thu, 1 Sep 2022 18:25:41 +0200 Message-Id: <20220901162613.6939-11-shentey@gmail.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220901162613.6939-1-shentey@gmail.com> References: <20220901162613.6939-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::634; envelope-from=shentey@gmail.com; helo=mail-ej1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Now that PIIX3 has the PIC integrated, the ACPI controller can be wired up internally. Signed-off-by: Bernhard Beschow --- hw/i386/pc_piix.c | 1 - hw/isa/piix3.c | 2 ++ 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index c76afbc7e3..907cf865b8 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -313,7 +313,6 @@ static void pc_init1(MachineState *machine, if (piix4_pm) { smi_irq = qemu_allocate_irq(pc_acpi_smi_interrupt, first_cpu, 0); - qdev_connect_gpio_out(DEVICE(piix4_pm), 0, x86ms->gsi[9]); qdev_connect_gpio_out_named(DEVICE(piix4_pm), "smi-irq", 0, smi_irq); pcms->smbus = I2C_BUS(qdev_get_child_bus(DEVICE(piix4_pm), "i2c")); /* TODO: Populate SPD eeprom data. */ diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index 0e86a9a3cb..e85dec3200 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -353,6 +353,8 @@ static void pci_piix3_realize(PCIDevice *dev, Error **errp) if (!qdev_realize(DEVICE(&d->pm), BUS(pci_bus), errp)) { return; } + qdev_connect_gpio_out(DEVICE(&d->pm), 0, + qdev_get_gpio_in(DEVICE(&d->pic), 9)); } } From patchwork Thu Sep 1 16:25:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 12962922 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 48530ECAAD3 for ; Thu, 1 Sep 2022 16:42:46 +0000 (UTC) Received: from localhost ([::1]:40916 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oTnHB-00067h-8c for qemu-devel@archiver.kernel.org; Thu, 01 Sep 2022 12:42:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53522) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oTn1x-0001nZ-6I for qemu-devel@nongnu.org; Thu, 01 Sep 2022 12:27:01 -0400 Received: from mail-ed1-x536.google.com ([2a00:1450:4864:20::536]:35563) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oTn1v-0001UA-1e for qemu-devel@nongnu.org; Thu, 01 Sep 2022 12:27:00 -0400 Received: by mail-ed1-x536.google.com with SMTP id y64so11483536ede.2 for ; Thu, 01 Sep 2022 09:26:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=BMmSdP4ZZVtB54ezr9h7KI51scbR0FMH6vF9qMiRlSs=; b=M5xoyQq+B4UC9JlKPpaQsh3f5Ot4yjahZUg+QRu0nCCXi2fXIh0gTZk5S2+tIZIWWA NVtFubYDEDb0zmT6VJRFMptDvfojlSi6+gPttJ2x3W2upaDffMOiIPcEyaibTGhBs7+r P9jjHKCjfZ5PBIdhxPh9Yi5qkQIabev6TdJF5ookuAlyZPN++yKl6m4QoLHbqnLBiFUP gD7tyAP4svCKuiCgZmviDHj4JxDYsrhcvtlhB2NlL/o2cvFam2fw6V+ByuFBmknr2d/M taZ1O520nzK70Yxn0JWErmxCVHTRYg/NZi2q2A2EIoyYUeqgA9emRjvPSKuM+psliLtw 5jfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=BMmSdP4ZZVtB54ezr9h7KI51scbR0FMH6vF9qMiRlSs=; b=nXEHmqnGnqRynpQ1VUtiUX6SVLmj1VP14VET7Q4uHqTZgrRJPbRaz0UcKiB8E03y7K FX/rXRGJyL4v71NQ/HJzIEg6GzpaX51+JrMggyAAeCUd9xFg7276YeqQZ1AUmrxeDKVp fT9wfjSwH+mVIwTgAd+kUab7JECKO6d47/IzgLxVRw+AsHhlUiZorcwAXZvNqEHLB2HZ N1zq61lsoX9/9yhmUPfNQJdoD5GCXJ8+vekxJkQxaONPYyS/30V6ZkkJdXPuKFP1gLKD de8pmC5CTg4eOvwD/zWQIDyKM3KAdO5lIskWvOM7+ByiOQfB+u4Tnq4HIe24lW165QMj DFkA== X-Gm-Message-State: ACgBeo1pf20snZdIxsGtCaZaQYuUAr9y7t0qeT1FzA6A77jKso3a2rNT otHC3+rBJs7WaT/RJxzz+toQgkHoylA= X-Google-Smtp-Source: AA6agR4/YWqmay54hSbUrfmVBIk0JW7ouWou6rOnPaiLDXLRXSqFdf5zLdks8OWPYAMGSzJdGEh9Cg== X-Received: by 2002:a05:6402:190d:b0:447:ed22:4d0d with SMTP id e13-20020a056402190d00b00447ed224d0dmr25616390edz.309.1662049618214; Thu, 01 Sep 2022 09:26:58 -0700 (PDT) Received: from osoxes.fritz.box (p200300faaf0bb2009c4947838afc41b6.dip0.t-ipconnect.de. [2003:fa:af0b:b200:9c49:4783:8afc:41b6]) by smtp.gmail.com with ESMTPSA id p6-20020aa7d306000000b00447c0dcbb99sm1587672edq.83.2022.09.01.09.26.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Sep 2022 09:26:57 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Her?= =?utf-8?q?v=C3=A9_Poussineau?= , Aurelien Jarno , Paolo Bonzini , Eduardo Habkost , Richard Henderson , Jiaxun Yang , Ani Sinha , Igor Mammedov , Marcel Apfelbaum , "Michael S. Tsirkin" , Bernhard Beschow , Peter Maydell Subject: [PATCH 11/42] hw/isa/piix3: Remove extra ';' outside of functions Date: Thu, 1 Sep 2022 18:25:42 +0200 Message-Id: <20220901162613.6939-12-shentey@gmail.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220901162613.6939-1-shentey@gmail.com> References: <20220901162613.6939-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::536; envelope-from=shentey@gmail.com; helo=mail-ed1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Fixes the "extra-semi" clang-tidy check. Signed-off-by: Bernhard Beschow Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé --- hw/isa/piix3.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index e85dec3200..0117f896d2 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -438,7 +438,7 @@ static void piix3_realize(PCIDevice *dev, Error **errp) pci_bus_irqs(pci_bus, piix3_set_irq, pci_slot_get_pirq, piix3, PIIX_NUM_PIRQS); pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq); -}; +} static void piix3_class_init(ObjectClass *klass, void *data) { @@ -473,7 +473,7 @@ static void piix3_xen_realize(PCIDevice *dev, Error **errp) */ pci_bus_irqs(pci_bus, xen_piix3_set_irq, xen_pci_slot_get_pirq, piix3, XEN_PIIX_NUM_PIRQS); -}; +} static void piix3_xen_class_init(ObjectClass *klass, void *data) { @@ -481,7 +481,7 @@ static void piix3_xen_class_init(ObjectClass *klass, void *data) k->config_write = piix3_write_config_xen; k->realize = piix3_xen_realize; -}; +} static const TypeInfo piix3_xen_info = { .name = TYPE_PIIX3_XEN_DEVICE, From patchwork Thu Sep 1 16:25:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 12962926 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 55F4FECAAD3 for ; Thu, 1 Sep 2022 16:46:07 +0000 (UTC) Received: from localhost ([::1]:35578 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oTnKQ-0003ZP-Ep for qemu-devel@archiver.kernel.org; Thu, 01 Sep 2022 12:46:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53524) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oTn1y-0001sA-Bc for qemu-devel@nongnu.org; Thu, 01 Sep 2022 12:27:02 -0400 Received: from mail-ej1-x62d.google.com ([2a00:1450:4864:20::62d]:39477) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oTn1w-0001VH-Mu for qemu-devel@nongnu.org; Thu, 01 Sep 2022 12:27:02 -0400 Received: by mail-ej1-x62d.google.com with SMTP id fy31so35421750ejc.6 for ; Thu, 01 Sep 2022 09:27:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=31lPKLYnuDCb1yDq5SV4IaHEb8zoMnE3VsuK5jWdAf8=; b=jBN/Y+NZ0iW7vQ9ssRpiDDYvWQq0MVS8FIE/GHhD5m6TB0IwhwA/xRV6NjjrPQ+gK3 UOq0VBhPxqjEj3iIXBqy7XOoj+wsbrFwQ2D/NONDb4Quz4FfCmxlFP1vW1e/wkj2NPPX /1yuo+n7+Mb1O10ZpfAcVdK5FbVMzaDdeFjeWv1CaHRndSYhd9JVYN8NghBqrxj/Z047 c8Q4a/s8akWODf1FOBMZyaLNQed3HPvV6pZDSWOmmKtLes55087VaD2U5ZBjbDe4v2Z5 JDs9h6OXoIwm3avykkADVamjbilxBMeQ/gdAWkKYQ6bU3D+Gom+jmusbe31hidEH+L1Q Sqhw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=31lPKLYnuDCb1yDq5SV4IaHEb8zoMnE3VsuK5jWdAf8=; b=HsecyipiAy7uZjpCjGqLXiTRKdxkBfigBrXZdhq2nQ+KlKCjMGzJZDM29y/V1mvoMj GiHuxzWj3kiE1Jb7OQZoxRz5Rg8txhAnxB4NK0qENuJITz/mL2JHykIf7pthePOomL74 Dm+0hfXaLGcHfK9DyDwc+umZFnTAskWdnNYHJBrmGKMkZaXmqcv5Nzxyt/2PVFPkdNoE sDuALg3RQLZ7pX+vbWPRjtuc0n+ieXwjZCU80HKTyNFxI3AVe972N57+XXObT6AoUpK1 lSOQbc1xmOFNPKF39cSZIuEoO6KTNrVDumumRo6lM6Bd8cGv0FNON6OE5OzgUegcujzD R1Ww== X-Gm-Message-State: ACgBeo14Io31PSDlzPVFmkTWUwVTA+ZHkCjKs2Jc8rTom9ZZ66BrIcfS qXXb1JVeCfn9qjEZy798WPK6FGORTmo= X-Google-Smtp-Source: AA6agR4+RK+LTyzJ7ndq710qxb4Ebn07lezPJdZaIf4DZ+a1xk5la59rw5w6+TQdnreKobKbOdk+Kw== X-Received: by 2002:a17:906:cc0e:b0:73d:d898:3900 with SMTP id ml14-20020a170906cc0e00b0073dd8983900mr22466134ejb.82.1662049619229; Thu, 01 Sep 2022 09:26:59 -0700 (PDT) Received: from osoxes.fritz.box (p200300faaf0bb2009c4947838afc41b6.dip0.t-ipconnect.de. [2003:fa:af0b:b200:9c49:4783:8afc:41b6]) by smtp.gmail.com with ESMTPSA id p6-20020aa7d306000000b00447c0dcbb99sm1587672edq.83.2022.09.01.09.26.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Sep 2022 09:26:58 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Her?= =?utf-8?q?v=C3=A9_Poussineau?= , Aurelien Jarno , Paolo Bonzini , Eduardo Habkost , Richard Henderson , Jiaxun Yang , Ani Sinha , Igor Mammedov , Marcel Apfelbaum , "Michael S. Tsirkin" , Bernhard Beschow Subject: [PATCH 12/42] hw/isa/piix3: Remove unused include Date: Thu, 1 Sep 2022 18:25:43 +0200 Message-Id: <20220901162613.6939-13-shentey@gmail.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220901162613.6939-1-shentey@gmail.com> References: <20220901162613.6939-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62d; envelope-from=shentey@gmail.com; helo=mail-ej1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Ammends commit 988fb613215993dd0ce642b89ca8182c479d39dd. Signed-off-by: Bernhard Beschow --- hw/isa/piix3.c | 1 - 1 file changed, 1 deletion(-) diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index 0117f896d2..b54ff1c948 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -31,7 +31,6 @@ #include "hw/qdev-properties.h" #include "hw/isa/isa.h" #include "hw/xen/xen.h" -#include "sysemu/xen.h" #include "sysemu/reset.h" #include "sysemu/runstate.h" #include "migration/vmstate.h" From patchwork Thu Sep 1 16:25:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 12962931 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3635AECAAD1 for ; Thu, 1 Sep 2022 16:52:05 +0000 (UTC) Received: from localhost ([::1]:46888 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oTnQ9-0001Fz-SA for qemu-devel@archiver.kernel.org; Thu, 01 Sep 2022 12:52:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53526) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oTn1z-0001uu-Ac for qemu-devel@nongnu.org; Thu, 01 Sep 2022 12:27:07 -0400 Received: from mail-ed1-x52d.google.com ([2a00:1450:4864:20::52d]:37531) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oTn1x-0001VT-J2 for qemu-devel@nongnu.org; Thu, 01 Sep 2022 12:27:02 -0400 Received: by mail-ed1-x52d.google.com with SMTP id b16so23297092edd.4 for ; Thu, 01 Sep 2022 09:27:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=Lk5BY/vi+uufGxfeaoPsPFkaEoogAtEkcyasHy2Pd/s=; b=T/VT8ej2MA+bhgjSNhcAaLTUCsOeH4BnvgFqhXJRk+38MWqFya/yFnToyKgca8MX2T lIdFBGu4i4v05f8AhfZhLW/qrvcY+K116o8C+OheOcvV3yZlkk0mO2lBBzc6OKB/EU+E BSCGtWt1C5UDdab14C7KirnMxCTE3jb7hGMOdsso81Y5t5mUd45cvxcn8MFboHWCHEPP 3JR0AIVflOC21PSzpiFJSgLP4nHuVQpfn5rkZZGRqaX6K/RhV1AJFRXSR8enbCNGPTVY GgmfSB4fHjWsCEQLXzz3mOzXWl+HGF2JflOIE+NJHyEJsssr1um0u355yvHxsToEx6aO N11g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=Lk5BY/vi+uufGxfeaoPsPFkaEoogAtEkcyasHy2Pd/s=; b=qVw3o1ZsnC4nEEgWB2sLT4uywx7uhFsuBx1y365SLByrUXEJN00mgxQU3UYybBxHP5 6yPZoy4SkAgvK74zujA7nzH/0MJWQ8zHVKH8/ybK8GL2jRBwgf5a8xoDUW1Yvf2lCTuP W1szPqG1IwRfVnPcUujZfd4bXLbLyo2TryG3dYJBIZpFu27bFXoMT1ZzU8Dq7OfG9bHX cPrZe2EwqbyIIi97WuTF96vJTfigvncAUxkqdWXA5YOh7t3XIGJl5xPtxWYq0rPNwqwr XbLzhbERhLD+C3qmpeiWW/aVA/cBEvU8WMaFEc9CY8y4LrPcW+7HLuXPUqplPoKxcRUs A+/A== X-Gm-Message-State: ACgBeo0cmyPvRgBGX9KdvFRRqmCsf4zGVKBfTYVflHtlmPaHylBODZqs l9GjD9KTrssQ0MN6LTpiXLDHmtCah20= X-Google-Smtp-Source: AA6agR5VBymWPOCnwVkwqPO/hgGuMq6/MiGuvLjXFnnv751pHnCDEd2cZa7ABCkEqE0SYO/h4UU0ag== X-Received: by 2002:a05:6402:5cd:b0:446:5965:f4af with SMTP id n13-20020a05640205cd00b004465965f4afmr29444178edx.12.1662049620117; Thu, 01 Sep 2022 09:27:00 -0700 (PDT) Received: from osoxes.fritz.box (p200300faaf0bb2009c4947838afc41b6.dip0.t-ipconnect.de. [2003:fa:af0b:b200:9c49:4783:8afc:41b6]) by smtp.gmail.com with ESMTPSA id p6-20020aa7d306000000b00447c0dcbb99sm1587672edq.83.2022.09.01.09.26.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Sep 2022 09:26:59 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Her?= =?utf-8?q?v=C3=A9_Poussineau?= , Aurelien Jarno , Paolo Bonzini , Eduardo Habkost , Richard Henderson , Jiaxun Yang , Ani Sinha , Igor Mammedov , Marcel Apfelbaum , "Michael S. Tsirkin" , Bernhard Beschow Subject: [PATCH 13/42] hw/isa/piix3: Add size constraints to rcr_ops Date: Thu, 1 Sep 2022 18:25:44 +0200 Message-Id: <20220901162613.6939-14-shentey@gmail.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220901162613.6939-1-shentey@gmail.com> References: <20220901162613.6939-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52d; envelope-from=shentey@gmail.com; helo=mail-ed1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" According to the PIIX3 datasheet, the reset control register is one byte in size. Moreover, PIIX4 has it, so add it to PIIX3 as well. Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daudé --- hw/isa/piix3.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index b54ff1c948..c8c2dd6048 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -290,7 +290,11 @@ static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len) static const MemoryRegionOps rcr_ops = { .read = rcr_read, .write = rcr_write, - .endianness = DEVICE_LITTLE_ENDIAN + .endianness = DEVICE_LITTLE_ENDIAN, + .impl = { + .min_access_size = 1, + .max_access_size = 1, + }, }; static void pci_piix3_realize(PCIDevice *dev, Error **errp) From patchwork Thu Sep 1 16:25:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 12962923 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B7012ECAAD3 for ; Thu, 1 Sep 2022 16:42:49 +0000 (UTC) Received: from localhost ([::1]:42856 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oTnHE-0006RT-MI for qemu-devel@archiver.kernel.org; Thu, 01 Sep 2022 12:42:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53534) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oTn20-0001v8-G6 for qemu-devel@nongnu.org; Thu, 01 Sep 2022 12:27:07 -0400 Received: from mail-ej1-x629.google.com ([2a00:1450:4864:20::629]:34582) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oTn1x-0001Sk-SS for qemu-devel@nongnu.org; Thu, 01 Sep 2022 12:27:04 -0400 Received: by mail-ej1-x629.google.com with SMTP id y3so35860461ejc.1 for ; Thu, 01 Sep 2022 09:27:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=bCZYZWD3Kd3XMd5O2nNXe28bh4cYB+1rKUIfZeHrag8=; b=npas1mwmoEMnI/XueUoXBwuDTiPv0flL71XBeo2ie6fN1Pd/4A2BXnZElvPRbS/Mvj Vl+72DqRxXRM8xKqCsf6aU/pSr1X61J2ZbSbvd89z+Admta3OXRh2mYK3mFn0cdSOSdz zNLw7et4MLSgdAouSdFD6u6T8gWiO+J6QcQhbjpTtigskYuNS9oBnomswCjj05Anc3G8 qqd380cfImpeZ8UMCQs/3NQizBSBkAhggfgqNoe9Ol90lybJp8n6xeqFzSaDp0xpkOnS Mr/m+35ZP99S7y+QNRuFrFR9QhHDGqaAPpfKptdjIsRLX/L20EaikEPm54Ambn6NkRrZ ht+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=bCZYZWD3Kd3XMd5O2nNXe28bh4cYB+1rKUIfZeHrag8=; b=L07IhXOn+HFMt3QrH3hW4OJd6qvQ9vE1Kea8CZEBlz8h1LggdbMEjFnczD8sn8C6yj xlrLotY9nRJq5AWxobzO2vYz0mGldf5TR27BJcu0cr++Bp89CvB2boa29SaZBw5oVM4w Nh/coJm7HQ771rsr66mukaXHKRGq/cEkgZhzxYcEqHc1bz0hfBLZxnJC+tEGh+jIE/34 FJT6OpkDVYYYeo3h/bdgUGR0WsbYbSH0oyOq1PzA7CZVHAuK3zWZIsBuGJJ3pouj8EeH bz3WMnSc14xGcCT4I1EwdIjzw0jJqpVp1NZgV5LAcfn3NBYfYh3CZChe5kdxhlcu7hIw jgPA== X-Gm-Message-State: ACgBeo3AQIPIwIpuf7D7vd5fLvfJOzMjvfzbnMsq58NN4h/v0qlTIUMb Mt8IwTPd71rDStw6Se2ggDR54l/7g+Q= X-Google-Smtp-Source: AA6agR7tvMKBeEKWe7A2TJ+FHGUD+ggzRLKsqxif/mmsFY8tB5Pw8PTZ5hvSJtLoFJbCCZbSeq1toA== X-Received: by 2002:a17:907:2d20:b0:741:a251:1f10 with SMTP id gs32-20020a1709072d2000b00741a2511f10mr11867640ejc.400.1662049621018; Thu, 01 Sep 2022 09:27:01 -0700 (PDT) Received: from osoxes.fritz.box (p200300faaf0bb2009c4947838afc41b6.dip0.t-ipconnect.de. [2003:fa:af0b:b200:9c49:4783:8afc:41b6]) by smtp.gmail.com with ESMTPSA id p6-20020aa7d306000000b00447c0dcbb99sm1587672edq.83.2022.09.01.09.27.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Sep 2022 09:27:00 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Her?= =?utf-8?q?v=C3=A9_Poussineau?= , Aurelien Jarno , Paolo Bonzini , Eduardo Habkost , Richard Henderson , Jiaxun Yang , Ani Sinha , Igor Mammedov , Marcel Apfelbaum , "Michael S. Tsirkin" , Bernhard Beschow Subject: [PATCH 14/42] hw/isa/piix3: Modernize reset handling Date: Thu, 1 Sep 2022 18:25:45 +0200 Message-Id: <20220901162613.6939-15-shentey@gmail.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220901162613.6939-1-shentey@gmail.com> References: <20220901162613.6939-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::629; envelope-from=shentey@gmail.com; helo=mail-ej1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Rather than registering the reset handler via a function which appends the handler to a global list, prefer to implement it as a virtual method - PIIX4 does the same already. Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daudé --- hw/isa/piix3.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index c8c2dd6048..0350f70706 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -31,7 +31,6 @@ #include "hw/qdev-properties.h" #include "hw/isa/isa.h" #include "hw/xen/xen.h" -#include "sysemu/reset.h" #include "sysemu/runstate.h" #include "migration/vmstate.h" #include "hw/acpi/acpi_aml_interface.h" @@ -156,9 +155,9 @@ static void piix3_write_config_xen(PCIDevice *dev, piix3_write_config(dev, address, val, len); } -static void piix3_reset(void *opaque) +static void piix3_reset(DeviceState *dev) { - PIIX3State *d = opaque; + PIIX3State *d = PIIX3_PCI_DEVICE(dev); uint8_t *pci_conf = d->dev.config; pci_conf[0x04] = 0x07; /* master, memory and I/O */ @@ -321,8 +320,6 @@ static void pci_piix3_realize(PCIDevice *dev, Error **errp) memory_region_add_subregion_overlap(pci_address_space_io(dev), PIIX_RCR_IOPORT, &d->rcr_mem, 1); - qemu_register_reset(piix3_reset, d); - i8257_dma_init(isa_bus, 0); /* RTC */ @@ -397,6 +394,7 @@ static void pci_piix3_class_init(ObjectClass *klass, void *data) PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); AcpiDevAmlIfClass *adevc = ACPI_DEV_AML_IF_CLASS(klass); + dc->reset = piix3_reset; dc->desc = "ISA bridge"; dc->vmsd = &vmstate_piix3; dc->hotpluggable = false; From patchwork Thu Sep 1 16:25:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 12962937 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 60031ECAAD3 for ; Thu, 1 Sep 2022 16:55:47 +0000 (UTC) Received: from localhost ([::1]:56240 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oTnTl-0001Gs-G9 for qemu-devel@archiver.kernel.org; Thu, 01 Sep 2022 12:55:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37788) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oTn2B-00022l-KR for qemu-devel@nongnu.org; Thu, 01 Sep 2022 12:27:15 -0400 Received: from mail-ed1-x52c.google.com ([2a00:1450:4864:20::52c]:43638) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oTn1z-0001Vo-ET for qemu-devel@nongnu.org; Thu, 01 Sep 2022 12:27:04 -0400 Received: by mail-ed1-x52c.google.com with SMTP id c59so17069584edf.10 for ; Thu, 01 Sep 2022 09:27:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=Tq7c8yKqxSyAFEmOm4dcRmVPkGIjGIdrC1sBrJkCEEI=; b=CVSiw0JQLzw3T+OHlUhrC7lQuIuFEw4lwAspkjitxVs0qdqE6GgQ2CMqR3tA4tUx5y SaSJYiI3CA9dNMX2cgvSQIHWi4bcsvxTCJcIgZw8AFyGpGxQ7smwgHSNMw0o07aUOI3v M7obzpTPWVv7hBy5jNHIrFO3RVMlSJoS5YEvNOhQtX6I7q3JZ+1UhCdtIuOkImF5gf9Z O5kjwVc+qtjvTClaeGVqnzPWDLa63O+Cu4nTmSoZSsqkSZEShvdZhPjQndBvQZaZ1dlB 8nTWSKvLH2RTo/ETDPfMjQ4lz4En9soVXsfqTkBG5H9/3xD1MGxDSF+6BvNr4qwkXLtE /tDw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=Tq7c8yKqxSyAFEmOm4dcRmVPkGIjGIdrC1sBrJkCEEI=; b=JvYfJDHHKL6gIWxXq7fy7GF7pyzrB6BYseqBJSI/KCuNeloGqyDi3IY+5pDrhp83CI 6ECLy+X0Vt2+td9tGNS4o3/B4og4nX0QGBV2BHxpRu0ysv9JXikxJItGcsepiQ/BHGrb SKeg/Qpy6xY0Vv6g/rA2Rjsyr+18tZl/EGQusYSDtcI3GN/NaslJyE6eEiZYzgBGBbea rhkGXbvOWLnBNvq0WN88dEUmpjBNUzdoKsSIF/pMEg8QhRhhhgMawKy3sCpYL4hqxbkg t1mTViHGa2YwD9oKCqpAeqhZGny4HzsyafATjo8VHIelriREXsXkmRTG6tYvpqm9aB9k hA1w== X-Gm-Message-State: ACgBeo34kSepj83He67XiCMZEQoKAg6I5vK+Dv98x1gydRJTQ9CTYrPC gaM16NzxpMg5bVhU/j71lBm//6lDde4= X-Google-Smtp-Source: AA6agR5uFc3bocwDDeQN3R4b2nQ0kA42NWZsWwLrhO6AlKR/6l1zD6DdLmak9RhiZrXpyASczdLeZw== X-Received: by 2002:a05:6402:e96:b0:443:a086:e3e8 with SMTP id h22-20020a0564020e9600b00443a086e3e8mr30216722eda.330.1662049621964; Thu, 01 Sep 2022 09:27:01 -0700 (PDT) Received: from osoxes.fritz.box (p200300faaf0bb2009c4947838afc41b6.dip0.t-ipconnect.de. [2003:fa:af0b:b200:9c49:4783:8afc:41b6]) by smtp.gmail.com with ESMTPSA id p6-20020aa7d306000000b00447c0dcbb99sm1587672edq.83.2022.09.01.09.27.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Sep 2022 09:27:01 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Her?= =?utf-8?q?v=C3=A9_Poussineau?= , Aurelien Jarno , Paolo Bonzini , Eduardo Habkost , Richard Henderson , Jiaxun Yang , Ani Sinha , Igor Mammedov , Marcel Apfelbaum , "Michael S. Tsirkin" , Bernhard Beschow Subject: [PATCH 15/42] hw/isa/piix3: Prefer pci_address_space() over get_system_memory() Date: Thu, 1 Sep 2022 18:25:46 +0200 Message-Id: <20220901162613.6939-16-shentey@gmail.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220901162613.6939-1-shentey@gmail.com> References: <20220901162613.6939-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52c; envelope-from=shentey@gmail.com; helo=mail-ed1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" get_system_memory() accesses global state while pci_address_space() uses whatever has been passed to the device instance, so avoid the global. Moreover, PIIX4 uses pci_address_space() here as well. Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daudé --- hw/isa/piix3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index 0350f70706..f8fcd47e24 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -302,7 +302,7 @@ static void pci_piix3_realize(PCIDevice *dev, Error **errp) PCIBus *pci_bus = pci_get_bus(dev); ISABus *isa_bus; - isa_bus = isa_bus_new(DEVICE(d), get_system_memory(), + isa_bus = isa_bus_new(DEVICE(d), pci_address_space(dev), pci_address_space_io(dev), errp); if (!isa_bus) { return; From patchwork Thu Sep 1 16:25:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 12962927 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 58661ECAAD1 for ; Thu, 1 Sep 2022 16:46:13 +0000 (UTC) Received: from localhost ([::1]:36596 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oTnKW-0003dE-DI for qemu-devel@archiver.kernel.org; Thu, 01 Sep 2022 12:46:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37786) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oTn2B-00022f-IK for qemu-devel@nongnu.org; Thu, 01 Sep 2022 12:27:15 -0400 Received: from mail-ed1-x535.google.com ([2a00:1450:4864:20::535]:40941) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oTn1z-0001Um-R4 for qemu-devel@nongnu.org; Thu, 01 Sep 2022 12:27:05 -0400 Received: by mail-ed1-x535.google.com with SMTP id m1so23309632edb.7 for ; Thu, 01 Sep 2022 09:27:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=xpOEupceP6ggkWs0es2939NeRGz3LaBkqUTHnvoPK/k=; b=CoDqNwY7PXjfrG63Sl60x5vVn67zV2doOM6JAs/Jx/hrhHlOMG65Wsp6htSS6ftaDY kKDRdUdiOAPM+PIY2Bz36l+U/MAs3XqTsosegJS0M31b1ZHNIymzD1Q6hzRd3MZVRFAq koSAzm7T0/0iYCGVxbsNFR/VSy8viUgly+/4vWWuMylDefLDAL7B5k84ZJ4E2IV5jPdV c2EOc/mgrFUNMRfGzCDVe3BtTzE2hqyUis9fiEVhMwLsfQaBYNje/rz2MEp2LZd4GQ5s HsWx4ZEWYGEsKKTzAjEAYm6V0CA5Q86m2dvzX7SnwHGHYI7VdczWOc5wg/vEMOZ0KBHE 51CA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=xpOEupceP6ggkWs0es2939NeRGz3LaBkqUTHnvoPK/k=; b=Wls+LWyb+51dRacmEsV8+9Ks7QdtD/2QyUMXFC911izYiUMC1rxHnXMsEImtSHO/FU WiKBGZL3PqMaJ0ytui6PnvxG1vFHKh0chibOd0SVHpNfoA4ExRPyyOKkZkkH4oodDA9U 1P05QQfMPhJRQxfKIR/YQtuDyx6kbwkyOIEBJgIbGWODXPklc5vpSpOw6DF42jViITn+ Oxjo55H9ed9XRFLXGLNYQLn9OD6yBudlcMZ21oV0h4SVWXjPWmDXbAnMXJJRtAyNtbjS iyKktVJdRhMSiOzST636rIhLJG1KPeZK5Nk1HvmTxvwTHjVOXPtDorzfxXlB5LIU3LiG XUiw== X-Gm-Message-State: ACgBeo2sAS1HIP3gygtjU+gE47YoWt5SD3S/5fFO+K+lx7S5LymVCpEW UI/NidhwW3TmjXR5F+Icrv2rA4UN85U= X-Google-Smtp-Source: AA6agR4Wd16j0YaawYKMnLtoCEDeyTvZ/6+6p44xA8R31D7v3ycHAWt/j+gNZBSxCFQ/lCvfRisd7g== X-Received: by 2002:a05:6402:1ccb:b0:446:4346:8597 with SMTP id ds11-20020a0564021ccb00b0044643468597mr29048053edb.177.1662049622907; Thu, 01 Sep 2022 09:27:02 -0700 (PDT) Received: from osoxes.fritz.box (p200300faaf0bb2009c4947838afc41b6.dip0.t-ipconnect.de. [2003:fa:af0b:b200:9c49:4783:8afc:41b6]) by smtp.gmail.com with ESMTPSA id p6-20020aa7d306000000b00447c0dcbb99sm1587672edq.83.2022.09.01.09.27.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Sep 2022 09:27:02 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Her?= =?utf-8?q?v=C3=A9_Poussineau?= , Aurelien Jarno , Paolo Bonzini , Eduardo Habkost , Richard Henderson , Jiaxun Yang , Ani Sinha , Igor Mammedov , Marcel Apfelbaum , "Michael S. Tsirkin" , Bernhard Beschow Subject: [PATCH 16/42] hw/isa/piix3: Allow board to provide PCI interrupt routes Date: Thu, 1 Sep 2022 18:25:47 +0200 Message-Id: <20220901162613.6939-17-shentey@gmail.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220901162613.6939-1-shentey@gmail.com> References: <20220901162613.6939-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::535; envelope-from=shentey@gmail.com; helo=mail-ed1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" PIIX3 initializes the PIRQx route control registers to the default values as described in the 82371AB PCI-TO-ISA/IDE XCELERATOR (PIIX4) April 1997 manual. PIIX4, however, initializes the routes according to the Malta™ User’s Manual, ch 6.6, which are IRQs 10 and 11. In order to allow the reset methods to be consolidated, allow board code to specify the routes. Signed-off-by: Bernhard Beschow --- hw/isa/piix3.c | 12 ++++++++---- include/hw/southbridge/piix.h | 1 + 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index f8fcd47e24..a4a5f33d6e 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -167,10 +167,10 @@ static void piix3_reset(DeviceState *dev) pci_conf[0x4c] = 0x4d; pci_conf[0x4e] = 0x03; pci_conf[0x4f] = 0x00; - pci_conf[0x60] = 0x80; - pci_conf[0x61] = 0x80; - pci_conf[0x62] = 0x80; - pci_conf[0x63] = 0x80; + pci_conf[PIIX_PIRQCA] = d->pci_irq_reset_mappings[0]; + pci_conf[PIIX_PIRQCB] = d->pci_irq_reset_mappings[1]; + pci_conf[PIIX_PIRQCC] = d->pci_irq_reset_mappings[2]; + pci_conf[PIIX_PIRQCD] = d->pci_irq_reset_mappings[3]; pci_conf[0x69] = 0x02; pci_conf[0x70] = 0x80; pci_conf[0x76] = 0x0c; @@ -382,6 +382,10 @@ static void pci_piix3_init(Object *obj) static Property pci_piix3_props[] = { DEFINE_PROP_UINT32("smb_io_base", PIIX3State, smb_io_base, 0), + DEFINE_PROP_UINT8("pirqa", PIIX3State, pci_irq_reset_mappings[0], 0x80), + DEFINE_PROP_UINT8("pirqb", PIIX3State, pci_irq_reset_mappings[1], 0x80), + DEFINE_PROP_UINT8("pirqc", PIIX3State, pci_irq_reset_mappings[2], 0x80), + DEFINE_PROP_UINT8("pirqd", PIIX3State, pci_irq_reset_mappings[3], 0x80), DEFINE_PROP_BOOL("has-acpi", PIIX3State, has_acpi, true), DEFINE_PROP_BOOL("has-usb", PIIX3State, has_usb, true), DEFINE_PROP_BOOL("smm-enabled", PIIX3State, smm_enabled, false), diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index 1f22eb1444..df3e0084c5 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -54,6 +54,7 @@ struct PIIXState { /* This member isn't used. Just for save/load compatibility */ int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS]; + uint8_t pci_irq_reset_mappings[PIIX_NUM_PIRQS]; ISAPICState pic; RTCState rtc; From patchwork Thu Sep 1 16:25:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 12962932 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9ACA1ECAAD1 for ; Thu, 1 Sep 2022 16:52:16 +0000 (UTC) Received: from localhost ([::1]:46890 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oTnQN-0001Mn-N0 for qemu-devel@archiver.kernel.org; Thu, 01 Sep 2022 12:52:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44720) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oTn2E-000273-0U for qemu-devel@nongnu.org; Thu, 01 Sep 2022 12:27:18 -0400 Received: from mail-ej1-x62c.google.com ([2a00:1450:4864:20::62c]:36352) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oTn2B-0001WK-7X for qemu-devel@nongnu.org; Thu, 01 Sep 2022 12:27:17 -0400 Received: by mail-ej1-x62c.google.com with SMTP id h5so24263079ejb.3 for ; Thu, 01 Sep 2022 09:27:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=aEiXff7OiFXrmi8L5xjrdBt3NWxVbOQq4p04MAx7S14=; b=eNaF7sVVpjzebv4wNeYqtT54M+VxUm9kFcpisYANACYp1S/fq4rRvmuZE1RTl+P8YJ lbe+r++FLSO4WuGTsXIULCnDVVdidQCws4ut9FMo5O3+fQENGTtyWlTZ9vqODIPja9Jd 8vw9JZ3Zgc8eqmw85W8FrVwgT/vBB3e1uFkrTke2BYdxw/CMWj7oOi1sA03bTiliqNEW Irc/PcYKNPY+kc+kMdHzR4Lf2NUvJLI+dxZOHZrhDj8yEBOAomsG57P7kKKRzlHHWd4U ZrROdS1kYn7oWgMkokq0GPTdoL7IVnUZt+iuFm6rG2JU4FLJb+aTXesuO2b1YeiHldjY P12w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=aEiXff7OiFXrmi8L5xjrdBt3NWxVbOQq4p04MAx7S14=; b=5b+PFwNdFyEfSTQIfUMZZILqvryICpuCU6XMcpuQIH3EqFmfXdn9HLS94TqzVrDAlM kNfTKiiDa5NfkXr3/iMOEZX7NnweG+xGfFgMcfMThp/JXPSnEm+yGn2R3Op3+5hlOFrZ N2ORmRcAPafOLxDQqxIRl6+JtM25+UUKozmyUzHvVabVoyEaUu1LLfY2OFhj4rV7fJsw lXSt3bUkE/r3Z8HZ1A5UlbS7ci/u6XdQhyAMT+NjuR+jZ72YQ0ZNGIyt9Cag4v8XRIIQ imhEozKff9sY/1r+EqIJn8xmLj0nu47kwpngP8kcG6ZUoyq83YPim0f44XNO7jX3Sx/v Cr7Q== X-Gm-Message-State: ACgBeo1USIukoRdoqphU7BTY18h7yD7uABkmukDBh/nqDk+uKticiYVU urwWyHy5/wQnZ6fSn0sr2VUGzdADBuo= X-Google-Smtp-Source: AA6agR4KxDg2X4gR6JDn1wTARgrmMK65buDEo/8kpjA0pHxSiSUx/awH5Y92hzhV67JmWJL4ukCC8A== X-Received: by 2002:a17:907:7fac:b0:741:4247:d856 with SMTP id qk44-20020a1709077fac00b007414247d856mr17782242ejc.565.1662049623761; Thu, 01 Sep 2022 09:27:03 -0700 (PDT) Received: from osoxes.fritz.box (p200300faaf0bb2009c4947838afc41b6.dip0.t-ipconnect.de. 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Tsirkin" , Bernhard Beschow Subject: [PATCH 17/42] hw/isa/piix3: Resolve redundant PIIX_NUM_PIC_IRQS Date: Thu, 1 Sep 2022 18:25:48 +0200 Message-Id: <20220901162613.6939-18-shentey@gmail.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220901162613.6939-1-shentey@gmail.com> References: <20220901162613.6939-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62c; envelope-from=shentey@gmail.com; helo=mail-ej1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" PIIX_NUM_PIC_IRQS is assumed to be the same as ISA_NUM_IRQS, otherwise inconsistencies can occur. Signed-off-by: Bernhard Beschow --- hw/isa/piix3.c | 8 ++++---- include/hw/southbridge/piix.h | 5 ++--- 2 files changed, 6 insertions(+), 7 deletions(-) diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index a4a5f33d6e..ae1df8e73e 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -51,7 +51,7 @@ static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level) uint64_t mask; pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq]; - if (pic_irq >= PIIX_NUM_PIC_IRQS) { + if (pic_irq >= ISA_NUM_IRQS) { return; } @@ -65,7 +65,7 @@ static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level) int pic_irq; pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq]; - if (pic_irq >= PIIX_NUM_PIC_IRQS) { + if (pic_irq >= ISA_NUM_IRQS) { return; } @@ -97,7 +97,7 @@ static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin) int irq = piix3->dev.config[PIIX_PIRQCA + pin]; PCIINTxRoute route; - if (irq < PIIX_NUM_PIC_IRQS) { + if (irq < ISA_NUM_IRQS) { route.mode = PCI_INTX_ENABLED; route.irq = irq; } else { @@ -129,7 +129,7 @@ static void piix3_write_config(PCIDevice *dev, pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix3->dev)); piix3_update_irq_levels(piix3); - for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) { + for (pic_irq = 0; pic_irq < ISA_NUM_IRQS; pic_irq++) { piix3_set_irq_pic(piix3, pic_irq); } } diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index df3e0084c5..ae3b49fe93 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -32,7 +32,6 @@ */ #define PIIX_RCR_IOPORT 0xcf9 -#define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */ #define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */ struct PIIXState { @@ -44,10 +43,10 @@ struct PIIXState { * So one PIC level is tracked by PIIX_NUM_PIRQS bits. * * PIRQ is mapped to PIC pins, we track it by - * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with + * PIIX_NUM_PIRQS * ISA_NUM_IRQS = 64 bits with * pic_irq * PIIX_NUM_PIRQS + pirq */ -#if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64 +#if ISA_NUM_IRQS * PIIX_NUM_PIRQS > 64 #error "unable to encode pic state in 64bit in pic_levels." #endif uint64_t pic_levels; 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[2003:fa:af0b:b200:9c49:4783:8afc:41b6]) by smtp.gmail.com with ESMTPSA id p6-20020aa7d306000000b00447c0dcbb99sm1587672edq.83.2022.09.01.09.27.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Sep 2022 09:27:04 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Her?= =?utf-8?q?v=C3=A9_Poussineau?= , Aurelien Jarno , Paolo Bonzini , Eduardo Habkost , Richard Henderson , Jiaxun Yang , Ani Sinha , Igor Mammedov , Marcel Apfelbaum , "Michael S. Tsirkin" , Bernhard Beschow Subject: [PATCH 18/42] hw/isa/piix3: Rename pci_piix3_props for sharing with PIIX4 Date: Thu, 1 Sep 2022 18:25:49 +0200 Message-Id: <20220901162613.6939-19-shentey@gmail.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220901162613.6939-1-shentey@gmail.com> References: <20220901162613.6939-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62e; envelope-from=shentey@gmail.com; helo=mail-ej1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Bernhard Beschow --- hw/isa/piix3.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index ae1df8e73e..cb3fef7654 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -380,7 +380,7 @@ static void pci_piix3_init(Object *obj) object_initialize_child(obj, "ide", &d->ide, "piix3-ide"); } -static Property pci_piix3_props[] = { +static Property pci_piix_props[] = { DEFINE_PROP_UINT32("smb_io_base", PIIX3State, smb_io_base, 0), DEFINE_PROP_UINT8("pirqa", PIIX3State, pci_irq_reset_mappings[0], 0x80), DEFINE_PROP_UINT8("pirqb", PIIX3State, pci_irq_reset_mappings[1], 0x80), @@ -411,7 +411,7 @@ static void pci_piix3_class_init(ObjectClass *klass, void *data) * pc_piix.c's pc_init1() */ dc->user_creatable = false; - device_class_set_props(dc, pci_piix3_props); + device_class_set_props(dc, pci_piix_props); adevc->build_dev_aml = build_pci_isa_aml; } From patchwork Thu Sep 1 16:25:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 12962928 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 338A8ECAAD1 for ; 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[2003:fa:af0b:b200:9c49:4783:8afc:41b6]) by smtp.gmail.com with ESMTPSA id p6-20020aa7d306000000b00447c0dcbb99sm1587672edq.83.2022.09.01.09.27.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Sep 2022 09:27:05 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Her?= =?utf-8?q?v=C3=A9_Poussineau?= , Aurelien Jarno , Paolo Bonzini , Eduardo Habkost , Richard Henderson , Jiaxun Yang , Ani Sinha , Igor Mammedov , Marcel Apfelbaum , "Michael S. Tsirkin" , Bernhard Beschow Subject: [PATCH 19/42] hw/isa/piix3: Rename piix3_reset() for sharing with PIIX4 Date: Thu, 1 Sep 2022 18:25:50 +0200 Message-Id: <20220901162613.6939-20-shentey@gmail.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220901162613.6939-1-shentey@gmail.com> References: <20220901162613.6939-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::630; envelope-from=shentey@gmail.com; helo=mail-ej1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Bernhard Beschow --- hw/isa/piix3.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index cb3fef7654..d027c5b61e 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -155,7 +155,7 @@ static void piix3_write_config_xen(PCIDevice *dev, piix3_write_config(dev, address, val, len); } -static void piix3_reset(DeviceState *dev) +static void piix_reset(DeviceState *dev) { PIIX3State *d = PIIX3_PCI_DEVICE(dev); uint8_t *pci_conf = d->dev.config; @@ -398,7 +398,7 @@ static void pci_piix3_class_init(ObjectClass *klass, void *data) PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); AcpiDevAmlIfClass *adevc = ACPI_DEV_AML_IF_CLASS(klass); - dc->reset = piix3_reset; + dc->reset = piix_reset; dc->desc = "ISA bridge"; dc->vmsd = &vmstate_piix3; dc->hotpluggable = false; From patchwork Thu Sep 1 16:25:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 12962912 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 28854ECAAD3 for ; Thu, 1 Sep 2022 16:39:43 +0000 (UTC) Received: from localhost ([::1]:59696 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oTnEE-0008VU-8t for qemu-devel@archiver.kernel.org; Thu, 01 Sep 2022 12:39:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44722) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oTn2F-0002A8-AB for qemu-devel@nongnu.org; Thu, 01 Sep 2022 12:27:19 -0400 Received: from mail-ej1-x62d.google.com ([2a00:1450:4864:20::62d]:39477) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oTn2B-0001VH-7y for qemu-devel@nongnu.org; Thu, 01 Sep 2022 12:27:19 -0400 Received: by mail-ej1-x62d.google.com with SMTP id fy31so35422456ejc.6 for ; Thu, 01 Sep 2022 09:27:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=czze0c+OUMqF2Te1RN6krGNr4VtVef5mDNYvk0Wdy9k=; b=QCi5Cn9qG52n+MZ4v4eft/V+IrvvNkdnIrGf5TOPnd0xchVLLrMaVm7c0YP/p+7CuW +Wsx7i0Eu3amMFtkZKVa/lEAGjP2VZDWMBsATb8YYz7i8yGg5NVKf5fCG33SORFmCNlt walmmzw5RtD876uhwIRtJAxf+z6fo2hjgcTCs3fNSmLlH1DaW9rlPo3A+m3JmR0DEZDi 8XBa6kN2HT4rVwrV5xuL+jgo5lRcBRKEKqph30l1o6CH6h3ZYO6osX29sZBHhuGBMatD dGTEpyfp+U4dOgkZtnuCbUyWG3fVyGGsp452FfosOAg3WMx6JKGV+dGVzVDd7LHPHnnd PqFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=czze0c+OUMqF2Te1RN6krGNr4VtVef5mDNYvk0Wdy9k=; b=y8WLyVKOzrMmLnmfQ509xsR/0MaplNXuM77UhZ/vlZQjTBjM1S6moRXmXqbh1JTTAq SJI9AKh+ehF71yn8UuNQqo/Gv759uAPjV9TJb3SsFSHv1cq5VoX6WH5u9jJRD+gXtS62 TgpTjo4mgfOn232g/PAM/MnT8rL9UX7c09LKa+ampzAD/HO+GKB/qgSjLykuw4afR62k Ga2rIqPodgon6WUOhWiBU9YnS9FiVZnL3oufYM/4djXE258UbqtEdoPn7GDh0/CtC91v nu0cZySZ1K2lUMpC8okQBLVowpis+AJsIPYlrv0QKxIVA2G8leIypI6yRv0CKskDdhUd 6XYQ== X-Gm-Message-State: ACgBeo3BHdH7ie5XCVFQuiLswvE/EUqdXSANvP/AQfOfROOcoOLLbqcc HPNV2iHeIWGOsgb0k1s8DQTrUTM57f0= X-Google-Smtp-Source: AA6agR5S1GCx3QFGKizAr8ULPGcfcscopdbKfuT/EJx5DElz5NxWxKPnKeKTJtRyfhHTkndGG2zF/w== X-Received: by 2002:a17:907:9706:b0:741:64ca:ae10 with SMTP id jg6-20020a170907970600b0074164caae10mr15746800ejc.364.1662049626506; Thu, 01 Sep 2022 09:27:06 -0700 (PDT) Received: from osoxes.fritz.box (p200300faaf0bb2009c4947838afc41b6.dip0.t-ipconnect.de. [2003:fa:af0b:b200:9c49:4783:8afc:41b6]) by smtp.gmail.com with ESMTPSA id p6-20020aa7d306000000b00447c0dcbb99sm1587672edq.83.2022.09.01.09.27.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Sep 2022 09:27:06 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Her?= =?utf-8?q?v=C3=A9_Poussineau?= , Aurelien Jarno , Paolo Bonzini , Eduardo Habkost , Richard Henderson , Jiaxun Yang , Ani Sinha , Igor Mammedov , Marcel Apfelbaum , "Michael S. Tsirkin" , Bernhard Beschow Subject: [PATCH 20/42] hw/isa/piix3: Prefix pci_slot_get_pirq() with "piix3_" Date: Thu, 1 Sep 2022 18:25:51 +0200 Message-Id: <20220901162613.6939-21-shentey@gmail.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220901162613.6939-1-shentey@gmail.com> References: <20220901162613.6939-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62d; envelope-from=shentey@gmail.com; helo=mail-ej1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The additional prefix aligns the function name with both other piix3-internal functions as well as QEMU conventions. Furthermore, it will help to distinguish the function from its PIIX4 counterpart once merged. Signed-off-by: Bernhard Beschow --- hw/isa/piix3.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index d027c5b61e..e5772475be 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -84,7 +84,7 @@ static void piix3_set_irq(void *opaque, int pirq, int level) * Return the global irq number corresponding to a given device irq * pin. We could also use the bus number to have a more precise mapping. */ -static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx) +static int piix3_pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx) { int slot_addend; slot_addend = PCI_SLOT(pci_dev->devfn) - 1; @@ -440,7 +440,7 @@ static void piix3_realize(PCIDevice *dev, Error **errp) return; } - pci_bus_irqs(pci_bus, piix3_set_irq, pci_slot_get_pirq, + pci_bus_irqs(pci_bus, piix3_set_irq, piix3_pci_slot_get_pirq, piix3, PIIX_NUM_PIRQS); pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq); } From patchwork Thu Sep 1 16:25:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 12962946 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4EDB7ECAAD3 for ; Thu, 1 Sep 2022 17:06:04 +0000 (UTC) Received: from localhost ([::1]:47038 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oTndj-0004iT-9r for qemu-devel@archiver.kernel.org; Thu, 01 Sep 2022 13:06:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37932) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oTn2N-0002Jx-Qf for qemu-devel@nongnu.org; Thu, 01 Sep 2022 12:27:28 -0400 Received: from mail-ed1-x536.google.com ([2a00:1450:4864:20::536]:35563) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oTn2C-0001UA-B6 for qemu-devel@nongnu.org; Thu, 01 Sep 2022 12:27:26 -0400 Received: by mail-ed1-x536.google.com with SMTP id y64so11484133ede.2 for ; Thu, 01 Sep 2022 09:27:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=zjno28eeqiJDQD8cSUoofO/ILmkJb7ze4KyDRM4MZ/Y=; b=j3zk57nAu7Rm6jveZX06R1SaXEdc9MrQsoMF3G8Sg3IbnLTZwDthojWRjSf5sKuIrs HQQtOevdbG6Y4R/usAFL0zOsJxEFKxaequOlRNA8ZwoU3759by4sBCbtu3rHMPM30qQI UDQd6I4IXiegcCCfsH09X6VWVR6RuO44WkbSZTzmBHaZSw4tuAy9kWEgN5nFv2bnFx5t XV4xzEPmEiGJmRXnrfB8RTuRDWxSvOBeqzNOXWDD0gk2rvNfs0Frl6XGzRYbEo/1rxCh /5BKMKAHDpe650tuhIlwNA/q3LwweyXupT3JrRDDQQhaS5fOP7ydJhAHrwVn9T7HkBS9 PKUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=zjno28eeqiJDQD8cSUoofO/ILmkJb7ze4KyDRM4MZ/Y=; b=FQg9ssZ20QUUgGxkfloEZaWrBzkg6gcrOaf/aCArTwMEl2DXTJBVfRXppX02O9QoQ4 Yr6jWzAhK+6B84S/Hms7rKfUYiNiPzWgYPEKn3RGVzN9rWJwstheLraxZl4VmtbKkaJS xOCzFD1LIoSLHeUkcjfUITUJNP7ouBKjzliAc/wMFHFnfeqAC0n/OK9GKEaJPQrZSD1h lQO11t4bAODcyAMnnZx9tQ6mBTsucc6nFJu8qQ7i7No1cfptKge4B1rwqDMZ4ZfGflKM 9lwf67+3vMCrT0sN3PYJHzU/J18H7g0TnGouP/v5kqp/1EEYRNs6AYgads3MJofo+gf7 dGlg== X-Gm-Message-State: ACgBeo1J8bccWW/G5qW8mJpgyv6u6y92ulljMMzZToLTsX19NNVg66Hh fN/V0lPFdMZvyMnt7In0gKvexEph4zw= X-Google-Smtp-Source: AA6agR4qpmNTkh+xiAeChmNTAk0qogoAZgG6d2V755Zu6UGzaeI7VoEy1htuRRxT6YTIRxYwdOKTrg== X-Received: by 2002:aa7:d385:0:b0:447:d5ec:d452 with SMTP id x5-20020aa7d385000000b00447d5ecd452mr26040032edq.231.1662049627547; Thu, 01 Sep 2022 09:27:07 -0700 (PDT) Received: from osoxes.fritz.box (p200300faaf0bb2009c4947838afc41b6.dip0.t-ipconnect.de. [2003:fa:af0b:b200:9c49:4783:8afc:41b6]) by smtp.gmail.com with ESMTPSA id p6-20020aa7d306000000b00447c0dcbb99sm1587672edq.83.2022.09.01.09.27.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Sep 2022 09:27:07 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Her?= =?utf-8?q?v=C3=A9_Poussineau?= , Aurelien Jarno , Paolo Bonzini , Eduardo Habkost , Richard Henderson , Jiaxun Yang , Ani Sinha , Igor Mammedov , Marcel Apfelbaum , "Michael S. Tsirkin" , Bernhard Beschow Subject: [PATCH 21/42] hw/isa/piix3: Rename typedef PIIX3State to PIIXState Date: Thu, 1 Sep 2022 18:25:52 +0200 Message-Id: <20220901162613.6939-22-shentey@gmail.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220901162613.6939-1-shentey@gmail.com> References: <20220901162613.6939-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::536; envelope-from=shentey@gmail.com; helo=mail-ed1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" This commit marks the finalization of the PIIX3 preparations to be merged with PIIX4. In particular, PIIXState is prepared to be reused in piix4.c. Signed-off-by: Bernhard Beschow --- hw/isa/piix3.c | 58 +++++++++++++++++------------------ include/hw/southbridge/piix.h | 4 +-- 2 files changed, 31 insertions(+), 31 deletions(-) diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index e5772475be..75705a1fc1 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -37,7 +37,7 @@ #define XEN_PIIX_NUM_PIRQS 128ULL -static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq) +static void piix3_set_irq_pic(PIIXState *piix3, int pic_irq) { qemu_set_irq(piix3->pic.in_irqs[pic_irq], !!(piix3->pic_levels & @@ -45,7 +45,7 @@ static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq) (pic_irq * PIIX_NUM_PIRQS)))); } -static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level) +static void piix3_set_irq_level_internal(PIIXState *piix3, int pirq, int level) { int pic_irq; uint64_t mask; @@ -60,7 +60,7 @@ static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level) piix3->pic_levels |= mask * !!level; } -static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level) +static void piix3_set_irq_level(PIIXState *piix3, int pirq, int level) { int pic_irq; @@ -76,7 +76,7 @@ static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level) static void piix3_set_irq(void *opaque, int pirq, int level) { - PIIX3State *piix3 = opaque; + PIIXState *piix3 = opaque; piix3_set_irq_level(piix3, pirq, level); } @@ -93,7 +93,7 @@ static int piix3_pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx) static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin) { - PIIX3State *piix3 = opaque; + PIIXState *piix3 = opaque; int irq = piix3->dev.config[PIIX_PIRQCA + pin]; PCIINTxRoute route; @@ -108,7 +108,7 @@ static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin) } /* irq routing is changed. so rebuild bitmap */ -static void piix3_update_irq_levels(PIIX3State *piix3) +static void piix3_update_irq_levels(PIIXState *piix3) { PCIBus *bus = pci_get_bus(&piix3->dev); int pirq; @@ -124,7 +124,7 @@ static void piix3_write_config(PCIDevice *dev, { pci_default_write_config(dev, address, val, len); if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) { - PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev); + PIIXState *piix3 = PIIX_PCI_DEVICE(dev); int pic_irq; pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix3->dev)); @@ -157,7 +157,7 @@ static void piix3_write_config_xen(PCIDevice *dev, static void piix_reset(DeviceState *dev) { - PIIX3State *d = PIIX3_PCI_DEVICE(dev); + PIIXState *d = PIIX_PCI_DEVICE(dev); uint8_t *pci_conf = d->dev.config; pci_conf[0x04] = 0x07; /* master, memory and I/O */ @@ -198,7 +198,7 @@ static void piix_reset(DeviceState *dev) static int piix3_post_load(void *opaque, int version_id) { - PIIX3State *piix3 = opaque; + PIIXState *piix3 = opaque; int pirq; /* @@ -221,7 +221,7 @@ static int piix3_post_load(void *opaque, int version_id) static int piix3_pre_save(void *opaque) { int i; - PIIX3State *piix3 = opaque; + PIIXState *piix3 = opaque; for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) { piix3->pci_irq_levels_vmstate[i] = @@ -233,7 +233,7 @@ static int piix3_pre_save(void *opaque) static bool piix3_rcr_needed(void *opaque) { - PIIX3State *piix3 = opaque; + PIIXState *piix3 = opaque; return (piix3->rcr != 0); } @@ -244,7 +244,7 @@ static const VMStateDescription vmstate_piix3_rcr = { .minimum_version_id = 1, .needed = piix3_rcr_needed, .fields = (VMStateField[]) { - VMSTATE_UINT8(rcr, PIIX3State), + VMSTATE_UINT8(rcr, PIIXState), VMSTATE_END_OF_LIST() } }; @@ -256,8 +256,8 @@ static const VMStateDescription vmstate_piix3 = { .post_load = piix3_post_load, .pre_save = piix3_pre_save, .fields = (VMStateField[]) { - VMSTATE_PCI_DEVICE(dev, PIIX3State), - VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State, + VMSTATE_PCI_DEVICE(dev, PIIXState), + VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIXState, PIIX_NUM_PIRQS, 3), VMSTATE_END_OF_LIST() }, @@ -270,7 +270,7 @@ static const VMStateDescription vmstate_piix3 = { static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len) { - PIIX3State *d = opaque; + PIIXState *d = opaque; if (val & 4) { qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); @@ -281,7 +281,7 @@ static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len) static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len) { - PIIX3State *d = opaque; + PIIXState *d = opaque; return d->rcr; } @@ -298,7 +298,7 @@ static const MemoryRegionOps rcr_ops = { static void pci_piix3_realize(PCIDevice *dev, Error **errp) { - PIIX3State *d = PIIX3_PCI_DEVICE(dev); + PIIXState *d = PIIX_PCI_DEVICE(dev); PCIBus *pci_bus = pci_get_bus(dev); ISABus *isa_bus; @@ -373,7 +373,7 @@ static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope) static void pci_piix3_init(Object *obj) { - PIIX3State *d = PIIX3_PCI_DEVICE(obj); + PIIXState *d = PIIX_PCI_DEVICE(obj); object_initialize_child(obj, "pic", &d->pic, TYPE_ISA_PIC); object_initialize_child(obj, "rtc", &d->rtc, TYPE_MC146818_RTC); @@ -381,14 +381,14 @@ static void pci_piix3_init(Object *obj) } static Property pci_piix_props[] = { - DEFINE_PROP_UINT32("smb_io_base", PIIX3State, smb_io_base, 0), - DEFINE_PROP_UINT8("pirqa", PIIX3State, pci_irq_reset_mappings[0], 0x80), - DEFINE_PROP_UINT8("pirqb", PIIX3State, pci_irq_reset_mappings[1], 0x80), - DEFINE_PROP_UINT8("pirqc", PIIX3State, pci_irq_reset_mappings[2], 0x80), - DEFINE_PROP_UINT8("pirqd", PIIX3State, pci_irq_reset_mappings[3], 0x80), - DEFINE_PROP_BOOL("has-acpi", PIIX3State, has_acpi, true), - DEFINE_PROP_BOOL("has-usb", PIIX3State, has_usb, true), - DEFINE_PROP_BOOL("smm-enabled", PIIX3State, smm_enabled, false), + DEFINE_PROP_UINT32("smb_io_base", PIIXState, smb_io_base, 0), + DEFINE_PROP_UINT8("pirqa", PIIXState, pci_irq_reset_mappings[0], 0x80), + DEFINE_PROP_UINT8("pirqb", PIIXState, pci_irq_reset_mappings[1], 0x80), + DEFINE_PROP_UINT8("pirqc", PIIXState, pci_irq_reset_mappings[2], 0x80), + DEFINE_PROP_UINT8("pirqd", PIIXState, pci_irq_reset_mappings[3], 0x80), + DEFINE_PROP_BOOL("has-acpi", PIIXState, has_acpi, true), + DEFINE_PROP_BOOL("has-usb", PIIXState, has_usb, true), + DEFINE_PROP_BOOL("smm-enabled", PIIXState, smm_enabled, false), DEFINE_PROP_END_OF_LIST(), }; @@ -418,7 +418,7 @@ static void pci_piix3_class_init(ObjectClass *klass, void *data) static const TypeInfo piix3_pci_type_info = { .name = TYPE_PIIX3_PCI_DEVICE, .parent = TYPE_PCI_DEVICE, - .instance_size = sizeof(PIIX3State), + .instance_size = sizeof(PIIXState), .instance_init = pci_piix3_init, .abstract = true, .class_init = pci_piix3_class_init, @@ -432,7 +432,7 @@ static const TypeInfo piix3_pci_type_info = { static void piix3_realize(PCIDevice *dev, Error **errp) { ERRP_GUARD(); - PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev); + PIIXState *piix3 = PIIX_PCI_DEVICE(dev); PCIBus *pci_bus = pci_get_bus(dev); pci_piix3_realize(dev, errp); @@ -462,7 +462,7 @@ static const TypeInfo piix3_info = { static void piix3_xen_realize(PCIDevice *dev, Error **errp) { ERRP_GUARD(); - PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev); + PIIXState *piix3 = PIIX_PCI_DEVICE(dev); PCIBus *pci_bus = pci_get_bus(dev); pci_piix3_realize(dev, errp); diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index ae3b49fe93..c9fa0f1aa6 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -73,10 +73,10 @@ struct PIIXState { bool has_usb; bool smm_enabled; }; -typedef struct PIIXState PIIX3State; +typedef struct PIIXState PIIXState; #define TYPE_PIIX3_PCI_DEVICE "pci-piix3" -DECLARE_INSTANCE_CHECKER(PIIX3State, PIIX3_PCI_DEVICE, +DECLARE_INSTANCE_CHECKER(PIIXState, PIIX_PCI_DEVICE, TYPE_PIIX3_PCI_DEVICE) #define TYPE_PIIX3_DEVICE "PIIX3" From patchwork Thu Sep 1 16:25:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 12962949 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5B750ECAAD1 for ; Thu, 1 Sep 2022 17:09:58 +0000 (UTC) Received: from localhost ([::1]:58750 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oTnhV-0002Lk-CI for qemu-devel@archiver.kernel.org; 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[2003:fa:af0b:b200:9c49:4783:8afc:41b6]) by smtp.gmail.com with ESMTPSA id p6-20020aa7d306000000b00447c0dcbb99sm1587672edq.83.2022.09.01.09.27.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Sep 2022 09:27:08 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Her?= =?utf-8?q?v=C3=A9_Poussineau?= , Aurelien Jarno , Paolo Bonzini , Eduardo Habkost , Richard Henderson , Jiaxun Yang , Ani Sinha , Igor Mammedov , Marcel Apfelbaum , "Michael S. Tsirkin" , Bernhard Beschow Subject: [PATCH 22/42] hw/mips/malta: Reuse dev variable Date: Thu, 1 Sep 2022 18:25:53 +0200 Message-Id: <20220901162613.6939-23-shentey@gmail.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220901162613.6939-1-shentey@gmail.com> References: <20220901162613.6939-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52e; envelope-from=shentey@gmail.com; helo=mail-ed1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" While at it, move the assignments closer to where they are used. Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daudé --- hw/mips/malta.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 0e932988e0..0ec2ac2eaf 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -1239,7 +1239,6 @@ void mips_malta_init(MachineState *machine) MaltaState *s; PCIDevice *piix4; DeviceState *dev; - DeviceState *pm_dev; s = MIPS_MALTA(qdev_new(TYPE_MIPS_MALTA)); sysbus_realize_and_unref(SYS_BUS_DEVICE(s), &error_fatal); @@ -1405,13 +1404,13 @@ void mips_malta_init(MachineState *machine) TYPE_PIIX4_PCI_DEVICE); dev = DEVICE(piix4); isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0")); - pm_dev = DEVICE(object_resolve_path_component(OBJECT(dev), "pm")); - smbus = I2C_BUS(qdev_get_child_bus(pm_dev, "i2c")); /* Interrupt controller */ qdev_connect_gpio_out_named(dev, "intr", 0, i8259_irq); /* generate SPD EEPROM data */ + dev = DEVICE(object_resolve_path_component(OBJECT(piix4), "pm")); + smbus = I2C_BUS(qdev_get_child_bus(dev, "i2c")); generate_eeprom_spd(&smbus_eeprom_buf[0 * 256], ram_size); generate_eeprom_serial(&smbus_eeprom_buf[6 * 256]); smbus_eeprom_init(smbus, 8, smbus_eeprom_buf, smbus_eeprom_size); From patchwork Thu Sep 1 16:25:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 12962921 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F3A8BECAAD3 for ; Thu, 1 Sep 2022 16:42:41 +0000 (UTC) Received: from localhost ([::1]:40908 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oTnH6-0005wd-RE for qemu-devel@archiver.kernel.org; Thu, 01 Sep 2022 12:42:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44728) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oTn2G-0002DT-BH for qemu-devel@nongnu.org; Thu, 01 Sep 2022 12:27:20 -0400 Received: from mail-ed1-x52d.google.com ([2a00:1450:4864:20::52d]:41863) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oTn2C-0001Wg-BN for qemu-devel@nongnu.org; Thu, 01 Sep 2022 12:27:19 -0400 Received: by mail-ed1-x52d.google.com with SMTP id r4so23271458edi.8 for ; Thu, 01 Sep 2022 09:27:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=VkU8fXh1qvcuUfet/WByjtVq3rEvXiBhLPE3cdxFGIg=; b=RJG48bhgHgwDYqetfADTk0RXmdQOALXEBmLVyzDV+vGLsR453tSiVCfNUuuGAV3v2U hFBWzXlEwsf0SMbIRbWLp3vH9+JMxdLhnT5VKAsLwnYrKaM8HCZ4d47OWUahXwlWQ7CO Z4U89yyAzvqTLBb/WeVWqOoRvp+WIQeRvH3vgZ6/Is9W390mwTXBcKvVHUW3iYIME1HR 4WJLk6p/DsIUK/55kHGYC8si0S3bRpvI/aLDz3xKxh33nSCkJhyx0u4WVe5NLM/g1G41 rdeysEMeGph7qMKMuZ4BEU9wwVMHTfW2qqFM/wzDU+dUQHU8qFzkvgymEutFHjgzbQef UWXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=VkU8fXh1qvcuUfet/WByjtVq3rEvXiBhLPE3cdxFGIg=; b=U7poLRMIzso+b3qB/3Rn5bHOv2sQZ4Ot7PMKJcNRujFWCcwfFHXtxcCYpJgFTuHZ3E MKIaicuD7N2s3YR1uvhuAETMSkR55BXKje9DUvvKHfg0r7d51J85EkP2uuyWnAKgH7Ye 7wJPVZ0KIlyIfNah3O8UGmcVxGOp1kAV2xJPzqy/ElycdNPQobCadSOKVNgol1X8I2pm BDmB2uzXuXspTvNN2vUsms+gEMRZblYhnXXTsEtigfxf1nQwkPqFQdJvYbZNqKVv3axJ ToP3d7eIlA1jyydehnHHkisjyJ8Jg/HGoZ3xepLenUwwlROcHdiKkOyWujLgNLuXHzng ZknQ== X-Gm-Message-State: ACgBeo0SPKp6BEy1XRqfEJznwOZra1lIW0L7859rqbZ84JjiSpFWVm+o ohxpboNKiPnUSOElLUG1d/32vsnpRYc= X-Google-Smtp-Source: AA6agR5GglRpqbtcE/EdwFbnx/4k0SDYcndOE+L8TmtkZak7iwD28KNylVbirUyBUw0Ah4/GYulEAQ== X-Received: by 2002:aa7:ca46:0:b0:447:af0a:be68 with SMTP id j6-20020aa7ca46000000b00447af0abe68mr29183843edt.327.1662049629452; Thu, 01 Sep 2022 09:27:09 -0700 (PDT) Received: from osoxes.fritz.box (p200300faaf0bb2009c4947838afc41b6.dip0.t-ipconnect.de. [2003:fa:af0b:b200:9c49:4783:8afc:41b6]) by smtp.gmail.com with ESMTPSA id p6-20020aa7d306000000b00447c0dcbb99sm1587672edq.83.2022.09.01.09.27.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Sep 2022 09:27:09 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Her?= =?utf-8?q?v=C3=A9_Poussineau?= , Aurelien Jarno , Paolo Bonzini , Eduardo Habkost , Richard Henderson , Jiaxun Yang , Ani Sinha , Igor Mammedov , Marcel Apfelbaum , "Michael S. Tsirkin" , Bernhard Beschow Subject: [PATCH 23/42] meson: Fix dependencies of piix4 southbridge Date: Thu, 1 Sep 2022 18:25:54 +0200 Message-Id: <20220901162613.6939-24-shentey@gmail.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220901162613.6939-1-shentey@gmail.com> References: <20220901162613.6939-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52d; envelope-from=shentey@gmail.com; helo=mail-ed1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Bernhard Beschow --- configs/devices/mips-softmmu/common.mak | 1 - hw/isa/Kconfig | 6 ++++++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/configs/devices/mips-softmmu/common.mak b/configs/devices/mips-softmmu/common.mak index d2202c839e..416161f833 100644 --- a/configs/devices/mips-softmmu/common.mak +++ b/configs/devices/mips-softmmu/common.mak @@ -23,7 +23,6 @@ CONFIG_APM=y CONFIG_I8257=y CONFIG_PIIX4=y CONFIG_IDE_ISA=y -CONFIG_IDE_PIIX=y CONFIG_PFLASH_CFI01=y CONFIG_I8259=y CONFIG_MC146818RTC=y diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig index a021e1cbfc..1aa10f84f2 100644 --- a/hw/isa/Kconfig +++ b/hw/isa/Kconfig @@ -45,7 +45,13 @@ config PIIX4 bool # For historical reasons, SuperIO devices are created in the board # for PIIX4. + select ACPI_PIIX4 + select I8254 + select I8257 + select I8259 + select IDE_PIIX select ISA_BUS + select MC146818RTC select USB_UHCI config VT82C686 From patchwork Thu Sep 1 16:25:55 2022 Content-Type: text/plain; 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[2003:fa:af0b:b200:9c49:4783:8afc:41b6]) by smtp.gmail.com with ESMTPSA id p6-20020aa7d306000000b00447c0dcbb99sm1587672edq.83.2022.09.01.09.27.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Sep 2022 09:27:10 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Her?= =?utf-8?q?v=C3=A9_Poussineau?= , Aurelien Jarno , Paolo Bonzini , Eduardo Habkost , Richard Henderson , Jiaxun Yang , Ani Sinha , Igor Mammedov , Marcel Apfelbaum , "Michael S. Tsirkin" , Bernhard Beschow Subject: [PATCH 24/42] hw/isa/piix4: Add missing initialization Date: Thu, 1 Sep 2022 18:25:55 +0200 Message-Id: <20220901162613.6939-25-shentey@gmail.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220901162613.6939-1-shentey@gmail.com> References: <20220901162613.6939-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::534; envelope-from=shentey@gmail.com; helo=mail-ed1-x534.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" PIIX3 clears its reset control register, so do the same in PIIX4. Signed-off-by: Bernhard Beschow --- hw/isa/piix4.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 15f344dbb7..9e2f7b9b71 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -139,6 +139,8 @@ static void piix4_isa_reset(DeviceState *dev) pci_conf[0xab] = 0x00; pci_conf[0xac] = 0x00; pci_conf[0xae] = 0x00; + + d->rcr = 0; } static int piix4_ide_post_load(void *opaque, int version_id) From patchwork Thu Sep 1 16:25:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 12962948 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2F49CECAAD1 for ; Thu, 1 Sep 2022 17:08:12 +0000 (UTC) Received: from localhost ([::1]:43498 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oTnfm-000880-Ur for qemu-devel@archiver.kernel.org; Thu, 01 Sep 2022 13:08:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37944) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oTn2P-0002Nd-LZ for qemu-devel@nongnu.org; Thu, 01 Sep 2022 12:27:30 -0400 Received: from mail-ed1-x534.google.com ([2a00:1450:4864:20::534]:47069) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oTn2C-0001Wt-BY for qemu-devel@nongnu.org; Thu, 01 Sep 2022 12:27:27 -0400 Received: by mail-ed1-x534.google.com with SMTP id s11so23250080edd.13 for ; Thu, 01 Sep 2022 09:27:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=uB/A2AcNgLaibHCVY7qxQ6GQG2qlNpyMMr8R/rV08D4=; b=Gl5fWumj589GH+l+zGnEMGVYegRiS5LQ6QX15Mrxkn28TaGXiqRtyIyINZ7AJjJbpi mufmVgtJKpqM8mLjaSto7b+CgGQojHZD7CjkPo8TOzLaUS1ktGQN1CmGOj5vlN5aolNi fSGe5zlOor0E9aXHJc8PCC81nGz2YFtrXHHzWeLYyOb+mbBYBhzl0GavZ35VXAOb+eUI yxedSU0U0cqA1+2c3aMw3ao778YLAMN29bV3q+9cjk9jOSOFi66B21hEQz1apufNvGqH oxJRmzfL4QgGG4DzveCtWMGIwQjm1Rz9sCBkFsEJkP/D+woT7+9mw88hshPg/wyAaELE ZcDA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=uB/A2AcNgLaibHCVY7qxQ6GQG2qlNpyMMr8R/rV08D4=; b=Cu5JZnpKxuLTo+hLqPcC/mEuJiz/gjga//iyChuMTJFpImrPiSudv3/hpFLs39NYoh s8gcmr1G1BDWSiykbre7vj8dzvbdw5n5qJ7R4RhprcFs+7Na7hHOpKk0kKq8CNrgNHB2 FHc/JxV1BwaaCoV6BHZQyBYjV0/VE5lUjEE3ddH3FD/jAVDzfl3wBFXmk3omeRntn1FX IFjByBRa83I0xaRFyiGW3Rls7jSAF7r42iDBnikd6R9ueQ8sjxPGIupUVn48nRH22Txj CNtRIbpEkSOPCj6WssCjSawJiSZyDMDNlhY1F6AO/Ch+7H5UEWO3rDOxR9miRNTTkTRR kg7A== X-Gm-Message-State: ACgBeo2FA53+CDzq92iKvo8YgpX65sRQmRr4eAwhsD12GkvFm9yZiybP cLaDLjIie/SuAgSb9vH+RQnHv5s/rOg= X-Google-Smtp-Source: AA6agR6WO6gEz/UjHHtyzKqxHxFlCyznVEGcpz91IHnRBYFgUfgD7IR/lkyZgdUM97dgF/4MIZ4Ufw== X-Received: by 2002:aa7:d78b:0:b0:447:d501:14c8 with SMTP id s11-20020aa7d78b000000b00447d50114c8mr25198384edq.82.1662049631439; Thu, 01 Sep 2022 09:27:11 -0700 (PDT) Received: from osoxes.fritz.box (p200300faaf0bb2009c4947838afc41b6.dip0.t-ipconnect.de. [2003:fa:af0b:b200:9c49:4783:8afc:41b6]) by smtp.gmail.com with ESMTPSA id p6-20020aa7d306000000b00447c0dcbb99sm1587672edq.83.2022.09.01.09.27.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Sep 2022 09:27:11 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Her?= =?utf-8?q?v=C3=A9_Poussineau?= , Aurelien Jarno , Paolo Bonzini , Eduardo Habkost , Richard Henderson , Jiaxun Yang , Ani Sinha , Igor Mammedov , Marcel Apfelbaum , "Michael S. Tsirkin" , Bernhard Beschow Subject: [PATCH 25/42] hw/isa/piix4: Move pci_ide_create_devs() call to board code Date: Thu, 1 Sep 2022 18:25:56 +0200 Message-Id: <20220901162613.6939-26-shentey@gmail.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220901162613.6939-1-shentey@gmail.com> References: <20220901162613.6939-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::534; envelope-from=shentey@gmail.com; helo=mail-ed1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" For the VIA south bridges there was a comment to have the call in board code. Move it there for PIIX4 as well for consistency. Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daudé --- hw/isa/piix4.c | 1 - hw/mips/malta.c | 10 ++++++---- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 9e2f7b9b71..67881e3a75 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -256,7 +256,6 @@ static void piix4_realize(PCIDevice *dev, Error **errp) if (!qdev_realize(DEVICE(&s->ide), BUS(pci_bus), errp)) { return; } - pci_ide_create_devs(PCI_DEVICE(&s->ide)); /* USB */ qdev_prop_set_int32(DEVICE(&s->uhci), "addr", dev->devfn + 2); diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 0ec2ac2eaf..a4b866a2cf 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -39,7 +39,7 @@ #include "hw/pci/pci.h" #include "qemu/log.h" #include "hw/mips/bios.h" -#include "hw/ide.h" +#include "hw/ide/pci.h" #include "hw/irq.h" #include "hw/loader.h" #include "elf.h" @@ -1402,11 +1402,13 @@ void mips_malta_init(MachineState *machine) /* Southbridge */ piix4 = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0), true, TYPE_PIIX4_PCI_DEVICE); - dev = DEVICE(piix4); - isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0")); + isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix4), "isa.0")); + + dev = DEVICE(object_resolve_path_component(OBJECT(piix4), "ide")); + pci_ide_create_devs(PCI_DEVICE(dev)); /* Interrupt controller */ - qdev_connect_gpio_out_named(dev, "intr", 0, i8259_irq); + qdev_connect_gpio_out_named(DEVICE(piix4), "intr", 0, i8259_irq); /* generate SPD EEPROM data */ dev = DEVICE(object_resolve_path_component(OBJECT(piix4), "pm")); From patchwork Thu Sep 1 16:25:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 12962933 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 60DEBECAAD3 for ; Thu, 1 Sep 2022 16:52:40 +0000 (UTC) Received: from localhost ([::1]:41530 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oTnQk-0001jR-8J for qemu-devel@archiver.kernel.org; Thu, 01 Sep 2022 12:52:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37940) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oTn2N-0002K1-S6 for qemu-devel@nongnu.org; Thu, 01 Sep 2022 12:27:28 -0400 Received: from mail-ej1-x62b.google.com ([2a00:1450:4864:20::62b]:35460) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oTn2C-0001Tm-B9 for qemu-devel@nongnu.org; Thu, 01 Sep 2022 12:27:26 -0400 Received: by mail-ej1-x62b.google.com with SMTP id og21so35829985ejc.2 for ; Thu, 01 Sep 2022 09:27:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=oQBXM0jZm/4vrXDCw0I1YhZPppOIT89c2uqndTrQlA4=; b=MGsEW5UzfYlINgMdqdb8IyP2eWdB2pVPEhderaoyHdIk+/BQ8+hUScc5Qa8zD8szOH ugh6LTZ4oGfJIyd6jZ7qVwBmL+l1BhlXDaIGo82EzBCdRP/Kk5eZO8qIq8Q1+zlSUymO LOVxzO5rTee5D1AeZsnjjYjBXBwKoNQ9APbqdYEh4XLXJVgYyRJ4KdmcgLIionz086RD djSMaguiWkBoRDH4XDLva8Kn+SL9hVVIJWJL9TYiRinB4z3ffBzxOueqzDzreDne0ffY VXmPB4KpmboB8Kapp6jWxdV/KrYnE+Mv2rYpS7buXKZxtRi+fYenhjfNtIrosjNrK3d8 JvLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=oQBXM0jZm/4vrXDCw0I1YhZPppOIT89c2uqndTrQlA4=; b=RDHtIhuXM1vPPaULtlIbZhndRvdcYDTMTrVf+eysd4FJNqEWvDoj6Uwyhlisr3OcIY gxmgG6Zn3F7I8KK8k1oZhYzdpZMgvF4i32PRPDUmmxZzFih7rt1eG8UvMjYvU07Awy9E 4ZwDXmiVjZKEGYEqccWuUzWsKmkuO81N2ksJtGuIo12uL5L6x16g67t8hQa5szL2Vrmt HIk63NrrPC4SGq2xDYRaWOtr5qhUnwxm1/xVYkQ/nUO3GF2HVvdvvqiSaELlxepwrvVu AWukDGitCT3IKEyjp7Q5DeLILQLEyeNA2xb8xzYVWHCFza0Z6PCBbg20M6dof1G3awaz P3GA== X-Gm-Message-State: ACgBeo3Cu4yUtTDJ8qpblxwcQ/Y7jT0vgFedKhi7JOAK6mNdaUTefw7C gKyWLAN5EmhU2tLaS8tkhxBbg8d6Xf4= X-Google-Smtp-Source: AA6agR64Dnwmf9+SRYaK5Sn1CqiRNd0TxUpnim/dmpKAmoCdanoIgKl1b10YRRZ+tS3b4iO7mqrTUw== X-Received: by 2002:a17:907:7b8e:b0:741:5903:9307 with SMTP id ne14-20020a1709077b8e00b0074159039307mr17057688ejc.201.1662049632519; Thu, 01 Sep 2022 09:27:12 -0700 (PDT) Received: from osoxes.fritz.box (p200300faaf0bb2009c4947838afc41b6.dip0.t-ipconnect.de. [2003:fa:af0b:b200:9c49:4783:8afc:41b6]) by smtp.gmail.com with ESMTPSA id p6-20020aa7d306000000b00447c0dcbb99sm1587672edq.83.2022.09.01.09.27.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Sep 2022 09:27:12 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Her?= =?utf-8?q?v=C3=A9_Poussineau?= , Aurelien Jarno , Paolo Bonzini , Eduardo Habkost , Richard Henderson , Jiaxun Yang , Ani Sinha , Igor Mammedov , Marcel Apfelbaum , "Michael S. Tsirkin" , Bernhard Beschow Subject: [PATCH 26/42] hw/isa/piix4: Make PIIX4's ACPI and USB functions optional Date: Thu, 1 Sep 2022 18:25:57 +0200 Message-Id: <20220901162613.6939-27-shentey@gmail.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220901162613.6939-1-shentey@gmail.com> References: <20220901162613.6939-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62b; envelope-from=shentey@gmail.com; helo=mail-ej1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_HELO_TEMPERROR=0.01, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" This aligns PIIX4 with PIIX3. Signed-off-by: Bernhard Beschow --- hw/isa/piix4.c | 44 ++++++++++++++++++++++++++++++++------------ hw/mips/malta.c | 6 ++++-- 2 files changed, 36 insertions(+), 14 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 67881e3a75..ed9eca715f 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -50,9 +50,16 @@ struct PIIX4State { PCIIDEState ide; UHCIState uhci; PIIX4PMState pm; + + uint32_t smb_io_base; + /* Reset Control Register */ MemoryRegion rcr_mem; uint8_t rcr; + + bool has_acpi; + bool has_usb; + bool smm_enabled; }; OBJECT_DECLARE_SIMPLE_TYPE(PIIX4State, PIIX4_PCI_DEVICE) @@ -258,17 +265,26 @@ static void piix4_realize(PCIDevice *dev, Error **errp) } /* USB */ - qdev_prop_set_int32(DEVICE(&s->uhci), "addr", dev->devfn + 2); - if (!qdev_realize(DEVICE(&s->uhci), BUS(pci_bus), errp)) { - return; + if (s->has_usb) { + object_initialize_child(OBJECT(dev), "uhci", &s->uhci, + "piix4-usb-uhci"); + qdev_prop_set_int32(DEVICE(&s->uhci), "addr", dev->devfn + 2); + if (!qdev_realize(DEVICE(&s->uhci), BUS(pci_bus), errp)) { + return; + } } /* ACPI controller */ - qdev_prop_set_int32(DEVICE(&s->pm), "addr", dev->devfn + 3); - if (!qdev_realize(DEVICE(&s->pm), BUS(pci_bus), errp)) { - return; + if (s->has_acpi) { + object_initialize_child(OBJECT(s), "pm", &s->pm, TYPE_PIIX4_PM); + qdev_prop_set_int32(DEVICE(&s->pm), "addr", dev->devfn + 3); + qdev_prop_set_uint32(DEVICE(&s->pm), "smb_io_base", s->smb_io_base); + qdev_prop_set_bit(DEVICE(&s->pm), "smm-enabled", s->smm_enabled); + if (!qdev_realize(DEVICE(&s->pm), BUS(pci_bus), errp)) { + return; + } + qdev_connect_gpio_out(DEVICE(&s->pm), 0, s->isa[9]); } - qdev_connect_gpio_out(DEVICE(&s->pm), 0, s->isa[9]); pci_bus_irqs(pci_bus, piix4_set_irq, pci_slot_get_pirq, s, PIIX_NUM_PIRQS); } @@ -279,13 +295,16 @@ static void piix4_init(Object *obj) object_initialize_child(obj, "rtc", &s->rtc, TYPE_MC146818_RTC); object_initialize_child(obj, "ide", &s->ide, "piix4-ide"); - object_initialize_child(obj, "uhci", &s->uhci, "piix4-usb-uhci"); - - object_initialize_child(obj, "pm", &s->pm, TYPE_PIIX4_PM); - qdev_prop_set_uint32(DEVICE(&s->pm), "smb_io_base", 0x1100); - qdev_prop_set_bit(DEVICE(&s->pm), "smm-enabled", 0); } +static Property piix4_props[] = { + DEFINE_PROP_UINT32("smb_io_base", PIIX4State, smb_io_base, 0), + DEFINE_PROP_BOOL("has-acpi", PIIX4State, has_acpi, true), + DEFINE_PROP_BOOL("has-usb", PIIX4State, has_usb, true), + DEFINE_PROP_BOOL("smm-enabled", PIIX4State, smm_enabled, false), + DEFINE_PROP_END_OF_LIST(), +}; + static void piix4_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -304,6 +323,7 @@ static void piix4_class_init(ObjectClass *klass, void *data) */ dc->user_creatable = false; dc->hotpluggable = false; + device_class_set_props(dc, piix4_props); } static const TypeInfo piix4_info = { diff --git a/hw/mips/malta.c b/hw/mips/malta.c index a4b866a2cf..6339b0d66c 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -1400,8 +1400,10 @@ void mips_malta_init(MachineState *machine) empty_slot_init("GT64120", 0, 0x20000000); /* Southbridge */ - piix4 = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0), true, - TYPE_PIIX4_PCI_DEVICE); + piix4 = pci_new_multifunction(PCI_DEVFN(10, 0), true, + TYPE_PIIX4_PCI_DEVICE); + qdev_prop_set_uint32(DEVICE(piix4), "smb_io_base", 0x1100); + pci_realize_and_unref(piix4, pci_bus, &error_fatal); isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix4), "isa.0")); dev = DEVICE(object_resolve_path_component(OBJECT(piix4), "ide")); From patchwork Thu Sep 1 16:25:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 12962925 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DC646ECAAD8 for ; Thu, 1 Sep 2022 16:46:04 +0000 (UTC) Received: from localhost ([::1]:47484 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oTnKN-0003P0-Tp for qemu-devel@archiver.kernel.org; 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[2003:fa:af0b:b200:9c49:4783:8afc:41b6]) by smtp.gmail.com with ESMTPSA id p6-20020aa7d306000000b00447c0dcbb99sm1587672edq.83.2022.09.01.09.27.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Sep 2022 09:27:13 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Her?= =?utf-8?q?v=C3=A9_Poussineau?= , Aurelien Jarno , Paolo Bonzini , Eduardo Habkost , Richard Henderson , Jiaxun Yang , Ani Sinha , Igor Mammedov , Marcel Apfelbaum , "Michael S. Tsirkin" , Bernhard Beschow Subject: [PATCH 27/42] hw/isa/piix4: Allow board to provide PCI interrupt routes Date: Thu, 1 Sep 2022 18:25:58 +0200 Message-Id: <20220901162613.6939-28-shentey@gmail.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220901162613.6939-1-shentey@gmail.com> References: <20220901162613.6939-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52c; envelope-from=shentey@gmail.com; helo=mail-ed1-x52c.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" PIIX3 initializes the PIRQx route control registers to the default values as described in the 82371AB PCI-TO-ISA/IDE XCELERATOR (PIIX4) April 1997 manual. PIIX4, however, initializes the routes according to the Malta™ User’s Manual, ch 6.6, which are IRQs 10 and 11. In order to allow the reset methods to be consolidated, allow board code to specify the routes. Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daudé --- hw/isa/piix4.c | 14 ++++++++++---- hw/mips/malta.c | 4 ++++ 2 files changed, 14 insertions(+), 4 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index ed9eca715f..763c98b565 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -57,6 +57,8 @@ struct PIIX4State { MemoryRegion rcr_mem; uint8_t rcr; + uint8_t pci_irq_reset_mappings[PIIX_NUM_PIRQS]; + bool has_acpi; bool has_usb; bool smm_enabled; @@ -122,10 +124,10 @@ static void piix4_isa_reset(DeviceState *dev) pci_conf[0x4c] = 0x4d; pci_conf[0x4e] = 0x03; pci_conf[0x4f] = 0x00; - pci_conf[0x60] = 0x0a; // PCI A -> IRQ 10 - pci_conf[0x61] = 0x0a; // PCI B -> IRQ 10 - pci_conf[0x62] = 0x0b; // PCI C -> IRQ 11 - pci_conf[0x63] = 0x0b; // PCI D -> IRQ 11 + pci_conf[PIIX_PIRQCA] = d->pci_irq_reset_mappings[0]; + pci_conf[PIIX_PIRQCB] = d->pci_irq_reset_mappings[1]; + pci_conf[PIIX_PIRQCC] = d->pci_irq_reset_mappings[2]; + pci_conf[PIIX_PIRQCD] = d->pci_irq_reset_mappings[3]; pci_conf[0x69] = 0x02; pci_conf[0x70] = 0x80; pci_conf[0x76] = 0x0c; @@ -299,6 +301,10 @@ static void piix4_init(Object *obj) static Property piix4_props[] = { DEFINE_PROP_UINT32("smb_io_base", PIIX4State, smb_io_base, 0), + DEFINE_PROP_UINT8("pirqa", PIIX4State, pci_irq_reset_mappings[0], 0x80), + DEFINE_PROP_UINT8("pirqb", PIIX4State, pci_irq_reset_mappings[1], 0x80), + DEFINE_PROP_UINT8("pirqc", PIIX4State, pci_irq_reset_mappings[2], 0x80), + DEFINE_PROP_UINT8("pirqd", PIIX4State, pci_irq_reset_mappings[3], 0x80), DEFINE_PROP_BOOL("has-acpi", PIIX4State, has_acpi, true), DEFINE_PROP_BOOL("has-usb", PIIX4State, has_usb, true), DEFINE_PROP_BOOL("smm-enabled", PIIX4State, smm_enabled, false), diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 6339b0d66c..44b6b14f3d 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -1403,6 +1403,10 @@ void mips_malta_init(MachineState *machine) piix4 = pci_new_multifunction(PCI_DEVFN(10, 0), true, TYPE_PIIX4_PCI_DEVICE); qdev_prop_set_uint32(DEVICE(piix4), "smb_io_base", 0x1100); + qdev_prop_set_uint8(DEVICE(piix4), "pirqa", 10); + qdev_prop_set_uint8(DEVICE(piix4), "pirqb", 10); + qdev_prop_set_uint8(DEVICE(piix4), "pirqc", 11); + qdev_prop_set_uint8(DEVICE(piix4), "pirqd", 11); pci_realize_and_unref(piix4, pci_bus, &error_fatal); isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix4), "isa.0")); From patchwork Thu Sep 1 16:25:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 12962936 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3293BECAAD3 for ; Thu, 1 Sep 2022 16:54:49 +0000 (UTC) Received: from localhost ([::1]:51366 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oTnSq-0007JL-AI for qemu-devel@archiver.kernel.org; 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[2003:fa:af0b:b200:9c49:4783:8afc:41b6]) by smtp.gmail.com with ESMTPSA id p6-20020aa7d306000000b00447c0dcbb99sm1587672edq.83.2022.09.01.09.27.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Sep 2022 09:27:14 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Her?= =?utf-8?q?v=C3=A9_Poussineau?= , Aurelien Jarno , Paolo Bonzini , Eduardo Habkost , Richard Henderson , Jiaxun Yang , Ani Sinha , Igor Mammedov , Marcel Apfelbaum , "Michael S. Tsirkin" , Bernhard Beschow Subject: [PATCH 28/42] hw/isa/piix4: Remove unused code Date: Thu, 1 Sep 2022 18:25:59 +0200 Message-Id: <20220901162613.6939-29-shentey@gmail.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220901162613.6939-1-shentey@gmail.com> References: <20220901162613.6939-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62a; envelope-from=shentey@gmail.com; helo=mail-ej1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The Malta board, which is the only user of PIIX4, doesn't connect to the exported interrupt lines. Signed-off-by: Bernhard Beschow --- hw/isa/piix4.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 763c98b565..3e9a84de8b 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -181,12 +181,6 @@ static void piix4_request_i8259_irq(void *opaque, int irq, int level) qemu_set_irq(s->cpu_intr, level); } -static void piix4_set_i8259_irq(void *opaque, int irq, int level) -{ - PIIX4State *s = opaque; - qemu_set_irq(s->isa[irq], level); -} - static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned int len) { @@ -230,8 +224,6 @@ static void piix4_realize(PCIDevice *dev, Error **errp) return; } - qdev_init_gpio_in_named(DEVICE(dev), piix4_set_i8259_irq, - "isa", ISA_NUM_IRQS); qdev_init_gpio_out_named(DEVICE(dev), &s->cpu_intr, "intr", 1); From patchwork Thu Sep 1 16:26:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 12962935 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D1C14ECAAD1 for ; Thu, 1 Sep 2022 16:54:29 +0000 (UTC) Received: from localhost ([::1]:52840 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oTnSV-000733-9g for qemu-devel@archiver.kernel.org; Thu, 01 Sep 2022 12:54:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37954) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oTn2T-0002QR-OA for qemu-devel@nongnu.org; Thu, 01 Sep 2022 12:27:34 -0400 Received: from mail-ej1-x62b.google.com ([2a00:1450:4864:20::62b]:46747) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oTn2N-0001TY-Fh for qemu-devel@nongnu.org; Thu, 01 Sep 2022 12:27:31 -0400 Received: by mail-ej1-x62b.google.com with SMTP id bj12so35786353ejb.13 for ; Thu, 01 Sep 2022 09:27:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=fg262DyFFhJoLbDKo7DrKpLbeDb7ag02YxRokkeeINU=; b=pb6t6SN5RKm51YHrrpIof+qN6ICzu1/Cz5hbswIO0if7yYZzqFgZyR3WD4mKIHiYiQ zxBI+Rq/pguH5D+n5USncRgkhIxQ5JNtc1yyJdUCEXikHttZzz3JckRHnzBwYBWgrg3t sJMMHsWxNyH9SDcKVwnrZf9AW3v7uuDJ+nXvIfEe1w3CPsUmtBWXUk+OiK9VsmMyIBa6 PubL4YlJBg1xH2JQIKH/WG/mXZW1FGjmbIKuOX4aJwmqtHU4ydabSkwtKpDuPt8PLQGJ dnzfDPDVlZipURWkQtLhQ71lRD/Xc7mbNz0oZxuX7Mdcazq/G1+pXajAE6vuj3j9wJ5b 5zKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=fg262DyFFhJoLbDKo7DrKpLbeDb7ag02YxRokkeeINU=; b=rv2E2axoBYLc/3sUyGtoql6gQ+AiGicWLG+ARSWnydtn95mI6dM0TRWvT8Ab/AMqEm 3DqmhB5U4kRVY9l53tOCTHkhkvCk8WXhDNCsxtGP/c1YEQPmzd+n9EovTVBk5c5fT5C4 GXFOTIUI4Hyv5tJa4ura7xoSCzSaD/ilTqvJvFodYQY8IX3+TzP4lf9e4pDgyNRITbvS 0FddDQlv5wEUqqh7SMl9OoDKGnAJ7vg4BHF9dC3fte4eZnJvQlul/kHm0qaudQX2fPmy 1JU/TqwO5dra8LcCHpyNtdNg8nJYC4tpnaD6lM2BcIBD1ddclVadm/HpKI8CQ4HuAK8o VcnQ== X-Gm-Message-State: ACgBeo0MX/S6Qqaxtcm6tkOcOK8Y14IPBLyRQBznM/PN/1EWElyJ54Zh Wq/5r66K8nRtWRBIXHHamWNfZrDQ55Q= X-Google-Smtp-Source: AA6agR7jweUBLnUdTeSXq1HHPK50WiBX9IKC18mlWx/hapfB5n6F3qEUpEeMDBk9r3IKuyHQbxQBxw== X-Received: by 2002:a17:907:948f:b0:731:3f2e:8916 with SMTP id dm15-20020a170907948f00b007313f2e8916mr25110088ejc.442.1662049635398; Thu, 01 Sep 2022 09:27:15 -0700 (PDT) Received: from osoxes.fritz.box (p200300faaf0bb2009c4947838afc41b6.dip0.t-ipconnect.de. [2003:fa:af0b:b200:9c49:4783:8afc:41b6]) by smtp.gmail.com with ESMTPSA id p6-20020aa7d306000000b00447c0dcbb99sm1587672edq.83.2022.09.01.09.27.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Sep 2022 09:27:14 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Her?= =?utf-8?q?v=C3=A9_Poussineau?= , Aurelien Jarno , Paolo Bonzini , Eduardo Habkost , Richard Henderson , Jiaxun Yang , Ani Sinha , Igor Mammedov , Marcel Apfelbaum , "Michael S. Tsirkin" , Bernhard Beschow Subject: [PATCH 29/42] hw/isa/piix4: Use ISA PIC device Date: Thu, 1 Sep 2022 18:26:00 +0200 Message-Id: <20220901162613.6939-30-shentey@gmail.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220901162613.6939-1-shentey@gmail.com> References: <20220901162613.6939-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62b; envelope-from=shentey@gmail.com; helo=mail-ej1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Aligns the code with PIIX3 such that PIIXState can be used in PIIX4, too. Furthermore, using the isa-pic device in PIIX4 could allow the Malta board to gain KVM accelleration capabilities. Signed-off-by: Bernhard Beschow --- hw/isa/piix4.c | 28 ++++++++++------------------ hw/mips/malta.c | 11 +++++++++-- 2 files changed, 19 insertions(+), 20 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 3e9a84de8b..128284bd0a 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -43,9 +43,8 @@ struct PIIX4State { PCIDevice dev; - qemu_irq cpu_intr; - qemu_irq *isa; + ISAPICState pic; RTCState rtc; PCIIDEState ide; UHCIState uhci; @@ -83,7 +82,7 @@ static void piix4_set_irq(void *opaque, int irq_num, int level) pic_level |= pci_bus_get_irq_level(bus, i); } } - qemu_set_irq(s->isa[pic_irq], pic_level); + qemu_set_irq(s->pic.in_irqs[pic_irq], pic_level); } } @@ -175,12 +174,6 @@ static const VMStateDescription vmstate_piix4 = { } }; -static void piix4_request_i8259_irq(void *opaque, int irq, int level) -{ - PIIX4State *s = opaque; - qemu_set_irq(s->cpu_intr, level); -} - static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned int len) { @@ -216,7 +209,6 @@ static void piix4_realize(PCIDevice *dev, Error **errp) PIIX4State *s = PIIX4_PCI_DEVICE(dev); PCIBus *pci_bus = pci_get_bus(dev); ISABus *isa_bus; - qemu_irq *i8259_out_irq; isa_bus = isa_bus_new(DEVICE(dev), pci_address_space(dev), pci_address_space_io(dev), errp); @@ -224,20 +216,18 @@ static void piix4_realize(PCIDevice *dev, Error **errp) return; } - qdev_init_gpio_out_named(DEVICE(dev), &s->cpu_intr, - "intr", 1); - memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s, "reset-control", 1); memory_region_add_subregion_overlap(pci_address_space_io(dev), PIIX_RCR_IOPORT, &s->rcr_mem, 1); /* initialize i8259 pic */ - i8259_out_irq = qemu_allocate_irqs(piix4_request_i8259_irq, s, 1); - s->isa = i8259_init(isa_bus, *i8259_out_irq); + if (!qdev_realize(DEVICE(&s->pic), BUS(isa_bus), errp)) { + return; + } /* initialize ISA irqs */ - isa_bus_irqs(isa_bus, s->isa); + isa_bus_irqs(isa_bus, s->pic.in_irqs); /* initialize pit */ i8254_pit_init(isa_bus, 0x40, 0, NULL); @@ -250,7 +240,7 @@ static void piix4_realize(PCIDevice *dev, Error **errp) if (!qdev_realize(DEVICE(&s->rtc), BUS(isa_bus), errp)) { return; } - s->rtc.irq = isa_get_irq(ISA_DEVICE(&s->rtc), s->rtc.isairq); + s->rtc.irq = qdev_get_gpio_in(DEVICE(&s->pic), s->rtc.isairq); /* IDE */ qdev_prop_set_int32(DEVICE(&s->ide), "addr", dev->devfn + 1); @@ -277,7 +267,8 @@ static void piix4_realize(PCIDevice *dev, Error **errp) if (!qdev_realize(DEVICE(&s->pm), BUS(pci_bus), errp)) { return; } - qdev_connect_gpio_out(DEVICE(&s->pm), 0, s->isa[9]); + qdev_connect_gpio_out(DEVICE(&s->pm), 0, + qdev_get_gpio_in(DEVICE(&s->pic), 9)); } pci_bus_irqs(pci_bus, piix4_set_irq, pci_slot_get_pirq, s, PIIX_NUM_PIRQS); @@ -287,6 +278,7 @@ static void piix4_init(Object *obj) { PIIX4State *s = PIIX4_PCI_DEVICE(obj); + object_initialize_child(obj, "pic", &s->pic, TYPE_ISA_PIC); object_initialize_child(obj, "rtc", &s->rtc, TYPE_MC146818_RTC); object_initialize_child(obj, "ide", &s->ide, "piix4-ide"); } diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 44b6b14f3d..68e800b00f 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -28,6 +28,7 @@ #include "qemu/datadir.h" #include "hw/clock.h" #include "hw/southbridge/piix.h" +#include "hw/intc/i8259.h" #include "hw/isa/superio.h" #include "hw/char/serial.h" #include "net/net.h" @@ -1232,10 +1233,11 @@ void mips_malta_init(MachineState *machine) PCIBus *pci_bus; ISABus *isa_bus; qemu_irq cbus_irq, i8259_irq; + qemu_irq *i8259; I2CBus *smbus; DriveInfo *dinfo; int fl_idx = 0; - int be; + int be, i; MaltaState *s; PCIDevice *piix4; DeviceState *dev; @@ -1414,7 +1416,12 @@ void mips_malta_init(MachineState *machine) pci_ide_create_devs(PCI_DEVICE(dev)); /* Interrupt controller */ - qdev_connect_gpio_out_named(DEVICE(piix4), "intr", 0, i8259_irq); + dev = DEVICE(object_resolve_path_component(OBJECT(piix4), "pic")); + i8259 = i8259_init(isa_bus, i8259_irq); + for (i = 0; i < ISA_NUM_IRQS; i++) { + qdev_connect_gpio_out(dev, i, i8259[i]); + } + g_free(i8259); /* generate SPD EEPROM data */ dev = DEVICE(object_resolve_path_component(OBJECT(piix4), "pm")); From patchwork Thu Sep 1 16:26:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 12962945 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C18D7ECAAD3 for ; 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[2003:fa:af0b:b200:9c49:4783:8afc:41b6]) by smtp.gmail.com with ESMTPSA id p6-20020aa7d306000000b00447c0dcbb99sm1587672edq.83.2022.09.01.09.27.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Sep 2022 09:27:20 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Her?= =?utf-8?q?v=C3=A9_Poussineau?= , Aurelien Jarno , Paolo Bonzini , Eduardo Habkost , Richard Henderson , Jiaxun Yang , Ani Sinha , Igor Mammedov , Marcel Apfelbaum , "Michael S. Tsirkin" , Bernhard Beschow Subject: [PATCH 30/42] hw/isa/piix4: Reuse struct PIIXState from PIIX3 Date: Thu, 1 Sep 2022 18:26:01 +0200 Message-Id: <20220901162613.6939-31-shentey@gmail.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220901162613.6939-1-shentey@gmail.com> References: <20220901162613.6939-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52a; envelope-from=shentey@gmail.com; helo=mail-ed1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Now that PIIX4 also uses the "isa-pic" proxy, both implementations can share the same struct. Signed-off-by: Bernhard Beschow --- hw/isa/piix4.c | 61 ++++++++++++++++---------------------------------- 1 file changed, 19 insertions(+), 42 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 128284bd0a..95e4a9f3c1 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -41,34 +41,10 @@ #include "sysemu/runstate.h" #include "qom/object.h" -struct PIIX4State { - PCIDevice dev; - - ISAPICState pic; - RTCState rtc; - PCIIDEState ide; - UHCIState uhci; - PIIX4PMState pm; - - uint32_t smb_io_base; - - /* Reset Control Register */ - MemoryRegion rcr_mem; - uint8_t rcr; - - uint8_t pci_irq_reset_mappings[PIIX_NUM_PIRQS]; - - bool has_acpi; - bool has_usb; - bool smm_enabled; -}; - -OBJECT_DECLARE_SIMPLE_TYPE(PIIX4State, PIIX4_PCI_DEVICE) - static void piix4_set_irq(void *opaque, int irq_num, int level) { int i, pic_irq, pic_level; - PIIX4State *s = opaque; + PIIXState *s = opaque; PCIBus *bus = pci_get_bus(&s->dev); /* now we change the pic irq level according to the piix irq mappings */ @@ -113,7 +89,7 @@ static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num) static void piix4_isa_reset(DeviceState *dev) { - PIIX4State *d = PIIX4_PCI_DEVICE(dev); + PIIXState *d = PIIX_PCI_DEVICE(dev); uint8_t *pci_conf = d->dev.config; pci_conf[0x04] = 0x07; // master, memory and I/O @@ -148,12 +124,13 @@ static void piix4_isa_reset(DeviceState *dev) pci_conf[0xac] = 0x00; pci_conf[0xae] = 0x00; + d->pic_levels = 0; /* not used in PIIX4 */ d->rcr = 0; } static int piix4_ide_post_load(void *opaque, int version_id) { - PIIX4State *s = opaque; + PIIXState *s = opaque; if (version_id == 2) { s->rcr = 0; @@ -168,8 +145,8 @@ static const VMStateDescription vmstate_piix4 = { .minimum_version_id = 2, .post_load = piix4_ide_post_load, .fields = (VMStateField[]) { - VMSTATE_PCI_DEVICE(dev, PIIX4State), - VMSTATE_UINT8_V(rcr, PIIX4State, 3), + VMSTATE_PCI_DEVICE(dev, PIIXState), + VMSTATE_UINT8_V(rcr, PIIXState, 3), VMSTATE_END_OF_LIST() } }; @@ -177,7 +154,7 @@ static const VMStateDescription vmstate_piix4 = { static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned int len) { - PIIX4State *s = opaque; + PIIXState *s = opaque; if (val & 4) { qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); @@ -189,7 +166,7 @@ static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val, static uint64_t piix4_rcr_read(void *opaque, hwaddr addr, unsigned int len) { - PIIX4State *s = opaque; + PIIXState *s = opaque; return s->rcr; } @@ -206,7 +183,7 @@ static const MemoryRegionOps piix4_rcr_ops = { static void piix4_realize(PCIDevice *dev, Error **errp) { - PIIX4State *s = PIIX4_PCI_DEVICE(dev); + PIIXState *s = PIIX_PCI_DEVICE(dev); PCIBus *pci_bus = pci_get_bus(dev); ISABus *isa_bus; @@ -276,7 +253,7 @@ static void piix4_realize(PCIDevice *dev, Error **errp) static void piix4_init(Object *obj) { - PIIX4State *s = PIIX4_PCI_DEVICE(obj); + PIIXState *s = PIIX_PCI_DEVICE(obj); object_initialize_child(obj, "pic", &s->pic, TYPE_ISA_PIC); object_initialize_child(obj, "rtc", &s->rtc, TYPE_MC146818_RTC); @@ -284,14 +261,14 @@ static void piix4_init(Object *obj) } static Property piix4_props[] = { - DEFINE_PROP_UINT32("smb_io_base", PIIX4State, smb_io_base, 0), - DEFINE_PROP_UINT8("pirqa", PIIX4State, pci_irq_reset_mappings[0], 0x80), - DEFINE_PROP_UINT8("pirqb", PIIX4State, pci_irq_reset_mappings[1], 0x80), - DEFINE_PROP_UINT8("pirqc", PIIX4State, pci_irq_reset_mappings[2], 0x80), - DEFINE_PROP_UINT8("pirqd", PIIX4State, pci_irq_reset_mappings[3], 0x80), - DEFINE_PROP_BOOL("has-acpi", PIIX4State, has_acpi, true), - DEFINE_PROP_BOOL("has-usb", PIIX4State, has_usb, true), - DEFINE_PROP_BOOL("smm-enabled", PIIX4State, smm_enabled, false), + DEFINE_PROP_UINT32("smb_io_base", PIIXState, smb_io_base, 0), + DEFINE_PROP_UINT8("pirqa", PIIXState, pci_irq_reset_mappings[0], 0x80), + DEFINE_PROP_UINT8("pirqb", PIIXState, pci_irq_reset_mappings[1], 0x80), + DEFINE_PROP_UINT8("pirqc", PIIXState, pci_irq_reset_mappings[2], 0x80), + DEFINE_PROP_UINT8("pirqd", PIIXState, pci_irq_reset_mappings[3], 0x80), + DEFINE_PROP_BOOL("has-acpi", PIIXState, has_acpi, true), + DEFINE_PROP_BOOL("has-usb", PIIXState, has_usb, true), + DEFINE_PROP_BOOL("smm-enabled", PIIXState, smm_enabled, false), DEFINE_PROP_END_OF_LIST(), }; @@ -319,7 +296,7 @@ static void piix4_class_init(ObjectClass *klass, void *data) static const TypeInfo piix4_info = { .name = TYPE_PIIX4_PCI_DEVICE, .parent = TYPE_PCI_DEVICE, - .instance_size = sizeof(PIIX4State), + .instance_size = sizeof(PIIXState), .instance_init = piix4_init, .class_init = piix4_class_init, .interfaces = (InterfaceInfo[]) { From patchwork Thu Sep 1 16:26:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 12962941 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DD5E2ECAAD3 for ; Thu, 1 Sep 2022 16:57:48 +0000 (UTC) Received: from localhost ([::1]:58148 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oTnVj-0004e2-RA for qemu-devel@archiver.kernel.org; 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[2003:fa:af0b:b200:9c49:4783:8afc:41b6]) by smtp.gmail.com with ESMTPSA id p6-20020aa7d306000000b00447c0dcbb99sm1587672edq.83.2022.09.01.09.27.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Sep 2022 09:27:21 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Her?= =?utf-8?q?v=C3=A9_Poussineau?= , Aurelien Jarno , Paolo Bonzini , Eduardo Habkost , Richard Henderson , Jiaxun Yang , Ani Sinha , Igor Mammedov , Marcel Apfelbaum , "Michael S. Tsirkin" , Bernhard Beschow Subject: [PATCH 31/42] hw/isa/piix4: Rename reset control operations to match PIIX3 Date: Thu, 1 Sep 2022 18:26:02 +0200 Message-Id: <20220901162613.6939-32-shentey@gmail.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220901162613.6939-1-shentey@gmail.com> References: <20220901162613.6939-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::630; envelope-from=shentey@gmail.com; helo=mail-ej1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Both implementations are the same and will be shared upon merging. Signed-off-by: Bernhard Beschow --- hw/isa/piix4.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 95e4a9f3c1..e682370887 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -151,7 +151,7 @@ static const VMStateDescription vmstate_piix4 = { } }; -static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val, +static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned int len) { PIIXState *s = opaque; @@ -164,16 +164,16 @@ static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val, s->rcr = val & 2; /* keep System Reset type only */ } -static uint64_t piix4_rcr_read(void *opaque, hwaddr addr, unsigned int len) +static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned int len) { PIIXState *s = opaque; return s->rcr; } -static const MemoryRegionOps piix4_rcr_ops = { - .read = piix4_rcr_read, - .write = piix4_rcr_write, +static const MemoryRegionOps rcr_ops = { + .read = rcr_read, + .write = rcr_write, .endianness = DEVICE_LITTLE_ENDIAN, .impl = { .min_access_size = 1, @@ -193,7 +193,7 @@ static void piix4_realize(PCIDevice *dev, Error **errp) return; } - memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s, + memory_region_init_io(&s->rcr_mem, OBJECT(dev), &rcr_ops, s, "reset-control", 1); memory_region_add_subregion_overlap(pci_address_space_io(dev), PIIX_RCR_IOPORT, &s->rcr_mem, 1); From patchwork Thu Sep 1 16:26:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 12962952 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 49E98ECAAD3 for ; Thu, 1 Sep 2022 17:12:28 +0000 (UTC) Received: from localhost ([::1]:35258 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oTnjv-0005Hp-Cs for qemu-devel@archiver.kernel.org; Thu, 01 Sep 2022 13:12:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37950) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oTn2R-0002Pc-I8 for qemu-devel@nongnu.org; Thu, 01 Sep 2022 12:27:32 -0400 Received: from mail-ej1-x62c.google.com ([2a00:1450:4864:20::62c]:36352) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oTn2N-0001WK-FH for qemu-devel@nongnu.org; Thu, 01 Sep 2022 12:27:30 -0400 Received: by mail-ej1-x62c.google.com with SMTP id h5so24265066ejb.3 for ; Thu, 01 Sep 2022 09:27:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=bXJ8wvWe/ChmJ4OdCaLecAAvRLVcjegGXn5B2jOVT1Y=; b=aikx94wD6etGjqlDn2yDUbnHYIgLe/drTdHPUDP3HP126++EHDZRgYmGvo5pCcWxDZ KSUYKcmeYsQ+4rrWBzxFJIbJm8ZFbbvaTn+jUzl6Dw6gnQEzhU+MVQFBJb9z7hG39ND0 ETqRIozeEZpFvEvUNpUhgLXbSSq4NxSpdRyKpJYlDqLhM03f9zfCk5PIMSj4TgipwiVO 66/2eVxNA6r+HKO7fP9fVA2MIV8rYl0hJbIddhp1HsJ7CViB6h3bQNsO7mEQh8SQW/o+ J3UlGeUOr0HFtVcWgIAOAapBBkJbHRgUN8tj7OzB0IGRhr0GiBSpvREJ8ocAJZx+/Ld3 D1Jw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=bXJ8wvWe/ChmJ4OdCaLecAAvRLVcjegGXn5B2jOVT1Y=; b=W3oslXZIRDyT0dsTaqieCqLgQRLxEnv8HmngsAVFQOB0/XbPhbqbHb+EMQCIqm0Hrv mDk6fFmR3oTFVHzAbFa/F6gtNNqmcz5VNtsoguKbU5g19AbuluGRJpgu3ikcsxQ01RG7 1XXOeZIbBG/IA+MD01Zr4w2E5fo+nLTVJ6Jrjw3mBGgvlUBFB9pwJM00qK2uj3qQJF6Y NaJCBIm1LJOewtmy31DXDMOAkHZAqx62XrAI3CLJNi49ySDgzPJQ5FKl3j2pKGtLo77I nj7Qsug29WIjgsljSMtZtx0ETtSERjhPd0QSp4lDCf+Xcdn39hvAZuRoGLQirUmot0C7 5IPw== X-Gm-Message-State: ACgBeo17uC+qANUYBF/1Jqdvs4+0vYpbpUZ4zyygugazD3PzEvrjbZiv ZNjz+wdOe3kh/EqGzgdhpNisYf91y8M= X-Google-Smtp-Source: AA6agR7OlNTxfQwltuF+Hi99AvSWr+2e3r4Oau80QrBvP2Y3Sq/Q910RO7qI8DoNCv5ryQ9gLQQSHQ== X-Received: by 2002:a17:907:31c7:b0:740:e3e5:c025 with SMTP id xf7-20020a17090731c700b00740e3e5c025mr20682822ejb.341.1662049642951; Thu, 01 Sep 2022 09:27:22 -0700 (PDT) Received: from osoxes.fritz.box (p200300faaf0bb2009c4947838afc41b6.dip0.t-ipconnect.de. [2003:fa:af0b:b200:9c49:4783:8afc:41b6]) by smtp.gmail.com with ESMTPSA id p6-20020aa7d306000000b00447c0dcbb99sm1587672edq.83.2022.09.01.09.27.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Sep 2022 09:27:22 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Her?= =?utf-8?q?v=C3=A9_Poussineau?= , Aurelien Jarno , Paolo Bonzini , Eduardo Habkost , Richard Henderson , Jiaxun Yang , Ani Sinha , Igor Mammedov , Marcel Apfelbaum , "Michael S. Tsirkin" , Bernhard Beschow Subject: [PATCH 32/42] hw/isa/piix4: Rename wrongly named method Date: Thu, 1 Sep 2022 18:26:03 +0200 Message-Id: <20220901162613.6939-33-shentey@gmail.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220901162613.6939-1-shentey@gmail.com> References: <20220901162613.6939-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62c; envelope-from=shentey@gmail.com; helo=mail-ej1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" This method post-loads the southbridge, not the IDE device. Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daudé --- hw/isa/piix4.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index e682370887..72bd9ad74d 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -128,7 +128,7 @@ static void piix4_isa_reset(DeviceState *dev) d->rcr = 0; } -static int piix4_ide_post_load(void *opaque, int version_id) +static int piix4_post_load(void *opaque, int version_id) { PIIXState *s = opaque; @@ -143,7 +143,7 @@ static const VMStateDescription vmstate_piix4 = { .name = "PIIX4", .version_id = 3, .minimum_version_id = 2, - .post_load = piix4_ide_post_load, + .post_load = piix4_post_load, .fields = (VMStateField[]) { VMSTATE_PCI_DEVICE(dev, PIIXState), VMSTATE_UINT8_V(rcr, PIIXState, 3), From patchwork Thu Sep 1 16:26:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 12962930 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 043CDECAAD3 for ; Thu, 1 Sep 2022 16:51:55 +0000 (UTC) Received: from localhost ([::1]:43302 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oTnQ2-0000yd-Sa for qemu-devel@archiver.kernel.org; Thu, 01 Sep 2022 12:51:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37952) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oTn2R-0002Pd-Jt for qemu-devel@nongnu.org; Thu, 01 Sep 2022 12:27:32 -0400 Received: from mail-ed1-x534.google.com ([2a00:1450:4864:20::534]:38614) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oTn2N-0001YM-IF for qemu-devel@nongnu.org; Thu, 01 Sep 2022 12:27:31 -0400 Received: by mail-ed1-x534.google.com with SMTP id a36so19485947edf.5 for ; Thu, 01 Sep 2022 09:27:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=L2ZD0tf22k75Y60smdBIZGtimaHKATr8a5+W5rsYQ0M=; b=LDvzp45UD0Zry9SKWvo+q+B1QsrQydvy3lnPRPqEUz91kBPvOT6AvVzVXFVYKcViSt NSJdMZma3tHl9FWWS84jf9VevV+JHZUn6CNFt0GOTjq6Z7phsuDOkIKVsNi+WYTAqxcj DbZtKswv6NP9dQaq2lp1q409lvve+jtm/wtLiQAv07IX4xKVx8kt0ihMpSusunktQW8E DT94fjct+FJiXu2Ev+aac/T8C7OpdjMHUdht2zcacPFLipAUPh4qkZtVFRa+AkFfpLk+ n8iwPqWMFE8sSwklIOpG6sCTJ2K01J9cUZQmw2a9U2Rnts9PSBzFIT6aczrvV1f3rViE 5/kA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=L2ZD0tf22k75Y60smdBIZGtimaHKATr8a5+W5rsYQ0M=; b=OPwOAnxeTB2LjwmdMruTujfM1L1VF/4UqeUDkHgktnPGNW8f4U2NvsukqsNvZa+8VA w0VVry/WHcBuvqhtCr5+Gd8jqj9mixme2XPgVMr06PDNbdCtNJ9R1hjdc2JFbHaFcd7f 6zZtGOK2EbsB9EXu7klb8KsTRm/x/xhv8eqVsgqeRFzg24GH9osmdflr+jxAnJ0lis7X tEZWKM4zG7HPidW7kELm/SUY6QibwEL+9Wac8wynW+1pdctZIOHuJvgIXBFAbE0Jr9zH Mw9fOnKjDWFQJdE/yv0ggrBnpDzy5JGwcl3j4ClxBMj1k1UMpM9aIwTf5qy01yOb0C2Y 2fyQ== X-Gm-Message-State: ACgBeo0AJwHKkQK+XgizVTp0fGdIKgotpZ9asNriAh12UqfhSpdnNFiB nhrwItJPLJTJgf06NqwHemlyCwfos5o= X-Google-Smtp-Source: AA6agR7qkd0C2FOQlVFwR2kRRJOj/F5nB3wBXAWHZHS+JOfv2orxij4ev0sPjax5HwTVD2a31X3PeA== X-Received: by 2002:a05:6402:5ca:b0:43b:6e01:482c with SMTP id n10-20020a05640205ca00b0043b6e01482cmr30588799edx.189.1662049644163; Thu, 01 Sep 2022 09:27:24 -0700 (PDT) Received: from osoxes.fritz.box (p200300faaf0bb2009c4947838afc41b6.dip0.t-ipconnect.de. [2003:fa:af0b:b200:9c49:4783:8afc:41b6]) by smtp.gmail.com with ESMTPSA id p6-20020aa7d306000000b00447c0dcbb99sm1587672edq.83.2022.09.01.09.27.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Sep 2022 09:27:23 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Her?= =?utf-8?q?v=C3=A9_Poussineau?= , Aurelien Jarno , Paolo Bonzini , Eduardo Habkost , Richard Henderson , Jiaxun Yang , Ani Sinha , Igor Mammedov , Marcel Apfelbaum , "Michael S. Tsirkin" , Bernhard Beschow Subject: [PATCH 33/42] hw/isa/piix4: Prefix pci_slot_get_pirq() with "piix4_" Date: Thu, 1 Sep 2022 18:26:04 +0200 Message-Id: <20220901162613.6939-34-shentey@gmail.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220901162613.6939-1-shentey@gmail.com> References: <20220901162613.6939-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::534; envelope-from=shentey@gmail.com; helo=mail-ed1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Prefixing with "piix4_" makes the method distinguishable from its PIIX3 counterpart upon merging and also complies more with QEMU conventions. Signed-off-by: Bernhard Beschow --- hw/isa/piix4.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 72bd9ad74d..01a98990d6 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -62,7 +62,7 @@ static void piix4_set_irq(void *opaque, int irq_num, int level) } } -static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num) +static int piix4_pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num) { int slot; @@ -248,7 +248,8 @@ static void piix4_realize(PCIDevice *dev, Error **errp) qdev_get_gpio_in(DEVICE(&s->pic), 9)); } - pci_bus_irqs(pci_bus, piix4_set_irq, pci_slot_get_pirq, s, PIIX_NUM_PIRQS); + pci_bus_irqs(pci_bus, piix4_set_irq, piix4_pci_slot_get_pirq, s, + PIIX_NUM_PIRQS); } static void piix4_init(Object *obj) From patchwork Thu Sep 1 16:26:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 12962954 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 181E5ECAAD1 for ; Thu, 1 Sep 2022 17:17:06 +0000 (UTC) Received: from localhost ([::1]:38740 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oTnoP-0001BP-4a for qemu-devel@archiver.kernel.org; Thu, 01 Sep 2022 13:17:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37960) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oTn2T-0002QU-OJ for qemu-devel@nongnu.org; Thu, 01 Sep 2022 12:27:35 -0400 Received: from mail-ej1-x636.google.com ([2a00:1450:4864:20::636]:46765) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oTn2N-0001YY-Hr for qemu-devel@nongnu.org; Thu, 01 Sep 2022 12:27:31 -0400 Received: by mail-ej1-x636.google.com with SMTP id bj12so35786475ejb.13 for ; Thu, 01 Sep 2022 09:27:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=r8CbLyBqvRGT5fBomvg9jowjrWelJphzmCvCPXDNeJs=; b=CE/wQNeVr53HVcqdN2a3fhgxGHn00sVP/pPILpgR6zpKn0qnt2Zheywt63IRnPfstf coz87DL5ih0UD4QxsYixc5krpuBYPa9Hg2UNLBfgYMbwsJBPx6x/ff8pLr8b2tA3bcSW oQCCmq9urxRsdWHZzlaR78ZTzEL3fd3jqgn4ujoahSkXQ2pwlkQATFoow1Gd3OoqFKBn 5/cyBjgAZ9t9JsCv7v4aanDW3/Fdr/S0EPP3bCQ7IbED/05FBPP7J4A6U9JLn0fh5yOm CucD4uBl+aqQV7jbfwpEINVtIL1mZOrwse0qoBlXKZugdWbFbUYH/tY58fHFuT3We2Ac j3Cg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=r8CbLyBqvRGT5fBomvg9jowjrWelJphzmCvCPXDNeJs=; b=oYtSqt3b0EzxKTLL+eJ9nD2wU49/y2o5BllVOWLC+gBhFlftXFXWh+mI94H3JKeQHM Gb8UfiJJ9yQkPqzGn0P7/ZMWEMvOYACuUUiIF69JMig+T3pdZC7REoDNS1G1HJSb7bM6 YnlgbclGKe8fWaQgKF5WZFSLo5hTx3/NR9jU+fqqlUQtDl/8iBZ05Li4YMRiGj2UGt84 F5s11liJsUUOVO5nxrN1WkzKPrp2q5oUUrkmQm/lnXlQTfzTamW2Y89Tc/aWcOzo6BUk QlFO8MXpC7mCa7CwUOYeKfxhcGgA9//aquqms2QMKvtmMkpnrQOhfVLHI2GWon+lBxOV 3jbg== X-Gm-Message-State: ACgBeo3w00MBEajpYuMDcVADZJYmI/1wTn+8VhGJH9l39zdvvdY6TQ37 Rey9DWNfUnXaO0Bbb4JQ9FYoSVjnTsk= X-Google-Smtp-Source: AA6agR6dam5lJG+40/KAr0E2b5ojD+utVzQoT4QSEJNuyK3prpcMAsC2rojy1knbSiN9HfR3owPFNQ== X-Received: by 2002:a17:906:6a21:b0:741:430f:baca with SMTP id qw33-20020a1709066a2100b00741430fbacamr18935166ejc.507.1662049645424; Thu, 01 Sep 2022 09:27:25 -0700 (PDT) Received: from osoxes.fritz.box (p200300faaf0bb2009c4947838afc41b6.dip0.t-ipconnect.de. [2003:fa:af0b:b200:9c49:4783:8afc:41b6]) by smtp.gmail.com with ESMTPSA id p6-20020aa7d306000000b00447c0dcbb99sm1587672edq.83.2022.09.01.09.27.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Sep 2022 09:27:25 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Her?= =?utf-8?q?v=C3=A9_Poussineau?= , Aurelien Jarno , Paolo Bonzini , Eduardo Habkost , Richard Henderson , Jiaxun Yang , Ani Sinha , Igor Mammedov , Marcel Apfelbaum , "Michael S. Tsirkin" , Bernhard Beschow Subject: [PATCH 34/42] hw/isa/piix3: Merge hw/isa/piix4.c Date: Thu, 1 Sep 2022 18:26:05 +0200 Message-Id: <20220901162613.6939-35-shentey@gmail.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220901162613.6939-1-shentey@gmail.com> References: <20220901162613.6939-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::636; envelope-from=shentey@gmail.com; helo=mail-ej1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Now that the PIIX3 and PIIX4 device models are sufficiently consolidated Signed-off-by: Bernhard Beschow --- MAINTAINERS | 6 +- configs/devices/mips-softmmu/common.mak | 2 +- hw/i386/Kconfig | 2 +- hw/isa/Kconfig | 12 +- hw/isa/meson.build | 3 +- hw/isa/{piix3.c => piix.c} | 185 ++++++++++++++ hw/isa/piix4.c | 314 ------------------------ 7 files changed, 192 insertions(+), 332 deletions(-) rename hw/isa/{piix3.c => piix.c} (73%) delete mode 100644 hw/isa/piix4.c diff --git a/MAINTAINERS b/MAINTAINERS index 5ce4227ff6..f727f64a25 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1228,7 +1228,7 @@ Malta M: Philippe Mathieu-Daudé R: Aurelien Jarno S: Odd Fixes -F: hw/isa/piix4.c +F: hw/isa/piix.c F: hw/acpi/piix4.c F: hw/mips/malta.c F: hw/mips/gt64xxx_pci.c @@ -1643,7 +1643,7 @@ F: hw/pci-host/pam.c F: include/hw/pci-host/i440fx.h F: include/hw/pci-host/q35.h F: include/hw/pci-host/pam.h -F: hw/isa/piix3.c +F: hw/isa/piix.c F: hw/isa/lpc_ich9.c F: hw/i2c/smbus_ich9.c F: hw/acpi/piix4.c @@ -2302,7 +2302,7 @@ PIIX4 South Bridge (i82371AB) M: Hervé Poussineau M: Philippe Mathieu-Daudé S: Maintained -F: hw/isa/piix4.c +F: hw/isa/piix.c F: include/hw/southbridge/piix.h Firmware configuration (fw_cfg) diff --git a/configs/devices/mips-softmmu/common.mak b/configs/devices/mips-softmmu/common.mak index 416161f833..ef3b7390a6 100644 --- a/configs/devices/mips-softmmu/common.mak +++ b/configs/devices/mips-softmmu/common.mak @@ -21,7 +21,7 @@ CONFIG_ACPI=y CONFIG_ACPI_PIIX4=y CONFIG_APM=y CONFIG_I8257=y -CONFIG_PIIX4=y +CONFIG_PIIX=y CONFIG_IDE_ISA=y CONFIG_PFLASH_CFI01=y CONFIG_I8259=y diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig index dd247f215c..295693b32b 100644 --- a/hw/i386/Kconfig +++ b/hw/i386/Kconfig @@ -73,7 +73,7 @@ config I440FX select PC_ACPI select ACPI_SMBUS select PCI_I440FX - select PIIX3 + select PIIX select DIMM select SMBIOS select FW_CFG_DMA diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig index 1aa10f84f2..000c2312ab 100644 --- a/hw/isa/Kconfig +++ b/hw/isa/Kconfig @@ -31,17 +31,7 @@ config PC87312 select FDC_ISA select IDE_ISA -config PIIX3 - bool - select ACPI_PIIX4 - select I8257 - select I8259 - select IDE_PIIX - select ISA_BUS - select MC146818RTC - select USB_UHCI - -config PIIX4 +config PIIX bool # For historical reasons, SuperIO devices are created in the board # for PIIX4. diff --git a/hw/isa/meson.build b/hw/isa/meson.build index 8bf678ca0a..314bbd0860 100644 --- a/hw/isa/meson.build +++ b/hw/isa/meson.build @@ -3,8 +3,7 @@ softmmu_ss.add(when: 'CONFIG_I82378', if_true: files('i82378.c')) softmmu_ss.add(when: 'CONFIG_ISA_BUS', if_true: files('isa-bus.c')) softmmu_ss.add(when: 'CONFIG_ISA_SUPERIO', if_true: files('isa-superio.c')) softmmu_ss.add(when: 'CONFIG_PC87312', if_true: files('pc87312.c')) -softmmu_ss.add(when: 'CONFIG_PIIX3', if_true: files('piix3.c')) -softmmu_ss.add(when: 'CONFIG_PIIX4', if_true: files('piix4.c')) +softmmu_ss.add(when: 'CONFIG_PIIX', if_true: files('piix.c')) softmmu_ss.add(when: 'CONFIG_SMC37C669', if_true: files('smc37c669-superio.c')) softmmu_ss.add(when: 'CONFIG_VT82C686', if_true: files('vt82c686.c')) diff --git a/hw/isa/piix3.c b/hw/isa/piix.c similarity index 73% rename from hw/isa/piix3.c rename to hw/isa/piix.c index 75705a1fc1..5d3715b64e 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix.c @@ -2,6 +2,7 @@ * QEMU PIIX PCI ISA Bridge Emulation * * Copyright (c) 2006 Fabrice Bellard + * Copyright (c) 2018 Hervé Poussineau * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -26,7 +27,9 @@ #include "qemu/range.h" #include "qapi/error.h" #include "hw/dma/i8257.h" +#include "hw/intc/i8259.h" #include "hw/southbridge/piix.h" +#include "hw/timer/i8254.h" #include "hw/irq.h" #include "hw/qdev-properties.h" #include "hw/isa/isa.h" @@ -80,6 +83,27 @@ static void piix3_set_irq(void *opaque, int pirq, int level) piix3_set_irq_level(piix3, pirq, level); } +static void piix4_set_irq(void *opaque, int irq_num, int level) +{ + int i, pic_irq, pic_level; + PIIXState *s = opaque; + PCIBus *bus = pci_get_bus(&s->dev); + + /* now we change the pic irq level according to the piix irq mappings */ + /* XXX: optimize */ + pic_irq = s->dev.config[PIIX_PIRQCA + irq_num]; + if (pic_irq < ISA_NUM_IRQS) { + /* The pic level is the logical OR of all the PCI irqs mapped to it. */ + pic_level = 0; + for (i = 0; i < PIIX_NUM_PIRQS; i++) { + if (pic_irq == s->dev.config[PIIX_PIRQCA + i]) { + pic_level |= pci_bus_get_irq_level(bus, i); + } + } + qemu_set_irq(s->pic.in_irqs[pic_irq], pic_level); + } +} + /* * Return the global irq number corresponding to a given device irq * pin. We could also use the bus number to have a more precise mapping. @@ -91,6 +115,31 @@ static int piix3_pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx) return (pci_intx + slot_addend) & 3; } +static int piix4_pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num) +{ + int slot; + + slot = PCI_SLOT(pci_dev->devfn); + + switch (slot) { + /* PIIX4 USB */ + case 10: + return 3; + /* AMD 79C973 Ethernet */ + case 11: + return 1; + /* Crystal 4281 Sound */ + case 12: + return 2; + /* PCI slot 1 to 4 */ + case 18 ... 21: + return ((slot - 18) + irq_num) & 0x03; + /* Unknown device, don't do any translation */ + default: + return irq_num; + } +} + static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin) { PIIXState *piix3 = opaque; @@ -218,6 +267,17 @@ static int piix3_post_load(void *opaque, int version_id) return 0; } +static int piix4_post_load(void *opaque, int version_id) +{ + PIIXState *s = opaque; + + if (version_id == 2) { + s->rcr = 0; + } + + return 0; +} + static int piix3_pre_save(void *opaque) { int i; @@ -267,6 +327,17 @@ static const VMStateDescription vmstate_piix3 = { } }; +static const VMStateDescription vmstate_piix4 = { + .name = "PIIX4", + .version_id = 3, + .minimum_version_id = 2, + .post_load = piix4_post_load, + .fields = (VMStateField[]) { + VMSTATE_PCI_DEVICE(dev, PIIXState), + VMSTATE_UINT8_V(rcr, PIIXState, 3), + VMSTATE_END_OF_LIST() + } +}; static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len) { @@ -494,11 +565,125 @@ static const TypeInfo piix3_xen_info = { .class_init = piix3_xen_class_init, }; +static void piix4_realize(PCIDevice *dev, Error **errp) +{ + PIIXState *s = PIIX_PCI_DEVICE(dev); + PCIBus *pci_bus = pci_get_bus(dev); + ISABus *isa_bus; + + isa_bus = isa_bus_new(DEVICE(dev), pci_address_space(dev), + pci_address_space_io(dev), errp); + if (!isa_bus) { + return; + } + + memory_region_init_io(&s->rcr_mem, OBJECT(dev), &rcr_ops, s, + "reset-control", 1); + memory_region_add_subregion_overlap(pci_address_space_io(dev), + PIIX_RCR_IOPORT, &s->rcr_mem, 1); + + /* initialize i8259 pic */ + if (!qdev_realize(DEVICE(&s->pic), BUS(isa_bus), errp)) { + return; + } + + /* initialize ISA irqs */ + isa_bus_irqs(isa_bus, s->pic.in_irqs); + + /* initialize pit */ + i8254_pit_init(isa_bus, 0x40, 0, NULL); + + /* DMA */ + i8257_dma_init(isa_bus, 0); + + /* RTC */ + qdev_prop_set_int32(DEVICE(&s->rtc), "base_year", 2000); + if (!qdev_realize(DEVICE(&s->rtc), BUS(isa_bus), errp)) { + return; + } + s->rtc.irq = qdev_get_gpio_in(DEVICE(&s->pic), s->rtc.isairq); + + /* IDE */ + qdev_prop_set_int32(DEVICE(&s->ide), "addr", dev->devfn + 1); + if (!qdev_realize(DEVICE(&s->ide), BUS(pci_bus), errp)) { + return; + } + + /* USB */ + if (s->has_usb) { + object_initialize_child(OBJECT(dev), "uhci", &s->uhci, + "piix4-usb-uhci"); + qdev_prop_set_int32(DEVICE(&s->uhci), "addr", dev->devfn + 2); + if (!qdev_realize(DEVICE(&s->uhci), BUS(pci_bus), errp)) { + return; + } + } + + /* ACPI controller */ + if (s->has_acpi) { + object_initialize_child(OBJECT(s), "pm", &s->pm, TYPE_PIIX4_PM); + qdev_prop_set_int32(DEVICE(&s->pm), "addr", dev->devfn + 3); + qdev_prop_set_uint32(DEVICE(&s->pm), "smb_io_base", s->smb_io_base); + qdev_prop_set_bit(DEVICE(&s->pm), "smm-enabled", s->smm_enabled); + if (!qdev_realize(DEVICE(&s->pm), BUS(pci_bus), errp)) { + return; + } + qdev_connect_gpio_out(DEVICE(&s->pm), 0, + qdev_get_gpio_in(DEVICE(&s->pic), 9)); + } + + pci_bus_irqs(pci_bus, piix4_set_irq, piix4_pci_slot_get_pirq, s, + PIIX_NUM_PIRQS); +} + +static void piix4_init(Object *obj) +{ + PIIXState *s = PIIX_PCI_DEVICE(obj); + + object_initialize_child(obj, "pic", &s->pic, TYPE_ISA_PIC); + object_initialize_child(obj, "rtc", &s->rtc, TYPE_MC146818_RTC); + object_initialize_child(obj, "ide", &s->ide, "piix4-ide"); +} + +static void piix4_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); + + k->realize = piix4_realize; + k->vendor_id = PCI_VENDOR_ID_INTEL; + k->device_id = PCI_DEVICE_ID_INTEL_82371AB_0; + k->class_id = PCI_CLASS_BRIDGE_ISA; + dc->reset = piix_reset; + dc->desc = "ISA bridge"; + dc->vmsd = &vmstate_piix4; + /* + * Reason: part of PIIX4 southbridge, needs to be wired up, + * e.g. by mips_malta_init() + */ + dc->user_creatable = false; + dc->hotpluggable = false; + device_class_set_props(dc, pci_piix_props); +} + +static const TypeInfo piix4_info = { + .name = TYPE_PIIX4_PCI_DEVICE, + .parent = TYPE_PCI_DEVICE, + .instance_size = sizeof(PIIXState), + .instance_init = piix4_init, + .class_init = piix4_class_init, + .interfaces = (InterfaceInfo[]) { + { INTERFACE_CONVENTIONAL_PCI_DEVICE }, + { }, + }, +}; + static void piix3_register_types(void) { type_register_static(&piix3_pci_type_info); type_register_static(&piix3_info); type_register_static(&piix3_xen_info); + type_register_static(&piix4_info); } type_init(piix3_register_types) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c deleted file mode 100644 index 01a98990d6..0000000000 --- a/hw/isa/piix4.c +++ /dev/null @@ -1,314 +0,0 @@ -/* - * QEMU PIIX4 PCI Bridge Emulation - * - * Copyright (c) 2006 Fabrice Bellard - * Copyright (c) 2018 Hervé Poussineau - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "qemu/osdep.h" -#include "qapi/error.h" -#include "hw/irq.h" -#include "hw/southbridge/piix.h" -#include "hw/pci/pci.h" -#include "hw/isa/isa.h" -#include "hw/intc/i8259.h" -#include "hw/dma/i8257.h" -#include "hw/timer/i8254.h" -#include "hw/rtc/mc146818rtc.h" -#include "hw/ide/pci.h" -#include "hw/acpi/piix4.h" -#include "hw/usb/hcd-uhci.h" -#include "migration/vmstate.h" -#include "sysemu/reset.h" -#include "sysemu/runstate.h" -#include "qom/object.h" - -static void piix4_set_irq(void *opaque, int irq_num, int level) -{ - int i, pic_irq, pic_level; - PIIXState *s = opaque; - PCIBus *bus = pci_get_bus(&s->dev); - - /* now we change the pic irq level according to the piix irq mappings */ - /* XXX: optimize */ - pic_irq = s->dev.config[PIIX_PIRQCA + irq_num]; - if (pic_irq < ISA_NUM_IRQS) { - /* The pic level is the logical OR of all the PCI irqs mapped to it. */ - pic_level = 0; - for (i = 0; i < PIIX_NUM_PIRQS; i++) { - if (pic_irq == s->dev.config[PIIX_PIRQCA + i]) { - pic_level |= pci_bus_get_irq_level(bus, i); - } - } - qemu_set_irq(s->pic.in_irqs[pic_irq], pic_level); - } -} - -static int piix4_pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num) -{ - int slot; - - slot = PCI_SLOT(pci_dev->devfn); - - switch (slot) { - /* PIIX4 USB */ - case 10: - return 3; - /* AMD 79C973 Ethernet */ - case 11: - return 1; - /* Crystal 4281 Sound */ - case 12: - return 2; - /* PCI slot 1 to 4 */ - case 18 ... 21: - return ((slot - 18) + irq_num) & 0x03; - /* Unknown device, don't do any translation */ - default: - return irq_num; - } -} - -static void piix4_isa_reset(DeviceState *dev) -{ - PIIXState *d = PIIX_PCI_DEVICE(dev); - uint8_t *pci_conf = d->dev.config; - - pci_conf[0x04] = 0x07; // master, memory and I/O - pci_conf[0x05] = 0x00; - pci_conf[0x06] = 0x00; - pci_conf[0x07] = 0x02; // PCI_status_devsel_medium - pci_conf[0x4c] = 0x4d; - pci_conf[0x4e] = 0x03; - pci_conf[0x4f] = 0x00; - pci_conf[PIIX_PIRQCA] = d->pci_irq_reset_mappings[0]; - pci_conf[PIIX_PIRQCB] = d->pci_irq_reset_mappings[1]; - pci_conf[PIIX_PIRQCC] = d->pci_irq_reset_mappings[2]; - pci_conf[PIIX_PIRQCD] = d->pci_irq_reset_mappings[3]; - pci_conf[0x69] = 0x02; - pci_conf[0x70] = 0x80; - pci_conf[0x76] = 0x0c; - pci_conf[0x77] = 0x0c; - pci_conf[0x78] = 0x02; - pci_conf[0x79] = 0x00; - pci_conf[0x80] = 0x00; - pci_conf[0x82] = 0x00; - pci_conf[0xa0] = 0x08; - pci_conf[0xa2] = 0x00; - pci_conf[0xa3] = 0x00; - pci_conf[0xa4] = 0x00; - pci_conf[0xa5] = 0x00; - pci_conf[0xa6] = 0x00; - pci_conf[0xa7] = 0x00; - pci_conf[0xa8] = 0x0f; - pci_conf[0xaa] = 0x00; - pci_conf[0xab] = 0x00; - pci_conf[0xac] = 0x00; - pci_conf[0xae] = 0x00; - - d->pic_levels = 0; /* not used in PIIX4 */ - d->rcr = 0; -} - -static int piix4_post_load(void *opaque, int version_id) -{ - PIIXState *s = opaque; - - if (version_id == 2) { - s->rcr = 0; - } - - return 0; -} - -static const VMStateDescription vmstate_piix4 = { - .name = "PIIX4", - .version_id = 3, - .minimum_version_id = 2, - .post_load = piix4_post_load, - .fields = (VMStateField[]) { - VMSTATE_PCI_DEVICE(dev, PIIXState), - VMSTATE_UINT8_V(rcr, PIIXState, 3), - VMSTATE_END_OF_LIST() - } -}; - -static void rcr_write(void *opaque, hwaddr addr, uint64_t val, - unsigned int len) -{ - PIIXState *s = opaque; - - if (val & 4) { - qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); - return; - } - - s->rcr = val & 2; /* keep System Reset type only */ -} - -static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned int len) -{ - PIIXState *s = opaque; - - return s->rcr; -} - -static const MemoryRegionOps rcr_ops = { - .read = rcr_read, - .write = rcr_write, - .endianness = DEVICE_LITTLE_ENDIAN, - .impl = { - .min_access_size = 1, - .max_access_size = 1, - }, -}; - -static void piix4_realize(PCIDevice *dev, Error **errp) -{ - PIIXState *s = PIIX_PCI_DEVICE(dev); - PCIBus *pci_bus = pci_get_bus(dev); - ISABus *isa_bus; - - isa_bus = isa_bus_new(DEVICE(dev), pci_address_space(dev), - pci_address_space_io(dev), errp); - if (!isa_bus) { - return; - } - - memory_region_init_io(&s->rcr_mem, OBJECT(dev), &rcr_ops, s, - "reset-control", 1); - memory_region_add_subregion_overlap(pci_address_space_io(dev), - PIIX_RCR_IOPORT, &s->rcr_mem, 1); - - /* initialize i8259 pic */ - if (!qdev_realize(DEVICE(&s->pic), BUS(isa_bus), errp)) { - return; - } - - /* initialize ISA irqs */ - isa_bus_irqs(isa_bus, s->pic.in_irqs); - - /* initialize pit */ - i8254_pit_init(isa_bus, 0x40, 0, NULL); - - /* DMA */ - i8257_dma_init(isa_bus, 0); - - /* RTC */ - qdev_prop_set_int32(DEVICE(&s->rtc), "base_year", 2000); - if (!qdev_realize(DEVICE(&s->rtc), BUS(isa_bus), errp)) { - return; - } - s->rtc.irq = qdev_get_gpio_in(DEVICE(&s->pic), s->rtc.isairq); - - /* IDE */ - qdev_prop_set_int32(DEVICE(&s->ide), "addr", dev->devfn + 1); - if (!qdev_realize(DEVICE(&s->ide), BUS(pci_bus), errp)) { - return; - } - - /* USB */ - if (s->has_usb) { - object_initialize_child(OBJECT(dev), "uhci", &s->uhci, - "piix4-usb-uhci"); - qdev_prop_set_int32(DEVICE(&s->uhci), "addr", dev->devfn + 2); - if (!qdev_realize(DEVICE(&s->uhci), BUS(pci_bus), errp)) { - return; - } - } - - /* ACPI controller */ - if (s->has_acpi) { - object_initialize_child(OBJECT(s), "pm", &s->pm, TYPE_PIIX4_PM); - qdev_prop_set_int32(DEVICE(&s->pm), "addr", dev->devfn + 3); - qdev_prop_set_uint32(DEVICE(&s->pm), "smb_io_base", s->smb_io_base); - qdev_prop_set_bit(DEVICE(&s->pm), "smm-enabled", s->smm_enabled); - if (!qdev_realize(DEVICE(&s->pm), BUS(pci_bus), errp)) { - return; - } - qdev_connect_gpio_out(DEVICE(&s->pm), 0, - qdev_get_gpio_in(DEVICE(&s->pic), 9)); - } - - pci_bus_irqs(pci_bus, piix4_set_irq, piix4_pci_slot_get_pirq, s, - PIIX_NUM_PIRQS); -} - -static void piix4_init(Object *obj) -{ - PIIXState *s = PIIX_PCI_DEVICE(obj); - - object_initialize_child(obj, "pic", &s->pic, TYPE_ISA_PIC); - object_initialize_child(obj, "rtc", &s->rtc, TYPE_MC146818_RTC); - object_initialize_child(obj, "ide", &s->ide, "piix4-ide"); -} - -static Property piix4_props[] = { - DEFINE_PROP_UINT32("smb_io_base", PIIXState, smb_io_base, 0), - DEFINE_PROP_UINT8("pirqa", PIIXState, pci_irq_reset_mappings[0], 0x80), - DEFINE_PROP_UINT8("pirqb", PIIXState, pci_irq_reset_mappings[1], 0x80), - DEFINE_PROP_UINT8("pirqc", PIIXState, pci_irq_reset_mappings[2], 0x80), - DEFINE_PROP_UINT8("pirqd", PIIXState, pci_irq_reset_mappings[3], 0x80), - DEFINE_PROP_BOOL("has-acpi", PIIXState, has_acpi, true), - DEFINE_PROP_BOOL("has-usb", PIIXState, has_usb, true), - DEFINE_PROP_BOOL("smm-enabled", PIIXState, smm_enabled, false), - DEFINE_PROP_END_OF_LIST(), -}; - -static void piix4_class_init(ObjectClass *klass, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(klass); - PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); - - k->realize = piix4_realize; - k->vendor_id = PCI_VENDOR_ID_INTEL; - k->device_id = PCI_DEVICE_ID_INTEL_82371AB_0; - k->class_id = PCI_CLASS_BRIDGE_ISA; - dc->reset = piix4_isa_reset; - dc->desc = "ISA bridge"; - dc->vmsd = &vmstate_piix4; - /* - * Reason: part of PIIX4 southbridge, needs to be wired up, - * e.g. by mips_malta_init() - */ - dc->user_creatable = false; - dc->hotpluggable = false; - device_class_set_props(dc, piix4_props); -} - -static const TypeInfo piix4_info = { - .name = TYPE_PIIX4_PCI_DEVICE, - .parent = TYPE_PCI_DEVICE, - .instance_size = sizeof(PIIXState), - .instance_init = piix4_init, - .class_init = piix4_class_init, - .interfaces = (InterfaceInfo[]) { - { INTERFACE_CONVENTIONAL_PCI_DEVICE }, - { }, - }, -}; - -static void piix4_register_types(void) -{ - type_register_static(&piix4_info); -} - -type_init(piix4_register_types) From patchwork Thu Sep 1 16:26:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 12962940 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 166EDECAAD3 for ; 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[2003:fa:af0b:b200:9c49:4783:8afc:41b6]) by smtp.gmail.com with ESMTPSA id p6-20020aa7d306000000b00447c0dcbb99sm1587672edq.83.2022.09.01.09.27.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Sep 2022 09:27:26 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Her?= =?utf-8?q?v=C3=A9_Poussineau?= , Aurelien Jarno , Paolo Bonzini , Eduardo Habkost , Richard Henderson , Jiaxun Yang , Ani Sinha , Igor Mammedov , Marcel Apfelbaum , "Michael S. Tsirkin" , Bernhard Beschow Subject: [PATCH 35/42] hw/isa/piix: Harmonize names of reset control memory regions Date: Thu, 1 Sep 2022 18:26:06 +0200 Message-Id: <20220901162613.6939-36-shentey@gmail.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220901162613.6939-1-shentey@gmail.com> References: <20220901162613.6939-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62c; envelope-from=shentey@gmail.com; helo=mail-ej1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" There is no need for having different names here. Having the same name further allows code to be shared between PIIX3 and PIIX4. Signed-off-by: Bernhard Beschow --- hw/isa/piix.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/isa/piix.c b/hw/isa/piix.c index 5d3715b64e..ba7b5d953f 100644 --- a/hw/isa/piix.c +++ b/hw/isa/piix.c @@ -387,7 +387,7 @@ static void pci_piix3_realize(PCIDevice *dev, Error **errp) isa_bus_irqs(isa_bus, d->pic.in_irqs); memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d, - "piix3-reset-control", 1); + "piix-reset-control", 1); memory_region_add_subregion_overlap(pci_address_space_io(dev), PIIX_RCR_IOPORT, &d->rcr_mem, 1); @@ -578,7 +578,7 @@ static void piix4_realize(PCIDevice *dev, Error **errp) } memory_region_init_io(&s->rcr_mem, OBJECT(dev), &rcr_ops, s, - "reset-control", 1); + "piix-reset-control", 1); memory_region_add_subregion_overlap(pci_address_space_io(dev), PIIX_RCR_IOPORT, &s->rcr_mem, 1); From patchwork Thu Sep 1 16:26:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 12962934 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EC8C2ECAAD3 for ; Thu, 1 Sep 2022 16:54:17 +0000 (UTC) Received: from localhost ([::1]:52834 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oTnSL-0006eY-3w for qemu-devel@archiver.kernel.org; Thu, 01 Sep 2022 12:54:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37958) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oTn2T-0002QT-O8 for qemu-devel@nongnu.org; Thu, 01 Sep 2022 12:27:34 -0400 Received: from mail-ej1-x62f.google.com ([2a00:1450:4864:20::62f]:37782) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oTn2P-0001Z8-DL for qemu-devel@nongnu.org; Thu, 01 Sep 2022 12:27:32 -0400 Received: by mail-ej1-x62f.google.com with SMTP id nc14so30900222ejc.4 for ; Thu, 01 Sep 2022 09:27:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=HzrQWtSAwlp+S9qVoXjmvjfRbi8mzDnTXp4Tg8p4Ky0=; b=EfcGc/bg+axUAZqy+5eqzeOO3QiJr1z/mW/aZeH03jR5yAODd3pEBroa/i1RmQ1byH +xqxxaquk78cmcPrwjlKyEwtdDLCECVOH5usDXPKBVoIC4VBA5AdboS0sng69uXiJvOQ TzmB8kF7E8sO3/WuHd+MIDYsKy2IcKt7V2CCbRoje7cBBSdMgVeDrZN/ONcUCr8G+LBS PGmzoIUG/XP9og1RMN00USPeHYNU/aud5vlLyW2GuRevF/jaDtXSGKvoMEGP0pkQ70km 9NaqZH3kMDD1obMLXtc/+jJxLyVuRvBN924TOJKBIy9z4LZY1rwcN9dzfurQ11nuUSyU JgHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=HzrQWtSAwlp+S9qVoXjmvjfRbi8mzDnTXp4Tg8p4Ky0=; b=pBhoDeM+noC6RBPtxAv3DNqgB4aFCtUGTDRFb1p71xUZHFM1rHEcVS4i19zQOouu3U TSJbSZH7YHQ5Rlk8ag72E7LxjmNmc1mPsqZ8IhWMmnSC5mtJcNgo8VYbKyYIvFpg54Bi 79Oy4vA5Z99uBbm0+9m6tILG/ddPjBEAIXD039s5X+qKRQqiVqtBv7Fx5frnPtDcwibS RH2/5KMuRsjToreWpk5+F3XqUuQHtWCJQQj2DEKGz4IHsuUOAwPeG0ufacg7+DqbkHuY jU+A9FSxJcP1diedXWqHnd979Nw2JbRYVvcGw5rNGoPOLTljo0mkSM0On7AcDKTvbIis 28yQ== X-Gm-Message-State: ACgBeo1ZODrkysLS74mex/lmzLXx+N5ttZp1USxwywHbGlMyVgaEfOGs hUIoR+pDDgefptNfPkNbaHpI8s8ZQO0= X-Google-Smtp-Source: AA6agR7KAbAIZYgshVgKFOiAiteyZUThk8dGgTakYcleRFM2UPzaNRcbEfqoWxasksCtamhAriv8OQ== X-Received: by 2002:a17:907:8a14:b0:731:2198:627b with SMTP id sc20-20020a1709078a1400b007312198627bmr24515600ejc.635.1662049647397; Thu, 01 Sep 2022 09:27:27 -0700 (PDT) Received: from osoxes.fritz.box (p200300faaf0bb2009c4947838afc41b6.dip0.t-ipconnect.de. [2003:fa:af0b:b200:9c49:4783:8afc:41b6]) by smtp.gmail.com with ESMTPSA id p6-20020aa7d306000000b00447c0dcbb99sm1587672edq.83.2022.09.01.09.27.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Sep 2022 09:27:27 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Her?= =?utf-8?q?v=C3=A9_Poussineau?= , Aurelien Jarno , Paolo Bonzini , Eduardo Habkost , Richard Henderson , Jiaxun Yang , Ani Sinha , Igor Mammedov , Marcel Apfelbaum , "Michael S. Tsirkin" , Bernhard Beschow Subject: [PATCH 36/42] hw/isa/piix: Reuse PIIX3 base class' realize method in PIIX4 Date: Thu, 1 Sep 2022 18:26:07 +0200 Message-Id: <20220901162613.6939-37-shentey@gmail.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220901162613.6939-1-shentey@gmail.com> References: <20220901162613.6939-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=shentey@gmail.com; helo=mail-ej1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Resolves duplicate code. Signed-off-by: Bernhard Beschow --- hw/isa/piix.c | 65 +++++++-------------------------------------------- 1 file changed, 9 insertions(+), 56 deletions(-) diff --git a/hw/isa/piix.c b/hw/isa/piix.c index ba7b5d953f..af6d920eff 100644 --- a/hw/isa/piix.c +++ b/hw/isa/piix.c @@ -367,7 +367,8 @@ static const MemoryRegionOps rcr_ops = { }, }; -static void pci_piix3_realize(PCIDevice *dev, Error **errp) +static void pci_piix_realize(PCIDevice *dev, const char *uhci_type, + Error **errp) { PIIXState *d = PIIX_PCI_DEVICE(dev); PCIBus *pci_bus = pci_get_bus(dev); @@ -407,8 +408,7 @@ static void pci_piix3_realize(PCIDevice *dev, Error **errp) /* USB */ if (d->has_usb) { - object_initialize_child(OBJECT(dev), "uhci", &d->uhci, - "piix3-usb-uhci"); + object_initialize_child(OBJECT(dev), "uhci", &d->uhci, uhci_type); qdev_prop_set_int32(DEVICE(&d->uhci), "addr", dev->devfn + 2); if (!qdev_realize(DEVICE(&d->uhci), BUS(pci_bus), errp)) { return; @@ -506,7 +506,7 @@ static void piix3_realize(PCIDevice *dev, Error **errp) PIIXState *piix3 = PIIX_PCI_DEVICE(dev); PCIBus *pci_bus = pci_get_bus(dev); - pci_piix3_realize(dev, errp); + pci_piix_realize(dev, "piix3-usb-uhci", errp); if (*errp) { return; } @@ -536,7 +536,7 @@ static void piix3_xen_realize(PCIDevice *dev, Error **errp) PIIXState *piix3 = PIIX_PCI_DEVICE(dev); PCIBus *pci_bus = pci_get_bus(dev); - pci_piix3_realize(dev, errp); + pci_piix_realize(dev, "piix3-usb-uhci", errp); if (*errp) { return; } @@ -567,71 +567,24 @@ static const TypeInfo piix3_xen_info = { static void piix4_realize(PCIDevice *dev, Error **errp) { + ERRP_GUARD(); PIIXState *s = PIIX_PCI_DEVICE(dev); PCIBus *pci_bus = pci_get_bus(dev); ISABus *isa_bus; - isa_bus = isa_bus_new(DEVICE(dev), pci_address_space(dev), - pci_address_space_io(dev), errp); - if (!isa_bus) { - return; - } - - memory_region_init_io(&s->rcr_mem, OBJECT(dev), &rcr_ops, s, - "piix-reset-control", 1); - memory_region_add_subregion_overlap(pci_address_space_io(dev), - PIIX_RCR_IOPORT, &s->rcr_mem, 1); - - /* initialize i8259 pic */ - if (!qdev_realize(DEVICE(&s->pic), BUS(isa_bus), errp)) { + pci_piix_realize(dev, "piix4-usb-uhci", errp); + if (*errp) { return; } - /* initialize ISA irqs */ - isa_bus_irqs(isa_bus, s->pic.in_irqs); + isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(dev), "isa.0")); /* initialize pit */ i8254_pit_init(isa_bus, 0x40, 0, NULL); - /* DMA */ - i8257_dma_init(isa_bus, 0); - /* RTC */ - qdev_prop_set_int32(DEVICE(&s->rtc), "base_year", 2000); - if (!qdev_realize(DEVICE(&s->rtc), BUS(isa_bus), errp)) { - return; - } s->rtc.irq = qdev_get_gpio_in(DEVICE(&s->pic), s->rtc.isairq); - /* IDE */ - qdev_prop_set_int32(DEVICE(&s->ide), "addr", dev->devfn + 1); - if (!qdev_realize(DEVICE(&s->ide), BUS(pci_bus), errp)) { - return; - } - - /* USB */ - if (s->has_usb) { - object_initialize_child(OBJECT(dev), "uhci", &s->uhci, - "piix4-usb-uhci"); - qdev_prop_set_int32(DEVICE(&s->uhci), "addr", dev->devfn + 2); - if (!qdev_realize(DEVICE(&s->uhci), BUS(pci_bus), errp)) { - return; - } - } - - /* ACPI controller */ - if (s->has_acpi) { - object_initialize_child(OBJECT(s), "pm", &s->pm, TYPE_PIIX4_PM); - qdev_prop_set_int32(DEVICE(&s->pm), "addr", dev->devfn + 3); - qdev_prop_set_uint32(DEVICE(&s->pm), "smb_io_base", s->smb_io_base); - qdev_prop_set_bit(DEVICE(&s->pm), "smm-enabled", s->smm_enabled); - if (!qdev_realize(DEVICE(&s->pm), BUS(pci_bus), errp)) { - return; - } - qdev_connect_gpio_out(DEVICE(&s->pm), 0, - qdev_get_gpio_in(DEVICE(&s->pic), 9)); - } - pci_bus_irqs(pci_bus, piix4_set_irq, piix4_pci_slot_get_pirq, s, PIIX_NUM_PIRQS); } From patchwork Thu Sep 1 16:26:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 12962955 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DDE16ECAAD1 for ; Thu, 1 Sep 2022 17:18:29 +0000 (UTC) Received: from localhost ([::1]:44054 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oTnpk-0002yn-Vq for qemu-devel@archiver.kernel.org; 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[2003:fa:af0b:b200:9c49:4783:8afc:41b6]) by smtp.gmail.com with ESMTPSA id p6-20020aa7d306000000b00447c0dcbb99sm1587672edq.83.2022.09.01.09.27.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Sep 2022 09:27:28 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Her?= =?utf-8?q?v=C3=A9_Poussineau?= , Aurelien Jarno , Paolo Bonzini , Eduardo Habkost , Richard Henderson , Jiaxun Yang , Ani Sinha , Igor Mammedov , Marcel Apfelbaum , "Michael S. Tsirkin" , Bernhard Beschow Subject: [PATCH 37/42] hw/isa/piix: Rename functions to be shared for interrupt triggering Date: Thu, 1 Sep 2022 18:26:08 +0200 Message-Id: <20220901162613.6939-38-shentey@gmail.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220901162613.6939-1-shentey@gmail.com> References: <20220901162613.6939-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::631; envelope-from=shentey@gmail.com; helo=mail-ej1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" PIIX4 will get the same optimizations which are already implemented for PIIX3. Signed-off-by: Bernhard Beschow --- hw/isa/piix.c | 56 +++++++++++++++++++++++++-------------------------- 1 file changed, 28 insertions(+), 28 deletions(-) diff --git a/hw/isa/piix.c b/hw/isa/piix.c index af6d920eff..1d516de5cc 100644 --- a/hw/isa/piix.c +++ b/hw/isa/piix.c @@ -40,47 +40,47 @@ #define XEN_PIIX_NUM_PIRQS 128ULL -static void piix3_set_irq_pic(PIIXState *piix3, int pic_irq) +static void piix_set_irq_pic(PIIXState *piix, int pic_irq) { - qemu_set_irq(piix3->pic.in_irqs[pic_irq], - !!(piix3->pic_levels & + qemu_set_irq(piix->pic.in_irqs[pic_irq], + !!(piix->pic_levels & (((1ULL << PIIX_NUM_PIRQS) - 1) << (pic_irq * PIIX_NUM_PIRQS)))); } -static void piix3_set_irq_level_internal(PIIXState *piix3, int pirq, int level) +static void piix_set_irq_level_internal(PIIXState *piix, int pirq, int level) { int pic_irq; uint64_t mask; - pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq]; + pic_irq = piix->dev.config[PIIX_PIRQCA + pirq]; if (pic_irq >= ISA_NUM_IRQS) { return; } mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq); - piix3->pic_levels &= ~mask; - piix3->pic_levels |= mask * !!level; + piix->pic_levels &= ~mask; + piix->pic_levels |= mask * !!level; } -static void piix3_set_irq_level(PIIXState *piix3, int pirq, int level) +static void piix_set_irq_level(PIIXState *piix, int pirq, int level) { int pic_irq; - pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq]; + pic_irq = piix->dev.config[PIIX_PIRQCA + pirq]; if (pic_irq >= ISA_NUM_IRQS) { return; } - piix3_set_irq_level_internal(piix3, pirq, level); + piix_set_irq_level_internal(piix, pirq, level); - piix3_set_irq_pic(piix3, pic_irq); + piix_set_irq_pic(piix, pic_irq); } -static void piix3_set_irq(void *opaque, int pirq, int level) +static void piix_set_irq(void *opaque, int pirq, int level) { - PIIXState *piix3 = opaque; - piix3_set_irq_level(piix3, pirq, level); + PIIXState *piix = opaque; + piix_set_irq_level(piix, pirq, level); } static void piix4_set_irq(void *opaque, int irq_num, int level) @@ -157,29 +157,29 @@ static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin) } /* irq routing is changed. so rebuild bitmap */ -static void piix3_update_irq_levels(PIIXState *piix3) +static void piix_update_irq_levels(PIIXState *piix) { - PCIBus *bus = pci_get_bus(&piix3->dev); + PCIBus *bus = pci_get_bus(&piix->dev); int pirq; - piix3->pic_levels = 0; + piix->pic_levels = 0; for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) { - piix3_set_irq_level(piix3, pirq, pci_bus_get_irq_level(bus, pirq)); + piix_set_irq_level(piix, pirq, pci_bus_get_irq_level(bus, pirq)); } } -static void piix3_write_config(PCIDevice *dev, - uint32_t address, uint32_t val, int len) +static void piix_write_config(PCIDevice *dev, uint32_t address, uint32_t val, + int len) { pci_default_write_config(dev, address, val, len); if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) { - PIIXState *piix3 = PIIX_PCI_DEVICE(dev); + PIIXState *piix = PIIX_PCI_DEVICE(dev); int pic_irq; - pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix3->dev)); - piix3_update_irq_levels(piix3); + pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix->dev)); + piix_update_irq_levels(piix); for (pic_irq = 0; pic_irq < ISA_NUM_IRQS; pic_irq++) { - piix3_set_irq_pic(piix3, pic_irq); + piix_set_irq_pic(piix, pic_irq); } } } @@ -201,7 +201,7 @@ static void piix3_write_config_xen(PCIDevice *dev, } } - piix3_write_config(dev, address, val, len); + piix_write_config(dev, address, val, len); } static void piix_reset(DeviceState *dev) @@ -261,7 +261,7 @@ static int piix3_post_load(void *opaque, int version_id) */ piix3->pic_levels = 0; for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) { - piix3_set_irq_level_internal(piix3, pirq, + piix_set_irq_level_internal(piix3, pirq, pci_bus_get_irq_level(pci_get_bus(&piix3->dev), pirq)); } return 0; @@ -511,7 +511,7 @@ static void piix3_realize(PCIDevice *dev, Error **errp) return; } - pci_bus_irqs(pci_bus, piix3_set_irq, piix3_pci_slot_get_pirq, + pci_bus_irqs(pci_bus, piix_set_irq, piix3_pci_slot_get_pirq, piix3, PIIX_NUM_PIRQS); pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq); } @@ -520,7 +520,7 @@ static void piix3_class_init(ObjectClass *klass, void *data) { PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); - k->config_write = piix3_write_config; + k->config_write = piix_write_config; k->realize = piix3_realize; } From patchwork Thu Sep 1 16:26:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 12962947 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0771AECAAD3 for ; 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[2003:fa:af0b:b200:9c49:4783:8afc:41b6]) by smtp.gmail.com with ESMTPSA id p6-20020aa7d306000000b00447c0dcbb99sm1587672edq.83.2022.09.01.09.27.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Sep 2022 09:27:29 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Her?= =?utf-8?q?v=C3=A9_Poussineau?= , Aurelien Jarno , Paolo Bonzini , Eduardo Habkost , Richard Henderson , Jiaxun Yang , Ani Sinha , Igor Mammedov , Marcel Apfelbaum , "Michael S. Tsirkin" , Bernhard Beschow Subject: [PATCH 38/42] hw/isa/piix: Consolidate IRQ triggering Date: Thu, 1 Sep 2022 18:26:09 +0200 Message-Id: <20220901162613.6939-39-shentey@gmail.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220901162613.6939-1-shentey@gmail.com> References: <20220901162613.6939-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::634; envelope-from=shentey@gmail.com; helo=mail-ej1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Speeds up PIIX4 which resolves an old TODO. Signed-off-by: Bernhard Beschow --- hw/isa/piix.c | 26 +++----------------------- 1 file changed, 3 insertions(+), 23 deletions(-) diff --git a/hw/isa/piix.c b/hw/isa/piix.c index 1d516de5cc..e413d7e792 100644 --- a/hw/isa/piix.c +++ b/hw/isa/piix.c @@ -83,27 +83,6 @@ static void piix_set_irq(void *opaque, int pirq, int level) piix_set_irq_level(piix, pirq, level); } -static void piix4_set_irq(void *opaque, int irq_num, int level) -{ - int i, pic_irq, pic_level; - PIIXState *s = opaque; - PCIBus *bus = pci_get_bus(&s->dev); - - /* now we change the pic irq level according to the piix irq mappings */ - /* XXX: optimize */ - pic_irq = s->dev.config[PIIX_PIRQCA + irq_num]; - if (pic_irq < ISA_NUM_IRQS) { - /* The pic level is the logical OR of all the PCI irqs mapped to it. */ - pic_level = 0; - for (i = 0; i < PIIX_NUM_PIRQS; i++) { - if (pic_irq == s->dev.config[PIIX_PIRQCA + i]) { - pic_level |= pci_bus_get_irq_level(bus, i); - } - } - qemu_set_irq(s->pic.in_irqs[pic_irq], pic_level); - } -} - /* * Return the global irq number corresponding to a given device irq * pin. We could also use the bus number to have a more precise mapping. @@ -275,7 +254,7 @@ static int piix4_post_load(void *opaque, int version_id) s->rcr = 0; } - return 0; + return piix3_post_load(opaque, version_id); } static int piix3_pre_save(void *opaque) @@ -585,7 +564,7 @@ static void piix4_realize(PCIDevice *dev, Error **errp) /* RTC */ s->rtc.irq = qdev_get_gpio_in(DEVICE(&s->pic), s->rtc.isairq); - pci_bus_irqs(pci_bus, piix4_set_irq, piix4_pci_slot_get_pirq, s, + pci_bus_irqs(pci_bus, piix_set_irq, piix4_pci_slot_get_pirq, s, PIIX_NUM_PIRQS); } @@ -603,6 +582,7 @@ static void piix4_class_init(ObjectClass *klass, void *data) DeviceClass *dc = DEVICE_CLASS(klass); PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); + k->config_write = piix_write_config; k->realize = piix4_realize; k->vendor_id = PCI_VENDOR_ID_INTEL; k->device_id = PCI_DEVICE_ID_INTEL_82371AB_0; From patchwork Thu Sep 1 16:26:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 12962956 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 86428ECAAD3 for ; Thu, 1 Sep 2022 17:19:44 +0000 (UTC) Received: from localhost ([::1]:45272 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oTnqx-0004XD-Ke for qemu-devel@archiver.kernel.org; Thu, 01 Sep 2022 13:19:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51128) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oTn2Z-0002R7-U6 for qemu-devel@nongnu.org; Thu, 01 Sep 2022 12:27:43 -0400 Received: from mail-ej1-x62a.google.com ([2a00:1450:4864:20::62a]:45001) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oTn2T-0001Zn-FT for qemu-devel@nongnu.org; Thu, 01 Sep 2022 12:27:36 -0400 Received: by mail-ej1-x62a.google.com with SMTP id kk26so35781874ejc.11 for ; Thu, 01 Sep 2022 09:27:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=EYL1ArUXnBEDKheHV+RJi2vAyx0SKvcQH3qkVL+XdAA=; b=Ls8KsdDNf0XIVNsyGYKFhWiU1jlIxUHCl+qzcZflwuB62gWmN7NT+JtGyySK/tuHyX t9FzVoj1BwzCj133FB3U9RTNbLGuop5Olb0CkbFJ/BMHEskS7w1jhHgxTl9VYGlajNUF YfIutBWN5DWQRlDVfNkCAmOrKFU7eUiaCPjr63lQD7Lva0jxoo712Uif+dWbYllW6jk6 mjBqDIYV+z7PErgcaZdmY0p6aNiwMmSWTxOXZix3TI7xilFRBVnl79gkuXfA0LQPeYyx yEEBQw9gwmYbPl6dZx9HeOxUOgJRdPFOziP8YxL4pZ2QbFtMgyTUOHnKWeH4GrU9U2nT lOyw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=EYL1ArUXnBEDKheHV+RJi2vAyx0SKvcQH3qkVL+XdAA=; b=2jFywaot3LRQCZIvTVPAX6/E9EYfXg1iVHRci4/xSr55P/kYmpyKftu4iTZRrxmN8n ec7SVapaUqAwl77UeoStTyCYEkMJ7yjPFEIQTF1zb81AldCy+k4afMkZGGjFTZm07b46 GZ14i3XAW+vWiIUVWBx155hE2WZrwctxOmi7MzUnVQTQtITVm02PQuc+e+z+wKZAI2Tn cxyLrfMTrl/LS0Uzx7ORDQ/YqvmAqYWzJBMRkLWWQjqXoeX/wzxIFK2nv/0GscNmMLLn dB/v/iNxyraaH8dTrIA96rWmGOESsTpb1VBf+f/xGxDDXXjYkvy+nSCwZEouL25cJVur JcoA== X-Gm-Message-State: ACgBeo1DOIK2w0r8mMHA+xYpLdHuTglW9RdM7w9e6UcrWFWxfsR1iuGe 9vU4ug9Sz02GU4xpwn9LcBLi4dzvzuE= X-Google-Smtp-Source: AA6agR7vIgdUhVhnZyQp0IVBg0FU3xZVrEouW00VA4N3q5vLqNyCfKs1JaMKIdAWx3FpZXHbNsjxjA== X-Received: by 2002:a17:906:7315:b0:741:5b1b:920d with SMTP id di21-20020a170906731500b007415b1b920dmr16667089ejc.484.1662049650467; Thu, 01 Sep 2022 09:27:30 -0700 (PDT) Received: from osoxes.fritz.box (p200300faaf0bb2009c4947838afc41b6.dip0.t-ipconnect.de. [2003:fa:af0b:b200:9c49:4783:8afc:41b6]) by smtp.gmail.com with ESMTPSA id p6-20020aa7d306000000b00447c0dcbb99sm1587672edq.83.2022.09.01.09.27.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Sep 2022 09:27:30 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Her?= =?utf-8?q?v=C3=A9_Poussineau?= , Aurelien Jarno , Paolo Bonzini , Eduardo Habkost , Richard Henderson , Jiaxun Yang , Ani Sinha , Igor Mammedov , Marcel Apfelbaum , "Michael S. Tsirkin" , Bernhard Beschow Subject: [PATCH 39/42] hw/isa/piix: Unexport PIIXState Date: Thu, 1 Sep 2022 18:26:10 +0200 Message-Id: <20220901162613.6939-40-shentey@gmail.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220901162613.6939-1-shentey@gmail.com> References: <20220901162613.6939-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62a; envelope-from=shentey@gmail.com; helo=mail-ej1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The - deliberately exported - components can still be accessed via QOM properties. Signed-off-by: Bernhard Beschow --- hw/isa/piix.c | 52 +++++++++++++++++++++++++++++++++ include/hw/southbridge/piix.h | 54 ----------------------------------- 2 files changed, 52 insertions(+), 54 deletions(-) diff --git a/hw/isa/piix.c b/hw/isa/piix.c index e413d7e792..c503a6e836 100644 --- a/hw/isa/piix.c +++ b/hw/isa/piix.c @@ -26,20 +26,72 @@ #include "qemu/osdep.h" #include "qemu/range.h" #include "qapi/error.h" +#include "qom/object.h" +#include "hw/acpi/piix4.h" #include "hw/dma/i8257.h" +#include "hw/ide/pci.h" #include "hw/intc/i8259.h" #include "hw/southbridge/piix.h" #include "hw/timer/i8254.h" #include "hw/irq.h" #include "hw/qdev-properties.h" #include "hw/isa/isa.h" +#include "hw/pci/pci.h" +#include "hw/qdev-properties.h" +#include "hw/rtc/mc146818rtc.h" +#include "hw/usb/hcd-uhci.h" #include "hw/xen/xen.h" #include "sysemu/runstate.h" #include "migration/vmstate.h" #include "hw/acpi/acpi_aml_interface.h" +#define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */ #define XEN_PIIX_NUM_PIRQS 128ULL +struct PIIXState { + PCIDevice dev; + + /* + * bitmap to track pic levels. + * The pic level is the logical OR of all the PCI irqs mapped to it + * So one PIC level is tracked by PIIX_NUM_PIRQS bits. + * + * PIRQ is mapped to PIC pins, we track it by + * PIIX_NUM_PIRQS * ISA_NUM_IRQS = 64 bits with + * pic_irq * PIIX_NUM_PIRQS + pirq + */ +#if ISA_NUM_IRQS * PIIX_NUM_PIRQS > 64 +#error "unable to encode pic state in 64bit in pic_levels." +#endif + uint64_t pic_levels; + + /* This member isn't used. Just for save/load compatibility */ + int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS]; + uint8_t pci_irq_reset_mappings[PIIX_NUM_PIRQS]; + + ISAPICState pic; + RTCState rtc; + PCIIDEState ide; + UHCIState uhci; + PIIX4PMState pm; + + uint32_t smb_io_base; + + /* Reset Control Register contents */ + uint8_t rcr; + + /* IO memory region for Reset Control Register (PIIX_RCR_IOPORT) */ + MemoryRegion rcr_mem; + + bool has_acpi; + bool has_usb; + bool smm_enabled; +}; +typedef struct PIIXState PIIXState; + +DECLARE_INSTANCE_CHECKER(PIIXState, PIIX_PCI_DEVICE, + TYPE_PIIX3_PCI_DEVICE) + static void piix_set_irq_pic(PIIXState *piix, int pic_irq) { qemu_set_irq(piix->pic.in_irqs[pic_irq], diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index c9fa0f1aa6..0edc23710c 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -12,14 +12,6 @@ #ifndef HW_SOUTHBRIDGE_PIIX_H #define HW_SOUTHBRIDGE_PIIX_H -#include "hw/pci/pci.h" -#include "qom/object.h" -#include "hw/acpi/piix4.h" -#include "hw/ide/pci.h" -#include "hw/intc/i8259.h" -#include "hw/rtc/mc146818rtc.h" -#include "hw/usb/hcd-uhci.h" - /* PIRQRC[A:D]: PIRQx Route Control Registers */ #define PIIX_PIRQCA 0x60 #define PIIX_PIRQCB 0x61 @@ -32,53 +24,7 @@ */ #define PIIX_RCR_IOPORT 0xcf9 -#define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */ - -struct PIIXState { - PCIDevice dev; - - /* - * bitmap to track pic levels. - * The pic level is the logical OR of all the PCI irqs mapped to it - * So one PIC level is tracked by PIIX_NUM_PIRQS bits. - * - * PIRQ is mapped to PIC pins, we track it by - * PIIX_NUM_PIRQS * ISA_NUM_IRQS = 64 bits with - * pic_irq * PIIX_NUM_PIRQS + pirq - */ -#if ISA_NUM_IRQS * PIIX_NUM_PIRQS > 64 -#error "unable to encode pic state in 64bit in pic_levels." -#endif - uint64_t pic_levels; - - /* This member isn't used. Just for save/load compatibility */ - int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS]; - uint8_t pci_irq_reset_mappings[PIIX_NUM_PIRQS]; - - ISAPICState pic; - RTCState rtc; - PCIIDEState ide; - UHCIState uhci; - PIIX4PMState pm; - - uint32_t smb_io_base; - - /* Reset Control Register contents */ - uint8_t rcr; - - /* IO memory region for Reset Control Register (PIIX_RCR_IOPORT) */ - MemoryRegion rcr_mem; - - bool has_acpi; - bool has_usb; - bool smm_enabled; -}; -typedef struct PIIXState PIIXState; - #define TYPE_PIIX3_PCI_DEVICE "pci-piix3" -DECLARE_INSTANCE_CHECKER(PIIXState, PIIX_PCI_DEVICE, - TYPE_PIIX3_PCI_DEVICE) - #define TYPE_PIIX3_DEVICE "PIIX3" #define TYPE_PIIX3_XEN_DEVICE "PIIX3-xen" #define TYPE_PIIX4_PCI_DEVICE "piix4-isa" From patchwork Thu Sep 1 16:26:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 12962953 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DE5B3ECAAD3 for ; Thu, 1 Sep 2022 17:13:43 +0000 (UTC) Received: from localhost ([::1]:60742 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oTnl8-0007M2-UY for qemu-devel@archiver.kernel.org; Thu, 01 Sep 2022 13:13:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51132) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oTn2a-0002RM-Py for qemu-devel@nongnu.org; Thu, 01 Sep 2022 12:27:43 -0400 Received: from mail-ej1-x629.google.com ([2a00:1450:4864:20::629]:34582) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oTn2T-0001Sk-Fj for qemu-devel@nongnu.org; Thu, 01 Sep 2022 12:27:40 -0400 Received: by mail-ej1-x629.google.com with SMTP id y3so35863548ejc.1 for ; Thu, 01 Sep 2022 09:27:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=6PTQG7Rh7gB42f/nPpnGgEmjzyYid/w5xRMdsUMhn+c=; b=mJYllN+f3r4jRflfGmUoQBYUElCT674wHKTFlMsofBI3PsZn6yiz+nYnZ5kffqqvkt nA+6bn0lU+kOXjHxe8TPr0/iURP9nyZVjwcr/H6aJl3WC6/gDX8dYz4EA3kaZDXL2Eu+ qJrGY8Eu1qynrZJl/mILh8Q7D96qEDHvZgWgc6GTyoim1PRUSTwzrn1ifOdJjZF4nM1+ rE/ZAKXFav6PoR84Qo89C5MhfiIB5J3r1l4QkOrWLiKIIELBBpO3xkCBn3LJ7LTwwG0a pwZhqTN+idVaQLh8xiZqCaO9gKmsuRHlhQNB6M36bPGVvDoDknfe85MYUshKORN7vn+C GHJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=6PTQG7Rh7gB42f/nPpnGgEmjzyYid/w5xRMdsUMhn+c=; b=H1k5AcaLUqhwuMejWQr6IrczPelFgtp8cpY8BS/zaJLw+AZTudC/WK9tlByOjBW8X1 LWOSKRbl6Qh/mAHhXOds44qWmvo55QqS9gWvBhlFdVMut81xkXyH+CznlZvGwNxMrZBz eZ33AZY8HLTCdoNp8iIs1qicnnH/1xXCiX4IIDzvCW5IJ08lEMn/mGR/WcG9kLw9mPU3 K3EuQMnQjZbkhK/uOvPqfSVrhMYcxtAR+oai2o2Cx1XchbPCk3I7s04d65q0fBFEEymd YAmC3ju1M6kIbIJLX0HKVGqxuYB2fAgdLEzcMnQfWlDGuFjB1MDkKgrs/d9iFSVuZVNh +kgQ== X-Gm-Message-State: ACgBeo14/3NUAgKpyeuJif3wnIfWW373FKNFREz1AFdPB13WeIi3+owS mt7Val/j048nwQUz0675MrLbpaZ/Dw4= X-Google-Smtp-Source: AA6agR7801B9EsNhGdJXU1v5gf6+0yVEToN6okldlVzFFGerKVJ03BA4ncbCXqN0DApXgCu8irW95g== X-Received: by 2002:a17:907:2d20:b0:741:a251:1f10 with SMTP id gs32-20020a1709072d2000b00741a2511f10mr11869101ejc.400.1662049651444; Thu, 01 Sep 2022 09:27:31 -0700 (PDT) Received: from osoxes.fritz.box (p200300faaf0bb2009c4947838afc41b6.dip0.t-ipconnect.de. [2003:fa:af0b:b200:9c49:4783:8afc:41b6]) by smtp.gmail.com with ESMTPSA id p6-20020aa7d306000000b00447c0dcbb99sm1587672edq.83.2022.09.01.09.27.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Sep 2022 09:27:31 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Her?= =?utf-8?q?v=C3=A9_Poussineau?= , Aurelien Jarno , Paolo Bonzini , Eduardo Habkost , Richard Henderson , Jiaxun Yang , Ani Sinha , Igor Mammedov , Marcel Apfelbaum , "Michael S. Tsirkin" , Bernhard Beschow Subject: [PATCH 40/42] hw/isa/piix: Share PIIX3 base class with PIIX4 Date: Thu, 1 Sep 2022 18:26:11 +0200 Message-Id: <20220901162613.6939-41-shentey@gmail.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220901162613.6939-1-shentey@gmail.com> References: <20220901162613.6939-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::629; envelope-from=shentey@gmail.com; helo=mail-ej1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Having a common base class allows for substituting PIIX3 with PIIX4 and vice versa. Moreover, it makes PIIX4 implement the acpi-dev-aml-interface. Signed-off-by: Bernhard Beschow --- hw/isa/piix.c | 53 +++++++++++++++++++++++---------------------------- 1 file changed, 24 insertions(+), 29 deletions(-) diff --git a/hw/isa/piix.c b/hw/isa/piix.c index c503a6e836..25b86ddf17 100644 --- a/hw/isa/piix.c +++ b/hw/isa/piix.c @@ -473,13 +473,12 @@ static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope) } } -static void pci_piix3_init(Object *obj) +static void pci_piix_init(Object *obj) { PIIXState *d = PIIX_PCI_DEVICE(obj); object_initialize_child(obj, "pic", &d->pic, TYPE_ISA_PIC); object_initialize_child(obj, "rtc", &d->rtc, TYPE_MC146818_RTC); - object_initialize_child(obj, "ide", &d->ide, "piix3-ide"); } static Property pci_piix_props[] = { @@ -494,7 +493,7 @@ static Property pci_piix_props[] = { DEFINE_PROP_END_OF_LIST(), }; -static void pci_piix3_class_init(ObjectClass *klass, void *data) +static void pci_piix_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); @@ -502,11 +501,8 @@ static void pci_piix3_class_init(ObjectClass *klass, void *data) dc->reset = piix_reset; dc->desc = "ISA bridge"; - dc->vmsd = &vmstate_piix3; dc->hotpluggable = false; k->vendor_id = PCI_VENDOR_ID_INTEL; - /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */ - k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0; k->class_id = PCI_CLASS_BRIDGE_ISA; /* * Reason: part of PIIX3 southbridge, needs to be wired up by @@ -517,13 +513,13 @@ static void pci_piix3_class_init(ObjectClass *klass, void *data) adevc->build_dev_aml = build_pci_isa_aml; } -static const TypeInfo piix3_pci_type_info = { +static const TypeInfo piix_pci_type_info = { .name = TYPE_PIIX3_PCI_DEVICE, .parent = TYPE_PCI_DEVICE, .instance_size = sizeof(PIIXState), - .instance_init = pci_piix3_init, + .instance_init = pci_piix_init, .abstract = true, - .class_init = pci_piix3_class_init, + .class_init = pci_piix_class_init, .interfaces = (InterfaceInfo[]) { { INTERFACE_CONVENTIONAL_PCI_DEVICE }, { TYPE_ACPI_DEV_AML_IF }, @@ -547,17 +543,29 @@ static void piix3_realize(PCIDevice *dev, Error **errp) pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq); } +static void piix3_init(Object *obj) +{ + PIIXState *d = PIIX_PCI_DEVICE(obj); + + object_initialize_child(obj, "ide", &d->ide, "piix3-ide"); +} + static void piix3_class_init(ObjectClass *klass, void *data) { + DeviceClass *dc = DEVICE_CLASS(klass); PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); k->config_write = piix_write_config; k->realize = piix3_realize; + /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */ + k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0; + dc->vmsd = &vmstate_piix3; } static const TypeInfo piix3_info = { .name = TYPE_PIIX3_DEVICE, .parent = TYPE_PIIX3_PCI_DEVICE, + .instance_init = piix3_init, .class_init = piix3_class_init, }; @@ -584,15 +592,20 @@ static void piix3_xen_realize(PCIDevice *dev, Error **errp) static void piix3_xen_class_init(ObjectClass *klass, void *data) { + DeviceClass *dc = DEVICE_CLASS(klass); PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); k->config_write = piix3_write_config_xen; k->realize = piix3_xen_realize; + /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */ + k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0; + dc->vmsd = &vmstate_piix3; } static const TypeInfo piix3_xen_info = { .name = TYPE_PIIX3_XEN_DEVICE, .parent = TYPE_PIIX3_PCI_DEVICE, + .instance_init = piix3_init, .class_init = piix3_xen_class_init, }; @@ -624,8 +637,6 @@ static void piix4_init(Object *obj) { PIIXState *s = PIIX_PCI_DEVICE(obj); - object_initialize_child(obj, "pic", &s->pic, TYPE_ISA_PIC); - object_initialize_child(obj, "rtc", &s->rtc, TYPE_MC146818_RTC); object_initialize_child(obj, "ide", &s->ide, "piix4-ide"); } @@ -636,36 +647,20 @@ static void piix4_class_init(ObjectClass *klass, void *data) k->config_write = piix_write_config; k->realize = piix4_realize; - k->vendor_id = PCI_VENDOR_ID_INTEL; k->device_id = PCI_DEVICE_ID_INTEL_82371AB_0; - k->class_id = PCI_CLASS_BRIDGE_ISA; - dc->reset = piix_reset; - dc->desc = "ISA bridge"; dc->vmsd = &vmstate_piix4; - /* - * Reason: part of PIIX4 southbridge, needs to be wired up, - * e.g. by mips_malta_init() - */ - dc->user_creatable = false; - dc->hotpluggable = false; - device_class_set_props(dc, pci_piix_props); } static const TypeInfo piix4_info = { .name = TYPE_PIIX4_PCI_DEVICE, - .parent = TYPE_PCI_DEVICE, - .instance_size = sizeof(PIIXState), + .parent = TYPE_PIIX3_PCI_DEVICE, .instance_init = piix4_init, .class_init = piix4_class_init, - .interfaces = (InterfaceInfo[]) { - { INTERFACE_CONVENTIONAL_PCI_DEVICE }, - { }, - }, }; static void piix3_register_types(void) { - type_register_static(&piix3_pci_type_info); + type_register_static(&piix_pci_type_info); type_register_static(&piix3_info); type_register_static(&piix3_xen_info); type_register_static(&piix4_info); From patchwork Thu Sep 1 16:26:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 12962944 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6EB07ECAAD3 for ; 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Tsirkin" , Bernhard Beschow Subject: [PATCH 41/42] hw/isa/piix: Drop the "3" from the PIIX base class Date: Thu, 1 Sep 2022 18:26:12 +0200 Message-Id: <20220901162613.6939-42-shentey@gmail.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220901162613.6939-1-shentey@gmail.com> References: <20220901162613.6939-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62d; envelope-from=shentey@gmail.com; helo=mail-ej1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Now that the base class is used for both PIIX3 and PIIX4, the "3" became misleading. Signed-off-by: Bernhard Beschow --- hw/i386/acpi-build.c | 2 +- hw/isa/piix.c | 10 +++++----- include/hw/southbridge/piix.h | 2 +- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 0355bd3dda..8af75b1e22 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -1276,7 +1276,7 @@ static void build_piix4_isa_bridge(Aml *table) * once PCI is converted to AcpiDevAmlIf and would be ble to generate * AML for bridge itself */ - obj = object_resolve_path_type("", TYPE_PIIX3_PCI_DEVICE, &ambiguous); + obj = object_resolve_path_type("", TYPE_PIIX_PCI_DEVICE, &ambiguous); assert(obj && !ambiguous); scope = aml_scope("_SB.PCI0"); diff --git a/hw/isa/piix.c b/hw/isa/piix.c index 25b86ddf17..f70855541b 100644 --- a/hw/isa/piix.c +++ b/hw/isa/piix.c @@ -90,7 +90,7 @@ struct PIIXState { typedef struct PIIXState PIIXState; DECLARE_INSTANCE_CHECKER(PIIXState, PIIX_PCI_DEVICE, - TYPE_PIIX3_PCI_DEVICE) + TYPE_PIIX_PCI_DEVICE) static void piix_set_irq_pic(PIIXState *piix, int pic_irq) { @@ -514,7 +514,7 @@ static void pci_piix_class_init(ObjectClass *klass, void *data) } static const TypeInfo piix_pci_type_info = { - .name = TYPE_PIIX3_PCI_DEVICE, + .name = TYPE_PIIX_PCI_DEVICE, .parent = TYPE_PCI_DEVICE, .instance_size = sizeof(PIIXState), .instance_init = pci_piix_init, @@ -564,7 +564,7 @@ static void piix3_class_init(ObjectClass *klass, void *data) static const TypeInfo piix3_info = { .name = TYPE_PIIX3_DEVICE, - .parent = TYPE_PIIX3_PCI_DEVICE, + .parent = TYPE_PIIX_PCI_DEVICE, .instance_init = piix3_init, .class_init = piix3_class_init, }; @@ -604,7 +604,7 @@ static void piix3_xen_class_init(ObjectClass *klass, void *data) static const TypeInfo piix3_xen_info = { .name = TYPE_PIIX3_XEN_DEVICE, - .parent = TYPE_PIIX3_PCI_DEVICE, + .parent = TYPE_PIIX_PCI_DEVICE, .instance_init = piix3_init, .class_init = piix3_xen_class_init, }; @@ -653,7 +653,7 @@ static void piix4_class_init(ObjectClass *klass, void *data) static const TypeInfo piix4_info = { .name = TYPE_PIIX4_PCI_DEVICE, - .parent = TYPE_PIIX3_PCI_DEVICE, + .parent = TYPE_PIIX_PCI_DEVICE, .instance_init = piix4_init, .class_init = piix4_class_init, }; diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index 0edc23710c..60ff6d222a 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -24,7 +24,7 @@ */ #define PIIX_RCR_IOPORT 0xcf9 -#define TYPE_PIIX3_PCI_DEVICE "pci-piix3" +#define TYPE_PIIX_PCI_DEVICE "pci-piix" #define TYPE_PIIX3_DEVICE "PIIX3" #define TYPE_PIIX3_XEN_DEVICE "PIIX3-xen" #define TYPE_PIIX4_PCI_DEVICE "piix4-isa" From patchwork Thu Sep 1 16:26:13 2022 Content-Type: text/plain; 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[2003:fa:af0b:b200:9c49:4783:8afc:41b6]) by smtp.gmail.com with ESMTPSA id p6-20020aa7d306000000b00447c0dcbb99sm1587672edq.83.2022.09.01.09.27.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Sep 2022 09:27:32 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Her?= =?utf-8?q?v=C3=A9_Poussineau?= , Aurelien Jarno , Paolo Bonzini , Eduardo Habkost , Richard Henderson , Jiaxun Yang , Ani Sinha , Igor Mammedov , Marcel Apfelbaum , "Michael S. Tsirkin" , Bernhard Beschow Subject: [PATCH 42/42] hw/i386/acpi-build: Resolve PIIX ISA bridge rather than ACPI controller Date: Thu, 1 Sep 2022 18:26:13 +0200 Message-Id: <20220901162613.6939-43-shentey@gmail.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220901162613.6939-1-shentey@gmail.com> References: <20220901162613.6939-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52c; envelope-from=shentey@gmail.com; helo=mail-ed1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Resolving the PIIX ISA bridge rather than the PIIX ACPI controller mirrors the ICH9 code one line below. Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daudé --- hw/i386/acpi-build.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 8af75b1e22..d7bb1ccb26 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -288,7 +288,7 @@ static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm) static void acpi_get_misc_info(AcpiMiscInfo *info) { - Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM); + Object *piix = object_resolve_type_unambiguous(TYPE_PIIX_PCI_DEVICE); Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE); assert(!!piix != !!lpc);