From patchwork Sat Sep 3 02:13:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Chaitanya Chundru X-Patchwork-Id: 12964888 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3CE97C38145 for ; Sat, 3 Sep 2022 02:23:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231645AbiICCXM (ORCPT ); Fri, 2 Sep 2022 22:23:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44628 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231643AbiICCXJ (ORCPT ); Fri, 2 Sep 2022 22:23:09 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B2583EC4D6; Fri, 2 Sep 2022 19:23:08 -0700 (PDT) Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 2832MeOL009770; Sat, 3 Sep 2022 02:23:01 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references; s=qcppdkim1; bh=tivaJlTFp135Es+g5Zh7B1kts8fobVwuZjH3Kv1aMZI=; b=autodhW7OyAc5t0lsxscPBzzJWoWKlTKnLimQ97s/Z8TPiXi9tISsLxYKdBJBi6BB5S9 num2wZhGx4gHj0sq8pRkUurcaPchEdpKu+4yLp70opsZ6/vssx6rkarBDjK8FMous6TC +VLgradLehHtZ0tLYmo6nlNBSACbGh6vo13qq6cp+LYjNMYEvEXb0dtOg+qIpEmBi+8S kJ9mEYvUDXZtUnGwaefbJPUUoozPx31/3nN1KVMNey87MO6wNLDG/sOAM+PLDjjAf6bh r9nsnOEwO6h7Ryr2194uAjRsESY4HleISysfck3VNcbjijMBH05G4D3WOxt5KjBtZv8I uA== Received: from apblrppmta02.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3javjc68nr-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 03 Sep 2022 02:23:00 +0000 Received: from pps.filterd (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 2832MuHQ016084; Sat, 3 Sep 2022 02:22:56 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 3j7cbktj0x-1; Sat, 03 Sep 2022 02:22:56 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 2832Mu7F016061; Sat, 3 Sep 2022 02:22:56 GMT Received: from hu-sgudaval-hyd.qualcomm.com (hu-krichai-hyd.qualcomm.com [10.213.110.37]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 2832Mt8O016054; Sat, 03 Sep 2022 02:22:56 +0000 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 4058933) id 9C1AA41B7; Sat, 3 Sep 2022 07:43:06 +0530 (+0530) From: Krishna chaitanya chundru To: helgaas@kernel.org Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, mka@chromium.org, quic_vbadigan@quicinc.com, quic_hemantk@quicinc.com, quic_nitegupt@quicinc.com, quic_skananth@quicinc.com, quic_ramkri@quicinc.com, manivannan.sadhasivam@linaro.org, swboyd@chromium.org, dmitry.baryshkov@linaro.org, Krishna chaitanya chundru , Stanimir Varbanov , Andy Gross , Bjorn Andersson , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas Subject: [PATCH v3 1/3] PCI: qcom: Add sc7280 aggre0, aggre1 and ddr sf tbu clocks in PCIe driver Date: Sat, 3 Sep 2022 07:43:02 +0530 Message-Id: <1662171184-25211-2-git-send-email-quic_krichai@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1662171184-25211-1-git-send-email-quic_krichai@quicinc.com> References: <1662171184-25211-1-git-send-email-quic_krichai@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 9-5BoIEICl9jzHXnj5JLm_wR-VZBk8Wg X-Proofpoint-ORIG-GUID: 9-5BoIEICl9jzHXnj5JLm_wR-VZBk8Wg X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-09-02_08,2022-08-31_03,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 mlxscore=0 spamscore=0 phishscore=0 lowpriorityscore=0 malwarescore=0 clxscore=1015 bulkscore=0 mlxlogscore=707 suspectscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2207270000 definitions=main-2209030010 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add missing aggre0, aggre1 and ddrs sf tbu clocks in PCIe driver. If these clocks are not presenti, the PCIe link goes down in system suspend and resume. Signed-off-by: Krishna chaitanya chundru --- drivers/pci/controller/dwc/pcie-qcom.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 2ea1375..a7202f0 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1548,7 +1548,10 @@ static const struct qcom_pcie_cfg sm8450_pcie1_cfg = { static const struct qcom_pcie_cfg sc7280_cfg = { .ops = &ops_1_9_0, .has_tbu_clk = true, + .has_ddrss_sf_tbu_clk = true, .pipe_clk_need_muxing = true, + .has_aggre0_clk = true, + .has_aggre1_clk = true, }; static const struct qcom_pcie_cfg sc8180x_cfg = { From patchwork Sat Sep 3 02:13:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Chaitanya Chundru X-Patchwork-Id: 12964882 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D1B68C6FA86 for ; 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Signed-off-by: Krishna chaitanya chundru --- changes since v2: - Increase the max items of clock's in common properties. --- Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index 0b69b12..b759465 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -53,11 +53,11 @@ properties: # Platform constraints are described later. clocks: minItems: 3 - maxItems: 12 + maxItems: 13 clock-names: minItems: 3 - maxItems: 12 + maxItems: 13 resets: minItems: 1 @@ -423,8 +423,8 @@ allOf: then: properties: clocks: - minItems: 11 - maxItems: 11 + minItems: 13 + maxItems: 13 clock-names: items: - const: pipe # PIPE clock @@ -437,6 +437,8 @@ allOf: - const: bus_slave # Slave AXI clock - const: slave_q2a # Slave Q2A clock - const: tbu # PCIe TBU clock + - const: aggre0 # Aggre NoC PCIe CENTER SF AXI clock + - const: aggre1 # Aggre NoC PCIe1 AXI clock - const: ddrss_sf_tbu # PCIe SF TBU clock resets: maxItems: 1 From patchwork Sat Sep 3 02:13:04 2022 Content-Type: text/plain; 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Signed-off-by: Krishna chaitanya chundru --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index e66fc67..a5ce095 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2043,6 +2043,8 @@ <&gcc GCC_PCIE_1_SLV_AXI_CLK>, <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, <&gcc GCC_DDRSS_PCIE_SF_CLK>; clock-names = "pipe", @@ -2055,6 +2057,8 @@ "bus_slave", "slave_q2a", "tbu", + "aggre0", + "aggre1", "ddrss_sf_tbu"; assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;