From patchwork Mon Sep 5 18:51:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 12966475 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 14A75ECAAD5 for ; Mon, 5 Sep 2022 19:27:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; 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Mon, 5 Sep 2022 18:52:15 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4526FC433C1; Mon, 5 Sep 2022 18:52:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1662403934; bh=V3DhFxwkMch9V2j0LUuXL2Z76OR6gdn4dJaqm2PVFrA=; h=From:To:Cc:Subject:Date:From; b=D8ZX/7+6iZhkm7DwdyXnnAUNzjMMjFr600fMjbbqj6JCiqX/uMRKAW08L1eh96dVM pztQTMKUi0MMS9SIfBxS9E68k8SVFZ8JScoc0wPjAk9MVu4TylXvBXB0IfdgjV2ddM VWtDoXN2Uq2KrHmYNPwJwiY3tNMlOtIsAa8DFASBrczcHrgpB94fWDgJVG4vk32twt DeOAEKl/CnsJBFaztcxsWC5tQrZqRNTNIGM+xXk1u+whduyrpjliDFY62vZkWnWaaz asRH6kz471je4aKjgDNgHThxhrRHpSdbzg8rq/2VIdOtkNJb0EVQmM1WhRKUAzIPXO 3y4fX8uF9i6Ag== Received: by pali.im (Postfix) id C5AF47D7; Mon, 5 Sep 2022 20:52:11 +0200 (CEST) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas , Thomas Petazzoni Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 1/2] PCI: mvebu: use BIT() and GENMASK() macros instead of hardcoded hex values Date: Mon, 5 Sep 2022 20:51:49 +0200 Message-Id: <20220905185150.22220-1-pali@kernel.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220905_115216_118600_8CF5A776 X-CRM114-Status: GOOD ( 11.50 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Signed-off-by: Pali Rohár --- drivers/pci/controller/pci-mvebu.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c index 8bde4727aca4..c222dc189567 100644 --- a/drivers/pci/controller/pci-mvebu.c +++ b/drivers/pci/controller/pci-mvebu.c @@ -44,7 +44,7 @@ #define PCIE_WIN5_BASE_OFF 0x1884 #define PCIE_WIN5_REMAP_OFF 0x188c #define PCIE_CONF_ADDR_OFF 0x18f8 -#define PCIE_CONF_ADDR_EN 0x80000000 +#define PCIE_CONF_ADDR_EN BIT(31) #define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc)) #define PCIE_CONF_BUS(b) (((b) & 0xff) << 16) #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11) @@ -70,13 +70,13 @@ #define PCIE_INT_ERR_MASK (PCIE_INT_ERR_FATAL | PCIE_INT_ERR_NONFATAL | PCIE_INT_ERR_COR) #define PCIE_INT_ALL_MASK GENMASK(31, 0) #define PCIE_CTRL_OFF 0x1a00 -#define PCIE_CTRL_X1_MODE 0x0001 +#define PCIE_CTRL_X1_MODE BIT(0) #define PCIE_CTRL_RC_MODE BIT(1) #define PCIE_CTRL_MASTER_HOT_RESET BIT(24) #define PCIE_STAT_OFF 0x1a04 -#define PCIE_STAT_BUS 0xff00 -#define PCIE_STAT_DEV 0x1f0000 #define PCIE_STAT_LINK_DOWN BIT(0) +#define PCIE_STAT_BUS GENMASK(15, 8) +#define PCIE_STAT_DEV GENMASK(20, 16) #define PCIE_SSPL_OFF 0x1a0c #define PCIE_SSPL_VALUE_SHIFT 0 #define PCIE_SSPL_VALUE_MASK GENMASK(7, 0) From patchwork Mon Sep 5 18:51:50 2022 Content-Type: text/plain; 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Mon, 5 Sep 2022 18:52:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1662403936; bh=uYXn4ODMewN8FNKLW3ITPu9bWfeJ/vLE7EUtvluPaPc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UCKVrG6+DJD8gwdNjZb3JANtK+l84hxHKutZTIzGJOh9M22VuPsJndi5vzXac3M6a NgIAGG3Rft51H7//DAyD+p0UQSvNze2kRV5D4fF/xQyqDt+3N2EjYVLCueTTlsPftk FOvW/Zoz1AABIkj2q8whQVpeDmTdDCcwzHnemlwv1+YakCw5WGK4JqJry2N+s8OJnh 9AgfEkkKGB6JQ+2kv3j+BfgmUDJF+KVWey2xd6KaGv9uIgbP2c5YWdZ8vikRJa456N d0SFBWy2rdGTwrQmKAd4R5FocJ1DVgveEBE/LpmAk3KtnCZCUjbQhSJ+gZHhkhtnCC NgYbk4fduCP1Q== Received: by pali.im (Postfix) id D863820B1; Mon, 5 Sep 2022 20:52:12 +0200 (CEST) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas , Thomas Petazzoni Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 2/2] PCI: mvebu: For consistency add _OFF suffix to all registers Date: Mon, 5 Sep 2022 20:51:50 +0200 Message-Id: <20220905185150.22220-2-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220905185150.22220-1-pali@kernel.org> References: <20220905185150.22220-1-pali@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220905_115217_498184_7ED0A347 X-CRM114-Status: GOOD ( 15.27 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Signed-off-by: Pali Rohár --- This patch depends on now accepted patch: "PCI: pci-bridge-emul: Set position of PCI capabilities to real HW value" https://lore.kernel.org/linux-pci/20220824112124.21675-1-pali@kernel.org/ --- drivers/pci/controller/pci-mvebu.c | 40 +++++++++++++++--------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c index c222dc189567..6ef8c1ee4cbb 100644 --- a/drivers/pci/controller/pci-mvebu.c +++ b/drivers/pci/controller/pci-mvebu.c @@ -34,7 +34,7 @@ #define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3)) #define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3)) #define PCIE_SSDEV_ID_OFF 0x002c -#define PCIE_CAP_PCIEXP 0x0060 +#define PCIE_CAP_PCIEXP_OFF 0x0060 #define PCIE_CAP_PCIERR_OFF 0x0100 #define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4)) #define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4)) @@ -83,8 +83,8 @@ #define PCIE_SSPL_SCALE_SHIFT 8 #define PCIE_SSPL_SCALE_MASK GENMASK(9, 8) #define PCIE_SSPL_ENABLE BIT(16) -#define PCIE_RC_RTSTA 0x1a14 -#define PCIE_DEBUG_CTRL 0x1a60 +#define PCIE_RC_RTSTA_OFF 0x1a14 +#define PCIE_DEBUG_CTRL_OFF 0x1a60 #define PCIE_DEBUG_SOFT_RESET BIT(20) struct mvebu_pcie_port; @@ -296,10 +296,10 @@ static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port) * be set to number of SerDes PCIe lanes (1 or 4). If this register is * not set correctly then link with endpoint card is not established. */ - lnkcap = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCAP); + lnkcap = mvebu_readl(port, PCIE_CAP_PCIEXP_OFF + PCI_EXP_LNKCAP); lnkcap &= ~PCI_EXP_LNKCAP_MLW; lnkcap |= (port->is_x4 ? 4 : 1) << 4; - mvebu_writel(port, lnkcap, PCIE_CAP_PCIEXP + PCI_EXP_LNKCAP); + mvebu_writel(port, lnkcap, PCIE_CAP_PCIEXP_OFF + PCI_EXP_LNKCAP); /* Disable Root Bridge I/O space, memory space and bus mastering. */ cmd = mvebu_readl(port, PCIE_CMD_OFF); @@ -690,11 +690,11 @@ mvebu_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge, switch (reg) { case PCI_EXP_DEVCAP: - *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_DEVCAP); + *value = mvebu_readl(port, PCIE_CAP_PCIEXP_OFF + PCI_EXP_DEVCAP); break; case PCI_EXP_DEVCTL: - *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_DEVCTL); + *value = mvebu_readl(port, PCIE_CAP_PCIEXP_OFF + PCI_EXP_DEVCTL); break; case PCI_EXP_LNKCAP: @@ -704,13 +704,13 @@ mvebu_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge, * Additionally enable Data Link Layer Link Active Reporting * Capable bit as DL_Active indication is provided too. */ - *value = (mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCAP) & + *value = (mvebu_readl(port, PCIE_CAP_PCIEXP_OFF + PCI_EXP_LNKCAP) & ~PCI_EXP_LNKCAP_CLKPM) | PCI_EXP_LNKCAP_DLLLARC; break; case PCI_EXP_LNKCTL: /* DL_Active indication is provided via PCIE_STAT_OFF */ - *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL) | + *value = mvebu_readl(port, PCIE_CAP_PCIEXP_OFF + PCI_EXP_LNKCTL) | (mvebu_pcie_link_up(port) ? (PCI_EXP_LNKSTA_DLLLA << 16) : 0); break; @@ -748,19 +748,19 @@ mvebu_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge, break; case PCI_EXP_RTSTA: - *value = mvebu_readl(port, PCIE_RC_RTSTA); + *value = mvebu_readl(port, PCIE_RC_RTSTA_OFF); break; case PCI_EXP_DEVCAP2: - *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_DEVCAP2); + *value = mvebu_readl(port, PCIE_CAP_PCIEXP_OFF + PCI_EXP_DEVCAP2); break; case PCI_EXP_DEVCTL2: - *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_DEVCTL2); + *value = mvebu_readl(port, PCIE_CAP_PCIEXP_OFF + PCI_EXP_DEVCTL2); break; case PCI_EXP_LNKCTL2: - *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL2); + *value = mvebu_readl(port, PCIE_CAP_PCIEXP_OFF + PCI_EXP_LNKCTL2); break; default: @@ -902,7 +902,7 @@ mvebu_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge, switch (reg) { case PCI_EXP_DEVCTL: - mvebu_writel(port, new, PCIE_CAP_PCIEXP + PCI_EXP_DEVCTL); + mvebu_writel(port, new, PCIE_CAP_PCIEXP_OFF + PCI_EXP_DEVCTL); break; case PCI_EXP_LNKCTL: @@ -913,7 +913,7 @@ mvebu_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge, */ new &= ~PCI_EXP_LNKCTL_CLKREQ_EN; - mvebu_writel(port, new, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL); + mvebu_writel(port, new, PCIE_CAP_PCIEXP_OFF + PCI_EXP_LNKCTL); /* * When dropping to Detect via Hot Reset, Disable Link * or Loopback states, the Link Failure interrupt is not @@ -953,7 +953,7 @@ mvebu_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge, case PCI_EXP_RTSTA: /* - * PME Status bit in Root Status Register (PCIE_RC_RTSTA) + * PME Status bit in Root Status Register (PCIE_RC_RTSTA_OFF) * is read-only and can be cleared only by writing 0b to the * Interrupt Cause RW0C register (PCIE_INT_CAUSE_OFF). So * clear PME via Interrupt Cause and also set port->pme_pending @@ -978,11 +978,11 @@ mvebu_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge, break; case PCI_EXP_DEVCTL2: - mvebu_writel(port, new, PCIE_CAP_PCIEXP + PCI_EXP_DEVCTL2); + mvebu_writel(port, new, PCIE_CAP_PCIEXP_OFF + PCI_EXP_DEVCTL2); break; case PCI_EXP_LNKCTL2: - mvebu_writel(port, new, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL2); + mvebu_writel(port, new, PCIE_CAP_PCIEXP_OFF + PCI_EXP_LNKCTL2); break; default: @@ -1042,7 +1042,7 @@ static int mvebu_pci_bridge_emul_init(struct mvebu_pcie_port *port) u32 dev_id = mvebu_readl(port, PCIE_DEV_ID_OFF); u32 dev_rev = mvebu_readl(port, PCIE_DEV_REV_OFF); u32 ssdev_id = mvebu_readl(port, PCIE_SSDEV_ID_OFF); - u32 pcie_cap = mvebu_readl(port, PCIE_CAP_PCIEXP); + u32 pcie_cap = mvebu_readl(port, PCIE_CAP_PCIEXP_OFF); u8 pcie_cap_ver = ((pcie_cap >> 16) & PCI_EXP_FLAGS_VERS); bridge->conf.vendor = cpu_to_le16(dev_id & 0xffff); @@ -1103,7 +1103,7 @@ static int mvebu_pci_bridge_emul_init(struct mvebu_pcie_port *port) bridge->subsystem_vendor_id = ssdev_id & 0xffff; bridge->subsystem_id = ssdev_id >> 16; bridge->has_pcie = true; - bridge->pcie_start = PCIE_CAP_PCIEXP; + bridge->pcie_start = PCIE_CAP_PCIEXP_OFF; bridge->data = port; bridge->ops = &mvebu_pci_bridge_emul_ops;