From patchwork Tue Sep 6 13:55:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiu Moga X-Patchwork-Id: 12967636 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 31ED9ECAAA1 for ; Tue, 6 Sep 2022 14:37:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234716AbiIFOhU (ORCPT ); Tue, 6 Sep 2022 10:37:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38598 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233834AbiIFOgc (ORCPT ); Tue, 6 Sep 2022 10:36:32 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6BFE582FA8; Tue, 6 Sep 2022 07:00:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1662472806; x=1694008806; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=noxCcCO9xTSbTKYwLuG5H1vEfcZMJd3F9cqwqynfP/k=; b=lkxebIk75zkzSB34+lRT2w9u4ii5/gsGX1kP5KRF12NE/r+BCl+Xa3PH I1sKlgFKjtQrGpvLDpXVX4AhBaYzeUoJ3yHocBUqUhrQVh9ELXX89X6py iGolX0QatOb9clgQDTgGe7SbpTMUiMyDzEArz5OWeEDEBLdiVkSzxYJVh k1GA5UPP5ojtqM6I6xK5/U+DielLXPcZIEkG+c9kBK1wVaiLC1OrY0Euc Rp+zTxZ1ZE9f5FhqF0mYijvKq2P0gi/x/OjP5Z5ATcH0IrJP2rg1tJUqC fPpOcjRfvuYbx0Z6dxDRw0OrwoMgDDlcBRah5npEN9SAN+oFh5B48Lp2H Q==; X-IronPort-AV: E=Sophos;i="5.93,294,1654585200"; d="scan'208";a="172589921" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 06 Sep 2022 06:56:39 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 6 Sep 2022 06:56:38 -0700 Received: from ROB-ULT-M68701.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Tue, 6 Sep 2022 06:56:33 -0700 From: Sergiu Moga To: , , , , , , , , , , , , , , , , CC: , , , , , Subject: [PATCH v2 01/13] spi: dt-bindings: atmel,at91rm9200-spi: Add DMA related properties Date: Tue, 6 Sep 2022 16:55:00 +0300 Message-ID: <20220906135511.144725-2-sergiu.moga@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220906135511.144725-1-sergiu.moga@microchip.com> References: <20220906135511.144725-1-sergiu.moga@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org The DT nodes of the SPI IP's may contain DMA related properties so make sure that the binding is able to properly validate those as well by making it aware of these optional properties. Signed-off-by: Sergiu Moga Acked-by: Mark Brown Acked-by: Krzysztof Kozlowski --- v1 -> v2: - Nothing, this patch was not here before .../devicetree/bindings/spi/atmel,at91rm9200-spi.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/atmel,at91rm9200-spi.yaml b/Documentation/devicetree/bindings/spi/atmel,at91rm9200-spi.yaml index d85d54024b2e..4dd973e341e6 100644 --- a/Documentation/devicetree/bindings/spi/atmel,at91rm9200-spi.yaml +++ b/Documentation/devicetree/bindings/spi/atmel,at91rm9200-spi.yaml @@ -34,6 +34,16 @@ properties: clocks: maxItems: 1 + dmas: + items: + - description: TX DMA Channel + - description: RX DMA Channel + + dma-names: + items: + - const: tx + - const: rx + atmel,fifo-size: $ref: /schemas/types.yaml#/definitions/uint32 description: | From patchwork Tue Sep 6 13:55:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiu Moga X-Patchwork-Id: 12967632 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B77C2C6FA90 for ; Tue, 6 Sep 2022 14:34:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234670AbiIFOeV (ORCPT ); Tue, 6 Sep 2022 10:34:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35318 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242006AbiIFOd2 (ORCPT ); Tue, 6 Sep 2022 10:33:28 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 41F5482D32; Tue, 6 Sep 2022 06:58:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1662472726; x=1694008726; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=UsqJGlEdc6MmAq/temRPHof8NeB6n1P0o0Ib1Kl4G+I=; b=owyFQgnnJCV/p7VdcbqQftU5QJ56KMCOGyNr7zVnbBNWqgMcQGxbmAfv 3kySFmhkTgLEi0TlLywsQtVpV7QPKyNHtXF4cJxe+f3Z8qrDzQF+u+iBE E62ImXyhUpEEB1vdkzgkhDcsTQJPEYgffFcS8Yk1Gdde2mA+24srkLs5E UojXeVYBla+rY0Pt/WNNPcqqJls5xDbi4lUnILbtcl2ubeWadDidv1cU2 od1vNgGQ5AKRRrqAWHZSWaa6xJvUpkVFNiz6gtVHqB0p4HDo196TIV5Mt tNRW38qWkIMQOysnwFHB4ai2X3xBhHMCzQ72KqIcNFElN8bN7ktsx/aob Q==; X-IronPort-AV: E=Sophos;i="5.93,294,1654585200"; d="scan'208";a="189613821" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 06 Sep 2022 06:56:44 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 6 Sep 2022 06:56:44 -0700 Received: from ROB-ULT-M68701.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Tue, 6 Sep 2022 06:56:39 -0700 From: Sergiu Moga To: , , , , , , , , , , , , , , , , CC: , , , , , Subject: [PATCH v2 02/13] ARM: dts: at91: sama7g5: Swap rx and tx for spi11 Date: Tue, 6 Sep 2022 16:55:01 +0300 Message-ID: <20220906135511.144725-3-sergiu.moga@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220906135511.144725-1-sergiu.moga@microchip.com> References: <20220906135511.144725-1-sergiu.moga@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Swap the rx and tx of the DMA related DT properties of the spi11 node in order to maintain consistency across Microchip/Atmel SoC files. Signed-off-by: Sergiu Moga --- v1 -> v2: - Nothing, this patch was not here before arch/arm/boot/dts/sama7g5.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi index bb6d71e6dfeb..249f9c640b6c 100644 --- a/arch/arm/boot/dts/sama7g5.dtsi +++ b/arch/arm/boot/dts/sama7g5.dtsi @@ -866,9 +866,9 @@ spi11: spi@400 { #address-cells = <1>; #size-cells = <0>; atmel,fifo-size = <32>; - dmas = <&dma0 AT91_XDMAC_DT_PERID(27)>, - <&dma0 AT91_XDMAC_DT_PERID(28)>; - dma-names = "rx", "tx"; + dmas = <&dma0 AT91_XDMAC_DT_PERID(28)>, + <&dma0 AT91_XDMAC_DT_PERID(27)>; + dma-names = "tx", "rx"; status = "disabled"; }; }; From patchwork Tue Sep 6 13:55:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiu Moga X-Patchwork-Id: 12967631 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BDA06C6FA83 for ; Tue, 6 Sep 2022 14:34:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240290AbiIFOeW (ORCPT ); Tue, 6 Sep 2022 10:34:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34172 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242145AbiIFOdf (ORCPT ); Tue, 6 Sep 2022 10:33:35 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9AD3E98A41; Tue, 6 Sep 2022 06:58:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1662472736; x=1694008736; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=rxAl4C/+GYl9FO0p6O+KZF0I5ZhxVC6ijXZxrd6Fv+Y=; b=o+7xicXdzFEcS32OeQr4f8AQxm2pgROJj0kZUBcwZ6GmqZJNc8xEYsNR J+/QcbAL3Ca76LyCyZ871EbGKg5eo59mXWpdYepkjjdEzmu2+smY8J36g ZGVD6DciP25grXEgi3ShktH1WBP/PuZT3wzuCZfkCnVnDCV617DCE8Ijw kU2Uvya1LABYvztvDPZEBrywhZl0r4tXZQ4B3zktGwlIgVgwYg7XJA1Jf qg0vZ7CxykWPrOIPiqQarQimFRncz5NvR+ADRIVsjGUP73RMuxDIyPBBS 47JuhIxXmdr08wg0nbblosinfbuDJNfGETHHvmO3ag8LfW98YCLMzuQGj w==; X-IronPort-AV: E=Sophos;i="5.93,294,1654585200"; d="scan'208";a="189613846" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 06 Sep 2022 06:56:52 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 6 Sep 2022 06:56:49 -0700 Received: from ROB-ULT-M68701.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Tue, 6 Sep 2022 06:56:44 -0700 From: Sergiu Moga To: , , , , , , , , , , , , , , , , CC: , , , , , Subject: [PATCH v2 03/13] dt-bindings: mfd: atmel,sama5d2-flexcom: Add SPI child node ref binding Date: Tue, 6 Sep 2022 16:55:02 +0300 Message-ID: <20220906135511.144725-4-sergiu.moga@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220906135511.144725-1-sergiu.moga@microchip.com> References: <20220906135511.144725-1-sergiu.moga@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Another functionality of FLEXCOM is that of SPI. In order for the proper validation of the SPI children nodes through the binding to occur, the proper binding for SPI must be referenced. Signed-off-by: Sergiu Moga Reviewed-by: Krzysztof Kozlowski --- v1 -> v2: - use full schema paths .../devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml b/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml index 568da7cb630c..0db0f2728b65 100644 --- a/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml +++ b/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml @@ -78,10 +78,9 @@ patternProperties: of USART bindings. "^spi@[0-9a-f]+$": - type: object + $ref: /schemas/spi/atmel,at91rm9200-spi.yaml description: - Child node describing SPI. See ../spi/spi_atmel.txt for details - of SPI bindings. + Child node describing SPI. "^i2c@[0-9a-f]+$": $ref: ../i2c/atmel,at91sam-i2c.yaml From patchwork Tue Sep 6 13:55:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiu Moga X-Patchwork-Id: 12967635 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 89C2DC6FA89 for ; Tue, 6 Sep 2022 14:34:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241950AbiIFOe2 (ORCPT ); Tue, 6 Sep 2022 10:34:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52094 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242438AbiIFOd5 (ORCPT ); Tue, 6 Sep 2022 10:33:57 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DEC2997D7B; Tue, 6 Sep 2022 06:59:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1662472747; x=1694008747; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1ukzoA6GXOrZn1fR+vQ1H2MVExXptIL532zW/9q++y4=; b=0mtTwKfYoI0niDcWBzCban44d+3dp4+ABDOeYmcFnWD90DOPYP4WR/TW fK6UPWo4uE0YO1ZVcSwbLwXeoI/2x+4wOiTR7/b9AtGMleHESufOwUxzS xU47A28RgSJqYbfhrhwTobQZ+OVcCmT9Z2eIq8dJuqbiEQkL8HHIZ/+ky aVGYWWLgi8+9GcCaEW+u/tE6vWYzuydyhhCWWdrLNDhayQRwPS/d/PD+E /eZ2VzegnX/dPR/Zp2g/9xf6aUBar5LJDE5+dgRIr7tmi4fh6+CYRa/23 5K1kYhndVYDAUs0vEReClq1P5WsdGkgf5OHtV7F/CxJ4ELnI8Uoa2Nkzq A==; X-IronPort-AV: E=Sophos;i="5.93,294,1654585200"; d="scan'208";a="189613857" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 06 Sep 2022 06:56:55 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 6 Sep 2022 06:56:54 -0700 Received: from ROB-ULT-M68701.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Tue, 6 Sep 2022 06:56:49 -0700 From: Sergiu Moga To: , , , , , , , , , , , , , , , , CC: , , , , , Subject: [PATCH v2 04/13] ARM: dts: at91: sam9x60ek: Add DBGU compatibles to uart1 Date: Tue, 6 Sep 2022 16:55:03 +0300 Message-ID: <20220906135511.144725-5-sergiu.moga@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220906135511.144725-1-sergiu.moga@microchip.com> References: <20220906135511.144725-1-sergiu.moga@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Maintain consistency among the compatibles of the serial nodes of sam9x60ek and highlight the incremental characteristic of its serial IP's by making sure that all serial nodes contain both the sam9x60 and sam9260 usart/dbgu compatibles. Signed-off-by: Sergiu Moga --- v1 -> v2: - Nothing, this patch was not here before arch/arm/boot/dts/at91-sam9x60ek.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/at91-sam9x60ek.dts b/arch/arm/boot/dts/at91-sam9x60ek.dts index 81c38e101f58..49827e63508d 100644 --- a/arch/arm/boot/dts/at91-sam9x60ek.dts +++ b/arch/arm/boot/dts/at91-sam9x60ek.dts @@ -264,7 +264,7 @@ &flx5 { status = "okay"; uart1: serial@200 { - compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; + compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; reg = <0x200 0x200>; interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>; dmas = <&dma0 From patchwork Tue Sep 6 13:55:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiu Moga X-Patchwork-Id: 12967646 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1E18CECAAD5 for ; Tue, 6 Sep 2022 14:37:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242092AbiIFOhd (ORCPT ); Tue, 6 Sep 2022 10:37:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36040 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241875AbiIFOhF (ORCPT ); Tue, 6 Sep 2022 10:37:05 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5E27E8A7E4; Tue, 6 Sep 2022 07:00:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1662472811; x=1694008811; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=XAvOSIGCUjk54fk6WfpKKPO6o/ZWDeEaqk/cP6f7qdM=; b=l/sCXGQEmj9/1P/DyoEMTO49Pq73teoYLYFl7FHl4m/maheNwLM0fwYb CVH4xC/bzBp41NoPL4aIg+pyPLOUFfFLZe6u7vFBR7PcIpg/b9v0OR19o /buwex8g30CNpQOxGCGNsDblck2CR0oyUwc7X9Aahmhw0nRXfligNuxTP Sapvym3GWUFB1UHfbLhI4kB5VtoOlRHuDSzgwY+N5HyaJ1RAJNUv8rlr8 AAL8bMuaJYirNDwCu4Lag/yrL2zB06uwLg/4lYepINwzXicyYs0vLEt98 d23YvfMtxTrJfzFuYe3Avi4hcSdybVHWzqGtXiqd2AgI5Lo2MeZZzGmMw g==; X-IronPort-AV: E=Sophos;i="5.93,294,1654585200"; d="scan'208";a="172589973" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 06 Sep 2022 06:57:00 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 6 Sep 2022 06:57:00 -0700 Received: from ROB-ULT-M68701.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Tue, 6 Sep 2022 06:56:55 -0700 From: Sergiu Moga To: , , , , , , , , , , , , , , , , CC: , , , , , Subject: [PATCH v2 05/13] dt-bindings: serial: atmel,at91-usart: convert to json-schema Date: Tue, 6 Sep 2022 16:55:04 +0300 Message-ID: <20220906135511.144725-6-sergiu.moga@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220906135511.144725-1-sergiu.moga@microchip.com> References: <20220906135511.144725-1-sergiu.moga@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Convert at91 USART DT Binding for Atmel/Microchip SoCs to json-schema format. Furthermore, move this binding to the serial directory, since binding directories match hardware, unlike the driver subsystems which match Linux convention. Signed-off-by: Sergiu Moga --- v1 -> v2: - only do what the commit says, split the addition of other compatibles and properties in other patches - remove unnecessary "|"'s - mention header in `atmel,usart-mode`'s description - place `if:` under `allOf:` - respect order of spi0's DT properties: compatible, then reg then the reset of properties .../devicetree/bindings/mfd/atmel-usart.txt | 98 ---------- .../bindings/serial/atmel,at91-usart.yaml | 183 ++++++++++++++++++ 2 files changed, 183 insertions(+), 98 deletions(-) delete mode 100644 Documentation/devicetree/bindings/mfd/atmel-usart.txt create mode 100644 Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml diff --git a/Documentation/devicetree/bindings/mfd/atmel-usart.txt b/Documentation/devicetree/bindings/mfd/atmel-usart.txt deleted file mode 100644 index a09133066aff..000000000000 --- a/Documentation/devicetree/bindings/mfd/atmel-usart.txt +++ /dev/null @@ -1,98 +0,0 @@ -* Atmel Universal Synchronous Asynchronous Receiver/Transmitter (USART) - -Required properties for USART: -- compatible: Should be one of the following: - - "atmel,at91rm9200-usart" - - "atmel,at91sam9260-usart" - - "microchip,sam9x60-usart" - - "atmel,at91rm9200-dbgu", "atmel,at91rm9200-usart" - - "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart" - - "microchip,sam9x60-dbgu", "microchip,sam9x60-usart" -- reg: Should contain registers location and length -- interrupts: Should contain interrupt -- clock-names: tuple listing input clock names. - Required elements: "usart" -- clocks: phandles to input clocks. - -Required properties for USART in SPI mode: -- #size-cells : Must be <0> -- #address-cells : Must be <1> -- cs-gpios: chipselects (internal cs not supported) -- atmel,usart-mode : Must be (found in dt-bindings/mfd/at91-usart.h) - -Optional properties in serial and SPI mode: -- dma bindings for dma transfer: - - dmas: DMA specifier, consisting of a phandle to DMA controller node, - memory peripheral interface and USART DMA channel ID, FIFO configuration. - The order of DMA channels is fixed. The first DMA channel must be TX - associated channel and the second one must be RX associated channel. - Refer to dma.txt and atmel-dma.txt for details. - - dma-names: "tx" for TX channel. - "rx" for RX channel. - The order of dma-names is also fixed. The first name must be "tx" - and the second one must be "rx" as in the examples below. - -Optional properties in serial mode: -- atmel,use-dma-rx: use of PDC or DMA for receiving data -- atmel,use-dma-tx: use of PDC or DMA for transmitting data -- {rts,cts,dtr,dsr,rng,dcd}-gpios: specify a GPIO for RTS/CTS/DTR/DSR/RI/DCD line respectively. - It will use specified PIO instead of the peripheral function pin for the USART feature. - If unsure, don't specify this property. -- atmel,fifo-size: maximum number of data the RX and TX FIFOs can store for FIFO - capable USARTs. -- rs485-rts-delay, rs485-rx-during-tx, linux,rs485-enabled-at-boot-time: see rs485.txt - - compatible description: -- at91rm9200: legacy USART support -- at91sam9260: generic USART implementation for SAM9 SoCs - -Example: -- use PDC: - usart0: serial@fff8c000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfff8c000 0x4000>; - interrupts = <7>; - clocks = <&usart0_clk>; - clock-names = "usart"; - atmel,use-dma-rx; - atmel,use-dma-tx; - rts-gpios = <&pioD 15 GPIO_ACTIVE_LOW>; - cts-gpios = <&pioD 16 GPIO_ACTIVE_LOW>; - dtr-gpios = <&pioD 17 GPIO_ACTIVE_LOW>; - dsr-gpios = <&pioD 18 GPIO_ACTIVE_LOW>; - dcd-gpios = <&pioD 20 GPIO_ACTIVE_LOW>; - rng-gpios = <&pioD 19 GPIO_ACTIVE_LOW>; - }; - -- use DMA: - usart0: serial@f001c000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf001c000 0x100>; - interrupts = <12 4 5>; - clocks = <&usart0_clk>; - clock-names = "usart"; - atmel,use-dma-rx; - atmel,use-dma-tx; - dmas = <&dma0 2 0x3>, - <&dma0 2 0x204>; - dma-names = "tx", "rx"; - atmel,fifo-size = <32>; - }; - -- SPI mode: - #include - - spi0: spi@f001c000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91rm9200-usart", "atmel,at91sam9260-usart"; - atmel,usart-mode = ; - reg = <0xf001c000 0x100>; - interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>; - clocks = <&usart0_clk>; - clock-names = "usart"; - dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(3)>, - <&dma0 2 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>; - dma-names = "tx", "rx"; - cs-gpios = <&pioB 3 0>; - }; diff --git a/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml new file mode 100644 index 000000000000..b25535b7a4d2 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml @@ -0,0 +1,183 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/atmel,at91-usart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atmel Universal Synchronous Asynchronous Receiver/Transmitter (USART) + +maintainers: + - Richard Genoud + +properties: + compatible: + oneOf: + - enum: + - atmel,at91rm9200-usart + - atmel,at91sam9260-usart + - microchip,sam9x60-usart + - items: + - const: atmel,at91rm9200-dbgu + - const: atmel,at91rm9200-usart + - items: + - const: atmel,at91sam9260-dbgu + - const: atmel,at91sam9260-usart + - items: + - const: microchip,sam9x60-dbgu + - const: microchip,sam9x60-usart + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clock-names: + const: usart + + clocks: + maxItems: 1 + + dmas: + items: + - description: TX DMA Channel + - description: RX DMA Channel + + dma-names: + items: + - const: tx + - const: rx + + atmel,usart-mode: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Must be either for SPI or + for USART (found in dt-bindings/mfd/at91-usart.h). + enum: [ 0, 1 ] + +required: + - compatible + - reg + - interrupts + - clock-names + - clocks + +allOf: + - if: + properties: + $nodename: + pattern: "^serial@[0-9a-f]+$" + then: + allOf: + - $ref: /schemas/serial/serial.yaml# + - $ref: /schemas/serial/rs485.yaml# + + properties: + atmel,use-dma-rx: + type: boolean + description: use of PDC or DMA for receiving data + + atmel,use-dma-tx: + type: boolean + description: use of PDC or DMA for transmitting data + + atmel,fifo-size: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Maximum number of data the RX and TX FIFOs can store for FIFO + capable USARTS. + enum: [ 16, 32 ] + + else: + if: + properties: + $nodename: + pattern: "^spi@[0-9a-f]+$" + then: + allOf: + - $ref: /schemas/spi/spi-controller.yaml# + + properties: + atmel,usart-mode: + const: 1 + + "#size-cells": + const: 0 + + "#address-cells": + const: 1 + + required: + - atmel,usart-mode + - "#size-cells" + - "#address-cells" + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + + /* use PDC */ + usart0: serial@fff8c000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfff8c000 0x4000>; + interrupts = <7>; + clocks = <&usart0_clk>; + clock-names = "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + rts-gpios = <&pioD 15 GPIO_ACTIVE_LOW>; + cts-gpios = <&pioD 16 GPIO_ACTIVE_LOW>; + dtr-gpios = <&pioD 17 GPIO_ACTIVE_LOW>; + dsr-gpios = <&pioD 18 GPIO_ACTIVE_LOW>; + dcd-gpios = <&pioD 20 GPIO_ACTIVE_LOW>; + rng-gpios = <&pioD 19 GPIO_ACTIVE_LOW>; + }; + + - | + #include + #include + #include + #include + + /* use DMA */ + usart1: serial@f001c000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf001c000 0x100>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>; + clocks = <&usart0_clk>; + clock-names = "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(3)>, + <&dma0 2 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>; + dma-names = "tx", "rx"; + atmel,fifo-size = <32>; + }; + + - | + #include + #include + #include + #include + + /* SPI mode */ + spi0: spi@f001c000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf001c000 0x100>; + #address-cells = <1>; + #size-cells = <0>; + atmel,usart-mode = ; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>; + clocks = <&usart0_clk>; + clock-names = "usart"; + dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(3)>, + <&dma0 2 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>; + dma-names = "tx", "rx"; + cs-gpios = <&pioB 3 GPIO_ACTIVE_HIGH>; + }; From patchwork Tue Sep 6 13:55:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiu Moga X-Patchwork-Id: 12967671 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EE40CC6FA83 for ; Tue, 6 Sep 2022 14:53:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242211AbiIFOxH (ORCPT ); Tue, 6 Sep 2022 10:53:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57736 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238686AbiIFOwc (ORCPT ); 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06 Sep 2022 06:57:10 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 6 Sep 2022 06:57:05 -0700 Received: from ROB-ULT-M68701.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Tue, 6 Sep 2022 06:57:00 -0700 From: Sergiu Moga To: , , , , , , , , , , , , , , , , CC: , , , , , Subject: [PATCH v2 06/13] dt-bindings: serial: atmel,at91-usart: Add SAM9260 compatibles to SAM9x60 Date: Tue, 6 Sep 2022 16:55:05 +0300 Message-ID: <20220906135511.144725-7-sergiu.moga@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220906135511.144725-1-sergiu.moga@microchip.com> References: <20220906135511.144725-1-sergiu.moga@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Add the AT91SAM9260 serial compatibles to the list of SAM9X60 compatibles in order to highlight the incremental characteristics of the SAM9X60 serial IP. Signed-off-by: Sergiu Moga --- v1 -> v2: - Nothing, this patch was not here before Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml index b25535b7a4d2..4d80006963c7 100644 --- a/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml +++ b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml @@ -26,6 +26,8 @@ properties: - items: - const: microchip,sam9x60-dbgu - const: microchip,sam9x60-usart + - const: atmel,at91sam9260-dbgu + - const: atmel,at91sam9260-usart reg: maxItems: 1 From patchwork Tue Sep 6 13:55:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiu Moga X-Patchwork-Id: 12967664 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 97248C6FA86 for ; Tue, 6 Sep 2022 14:47:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240720AbiIFOrD (ORCPT ); Tue, 6 Sep 2022 10:47:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41002 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231342AbiIFOqm (ORCPT ); Tue, 6 Sep 2022 10:46:42 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 65DDD98A51; Tue, 6 Sep 2022 07:05:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1662473126; x=1694009126; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=sPvmXHZOZTxiNsV8wQo2cqTLQ91qkb2yzTXY3QfEQ3U=; b=ljYQYc+SvScQBoglQ4NCQuG93fnqmL48wjxSOWHlyPfKS7AqkIcurUCh rndVYmIgq0XaOr+zZBRb/nkXlxvmUEnZFHhFC0hNkjFfOe4AwvwEs0De1 8HcmqYjkbx5+rSLf95WC7hWwsug8Xjlim4IbRn/1q/qfsWkQPhRpd0drP r265D/Y1cewcqSpSadrUbPe5DGANh7wCgCGcPN4ozA2fZXs4IqvkcNW8n 6xumx27Pg//QXzW8zJNWKB9D/LHTXXRQCWy9OL3Uapr9ffXS4do2UFxpb +uzYFL4U5fcHUZalFHk8BQAu7qTGlIHKnTyBSXLWXIaZIDpn2Hpaqn0dS w==; X-IronPort-AV: E=Sophos;i="5.93,294,1654585200"; d="scan'208";a="179223615" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 06 Sep 2022 06:57:12 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 6 Sep 2022 06:57:10 -0700 Received: from ROB-ULT-M68701.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Tue, 6 Sep 2022 06:57:05 -0700 From: Sergiu Moga To: , , , , , , , , , , , , , , , , CC: , , , , , Subject: [PATCH v2 07/13] dt-bindings: mfd: atmel,sama5d2-flexcom: Add USART child node ref binding Date: Tue, 6 Sep 2022 16:55:06 +0300 Message-ID: <20220906135511.144725-8-sergiu.moga@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220906135511.144725-1-sergiu.moga@microchip.com> References: <20220906135511.144725-1-sergiu.moga@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org FLEXCOM, among other functionalities, has the ability to offer the USART serial communication protocol. To have the FLEXCOM binding properly validate its USART children nodes, we must reference the correct binding. To differentiate between the SPI of FLEXCOM and the SPI of USART in SPI mode, use the clock-names property, since the latter's respective property is supposed to contain the "usart" string. Signed-off-by: Sergiu Moga --- v1 -> v2: - Nothing .../bindings/mfd/atmel,sama5d2-flexcom.yaml | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml b/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml index 0db0f2728b65..b5fb509f07ec 100644 --- a/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml +++ b/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml @@ -72,13 +72,21 @@ properties: patternProperties: "^serial@[0-9a-f]+$": - type: object + $ref: /schemas/serial/atmel,at91-usart.yaml description: - Child node describing USART. See atmel-usart.txt for details - of USART bindings. + Child node describing USART. "^spi@[0-9a-f]+$": - $ref: /schemas/spi/atmel,at91rm9200-spi.yaml + allOf: + - if: + properties: + clock-names: + contains: + const: usart + then: + $ref: /schemas/serial/atmel,at91-usart.yaml + else: + $ref: /schemas/spi/atmel,at91rm9200-spi.yaml description: Child node describing SPI. From patchwork Tue Sep 6 13:55:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiu Moga X-Patchwork-Id: 12967634 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 34284C6FA86 for ; Tue, 6 Sep 2022 14:34:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241945AbiIFOe0 (ORCPT ); Tue, 6 Sep 2022 10:34:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55372 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242342AbiIFOdr (ORCPT ); Tue, 6 Sep 2022 10:33:47 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8977E8276D; Tue, 6 Sep 2022 06:59:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1662472748; x=1694008748; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ttW5D/aDzcSJYKXL2Ks4x6nT/tiEMuarCbgMkNwvAac=; b=bS4iemoHyFCEbwfTooy+f95UT5QlEwm1z+kaJiKB4Nkb014au3/ri01F QwGtkuRjo9IX+lz9mYAAtmQmBolnDQ0waEXwGtQswIvpAQ9FJ6JeMBFqC 7KOWowNi3/K0S4uzDVX6mxz2vTClz1tjnYrjrPZia5cdei8b94FHn/hzi iK+KunY45V9/8fppgN29+WWlp5cOXaWQiqnjvmLBo2BHURU2OyknpHr6h UgCDq6kuCQ6K8fo73W6K0L1NpSLYhmAkMA3qKD1j9g3xMlGsT61uP1HJq RvH+4Gwe1bJ2P9H8i0VzM/tbtt5gp8KtBxuRaqxcTAi58Y7SJfxV1eVJi w==; X-IronPort-AV: E=Sophos;i="5.93,294,1654585200"; d="scan'208";a="189613904" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 06 Sep 2022 06:57:16 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 6 Sep 2022 06:57:15 -0700 Received: from ROB-ULT-M68701.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Tue, 6 Sep 2022 06:57:10 -0700 From: Sergiu Moga To: , , , , , , , , , , , , , , , , CC: , , , , , Subject: [PATCH v2 08/13] tty: serial: atmel: Define GCLK as USART baudrate source clock Date: Tue, 6 Sep 2022 16:55:07 +0300 Message-ID: <20220906135511.144725-9-sergiu.moga@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220906135511.144725-1-sergiu.moga@microchip.com> References: <20220906135511.144725-1-sergiu.moga@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Define the bit that represents the choice of having GCLK as a baudrate source clock inside the USCLKS bitmask of the Mode Register of USART IP's. Signed-off-by: Sergiu Moga --- v1 -> v2: - Nothing, this patch was not here before drivers/tty/serial/atmel_serial.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/tty/serial/atmel_serial.h b/drivers/tty/serial/atmel_serial.h index 0d8a0f9cc5c3..70d0611e56fd 100644 --- a/drivers/tty/serial/atmel_serial.h +++ b/drivers/tty/serial/atmel_serial.h @@ -49,6 +49,7 @@ #define ATMEL_US_USCLKS GENMASK(5, 4) /* Clock Selection */ #define ATMEL_US_USCLKS_MCK (0 << 4) #define ATMEL_US_USCLKS_MCK_DIV8 (1 << 4) +#define ATMEL_US_USCLKS_GCLK (2 << 4) #define ATMEL_US_USCLKS_SCK (3 << 4) #define ATMEL_US_CHRL GENMASK(7, 6) /* Character Length */ #define ATMEL_US_CHRL_5 (0 << 6) From patchwork Tue Sep 6 13:55:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiu Moga X-Patchwork-Id: 12967649 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 70C67C6FA89 for ; Tue, 6 Sep 2022 14:39:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242184AbiIFOjz (ORCPT ); Tue, 6 Sep 2022 10:39:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52796 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239754AbiIFOi0 (ORCPT ); Tue, 6 Sep 2022 10:38:26 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8F0D49A6A8; Tue, 6 Sep 2022 07:00:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1662472848; x=1694008848; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=X/ar3dqdTBAXl4yVl+JbHybkXPhhp+6FzbNlV23f2H0=; b=TumRLoQuuJJGOSgu5XUdHvbxCU81El62UYukzwZ2RD3Y0VARXe7cy5au mXzwgzoFaOq2PHoHcq1PlTl/d8WMNx5kSU63gfn3ivP+jMw32GlKf723i 9tRE9y0YUTNRwA5ORFUzLOEaFKQxw9NnwHmcFvPr+ObHC834rwh8GKeNT pB+rj8yr5Xmck3lgTETTVLRduny4QbdBytBtdwd4nbQ/nP2ALsu2J0WQT SU7Mp3IxeexXEcK4zV9UTW4j4J5sbyQD6EFyrQgi9Xy/OXvsXhdyAqDNj LFkit6NuAab6TWe5xitAPo+PU6eoZ5LBYabT/1Ht26WsjcnIm9YaBXLG6 g==; X-IronPort-AV: E=Sophos;i="5.93,294,1654585200"; d="scan'208";a="175830153" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 06 Sep 2022 06:57:30 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 6 Sep 2022 06:57:21 -0700 Received: from ROB-ULT-M68701.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Tue, 6 Sep 2022 06:57:16 -0700 From: Sergiu Moga To: , , , , , , , , , , , , , , , , CC: , , , , , Subject: [PATCH v2 09/13] tty: serial: atmel: Define BRSRCCK bitmask of UART IP's Mode Register Date: Tue, 6 Sep 2022 16:55:08 +0300 Message-ID: <20220906135511.144725-10-sergiu.moga@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220906135511.144725-1-sergiu.moga@microchip.com> References: <20220906135511.144725-1-sergiu.moga@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Add definitions for the Baud Rate Source Clock bitmask of the Mode Register of UART IP's and its bitfields. Signed-off-by: Sergiu Moga --- v1 -> v2: - Nothing, this patch was not here before drivers/tty/serial/atmel_serial.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/tty/serial/atmel_serial.h b/drivers/tty/serial/atmel_serial.h index 70d0611e56fd..ed64035ba6c3 100644 --- a/drivers/tty/serial/atmel_serial.h +++ b/drivers/tty/serial/atmel_serial.h @@ -68,6 +68,9 @@ #define ATMEL_US_NBSTOP_1 (0 << 12) #define ATMEL_US_NBSTOP_1_5 (1 << 12) #define ATMEL_US_NBSTOP_2 (2 << 12) +#define ATMEL_UA_BRSRCCK GENMASK(13, 12) /* Clock Selection for UART */ +#define ATMEL_UA_BRSRCCK_PERIPH_CLK (0 << 12) +#define ATMEL_UA_BRSRCCK_GCLK (1 << 12) #define ATMEL_US_CHMODE GENMASK(15, 14) /* Channel Mode */ #define ATMEL_US_CHMODE_NORMAL (0 << 14) #define ATMEL_US_CHMODE_ECHO (1 << 14) From patchwork Tue Sep 6 13:55:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiu Moga X-Patchwork-Id: 12967648 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 32DC0ECAAA1 for ; Tue, 6 Sep 2022 14:39:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233110AbiIFOjy (ORCPT ); Tue, 6 Sep 2022 10:39:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49154 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242215AbiIFOir (ORCPT ); Tue, 6 Sep 2022 10:38:47 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9C1F49A964; Tue, 6 Sep 2022 07:00:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1662472857; x=1694008857; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=pk0hBeRzv9yrSvjx77z7pR8KMLbpypDtOQMtHWLcCCU=; b=OWPO9sIzkxP4jocz/tYqCEZPLZBqAyq6myzvB1OVIVjJN+6TmZhgdVBH uCGp7bXKA4cMtUf1S3g6cthOgsgMnpjpEqNV+xqVVCva96n3Hk6JROMxv UOleduYl7jCJ7jYwGEH7s3HgFoSef66iEN3cHXJrekfkbDoZ0b1mT4Xfh ylfBkPI8pAYIeWkXLrpYkvJUjpWM8LIPmVLSlm4RoWvB4nWp6YPKUNmOj KOWvK7xVqrs6MSGKfMyw57daMPKUT3CTuZG5bW+6dcnX8TaGIOIGTvcPl neJdUZz7k9+inxZjsLicfSRfCuh3zv2HyFKGOv4NEKx4InCS5DmRT6poh w==; X-IronPort-AV: E=Sophos;i="5.93,294,1654585200"; d="scan'208";a="175830165" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 06 Sep 2022 06:57:31 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 6 Sep 2022 06:57:26 -0700 Received: from ROB-ULT-M68701.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Tue, 6 Sep 2022 06:57:21 -0700 From: Sergiu Moga To: , , , , , , , , , , , , , , , , CC: , , , , , Subject: [PATCH v2 10/13] tty: serial: atmel: Only divide Clock Divisor if the IP is USART Date: Tue, 6 Sep 2022 16:55:09 +0300 Message-ID: <20220906135511.144725-11-sergiu.moga@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220906135511.144725-1-sergiu.moga@microchip.com> References: <20220906135511.144725-1-sergiu.moga@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Make sure that the driver only divides the clock divisor if the IP handled at that point is USART, since UART IP's do not support implicit peripheral clock division. Instead, in the case of UART, go with the highest possible clock divisor. Signed-off-by: Sergiu Moga --- v1 -> v2: - Nothing, this patch was not here before and is mainly meant as both cleanup and as a way to introduce a new field into struct atmel_uart_port that will be used by the last patch to diferentiate between USART and UART regarding the location of the Baudrate Clock Source bitmask. drivers/tty/serial/atmel_serial.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/tty/serial/atmel_serial.c b/drivers/tty/serial/atmel_serial.c index 7450d3853031..6aa01ca5489c 100644 --- a/drivers/tty/serial/atmel_serial.c +++ b/drivers/tty/serial/atmel_serial.c @@ -150,6 +150,7 @@ struct atmel_uart_port { u32 rts_low; bool ms_irq_enabled; u32 rtor; /* address of receiver timeout register if it exists */ + bool is_usart; bool has_frac_baudrate; bool has_hw_timer; struct timer_list uart_timer; @@ -1825,6 +1826,7 @@ static void atmel_get_ip_name(struct uart_port *port) */ atmel_port->has_frac_baudrate = false; atmel_port->has_hw_timer = false; + atmel_port->is_usart = false; if (name == new_uart) { dev_dbg(port->dev, "Uart with hw timer"); @@ -1834,6 +1836,7 @@ static void atmel_get_ip_name(struct uart_port *port) dev_dbg(port->dev, "Usart\n"); atmel_port->has_frac_baudrate = true; atmel_port->has_hw_timer = true; + atmel_port->is_usart = true; atmel_port->rtor = ATMEL_US_RTOR; version = atmel_uart_readl(port, ATMEL_US_VERSION); switch (version) { @@ -1863,6 +1866,7 @@ static void atmel_get_ip_name(struct uart_port *port) dev_dbg(port->dev, "This version is usart\n"); atmel_port->has_frac_baudrate = true; atmel_port->has_hw_timer = true; + atmel_port->is_usart = true; atmel_port->rtor = ATMEL_US_RTOR; break; case 0x203: @@ -2282,10 +2286,17 @@ static void atmel_set_termios(struct uart_port *port, struct ktermios *termios, cd = uart_get_divisor(port, baud); } - if (cd > 65535) { /* BRGR is 16-bit, so switch to slower clock */ + /* + * BRGR is 16-bit, so switch to slower clock. + * Otherwise, keep the highest possible value for the clock divisor. + */ + if (atmel_port->is_usart && cd > 65535) { cd /= 8; mode |= ATMEL_US_USCLKS_MCK_DIV8; + } else { + cd &= 65535; } + quot = cd | fp << ATMEL_US_FP_OFFSET; if (!(port->iso7816.flags & SER_ISO7816_ENABLED)) From patchwork Tue Sep 6 13:55:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiu Moga X-Patchwork-Id: 12967647 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5C13FC6FA86 for ; Tue, 6 Sep 2022 14:39:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239907AbiIFOjw (ORCPT ); Tue, 6 Sep 2022 10:39:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46364 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242301AbiIFOjD (ORCPT ); Tue, 6 Sep 2022 10:39:03 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9C64A9A95D; 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Tue, 6 Sep 2022 06:57:31 -0700 Received: from ROB-ULT-M68701.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Tue, 6 Sep 2022 06:57:26 -0700 From: Sergiu Moga To: , , , , , , , , , , , , , , , , CC: , , , , , Subject: [PATCH v2 11/13] clk: at91: sama5d2: Add Generic Clocks for UART/USART Date: Tue, 6 Sep 2022 16:55:10 +0300 Message-ID: <20220906135511.144725-12-sergiu.moga@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220906135511.144725-1-sergiu.moga@microchip.com> References: <20220906135511.144725-1-sergiu.moga@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Add the generic clocks for UART/USART in the sama5d2 driver to allow them to be registered in the Common Clock Framework. Signed-off-by: Sergiu Moga Reviewed-by: Claudiu Beznea --- v1 -> v2: - Added R-b tag drivers/clk/at91/sama5d2.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/clk/at91/sama5d2.c b/drivers/clk/at91/sama5d2.c index cfd0f5e23b99..84156dc52bff 100644 --- a/drivers/clk/at91/sama5d2.c +++ b/drivers/clk/at91/sama5d2.c @@ -120,6 +120,16 @@ static const struct { struct clk_range r; int chg_pid; } sama5d2_gck[] = { + { .n = "flx0_gclk", .id = 19, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, }, + { .n = "flx1_gclk", .id = 20, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, }, + { .n = "flx2_gclk", .id = 21, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, }, + { .n = "flx3_gclk", .id = 22, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, }, + { .n = "flx4_gclk", .id = 23, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, }, + { .n = "uart0_gclk", .id = 24, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, }, + { .n = "uart1_gclk", .id = 25, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, }, + { .n = "uart2_gclk", .id = 26, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, }, + { .n = "uart3_gclk", .id = 27, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, }, + { .n = "uart4_gclk", .id = 28, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, }, { .n = "sdmmc0_gclk", .id = 31, .chg_pid = INT_MIN, }, { .n = "sdmmc1_gclk", .id = 32, .chg_pid = INT_MIN, }, { .n = "tcb0_gclk", .id = 35, .chg_pid = INT_MIN, .r = { .min = 0, .max = 83000000 }, }, From patchwork Tue Sep 6 13:55:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiu Moga X-Patchwork-Id: 12967665 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5E6A5C6FA83 for ; Tue, 6 Sep 2022 14:48:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237517AbiIFOsB (ORCPT ); Tue, 6 Sep 2022 10:48:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52130 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238150AbiIFOrd (ORCPT ); Tue, 6 Sep 2022 10:47:33 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8BFD89F0D2; Tue, 6 Sep 2022 07:05:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1662473150; x=1694009150; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=73Fho7ppKG3cNkllUIc8oZOXuO1dn/FLBA9ZkmVxUtw=; b=fv0AJly9EEhcUvSSrHV9ix7WdBs60qegWJpjpYxkicG1wRsql9nLFoFr tJTrkjbgaQka18iEsv8AfCY6QuVVUXI2+jJJo03CoE8tTtQC3mB+izbh6 4+fhkNv0sVURKWthwoHlBiGPtAzrJX1UKDFZKT3asHwpdYItmxWoCBXvH LbHsj6rSrHxu8I/ATrQRELYaAqN/1NCjmWOstIM3I6bAu1GQW9RCdAg8r WjMixDFu92ESHzwquEHZVuIVLqZZ1SjtVsVjhLQsKdMWDNbUqqdI/P9az YG+808Lzs14Z5wANJYA9LCPSvrY3sn6wkH0GOoxJ/9k77YmfeVhE/hJU/ g==; X-IronPort-AV: E=Sophos;i="5.93,294,1654585200"; d="scan'208";a="179351255" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 06 Sep 2022 06:57:38 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 6 Sep 2022 06:57:37 -0700 Received: from ROB-ULT-M68701.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Tue, 6 Sep 2022 06:57:32 -0700 From: Sergiu Moga To: , , , , , , , , , , , , , , , , CC: , , , , , Subject: [PATCH v2 12/13] tty: serial: atmel: Make the driver aware of the existence of GCLK Date: Tue, 6 Sep 2022 16:55:11 +0300 Message-ID: <20220906135511.144725-13-sergiu.moga@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220906135511.144725-1-sergiu.moga@microchip.com> References: <20220906135511.144725-1-sergiu.moga@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Previously, the atmel serial driver did not take into account the possibility of using the more customizable generic clock as its baudrate generator. Unless there is a Fractional Part available to increase accuracy, there is a high chance that we may be able to generate a baudrate closer to the desired one by using the GCLK as the clock source. Now, depending on the error rate between the desired baudrate and the actual baudrate, the serial driver will fallback on the generic clock. The generic clock must be provided in the DT node of the serial that may need a more flexible clock source. Signed-off-by: Sergiu Moga --- v1 -> v2: - take into account the different placement of the baudrate clock source into the IP's Mode Register (USART vs UART) - don't check for atmel_port->gclk != NULL - use clk_round_rate instead of clk_set_rate + clk_get_rate - remove clk_disable_unprepare from the end of the probe method drivers/tty/serial/atmel_serial.c | 52 ++++++++++++++++++++++++++++++- 1 file changed, 51 insertions(+), 1 deletion(-) diff --git a/drivers/tty/serial/atmel_serial.c b/drivers/tty/serial/atmel_serial.c index 6aa01ca5489c..b2b6fd6ea2a5 100644 --- a/drivers/tty/serial/atmel_serial.c +++ b/drivers/tty/serial/atmel_serial.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -77,6 +78,8 @@ static void atmel_stop_rx(struct uart_port *port); #endif #define ATMEL_ISR_PASS_LIMIT 256 +#define ERROR_RATE(desired_value, actual_value) \ + ((int)(100 - ((desired_value) * 100) / (actual_value))) struct atmel_dma_buffer { unsigned char *buf; @@ -110,6 +113,7 @@ struct atmel_uart_char { struct atmel_uart_port { struct uart_port uart; /* uart */ struct clk *clk; /* uart clock */ + struct clk *gclk; /* uart generic clock */ int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */ u32 backup_imr; /* IMR saved during suspend */ int break_active; /* break being received */ @@ -2117,6 +2121,8 @@ static void atmel_serial_pm(struct uart_port *port, unsigned int state, * This is called on uart_close() or a suspend event. */ clk_disable_unprepare(atmel_port->clk); + if (__clk_is_enabled(atmel_port->gclk)) + clk_disable_unprepare(atmel_port->gclk); break; default: dev_err(port->dev, "atmel_serial: unknown pm %d\n", state); @@ -2131,7 +2137,8 @@ static void atmel_set_termios(struct uart_port *port, struct ktermios *termios, { struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); unsigned long flags; - unsigned int old_mode, mode, imr, quot, baud, div, cd, fp = 0; + unsigned int old_mode, mode, imr, quot, div, cd, fp = 0; + unsigned int baud, actual_baud, gclk_rate; /* save the current mode register */ mode = old_mode = atmel_uart_readl(port, ATMEL_US_MR); @@ -2297,6 +2304,43 @@ static void atmel_set_termios(struct uart_port *port, struct ktermios *termios, cd &= 65535; } + /* + * If there is no Fractional Part, there is a high chance that + * we may be able to generate a baudrate closer to the desired one + * if we use the GCLK as the clock source driving the baudrate + * generator. + */ + if (!atmel_port->has_frac_baudrate) { + if (__clk_is_enabled(atmel_port->gclk)) + clk_disable_unprepare(atmel_port->gclk); + gclk_rate = clk_round_rate(atmel_port->gclk, 16 * baud); + actual_baud = clk_get_rate(atmel_port->clk) / (16 * cd); + if (gclk_rate && abs(ERROR_RATE(baud, actual_baud)) > + abs(ERROR_RATE(baud, gclk_rate / 16))) { + clk_set_rate(atmel_port->gclk, 16 * baud); + if (!clk_prepare_enable(atmel_port->gclk)) { + if (atmel_port->is_usart) { + mode &= ~ATMEL_US_USCLKS; + mode |= ATMEL_US_USCLKS_GCLK; + } else { + mode &= ~ATMEL_UA_BRSRCCK; + mode |= ATMEL_UA_BRSRCCK_GCLK; + } + + /* + * Set the Clock Divisor for GCLK to 1. + * Since we were able to generate the smallest + * multiple of the desired baudrate times 16, + * then we surely can generate a bigger multiple + * with the exact error rate for an equally increased + * CD. Thus no need to take into account + * a higher value for CD. + */ + cd = 1; + } + } + } + quot = cd | fp << ATMEL_US_FP_OFFSET; if (!(port->iso7816.flags & SER_ISO7816_ENABLED)) @@ -2892,6 +2936,12 @@ static int atmel_serial_probe(struct platform_device *pdev) if (ret) goto err; + atmel_port->gclk = devm_clk_get_optional(&pdev->dev, "gclk"); + if (IS_ERR(atmel_port->gclk)) { + ret = PTR_ERR(atmel_port->gclk); + goto err; + } + ret = atmel_init_port(atmel_port, pdev); if (ret) goto err_clk_disable_unprepare; From patchwork Tue Sep 6 13:55:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiu Moga X-Patchwork-Id: 12967672 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 39769C6FA83 for ; Tue, 6 Sep 2022 14:54:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234054AbiIFOx1 (ORCPT ); Tue, 6 Sep 2022 10:53:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57174 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233360AbiIFOw6 (ORCPT ); Tue, 6 Sep 2022 10:52:58 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 66A7A95B4; Tue, 6 Sep 2022 07:09:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1662473372; x=1694009372; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=qnRuIvqb2EIJBjRR/INNwmO5YT4t+bc7TsYz9wHYHEA=; b=Jo21PHGXDG1tZiUjZ0tHAPOkaphsG2G3IRDEEAKvQxg+lgKWEhjCETAz kW1TPPOMVVqUWHNL0pMBpwZDBMOCmIRchn8eqvVlwlh5ak2TfGkoDkJIX ZS41t/SrfpY5gAO2BMUowgujnH2SyBljKxrJDwHbbFouNuCyjEQx0p2Am x49hJwoGG9KFcLzasWHzNjovB5LTHH7pQbfxfnRpZHBJEMnJRK1z/yrcA OrJ0106dwRPFR2TfXF4qdILzpZcafrdoUfE9aiQKZo/KTfkxPTmmWPMZN X2n3UAoGEOHyTzio36lvN8ypxKWJw0ad3rzby19ojnToFSbIxgqV2fxXn Q==; X-IronPort-AV: E=Sophos;i="5.93,294,1654585200"; d="scan'208";a="112380574" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 06 Sep 2022 06:57:42 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 6 Sep 2022 06:57:42 -0700 Received: from ROB-ULT-M68701.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Tue, 6 Sep 2022 06:57:37 -0700 From: Sergiu Moga To: , , , , , , , , , , , , , , , , CC: , , , , , Subject: [PATCH v2 13/13] dt-bindings: serial: atmel,at91-usart: Add gclk as a possible USART clock Date: Tue, 6 Sep 2022 16:55:12 +0300 Message-ID: <20220906135511.144725-14-sergiu.moga@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220906135511.144725-1-sergiu.moga@microchip.com> References: <20220906135511.144725-1-sergiu.moga@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org The Devicetree nodes for FLEXCOM's USART can also have an alternative clock source for the baudrate generator (other than the peripheral clock), namely the Generick Clock. Thus make the binding aware of this potential clock that someone may place in the clock related properties of the USART node. Signed-off-by: Sergiu Moga --- v1 -> v2: - Nothing, this patch was not here before .../devicetree/bindings/serial/atmel,at91-usart.yaml | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml index 4d80006963c7..db595b498bad 100644 --- a/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml +++ b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml @@ -36,10 +36,16 @@ properties: maxItems: 1 clock-names: - const: usart + minItems: 1 + items: + - const: usart + - const: gclk clocks: - maxItems: 1 + minItems: 1 + items: + - description: USART Peripheral Clock + - description: USART Generic Clock dmas: items: