From patchwork Wed Sep 7 10:48:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Like Xu X-Patchwork-Id: 12968804 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 462A6C38145 for ; Wed, 7 Sep 2022 10:49:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229723AbiIGKs7 (ORCPT ); Wed, 7 Sep 2022 06:48:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38876 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229477AbiIGKs5 (ORCPT ); Wed, 7 Sep 2022 06:48:57 -0400 Received: from mail-pf1-x42a.google.com (mail-pf1-x42a.google.com [IPv6:2607:f8b0:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2AFFE85FF4; Wed, 7 Sep 2022 03:48:57 -0700 (PDT) Received: by mail-pf1-x42a.google.com with SMTP id y136so9273804pfb.3; Wed, 07 Sep 2022 03:48:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date; bh=TeQlVcT77pEQtuTbf7OOQb9vpiZRFZqlXe4X8qaQLZQ=; b=hnsvqfhuUA55epY9rfkfpSssISb5V7LmfXGduqnJSdY91WYQH704F/AxVEO1hlI5Jg 3+Gj/Tk5c0lMP5WTUbQK6idPtTAJ53brKLNpmX/gxhdoMwJnfqiUdhOjoWWGX9djgiCr GGI21an9QH8JF/lPmZBfKIEyJ9eyWjk5ipMn6rnbDopuquW5KVDKCwE9PPUdFoE4yiTo ewUieeOwx8l69kZ+v7tWnG2jrJ0oxMtj2bbvfmlav/kvvM4p0XgXmUP4glLk80jXAABd D/oZnTLKUUcN2248bLT0ZJQTUzSKoEH9IX/kPXh6eO5eb76hr6mTaDB9xUS9Kin93iQ1 wusg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date; bh=TeQlVcT77pEQtuTbf7OOQb9vpiZRFZqlXe4X8qaQLZQ=; b=xExwlylsRA89rJGJLr8WWPLavRdyMReOTnkROBe/rdcycx7MQfO1HG6t6aEz3t3iGk 1EVlC8O3eMwGLDHUjc3zW8SQYBaIefb9Sfbam3pOSw/o6FbTIfXQ7s4ULpYELunDYDX2 wme4aWbq5smloMYRZ/7R97kQ/+8/4G7ZW0qUDgm9zrZkiALeUWgI8WsNBFpuC+WJngxt D4a7dwxxrIYwQtVRjfngGKWtJYHIAF9hIRB0BxE/StSZhxjHO9Jp6jlE/tHGdokOwDdm g6UIAgt5FDT9eX2q/zhTfOACZprJ440ndFXflAmlZ+eJStq8er+DIMxeKhyGIMBSXgkx 6KQw== X-Gm-Message-State: ACgBeo2986m36Sa6pbZZjYJZS+D+KJPIw4jaUg0aP3qaGtmay91RhOu+ qtpuX4H8T5aVt8VdfbJwA+E= X-Google-Smtp-Source: AA6agR7DQtvn0PvFjeuiADxzE0kJBFyK1O5StlJvBR9RCLvr3sfWj68GbVSZ7XrldEqdfNp7fD0++Q== X-Received: by 2002:a63:5757:0:b0:434:fe36:3fe8 with SMTP id h23-20020a635757000000b00434fe363fe8mr860920pgm.619.1662547736634; Wed, 07 Sep 2022 03:48:56 -0700 (PDT) Received: from localhost.localdomain ([103.7.29.32]) by smtp.gmail.com with ESMTPSA id x14-20020aa79a4e000000b0053e22fc5b4fsm4044044pfj.0.2022.09.07.03.48.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Sep 2022 03:48:56 -0700 (PDT) From: Like Xu X-Google-Original-From: Like Xu To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Vitaly Kuznetsov , Jim Mattson Subject: [PATCH v2 1/3] KVM: x86/pmu: Stop adding speculative Intel GP PMCs that don't exist yet Date: Wed, 7 Sep 2022 18:48:36 +0800 Message-Id: <20220907104838.8424-1-likexu@tencent.com> X-Mailer: git-send-email 2.37.3 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Like Xu The Intel April 2022 SDM - Table 2-2. IA-32 Architectural MSRs adds a new architectural IA32_OVERCLOCKING_STATUS msr (0x195), plus the presence of IA32_CORE_CAPABILITIES (0xCF), the theoretical effective maximum value of the Intel GP PMCs is 14 (0xCF - 0xC1) instead of 18. But the conclusion of this speculation "14" is very fragile and can easily be overturned once Intel declares another meaningful arch msr in the above reserved range, and even worse, Intel probably put PMCs 8-15 in a completely different range of MSR indices. A conservative proposal would be to stop at the maximum number of Intel GP PMCs supported today. Also subsequent changes would limit both AMD and Intel on the number of GP counter supported by KVM. There are some boxes like Intel P4 may indeed have 18 counters, but those counters are in a completely different msr address range and do not strictly adhere to the Intel Arch PMU specification, and will not be supported by KVM in the near future. Cc: Vitaly Kuznetsov Suggested-by: Jim Mattson Signed-off-by: Like Xu Reviewed-by: Jim Mattson --- Previous: https://lore.kernel.org/kvm/20220906081604.24035-1-likexu@tencent.com/ V1 -> V2 Changelog: - Stop at the maximum number of GP PMCs supported today; (Jim) arch/x86/kvm/x86.c | 14 ++------------ 1 file changed, 2 insertions(+), 12 deletions(-) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 43a6a7efc6ec..884f6de11a33 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -1428,20 +1428,10 @@ static const u32 msrs_to_save_all[] = { MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3, MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5, MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7, - MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9, - MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11, - MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13, - MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15, - MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17, MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1, MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3, MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5, MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7, - MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9, - MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11, - MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13, - MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15, - MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17, MSR_IA32_PEBS_ENABLE, MSR_IA32_DS_AREA, MSR_PEBS_DATA_CFG, MSR_K7_EVNTSEL0, MSR_K7_EVNTSEL1, MSR_K7_EVNTSEL2, MSR_K7_EVNTSEL3, @@ -6943,12 +6933,12 @@ static void kvm_init_msr_list(void) intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2) continue; break; - case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17: + case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 7: if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >= min(INTEL_PMC_MAX_GENERIC, kvm_pmu_cap.num_counters_gp)) continue; break; - case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17: + case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 7: if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >= min(INTEL_PMC_MAX_GENERIC, kvm_pmu_cap.num_counters_gp)) continue; From patchwork Wed Sep 7 10:48:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Like Xu X-Patchwork-Id: 12968805 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2148FC38145 for ; Wed, 7 Sep 2022 10:49:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229829AbiIGKtB (ORCPT ); Wed, 7 Sep 2022 06:49:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38884 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229773AbiIGKs7 (ORCPT ); Wed, 7 Sep 2022 06:48:59 -0400 Received: from mail-pj1-x1035.google.com (mail-pj1-x1035.google.com [IPv6:2607:f8b0:4864:20::1035]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E3C7D85FF4; Wed, 7 Sep 2022 03:48:58 -0700 (PDT) Received: by mail-pj1-x1035.google.com with SMTP id o2-20020a17090a9f8200b0020025a22208so10642376pjp.2; Wed, 07 Sep 2022 03:48:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=dfT4FzvwwKlQZnIuSLlYyTj6W7EjK7O33+q3fAWSgb0=; b=jdJK35vQ1696uJEUPo5YpRTagxp335KyDP1YpvfBWjBqnRZm3s5ZGRd25bzywXmoP+ MX9ZObSxNn2Gr92zYPUkxNWeNDsnKTvltL5dACVVT52ZdAp/rNQQR77hLMeoCvBqVM+U vWbWK4x2FXXcKVWNSN+urNKbkc8Hv6Kvj9HO+Un8BMt4HTXlszxxTgZ5BhV+9EwsV3nk LoLV4ep8c5bD7pzlq7Up3QIg5bjtHF+gapaWLjhkFCTGbXMAKaNTBbyuYaW7uKUeahpy 4LmQDXLRC9Q3AMb7MWQp2mGr5dH7O4XjoFV0bUHFQvn0+PZwY5LrE+jhEM0SK5jnq8Q1 hQiw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=dfT4FzvwwKlQZnIuSLlYyTj6W7EjK7O33+q3fAWSgb0=; b=tgxmbjJUQe0F5KxytfzLN0DujOQh/ranI/b+DuUIG96zmCzb2lCkpv2SsOCene9qEj Ecv3TaF489NC50Nn9rfdhz2ZeooKa5NH1gPK6pHZbaCU3cVWHI8Ily8F5e99Ga0XAGAF MgSTwhO/vH1WJC0LB88DunWqEXL2FPjxQnxfKYoKIXtxskHYvmhtQUjonsEF9hHY0Epz dG+fjnMAf1/+pKegZthV1Dy/5b/aRaZfPZb4Hg0E87kMTRQpF9XhGBztxVnMCGwUDwRH 5c1LFP7dCguILynOhkoEovEnm2drX8/ovOVbpt9DopWhz++05fpfRsCLbeQepQL4tok+ bJXQ== X-Gm-Message-State: ACgBeo32aYx3BLquJeHHGnTE3L/viFmwwAoviGnFidSPNbtvKI6tNsWJ j+Bh5DKX+OAbUZ6LQm3qRpI= X-Google-Smtp-Source: AA6agR6xpCEuiVlL/Wab33T0UddoBiEkorLuScSKLU76v440XPw0EhTHEhtE8nNvtlB1m2W5fApBrw== X-Received: by 2002:a17:90b:3e82:b0:1f7:3792:d33c with SMTP id rj2-20020a17090b3e8200b001f73792d33cmr3254090pjb.222.1662547738391; Wed, 07 Sep 2022 03:48:58 -0700 (PDT) Received: from localhost.localdomain ([103.7.29.32]) by smtp.gmail.com with ESMTPSA id x14-20020aa79a4e000000b0053e22fc5b4fsm4044044pfj.0.2022.09.07.03.48.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Sep 2022 03:48:58 -0700 (PDT) From: Like Xu X-Google-Original-From: Like Xu To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Jim Mattson Subject: [PATCH v2 2/3] KVM: x86/pmu: Limit the maximum number of supported Intel GP counters Date: Wed, 7 Sep 2022 18:48:37 +0800 Message-Id: <20220907104838.8424-2-likexu@tencent.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220907104838.8424-1-likexu@tencent.com> References: <20220907104838.8424-1-likexu@tencent.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Like Xu The Intel Architectural IA32_PMCx MSRs addresses range allows for a maximum of 8 GP counters. A local macro (named KVM_INTEL_PMC_MAX_GENERIC) is introduced to take back control of this virtual capability to avoid errors introduced by the out-of-bound counter emulations. Suggested-by: Jim Mattson Signed-off-by: Like Xu Reviewed-by: Jim Mattson --- arch/x86/include/asm/kvm_host.h | 6 +++++- arch/x86/kvm/pmu.c | 2 +- arch/x86/kvm/vmx/pmu_intel.c | 4 ++-- arch/x86/kvm/x86.c | 12 +++++++----- 4 files changed, 15 insertions(+), 9 deletions(-) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h index 2c96c43c313a..70b8266b0474 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -501,6 +501,10 @@ struct kvm_pmc { bool intr; }; +/* More counters may conflict with other existing Architectural MSRs */ +#define KVM_INTEL_PMC_MAX_GENERIC 8 +#define MSR_ARCH_PERFMON_PERFCTR_MAX (MSR_ARCH_PERFMON_PERFCTR0 + KVM_INTEL_PMC_MAX_GENERIC - 1) +#define MSR_ARCH_PERFMON_EVENTSEL_MAX (MSR_ARCH_PERFMON_EVENTSEL0 + KVM_INTEL_PMC_MAX_GENERIC - 1) #define KVM_PMC_MAX_FIXED 3 struct kvm_pmu { unsigned nr_arch_gp_counters; @@ -516,7 +520,7 @@ struct kvm_pmu { u64 reserved_bits; u64 raw_event_mask; u8 version; - struct kvm_pmc gp_counters[INTEL_PMC_MAX_GENERIC]; + struct kvm_pmc gp_counters[KVM_INTEL_PMC_MAX_GENERIC]; struct kvm_pmc fixed_counters[KVM_PMC_MAX_FIXED]; struct irq_work irq_work; DECLARE_BITMAP(reprogram_pmi, X86_PMC_IDX_MAX); diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index 02f9e4f245bd..15625b858800 100644 --- a/arch/x86/kvm/pmu.c +++ b/arch/x86/kvm/pmu.c @@ -56,7 +56,7 @@ static const struct x86_cpu_id vmx_icl_pebs_cpu[] = { * code. Each pmc, stored in kvm_pmc.idx field, is unique across * all perf counters (both gp and fixed). The mapping relationship * between pmc and perf counters is as the following: - * * Intel: [0 .. INTEL_PMC_MAX_GENERIC-1] <=> gp counters + * * Intel: [0 .. KVM_INTEL_PMC_MAX_GENERIC-1] <=> gp counters * [INTEL_PMC_IDX_FIXED .. INTEL_PMC_IDX_FIXED + 2] <=> fixed * * AMD: [0 .. AMD64_NUM_COUNTERS-1] and, for families 15H * and later, [0 .. AMD64_NUM_COUNTERS_CORE-1] <=> gp counters diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index c399637a3a79..ac74fb88e3c8 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -617,7 +617,7 @@ static void intel_pmu_init(struct kvm_vcpu *vcpu) struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); struct lbr_desc *lbr_desc = vcpu_to_lbr_desc(vcpu); - for (i = 0; i < INTEL_PMC_MAX_GENERIC; i++) { + for (i = 0; i < KVM_INTEL_PMC_MAX_GENERIC; i++) { pmu->gp_counters[i].type = KVM_PMC_GP; pmu->gp_counters[i].vcpu = vcpu; pmu->gp_counters[i].idx = i; @@ -643,7 +643,7 @@ static void intel_pmu_reset(struct kvm_vcpu *vcpu) struct kvm_pmc *pmc = NULL; int i; - for (i = 0; i < INTEL_PMC_MAX_GENERIC; i++) { + for (i = 0; i < KVM_INTEL_PMC_MAX_GENERIC; i++) { pmc = &pmu->gp_counters[i]; pmc_stop_counter(pmc); diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 884f6de11a33..fd64003ee0e0 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -1424,6 +1424,9 @@ static const u32 msrs_to_save_all[] = { MSR_ARCH_PERFMON_FIXED_CTR0 + 2, MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS, MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL, + MSR_IA32_PEBS_ENABLE, MSR_IA32_DS_AREA, MSR_PEBS_DATA_CFG, + + /* This part of MSRs should match KVM_INTEL_PMC_MAX_GENERIC. */ MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1, MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3, MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5, @@ -1432,7 +1435,6 @@ static const u32 msrs_to_save_all[] = { MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3, MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5, MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7, - MSR_IA32_PEBS_ENABLE, MSR_IA32_DS_AREA, MSR_PEBS_DATA_CFG, MSR_K7_EVNTSEL0, MSR_K7_EVNTSEL1, MSR_K7_EVNTSEL2, MSR_K7_EVNTSEL3, MSR_K7_PERFCTR0, MSR_K7_PERFCTR1, MSR_K7_PERFCTR2, MSR_K7_PERFCTR3, @@ -6933,14 +6935,14 @@ static void kvm_init_msr_list(void) intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2) continue; break; - case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 7: + case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR_MAX: if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >= - min(INTEL_PMC_MAX_GENERIC, kvm_pmu_cap.num_counters_gp)) + min(KVM_INTEL_PMC_MAX_GENERIC, kvm_pmu_cap.num_counters_gp)) continue; break; - case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 7: + case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL_MAX: if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >= - min(INTEL_PMC_MAX_GENERIC, kvm_pmu_cap.num_counters_gp)) + min(KVM_INTEL_PMC_MAX_GENERIC, kvm_pmu_cap.num_counters_gp)) continue; break; case MSR_IA32_XFD: From patchwork Wed Sep 7 10:48:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Like Xu X-Patchwork-Id: 12968806 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F2749C38145 for ; Wed, 7 Sep 2022 10:49:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229893AbiIGKtE (ORCPT ); Wed, 7 Sep 2022 06:49:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38936 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229834AbiIGKtB (ORCPT ); Wed, 7 Sep 2022 06:49:01 -0400 Received: from mail-pf1-x435.google.com (mail-pf1-x435.google.com [IPv6:2607:f8b0:4864:20::435]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9833C861D1; Wed, 7 Sep 2022 03:49:00 -0700 (PDT) Received: by mail-pf1-x435.google.com with SMTP id c198so4351057pfc.13; Wed, 07 Sep 2022 03:49:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=KEiBaoH8BEFroOX7977NTfxNkLv87R80XoxhrOTm94o=; b=cUIfE25JIN21oOq1fgNr5PeFI9PWq1WRdKeSjjTHBzKD2vrfVcciv99nWm+TvGx3mb /jtYFU/TXEkmlLC24VEExHdmNR8OalX7PBYkPcH1dqB/G5AceCZFLSs/fwfgkcFj9UnC 1A4v4qPwOlOodbxoxZFlm6m+4E7QnAhk/U7WP1n6R3id0dVZ13bV57UdMwXpIucCDqJg kA0anLUYT2h40kBEVHBaKnHik9T5y8iyvptLR3T5FeY0EpmTbdx0ApHyeOYjqJT+nH25 GE6Q5pag/FhSj7TtV+Jr7KqgfTdGV+ZZEMhSXQQl0NmFXtcVxagVh57sJVqEzmESbJwp sdjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=KEiBaoH8BEFroOX7977NTfxNkLv87R80XoxhrOTm94o=; b=iA8pu81Z3fyJhq+njpXJu2ZhwTUPdBqnCufHvQ6TUDgnmCDNu3flg+VXdkFOeOa5Vx ivpu9bUodbEfjOWqoG8pV5qbJkP7t2BXOBJP+rfaK9DBpIKy9cMoW1RSPj0696J4JOZ6 75tLNG0iNp7j0l6bBU6bexMIcAcgDajwHXjxpl2TXTTYlru2vExglt9mPUA8NPeoXt1R H5WvtV+5n+qyNxQC3/UMxlPAOePE5e4ceYNEU9G8FvE8kIrKHq4PXIfKZrV6aUUCJSYw UxsDF4GyMBz8nAe7H6cVWDJnJfGlvBKbRUYCUjVm8MeXdm81GYyyWDg7tAn/5wlMRdIK eaKQ== X-Gm-Message-State: ACgBeo3ygIyEaERph2jrqMGGCpcd0mSD8XMgbvaZRlbC6NeEHvNjlDbN 5GhUhExpE8O2IVU5WN21mx5TlB4Fk5LgnA== X-Google-Smtp-Source: AA6agR42F7XDh2ic8iNGiYRTb81uwV3BmUQbQsm7FbaD7TtrwqrgkPdg3ahpBnEqGpj/qmFWA1JmVg== X-Received: by 2002:a05:6a00:ad1:b0:530:2cb7:84de with SMTP id c17-20020a056a000ad100b005302cb784demr3250486pfl.3.1662547740154; Wed, 07 Sep 2022 03:49:00 -0700 (PDT) Received: from localhost.localdomain ([103.7.29.32]) by smtp.gmail.com with ESMTPSA id x14-20020aa79a4e000000b0053e22fc5b4fsm4044044pfj.0.2022.09.07.03.48.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Sep 2022 03:48:59 -0700 (PDT) From: Like Xu X-Google-Original-From: Like Xu To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Jim Mattson Subject: [PATCH v2 3/3] KVM: x86/pmu: Limit the maximum number of supported AMD GP counters Date: Wed, 7 Sep 2022 18:48:38 +0800 Message-Id: <20220907104838.8424-3-likexu@tencent.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220907104838.8424-1-likexu@tencent.com> References: <20220907104838.8424-1-likexu@tencent.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Like Xu The AMD PerfMonV2 specification allows for a maximum of 16 GP counters, which is clearly not supported with zero code effort in the current KVM. A local macro (named like INTEL_PMC_MAX_GENERIC) is introduced to take back control of this virt capability, which also makes it easier to statically partition all available counters between hosts and guests. Signed-off-by: Like Xu Reviewed-by: Jim Mattson --- arch/x86/include/asm/kvm_host.h | 1 + arch/x86/kvm/svm/pmu.c | 7 ++++--- arch/x86/kvm/x86.c | 3 +++ 3 files changed, 8 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h index 70b8266b0474..5c941ace8f67 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -506,6 +506,7 @@ struct kvm_pmc { #define MSR_ARCH_PERFMON_PERFCTR_MAX (MSR_ARCH_PERFMON_PERFCTR0 + KVM_INTEL_PMC_MAX_GENERIC - 1) #define MSR_ARCH_PERFMON_EVENTSEL_MAX (MSR_ARCH_PERFMON_EVENTSEL0 + KVM_INTEL_PMC_MAX_GENERIC - 1) #define KVM_PMC_MAX_FIXED 3 +#define KVM_AMD_PMC_MAX_GENERIC AMD64_NUM_COUNTERS_CORE struct kvm_pmu { unsigned nr_arch_gp_counters; unsigned nr_arch_fixed_counters; diff --git a/arch/x86/kvm/svm/pmu.c b/arch/x86/kvm/svm/pmu.c index f24613a108c5..e696979ee395 100644 --- a/arch/x86/kvm/svm/pmu.c +++ b/arch/x86/kvm/svm/pmu.c @@ -271,9 +271,10 @@ static void amd_pmu_init(struct kvm_vcpu *vcpu) struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); int i; - BUILD_BUG_ON(AMD64_NUM_COUNTERS_CORE > INTEL_PMC_MAX_GENERIC); + BUILD_BUG_ON(AMD64_NUM_COUNTERS_CORE > KVM_AMD_PMC_MAX_GENERIC); + BUILD_BUG_ON(KVM_AMD_PMC_MAX_GENERIC > INTEL_PMC_MAX_GENERIC); - for (i = 0; i < AMD64_NUM_COUNTERS_CORE ; i++) { + for (i = 0; i < KVM_AMD_PMC_MAX_GENERIC ; i++) { pmu->gp_counters[i].type = KVM_PMC_GP; pmu->gp_counters[i].vcpu = vcpu; pmu->gp_counters[i].idx = i; @@ -286,7 +287,7 @@ static void amd_pmu_reset(struct kvm_vcpu *vcpu) struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); int i; - for (i = 0; i < AMD64_NUM_COUNTERS_CORE; i++) { + for (i = 0; i < KVM_AMD_PMC_MAX_GENERIC; i++) { struct kvm_pmc *pmc = &pmu->gp_counters[i]; pmc_stop_counter(pmc); diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index fd64003ee0e0..1d28d147fc34 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -1438,10 +1438,13 @@ static const u32 msrs_to_save_all[] = { MSR_K7_EVNTSEL0, MSR_K7_EVNTSEL1, MSR_K7_EVNTSEL2, MSR_K7_EVNTSEL3, MSR_K7_PERFCTR0, MSR_K7_PERFCTR1, MSR_K7_PERFCTR2, MSR_K7_PERFCTR3, + + /* This part of MSRs should match KVM_AMD_PMC_MAX_GENERIC. */ MSR_F15H_PERF_CTL0, MSR_F15H_PERF_CTL1, MSR_F15H_PERF_CTL2, MSR_F15H_PERF_CTL3, MSR_F15H_PERF_CTL4, MSR_F15H_PERF_CTL5, MSR_F15H_PERF_CTR0, MSR_F15H_PERF_CTR1, MSR_F15H_PERF_CTR2, MSR_F15H_PERF_CTR3, MSR_F15H_PERF_CTR4, MSR_F15H_PERF_CTR5, + MSR_IA32_XFD, MSR_IA32_XFD_ERR, };