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[144.168.56.201]) by smtp.gmail.com with ESMTPSA id 196-20020a6306cd000000b0042a4612c07esm513172pgg.39.2022.09.09.06.42.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Sep 2022 06:42:23 -0700 (PDT) From: Bin Meng To: qemu-devel@nongnu.org Cc: Frank Chang , Alistair Francis , Bin Meng , Palmer Dabbelt , qemu-riscv@nongnu.org Subject: [PATCH v2 1/8] target/riscv: debug: Determine the trigger type from tdata1.type Date: Fri, 9 Sep 2022 21:42:08 +0800 Message-Id: <20220909134215.1843865-2-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220909134215.1843865-1-bmeng.cn@gmail.com> References: <20220909134215.1843865-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=bmeng.cn@gmail.com; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Frank Chang Current RISC-V debug assumes that only type 2 trigger is supported. To allow more types of triggers to be supported in the future (e.g. type 6 trigger, which is similar to type 2 trigger with additional functionality), we should determine the trigger type from tdata1.type. RV_MAX_TRIGGERS is also introduced in replacement of TRIGGER_TYPE2_NUM. Signed-off-by: Frank Chang Reviewed-by: Bin Meng [bmeng: fixed MXL_RV128 case, and moved macros to the following patch] Signed-off-by: Bin Meng Reviewed-by: LIU Zhiwei --- Changes in v2: - fixed MXL_RV128 case - moved macros to patch#2 - added log guest errors for TRIGGER_TYPE_{NO_EXIST,UNAVAIL} target/riscv/cpu.h | 2 +- target/riscv/debug.h | 13 +-- target/riscv/csr.c | 2 +- target/riscv/debug.c | 188 +++++++++++++++++++++++++++++------------ target/riscv/machine.c | 2 +- 5 files changed, 140 insertions(+), 67 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 06751e1e3e..4d82a3250b 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -324,7 +324,7 @@ struct CPUArchState { /* trigger module */ target_ulong trigger_cur; - type2_trigger_t type2_trig[TRIGGER_TYPE2_NUM]; + type2_trigger_t type2_trig[RV_MAX_TRIGGERS]; /* machine specific rdtime callback */ uint64_t (*rdtime_fn)(void *); diff --git a/target/riscv/debug.h b/target/riscv/debug.h index 27b9cac6b4..72e4edcd8c 100644 --- a/target/riscv/debug.h +++ b/target/riscv/debug.h @@ -22,13 +22,7 @@ #ifndef RISCV_DEBUG_H #define RISCV_DEBUG_H -/* trigger indexes implemented */ -enum { - TRIGGER_TYPE2_IDX_0 = 0, - TRIGGER_TYPE2_IDX_1, - TRIGGER_TYPE2_NUM, - TRIGGER_NUM = TRIGGER_TYPE2_NUM -}; +#define RV_MAX_TRIGGERS 2 /* register index of tdata CSRs */ enum { @@ -46,7 +40,8 @@ typedef enum { TRIGGER_TYPE_EXCP = 5, /* exception trigger */ TRIGGER_TYPE_AD_MATCH6 = 6, /* new address/data match trigger */ TRIGGER_TYPE_EXT_SRC = 7, /* external source trigger */ - TRIGGER_TYPE_UNAVAIL = 15 /* trigger exists, but unavailable */ + TRIGGER_TYPE_UNAVAIL = 15, /* trigger exists, but unavailable */ + TRIGGER_TYPE_NUM } trigger_type_t; typedef struct { @@ -56,7 +51,7 @@ typedef struct { struct CPUWatchpoint *wp; } type2_trigger_t; -/* tdata field masks */ +/* tdata1 field masks */ #define RV32_TYPE(t) ((uint32_t)(t) << 28) #define RV32_TYPE_MASK (0xf << 28) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index b96db1b62b..3d0d8e0340 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -3065,7 +3065,7 @@ static RISCVException read_tdata(CPURISCVState *env, int csrno, target_ulong *val) { /* return 0 in tdata1 to end the trigger enumeration */ - if (env->trigger_cur >= TRIGGER_NUM && csrno == CSR_TDATA1) { + if (env->trigger_cur >= RV_MAX_TRIGGERS && csrno == CSR_TDATA1) { *val = 0; return RISCV_EXCP_NONE; } diff --git a/target/riscv/debug.c b/target/riscv/debug.c index fc6e13222f..9dd468753a 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -52,8 +52,15 @@ /* tdata availability of a trigger */ typedef bool tdata_avail[TDATA_NUM]; -static tdata_avail tdata_mapping[TRIGGER_NUM] = { - [TRIGGER_TYPE2_IDX_0 ... TRIGGER_TYPE2_IDX_1] = { true, true, false }, +static tdata_avail tdata_mapping[TRIGGER_TYPE_NUM] = { + [TRIGGER_TYPE_NO_EXIST] = { false, false, false }, + [TRIGGER_TYPE_AD_MATCH] = { true, true, true }, + [TRIGGER_TYPE_INST_CNT] = { true, false, true }, + [TRIGGER_TYPE_INT] = { true, true, true }, + [TRIGGER_TYPE_EXCP] = { true, true, true }, + [TRIGGER_TYPE_AD_MATCH6] = { true, true, true }, + [TRIGGER_TYPE_EXT_SRC] = { true, false, false }, + [TRIGGER_TYPE_UNAVAIL] = { true, true, true } }; /* only breakpoint size 1/2/4/8 supported */ @@ -67,6 +74,27 @@ static int access_size[SIZE_NUM] = { [6 ... 15] = -1, }; +static inline target_ulong extract_trigger_type(CPURISCVState *env, + target_ulong tdata1) +{ + switch (riscv_cpu_mxl(env)) { + case MXL_RV32: + return extract32(tdata1, 28, 4); + case MXL_RV64: + case MXL_RV128: + return extract64(tdata1, 60, 4); + default: + g_assert_not_reached(); + } +} + +static inline target_ulong get_trigger_type(CPURISCVState *env, + target_ulong trigger_index) +{ + target_ulong tdata1 = env->type2_trig[trigger_index].mcontrol; + return extract_trigger_type(env, tdata1); +} + static inline target_ulong trigger_type(CPURISCVState *env, trigger_type_t type) { @@ -89,15 +117,17 @@ static inline target_ulong trigger_type(CPURISCVState *env, bool tdata_available(CPURISCVState *env, int tdata_index) { + int trigger_type = get_trigger_type(env, env->trigger_cur); + if (unlikely(tdata_index >= TDATA_NUM)) { return false; } - if (unlikely(env->trigger_cur >= TRIGGER_NUM)) { + if (unlikely(env->trigger_cur >= RV_MAX_TRIGGERS)) { return false; } - return tdata_mapping[env->trigger_cur][tdata_index]; + return tdata_mapping[trigger_type][tdata_index]; } target_ulong tselect_csr_read(CPURISCVState *env) @@ -137,6 +167,7 @@ static target_ulong tdata1_validate(CPURISCVState *env, target_ulong val, qemu_log_mask(LOG_GUEST_ERROR, "ignoring type write to tdata1 register\n"); } + if (dmode != 0) { qemu_log_mask(LOG_UNIMP, "debug mode is not supported\n"); } @@ -261,9 +292,8 @@ static void type2_breakpoint_remove(CPURISCVState *env, target_ulong index) } static target_ulong type2_reg_read(CPURISCVState *env, - target_ulong trigger_index, int tdata_index) + target_ulong index, int tdata_index) { - uint32_t index = trigger_index - TRIGGER_TYPE2_IDX_0; target_ulong tdata; switch (tdata_index) { @@ -280,10 +310,9 @@ static target_ulong type2_reg_read(CPURISCVState *env, return tdata; } -static void type2_reg_write(CPURISCVState *env, target_ulong trigger_index, +static void type2_reg_write(CPURISCVState *env, target_ulong index, int tdata_index, target_ulong val) { - uint32_t index = trigger_index - TRIGGER_TYPE2_IDX_0; target_ulong new_val; switch (tdata_index) { @@ -309,35 +338,64 @@ static void type2_reg_write(CPURISCVState *env, target_ulong trigger_index, return; } -typedef target_ulong (*tdata_read_func)(CPURISCVState *env, - target_ulong trigger_index, - int tdata_index); - -static tdata_read_func trigger_read_funcs[TRIGGER_NUM] = { - [TRIGGER_TYPE2_IDX_0 ... TRIGGER_TYPE2_IDX_1] = type2_reg_read, -}; - -typedef void (*tdata_write_func)(CPURISCVState *env, - target_ulong trigger_index, - int tdata_index, - target_ulong val); - -static tdata_write_func trigger_write_funcs[TRIGGER_NUM] = { - [TRIGGER_TYPE2_IDX_0 ... TRIGGER_TYPE2_IDX_1] = type2_reg_write, -}; - target_ulong tdata_csr_read(CPURISCVState *env, int tdata_index) { - tdata_read_func read_func = trigger_read_funcs[env->trigger_cur]; + int trigger_type = get_trigger_type(env, env->trigger_cur); + + switch (trigger_type) { + case TRIGGER_TYPE_AD_MATCH: + return type2_reg_read(env, env->trigger_cur, tdata_index); + break; + case TRIGGER_TYPE_INST_CNT: + case TRIGGER_TYPE_INT: + case TRIGGER_TYPE_EXCP: + case TRIGGER_TYPE_AD_MATCH6: + case TRIGGER_TYPE_EXT_SRC: + qemu_log_mask(LOG_UNIMP, "trigger type: %d is not supported\n", + trigger_type); + break; + case TRIGGER_TYPE_NO_EXIST: + case TRIGGER_TYPE_UNAVAIL: + qemu_log_mask(LOG_GUEST_ERROR, "trigger type: %d does not exit\n", + trigger_type); + break; + default: + g_assert_not_reached(); + } - return read_func(env, env->trigger_cur, tdata_index); + return 0; } void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val) { - tdata_write_func write_func = trigger_write_funcs[env->trigger_cur]; + int trigger_type; - return write_func(env, env->trigger_cur, tdata_index, val); + if (tdata_index == TDATA1) { + trigger_type = extract_trigger_type(env, val); + } else { + trigger_type = get_trigger_type(env, env->trigger_cur); + } + + switch (trigger_type) { + case TRIGGER_TYPE_AD_MATCH: + type2_reg_write(env, env->trigger_cur, tdata_index, val); + break; + case TRIGGER_TYPE_INST_CNT: + case TRIGGER_TYPE_INT: + case TRIGGER_TYPE_EXCP: + case TRIGGER_TYPE_AD_MATCH6: + case TRIGGER_TYPE_EXT_SRC: + qemu_log_mask(LOG_UNIMP, "trigger type: %d is not supported\n", + trigger_type); + break; + case TRIGGER_TYPE_NO_EXIST: + case TRIGGER_TYPE_UNAVAIL: + qemu_log_mask(LOG_GUEST_ERROR, "trigger type: %d does not exit\n", + trigger_type); + break; + default: + g_assert_not_reached(); + } } void riscv_cpu_debug_excp_handler(CPUState *cs) @@ -364,18 +422,28 @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs) CPUBreakpoint *bp; target_ulong ctrl; target_ulong pc; + int trigger_type; int i; QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { - for (i = 0; i < TRIGGER_TYPE2_NUM; i++) { - ctrl = env->type2_trig[i].mcontrol; - pc = env->type2_trig[i].maddress; - - if ((ctrl & TYPE2_EXEC) && (bp->pc == pc)) { - /* check U/S/M bit against current privilege level */ - if ((ctrl >> 3) & BIT(env->priv)) { - return true; + for (i = 0; i < RV_MAX_TRIGGERS; i++) { + trigger_type = get_trigger_type(env, i); + + switch (trigger_type) { + case TRIGGER_TYPE_AD_MATCH: + ctrl = env->type2_trig[i].mcontrol; + pc = env->type2_trig[i].maddress; + + if ((ctrl & TYPE2_EXEC) && (bp->pc == pc)) { + /* check U/S/M bit against current privilege level */ + if ((ctrl >> 3) & BIT(env->priv)) { + return true; + } } + break; + default: + /* other trigger types are not supported or irrelevant */ + break; } } } @@ -389,26 +457,36 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp) CPURISCVState *env = &cpu->env; target_ulong ctrl; target_ulong addr; + int trigger_type; int flags; int i; - for (i = 0; i < TRIGGER_TYPE2_NUM; i++) { - ctrl = env->type2_trig[i].mcontrol; - addr = env->type2_trig[i].maddress; - flags = 0; + for (i = 0; i < RV_MAX_TRIGGERS; i++) { + trigger_type = get_trigger_type(env, i); - if (ctrl & TYPE2_LOAD) { - flags |= BP_MEM_READ; - } - if (ctrl & TYPE2_STORE) { - flags |= BP_MEM_WRITE; - } + switch (trigger_type) { + case TRIGGER_TYPE_AD_MATCH: + ctrl = env->type2_trig[i].mcontrol; + addr = env->type2_trig[i].maddress; + flags = 0; - if ((wp->flags & flags) && (wp->vaddr == addr)) { - /* check U/S/M bit against current privilege level */ - if ((ctrl >> 3) & BIT(env->priv)) { - return true; + if (ctrl & TYPE2_LOAD) { + flags |= BP_MEM_READ; + } + if (ctrl & TYPE2_STORE) { + flags |= BP_MEM_WRITE; + } + + if ((wp->flags & flags) && (wp->vaddr == addr)) { + /* check U/S/M bit against current privilege level */ + if ((ctrl >> 3) & BIT(env->priv)) { + return true; + } } + break; + default: + /* other trigger types are not supported */ + break; } } @@ -417,11 +495,11 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp) void riscv_trigger_init(CPURISCVState *env) { - target_ulong type2 = trigger_type(env, TRIGGER_TYPE_AD_MATCH); + target_ulong tdata1 = trigger_type(env, TRIGGER_TYPE_AD_MATCH); int i; - /* type 2 triggers */ - for (i = 0; i < TRIGGER_TYPE2_NUM; i++) { + /* init to type 2 triggers */ + for (i = 0; i < RV_MAX_TRIGGERS; i++) { /* * type = TRIGGER_TYPE_AD_MATCH * dmode = 0 (both debug and M-mode can write tdata) @@ -435,7 +513,7 @@ void riscv_trigger_init(CPURISCVState *env) * chain = 0 (unimplemented, always 0) * match = 0 (always 0, when any compare value equals tdata2) */ - env->type2_trig[i].mcontrol = type2; + env->type2_trig[i].mcontrol = tdata1; env->type2_trig[i].maddress = 0; env->type2_trig[i].bp = NULL; env->type2_trig[i].wp = NULL; diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 41098f6ad0..b8173394a2 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -247,7 +247,7 @@ static const VMStateDescription vmstate_debug = { .needed = debug_needed, .fields = (VMStateField[]) { VMSTATE_UINTTL(env.trigger_cur, RISCVCPU), - VMSTATE_STRUCT_ARRAY(env.type2_trig, RISCVCPU, TRIGGER_TYPE2_NUM, + VMSTATE_STRUCT_ARRAY(env.type2_trig, RISCVCPU, RV_MAX_TRIGGERS, 0, vmstate_debug_type2, type2_trigger_t), VMSTATE_END_OF_LIST() } From patchwork Fri Sep 9 13:42:09 2022 Content-Type: text/plain; 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[144.168.56.201]) by smtp.gmail.com with ESMTPSA id 196-20020a6306cd000000b0042a4612c07esm513172pgg.39.2022.09.09.06.42.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Sep 2022 06:42:25 -0700 (PDT) From: Bin Meng To: qemu-devel@nongnu.org Cc: Frank Chang , Alistair Francis , Bin Meng , Palmer Dabbelt , qemu-riscv@nongnu.org Subject: [PATCH v2 2/8] target/riscv: debug: Introduce build_tdata1() to build tdata1 register content Date: Fri, 9 Sep 2022 21:42:09 +0800 Message-Id: <20220909134215.1843865-3-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220909134215.1843865-1-bmeng.cn@gmail.com> References: <20220909134215.1843865-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=bmeng.cn@gmail.com; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Frank Chang Introduce build_tdata1() to build tdata1 register content, which can be shared among all types of triggers. Signed-off-by: Frank Chang Reviewed-by: Bin Meng [bmeng: moved RV{32,64}_DATA_MASK definition to this patch] Signed-off-by: Bin Meng Reviewed-by: LIU Zhiwei --- Changes in v2: - moved RV{32,64}_DATA_MASK definition to this patch target/riscv/debug.h | 2 ++ target/riscv/debug.c | 15 ++++++++++----- 2 files changed, 12 insertions(+), 5 deletions(-) diff --git a/target/riscv/debug.h b/target/riscv/debug.h index 72e4edcd8c..c422553c27 100644 --- a/target/riscv/debug.h +++ b/target/riscv/debug.h @@ -56,9 +56,11 @@ typedef struct { #define RV32_TYPE(t) ((uint32_t)(t) << 28) #define RV32_TYPE_MASK (0xf << 28) #define RV32_DMODE BIT(27) +#define RV32_DATA_MASK 0x7ffffff #define RV64_TYPE(t) ((uint64_t)(t) << 60) #define RV64_TYPE_MASK (0xfULL << 60) #define RV64_DMODE BIT_ULL(59) +#define RV64_DATA_MASK 0x7ffffffffffffff /* mcontrol field masks */ diff --git a/target/riscv/debug.c b/target/riscv/debug.c index 9dd468753a..45aae87ec3 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -95,18 +95,23 @@ static inline target_ulong get_trigger_type(CPURISCVState *env, return extract_trigger_type(env, tdata1); } -static inline target_ulong trigger_type(CPURISCVState *env, - trigger_type_t type) +static inline target_ulong build_tdata1(CPURISCVState *env, + trigger_type_t type, + bool dmode, target_ulong data) { target_ulong tdata1; switch (riscv_cpu_mxl(env)) { case MXL_RV32: - tdata1 = RV32_TYPE(type); + tdata1 = RV32_TYPE(type) | + (dmode ? RV32_DMODE : 0) | + (data & RV32_DATA_MASK); break; case MXL_RV64: case MXL_RV128: - tdata1 = RV64_TYPE(type); + tdata1 = RV64_TYPE(type) | + (dmode ? RV64_DMODE : 0) | + (data & RV64_DATA_MASK); break; default: g_assert_not_reached(); @@ -495,7 +500,7 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp) void riscv_trigger_init(CPURISCVState *env) { - target_ulong tdata1 = trigger_type(env, TRIGGER_TYPE_AD_MATCH); + target_ulong tdata1 = build_tdata1(env, TRIGGER_TYPE_AD_MATCH, 0, 0); int i; /* init to type 2 triggers */ From patchwork Fri Sep 9 13:42:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 12971836 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4C642ECAAA1 for ; Fri, 9 Sep 2022 13:53:59 +0000 (UTC) Received: from localhost ([::1]:46650 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oWeSE-0005bn-C7 for qemu-devel@archiver.kernel.org; Fri, 09 Sep 2022 09:53:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59638) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oWeHB-0007A0-Ol; Fri, 09 Sep 2022 09:42:33 -0400 Received: from mail-pg1-x52b.google.com ([2607:f8b0:4864:20::52b]:37872) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oWeH9-0003HZ-GM; Fri, 09 Sep 2022 09:42:33 -0400 Received: by mail-pg1-x52b.google.com with SMTP id bh13so1613498pgb.4; Fri, 09 Sep 2022 06:42:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=zs4vAI2VUHXhBwHxhRHTJDw0cVDND/1fyJF5OYtMwwQ=; b=G99UApduVs689vtNgPNbG34VQBl8BPsDHAv+zz7zwAuXsZLme0zTTHZ7iTbNsBdYbR IRNjJLcMZUQ/PwY8N61vWe0OtpZYsqdOucqrTDDYlvuUo4f9z5496zorT3kyhWOXqvnu Kfht1gFg7y8DsV/prs/dffNke9McuvunBsHhnFW6jCP6/LnpXosnQiURA6uY4TGjfNCb mDvQTGzliPtOYGuH4qJC7xVvAqy0xHPZlIL1nffwdRFAV6Rd5E/ThHtv1lA3cVUYJiNO R3zjgwwbOC9jTuFjqM9Ku7WcJo6fPIRHbsXlzzwasjrQ6NghAd2f21PKfvcIRbJ/q0X8 nmSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=zs4vAI2VUHXhBwHxhRHTJDw0cVDND/1fyJF5OYtMwwQ=; b=s3TBZEM5uYzkM/btB6zJ7u9AA8tVMc5sXPnBHBllNywXGmwXDrbIUCEph5NDHB4iQ7 3AGV3vkspCl/DkFYDn+L4XTuzRAhikXAHkOBOwul2nLMLPdWys6/flnXXSQsfZcQK1bh BcodFu5G4copk4FrYGMMN6S7qkVeLe0AbpJ4bQfSmILLIKeQKRsPnZ3G3nlvqQ711GLZ 0dXaYLrKjEC3ClkI55G/Araa/kU8YJJi0fQ9rnHENjbjwjNi5J3JoKRJSg5HgtfShF9k Q2Q3yhz6FkkZO3m0+48TJbMc4g751ex4yCylNArZsdtj7+HVMpJHk+xQvKxiQYMvHARd irkQ== X-Gm-Message-State: ACgBeo1qUwt9MKZHB/jS6xCAOZHRgeF8JHCJfQaUASt4xg5p2dlQ568i sbtrwBV2cTZLFp2qHCPQcWRruf6PefM= X-Google-Smtp-Source: AA6agR57dCDCB8VNNtkiJwLsviM64CQVOQ77LFhOea1li9b9eWc/5zsZOxiw63aacG3PadfFxxp13Q== X-Received: by 2002:a63:fc11:0:b0:430:41b4:acf5 with SMTP id j17-20020a63fc11000000b0043041b4acf5mr12319454pgi.408.1662730949314; Fri, 09 Sep 2022 06:42:29 -0700 (PDT) Received: from ubuntu.. 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[144.168.56.201]) by smtp.gmail.com with ESMTPSA id 196-20020a6306cd000000b0042a4612c07esm513172pgg.39.2022.09.09.06.42.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Sep 2022 06:42:28 -0700 (PDT) From: Bin Meng To: qemu-devel@nongnu.org Cc: Frank Chang , Alistair Francis , Bin Meng , Palmer Dabbelt , qemu-riscv@nongnu.org Subject: [PATCH v2 3/8] target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRs Date: Fri, 9 Sep 2022 21:42:10 +0800 Message-Id: <20220909134215.1843865-4-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220909134215.1843865-1-bmeng.cn@gmail.com> References: <20220909134215.1843865-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=bmeng.cn@gmail.com; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Frank Chang Replace type2_trigger_t with the real tdata1, tdata2, and tdata3 CSRs, which allows us to support more types of triggers in the future. Signed-off-by: Frank Chang Reviewed-by: Bin Meng Signed-off-by: Bin Meng Reviewed-by: LIU Zhiwei --- (no changes since v1) target/riscv/cpu.h | 6 ++- target/riscv/debug.h | 7 --- target/riscv/debug.c | 103 +++++++++++++++-------------------------- target/riscv/machine.c | 20 ++------ 4 files changed, 48 insertions(+), 88 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 4d82a3250b..b0b05c19ca 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -324,7 +324,11 @@ struct CPUArchState { /* trigger module */ target_ulong trigger_cur; - type2_trigger_t type2_trig[RV_MAX_TRIGGERS]; + target_ulong tdata1[RV_MAX_TRIGGERS]; + target_ulong tdata2[RV_MAX_TRIGGERS]; + target_ulong tdata3[RV_MAX_TRIGGERS]; + struct CPUBreakpoint *cpu_breakpoint[RV_MAX_TRIGGERS]; + struct CPUWatchpoint *cpu_watchpoint[RV_MAX_TRIGGERS]; /* machine specific rdtime callback */ uint64_t (*rdtime_fn)(void *); diff --git a/target/riscv/debug.h b/target/riscv/debug.h index c422553c27..76146f373a 100644 --- a/target/riscv/debug.h +++ b/target/riscv/debug.h @@ -44,13 +44,6 @@ typedef enum { TRIGGER_TYPE_NUM } trigger_type_t; -typedef struct { - target_ulong mcontrol; - target_ulong maddress; - struct CPUBreakpoint *bp; - struct CPUWatchpoint *wp; -} type2_trigger_t; - /* tdata1 field masks */ #define RV32_TYPE(t) ((uint32_t)(t) << 28) diff --git a/target/riscv/debug.c b/target/riscv/debug.c index 45aae87ec3..06feef7d67 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -91,8 +91,7 @@ static inline target_ulong extract_trigger_type(CPURISCVState *env, static inline target_ulong get_trigger_type(CPURISCVState *env, target_ulong trigger_index) { - target_ulong tdata1 = env->type2_trig[trigger_index].mcontrol; - return extract_trigger_type(env, tdata1); + return extract_trigger_type(env, env->tdata1[trigger_index]); } static inline target_ulong build_tdata1(CPURISCVState *env, @@ -188,6 +187,8 @@ static inline void warn_always_zero_bit(target_ulong val, target_ulong mask, } } +/* type 2 trigger */ + static uint32_t type2_breakpoint_size(CPURISCVState *env, target_ulong ctrl) { uint32_t size, sizelo, sizehi = 0; @@ -247,8 +248,8 @@ static target_ulong type2_mcontrol_validate(CPURISCVState *env, static void type2_breakpoint_insert(CPURISCVState *env, target_ulong index) { - target_ulong ctrl = env->type2_trig[index].mcontrol; - target_ulong addr = env->type2_trig[index].maddress; + target_ulong ctrl = env->tdata1[index]; + target_ulong addr = env->tdata2[index]; bool enabled = type2_breakpoint_enabled(ctrl); CPUState *cs = env_cpu(env); int flags = BP_CPU | BP_STOP_BEFORE_ACCESS; @@ -259,7 +260,7 @@ static void type2_breakpoint_insert(CPURISCVState *env, target_ulong index) } if (ctrl & TYPE2_EXEC) { - cpu_breakpoint_insert(cs, addr, flags, &env->type2_trig[index].bp); + cpu_breakpoint_insert(cs, addr, flags, &env->cpu_breakpoint[index]); } if (ctrl & TYPE2_LOAD) { @@ -273,10 +274,10 @@ static void type2_breakpoint_insert(CPURISCVState *env, target_ulong index) size = type2_breakpoint_size(env, ctrl); if (size != 0) { cpu_watchpoint_insert(cs, addr, size, flags, - &env->type2_trig[index].wp); + &env->cpu_watchpoint[index]); } else { cpu_watchpoint_insert(cs, addr, 8, flags, - &env->type2_trig[index].wp); + &env->cpu_watchpoint[index]); } } } @@ -285,36 +286,17 @@ static void type2_breakpoint_remove(CPURISCVState *env, target_ulong index) { CPUState *cs = env_cpu(env); - if (env->type2_trig[index].bp) { - cpu_breakpoint_remove_by_ref(cs, env->type2_trig[index].bp); - env->type2_trig[index].bp = NULL; + if (env->cpu_breakpoint[index]) { + cpu_breakpoint_remove_by_ref(cs, env->cpu_breakpoint[index]); + env->cpu_breakpoint[index] = NULL; } - if (env->type2_trig[index].wp) { - cpu_watchpoint_remove_by_ref(cs, env->type2_trig[index].wp); - env->type2_trig[index].wp = NULL; + if (env->cpu_watchpoint[index]) { + cpu_watchpoint_remove_by_ref(cs, env->cpu_watchpoint[index]); + env->cpu_watchpoint[index] = NULL; } } -static target_ulong type2_reg_read(CPURISCVState *env, - target_ulong index, int tdata_index) -{ - target_ulong tdata; - - switch (tdata_index) { - case TDATA1: - tdata = env->type2_trig[index].mcontrol; - break; - case TDATA2: - tdata = env->type2_trig[index].maddress; - break; - default: - g_assert_not_reached(); - } - - return tdata; -} - static void type2_reg_write(CPURISCVState *env, target_ulong index, int tdata_index, target_ulong val) { @@ -323,19 +305,23 @@ static void type2_reg_write(CPURISCVState *env, target_ulong index, switch (tdata_index) { case TDATA1: new_val = type2_mcontrol_validate(env, val); - if (new_val != env->type2_trig[index].mcontrol) { - env->type2_trig[index].mcontrol = new_val; + if (new_val != env->tdata1[index]) { + env->tdata1[index] = new_val; type2_breakpoint_remove(env, index); type2_breakpoint_insert(env, index); } break; case TDATA2: - if (val != env->type2_trig[index].maddress) { - env->type2_trig[index].maddress = val; + if (val != env->tdata2[index]) { + env->tdata2[index] = val; type2_breakpoint_remove(env, index); type2_breakpoint_insert(env, index); } break; + case TDATA3: + qemu_log_mask(LOG_UNIMP, + "tdata3 is not supported for type 2 trigger\n"); + break; default: g_assert_not_reached(); } @@ -345,30 +331,16 @@ static void type2_reg_write(CPURISCVState *env, target_ulong index, target_ulong tdata_csr_read(CPURISCVState *env, int tdata_index) { - int trigger_type = get_trigger_type(env, env->trigger_cur); - - switch (trigger_type) { - case TRIGGER_TYPE_AD_MATCH: - return type2_reg_read(env, env->trigger_cur, tdata_index); - break; - case TRIGGER_TYPE_INST_CNT: - case TRIGGER_TYPE_INT: - case TRIGGER_TYPE_EXCP: - case TRIGGER_TYPE_AD_MATCH6: - case TRIGGER_TYPE_EXT_SRC: - qemu_log_mask(LOG_UNIMP, "trigger type: %d is not supported\n", - trigger_type); - break; - case TRIGGER_TYPE_NO_EXIST: - case TRIGGER_TYPE_UNAVAIL: - qemu_log_mask(LOG_GUEST_ERROR, "trigger type: %d does not exit\n", - trigger_type); - break; + switch (tdata_index) { + case TDATA1: + return env->tdata1[env->trigger_cur]; + case TDATA2: + return env->tdata2[env->trigger_cur]; + case TDATA3: + return env->tdata3[env->trigger_cur]; default: g_assert_not_reached(); } - - return 0; } void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val) @@ -436,8 +408,8 @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs) switch (trigger_type) { case TRIGGER_TYPE_AD_MATCH: - ctrl = env->type2_trig[i].mcontrol; - pc = env->type2_trig[i].maddress; + ctrl = env->tdata1[i]; + pc = env->tdata2[i]; if ((ctrl & TYPE2_EXEC) && (bp->pc == pc)) { /* check U/S/M bit against current privilege level */ @@ -471,8 +443,8 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp) switch (trigger_type) { case TRIGGER_TYPE_AD_MATCH: - ctrl = env->type2_trig[i].mcontrol; - addr = env->type2_trig[i].maddress; + ctrl = env->tdata1[i]; + addr = env->tdata2[i]; flags = 0; if (ctrl & TYPE2_LOAD) { @@ -518,9 +490,10 @@ void riscv_trigger_init(CPURISCVState *env) * chain = 0 (unimplemented, always 0) * match = 0 (always 0, when any compare value equals tdata2) */ - env->type2_trig[i].mcontrol = tdata1; - env->type2_trig[i].maddress = 0; - env->type2_trig[i].bp = NULL; - env->type2_trig[i].wp = NULL; + env->tdata1[i] = tdata1; + env->tdata2[i] = 0; + env->tdata3[i] = 0; + env->cpu_breakpoint[i] = NULL; + env->cpu_watchpoint[i] = NULL; } } diff --git a/target/riscv/machine.c b/target/riscv/machine.c index b8173394a2..cb1c4b83b7 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -229,26 +229,16 @@ static bool debug_needed(void *opaque) return riscv_feature(env, RISCV_FEATURE_DEBUG); } -static const VMStateDescription vmstate_debug_type2 = { - .name = "cpu/debug/type2", - .version_id = 1, - .minimum_version_id = 1, - .fields = (VMStateField[]) { - VMSTATE_UINTTL(mcontrol, type2_trigger_t), - VMSTATE_UINTTL(maddress, type2_trigger_t), - VMSTATE_END_OF_LIST() - } -}; - static const VMStateDescription vmstate_debug = { .name = "cpu/debug", - .version_id = 1, - .minimum_version_id = 1, + .version_id = 2, + .minimum_version_id = 2, .needed = debug_needed, .fields = (VMStateField[]) { VMSTATE_UINTTL(env.trigger_cur, RISCVCPU), - VMSTATE_STRUCT_ARRAY(env.type2_trig, RISCVCPU, RV_MAX_TRIGGERS, - 0, vmstate_debug_type2, type2_trigger_t), + VMSTATE_UINTTL_ARRAY(env.tdata1, RISCVCPU, RV_MAX_TRIGGERS), + VMSTATE_UINTTL_ARRAY(env.tdata2, RISCVCPU, RV_MAX_TRIGGERS), + VMSTATE_UINTTL_ARRAY(env.tdata3, RISCVCPU, RV_MAX_TRIGGERS), VMSTATE_END_OF_LIST() } }; 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[144.168.56.201]) by smtp.gmail.com with ESMTPSA id 196-20020a6306cd000000b0042a4612c07esm513172pgg.39.2022.09.09.06.42.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Sep 2022 06:42:31 -0700 (PDT) From: Bin Meng To: qemu-devel@nongnu.org Cc: Frank Chang , Alistair Francis , Bin Meng , Palmer Dabbelt , qemu-riscv@nongnu.org Subject: [PATCH v2 4/8] target/riscv: debug: Restrict the range of tselect value can be written Date: Fri, 9 Sep 2022 21:42:11 +0800 Message-Id: <20220909134215.1843865-5-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220909134215.1843865-1-bmeng.cn@gmail.com> References: <20220909134215.1843865-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=bmeng.cn@gmail.com; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Frank Chang The value of tselect CSR can be written should be limited within the range of supported triggers number. Signed-off-by: Frank Chang Reviewed-by: Bin Meng Signed-off-by: Bin Meng Reviewed-by: LIU Zhiwei --- (no changes since v1) target/riscv/debug.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/target/riscv/debug.c b/target/riscv/debug.c index 06feef7d67..d6666164cd 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -127,10 +127,6 @@ bool tdata_available(CPURISCVState *env, int tdata_index) return false; } - if (unlikely(env->trigger_cur >= RV_MAX_TRIGGERS)) { - return false; - } - return tdata_mapping[trigger_type][tdata_index]; } @@ -141,8 +137,9 @@ target_ulong tselect_csr_read(CPURISCVState *env) void tselect_csr_write(CPURISCVState *env, target_ulong val) { - /* all target_ulong bits of tselect are implemented */ - env->trigger_cur = val; + if (val < RV_MAX_TRIGGERS) { + env->trigger_cur = val; + } } static target_ulong tdata1_validate(CPURISCVState *env, target_ulong val, From patchwork Fri Sep 9 13:42:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 12971837 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CEA3CECAAD3 for ; Fri, 9 Sep 2022 13:56:42 +0000 (UTC) Received: from localhost ([::1]:36882 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oWeUr-0000ck-Od for qemu-devel@archiver.kernel.org; Fri, 09 Sep 2022 09:56:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59740) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oWeHG-0007Ky-If; Fri, 09 Sep 2022 09:42:38 -0400 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]:55007) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oWeHE-0003Hz-SA; Fri, 09 Sep 2022 09:42:38 -0400 Received: by mail-pj1-x102a.google.com with SMTP id o23so281937pji.4; Fri, 09 Sep 2022 06:42:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=Hce6YOD4G6yJWscv75mJR41gbJvGcOpIieu8G2xuK+g=; b=m/Yg5NgtMvqsXciQ04wCBpZnV5gMHMt+o/DGAmqLU3boVlPVMFFfKas+U/f2B0hEOO G1LjAfdyiL1wn94YUprINtEW4za3ncrPmgMrq4zYp/CG07irnVKsBnNvdoX4FNe/bUKd RZp9noNBDaW5PosMv4kyESpLiHZghiV/mQ0oYUpOfv3XSWXykmd/3xWLHCBqbT/2W/9z PxmiKxKt91FjLuApbzjdO/kfry/zwAGhY5TT5UEAK9U4CrrfD5HYOLIEK1tuErnAa7T6 LWroAdd5xrp+lM9Yu9d5UqAeavmTgKG81lhmj8I6IBAE1wLTEyu5m/3lZHANIZIlRKOF 2gdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=Hce6YOD4G6yJWscv75mJR41gbJvGcOpIieu8G2xuK+g=; b=m+hyGoEtkv0dPq6FNfWBUW3PrEuyTqGHMxGEQqUpUB+HwI5hSyF6981C28MkWimFsR s9+ffqDInz5nHTUyPMurFdqUqg2yAWspmkCUhXbvUKkPGBfZIkr7l2DcC3Z8FC8X3rjM xpdzlphffokNNQPFq8L19Z52dHvJZxjsOMJNf7qX+LlAVK0oZmfqGdnjD3KYytVzVXjz YpI53XttgL7+w1EGdDrWfO8gSFTPUCXntF9n/Q8YeqKGBRTfbMoFiI/v3/ZOTcHYWva0 H2FEgidVEz0pD5ONnn404EPZqHNZBg1O1fJQJX1eOHx9LIiCfkwWPL3GfLJbw92k9iT8 RVeQ== X-Gm-Message-State: ACgBeo0VykbIbiTgKkRHOPwtIBtvEeYk+1EJuBwvRNfZwWbeNsI5laRO jWmN1uF47cDrUQnQPspqyMlrZjuGZ34= X-Google-Smtp-Source: AA6agR5VhZYek0aINrlgBVOhp5m4cEWXymU9oir8PQ8Zs+Ht8Mxut8s2054dVm2vTEWiKzncpi11gg== X-Received: by 2002:a17:903:24c:b0:172:7090:64a4 with SMTP id j12-20020a170903024c00b00172709064a4mr13724759plh.124.1662730954955; Fri, 09 Sep 2022 06:42:34 -0700 (PDT) Received: from ubuntu.. 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[144.168.56.201]) by smtp.gmail.com with ESMTPSA id 196-20020a6306cd000000b0042a4612c07esm513172pgg.39.2022.09.09.06.42.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Sep 2022 06:42:34 -0700 (PDT) From: Bin Meng To: qemu-devel@nongnu.org Cc: Frank Chang , Alistair Francis , Bin Meng , Palmer Dabbelt , qemu-riscv@nongnu.org Subject: [PATCH v2 5/8] target/riscv: debug: Introduce tinfo CSR Date: Fri, 9 Sep 2022 21:42:12 +0800 Message-Id: <20220909134215.1843865-6-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220909134215.1843865-1-bmeng.cn@gmail.com> References: <20220909134215.1843865-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=bmeng.cn@gmail.com; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Frank Chang tinfo.info: One bit for each possible type enumerated in tdata1. If the bit is set, then that type is supported by the currently selected trigger. Signed-off-by: Frank Chang Reviewed-by: Bin Meng Signed-off-by: Bin Meng Reviewed-by: LIU Zhiwei --- (no changes since v1) target/riscv/cpu_bits.h | 1 + target/riscv/debug.h | 2 ++ target/riscv/csr.c | 8 ++++++++ target/riscv/debug.c | 10 +++++++--- 4 files changed, 18 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 7be12cac2e..1972aee3bb 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -321,6 +321,7 @@ #define CSR_TDATA1 0x7a1 #define CSR_TDATA2 0x7a2 #define CSR_TDATA3 0x7a3 +#define CSR_TINFO 0x7a4 /* Debug Mode Registers */ #define CSR_DCSR 0x7b0 diff --git a/target/riscv/debug.h b/target/riscv/debug.h index 76146f373a..9f69c64591 100644 --- a/target/riscv/debug.h +++ b/target/riscv/debug.h @@ -95,6 +95,8 @@ void tselect_csr_write(CPURISCVState *env, target_ulong val); target_ulong tdata_csr_read(CPURISCVState *env, int tdata_index); void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val); +target_ulong tinfo_csr_read(CPURISCVState *env); + void riscv_cpu_debug_excp_handler(CPUState *cs); bool riscv_cpu_debug_check_breakpoint(CPUState *cs); bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp); diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 3d0d8e0340..e66019048d 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -3089,6 +3089,13 @@ static RISCVException write_tdata(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } +static RISCVException read_tinfo(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val = tinfo_csr_read(env); + return RISCV_EXCP_NONE; +} + /* * Functions to access Pointer Masking feature registers * We have to check if current priv lvl could modify @@ -3893,6 +3900,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_TDATA1] = { "tdata1", debug, read_tdata, write_tdata }, [CSR_TDATA2] = { "tdata2", debug, read_tdata, write_tdata }, [CSR_TDATA3] = { "tdata3", debug, read_tdata, write_tdata }, + [CSR_TINFO] = { "tinfo", debug, read_tinfo, write_ignore }, /* User Pointer Masking */ [CSR_UMTE] = { "umte", pointer_masking, read_umte, write_umte }, diff --git a/target/riscv/debug.c b/target/riscv/debug.c index d6666164cd..7d546ace42 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -37,9 +37,7 @@ * - tdata1 * - tdata2 * - tdata3 - * - * We don't support writable 'type' field in the tdata1 register, so there is - * no need to implement the "tinfo" CSR. + * - tinfo * * The following triggers are implemented: * @@ -372,6 +370,12 @@ void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val) } } +target_ulong tinfo_csr_read(CPURISCVState *env) +{ + /* assume all triggers support the same types of triggers */ + return BIT(TRIGGER_TYPE_AD_MATCH); +} + void riscv_cpu_debug_excp_handler(CPUState *cs) { RISCVCPU *cpu = RISCV_CPU(cs); From patchwork Fri Sep 9 13:42:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 12971825 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 840C7ECAAA1 for ; Fri, 9 Sep 2022 13:49:31 +0000 (UTC) Received: from localhost ([::1]:56804 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oWeNu-00061e-D0 for qemu-devel@archiver.kernel.org; Fri, 09 Sep 2022 09:49:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59744) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oWeHL-0007Wu-9A; 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[144.168.56.201]) by smtp.gmail.com with ESMTPSA id 196-20020a6306cd000000b0042a4612c07esm513172pgg.39.2022.09.09.06.42.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Sep 2022 06:42:37 -0700 (PDT) From: Bin Meng To: qemu-devel@nongnu.org Cc: Frank Chang , Alistair Francis , Bin Meng , Palmer Dabbelt , qemu-riscv@nongnu.org Subject: [PATCH v2 6/8] target/riscv: debug: Create common trigger actions function Date: Fri, 9 Sep 2022 21:42:13 +0800 Message-Id: <20220909134215.1843865-7-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220909134215.1843865-1-bmeng.cn@gmail.com> References: <20220909134215.1843865-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=bmeng.cn@gmail.com; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Frank Chang Trigger actions are shared among all triggers. Extract to a common function. Signed-off-by: Frank Chang Reviewed-by: Bin Meng [bmeng: handle the DBG_ACTION_NONE case] Signed-off-by: Bin Meng Reviewed-by: LIU Zhiwei --- Changes in v2: - add handling of the DBG_ACTION_NONE case in do_trigger_action() target/riscv/debug.h | 13 ++++++++++ target/riscv/debug.c | 59 ++++++++++++++++++++++++++++++++++++++++++-- 2 files changed, 70 insertions(+), 2 deletions(-) diff --git a/target/riscv/debug.h b/target/riscv/debug.h index 9f69c64591..0e4859cf74 100644 --- a/target/riscv/debug.h +++ b/target/riscv/debug.h @@ -44,6 +44,19 @@ typedef enum { TRIGGER_TYPE_NUM } trigger_type_t; +/* actions */ +typedef enum { + DBG_ACTION_NONE = -1, /* sentinel value */ + DBG_ACTION_BP = 0, + DBG_ACTION_DBG_MODE, + DBG_ACTION_TRACE0, + DBG_ACTION_TRACE1, + DBG_ACTION_TRACE2, + DBG_ACTION_TRACE3, + DBG_ACTION_EXT_DBG0 = 8, + DBG_ACTION_EXT_DBG1 +} trigger_action_t; + /* tdata1 field masks */ #define RV32_TYPE(t) ((uint32_t)(t) << 28) diff --git a/target/riscv/debug.c b/target/riscv/debug.c index 7d546ace42..7a8910f980 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -92,6 +92,37 @@ static inline target_ulong get_trigger_type(CPURISCVState *env, return extract_trigger_type(env, env->tdata1[trigger_index]); } +static trigger_action_t get_trigger_action(CPURISCVState *env, + target_ulong trigger_index) +{ + target_ulong tdata1 = env->tdata1[trigger_index]; + int trigger_type = get_trigger_type(env, trigger_index); + trigger_action_t action = DBG_ACTION_NONE; + + switch (trigger_type) { + case TRIGGER_TYPE_AD_MATCH: + action = (tdata1 & TYPE2_ACTION) >> 12; + break; + case TRIGGER_TYPE_INST_CNT: + case TRIGGER_TYPE_INT: + case TRIGGER_TYPE_EXCP: + case TRIGGER_TYPE_AD_MATCH6: + case TRIGGER_TYPE_EXT_SRC: + qemu_log_mask(LOG_UNIMP, "trigger type: %d is not supported\n", + trigger_type); + break; + case TRIGGER_TYPE_NO_EXIST: + case TRIGGER_TYPE_UNAVAIL: + qemu_log_mask(LOG_GUEST_ERROR, "trigger type: %d does not exit\n", + trigger_type); + break; + default: + g_assert_not_reached(); + } + + return action; +} + static inline target_ulong build_tdata1(CPURISCVState *env, trigger_type_t type, bool dmode, target_ulong data) @@ -182,6 +213,30 @@ static inline void warn_always_zero_bit(target_ulong val, target_ulong mask, } } +static void do_trigger_action(CPURISCVState *env, target_ulong trigger_index) +{ + trigger_action_t action = get_trigger_action(env, trigger_index); + + switch (action) { + case DBG_ACTION_NONE: + break; + case DBG_ACTION_BP: + riscv_raise_exception(env, RISCV_EXCP_BREAKPOINT, 0); + break; + case DBG_ACTION_DBG_MODE: + case DBG_ACTION_TRACE0: + case DBG_ACTION_TRACE1: + case DBG_ACTION_TRACE2: + case DBG_ACTION_TRACE3: + case DBG_ACTION_EXT_DBG0: + case DBG_ACTION_EXT_DBG1: + qemu_log_mask(LOG_UNIMP, "action: %d is not supported\n", action); + break; + default: + g_assert_not_reached(); + } +} + /* type 2 trigger */ static uint32_t type2_breakpoint_size(CPURISCVState *env, target_ulong ctrl) @@ -384,11 +439,11 @@ void riscv_cpu_debug_excp_handler(CPUState *cs) if (cs->watchpoint_hit) { if (cs->watchpoint_hit->flags & BP_CPU) { cs->watchpoint_hit = NULL; - riscv_raise_exception(env, RISCV_EXCP_BREAKPOINT, 0); + do_trigger_action(env, DBG_ACTION_BP); } } else { if (cpu_breakpoint_test(cs, env->pc, BP_CPU)) { - riscv_raise_exception(env, RISCV_EXCP_BREAKPOINT, 0); + do_trigger_action(env, DBG_ACTION_BP); } } } From patchwork Fri Sep 9 13:42:14 2022 Content-Type: text/plain; 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[144.168.56.201]) by smtp.gmail.com with ESMTPSA id 196-20020a6306cd000000b0042a4612c07esm513172pgg.39.2022.09.09.06.42.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Sep 2022 06:42:40 -0700 (PDT) From: Bin Meng To: qemu-devel@nongnu.org Cc: Frank Chang , Alistair Francis , Bin Meng , Palmer Dabbelt , qemu-riscv@nongnu.org Subject: [PATCH v2 7/8] target/riscv: debug: Check VU/VS modes for type 2 trigger Date: Fri, 9 Sep 2022 21:42:14 +0800 Message-Id: <20220909134215.1843865-8-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220909134215.1843865-1-bmeng.cn@gmail.com> References: <20220909134215.1843865-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=bmeng.cn@gmail.com; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Frank Chang Type 2 trigger cannot be fired in VU/VS modes. Signed-off-by: Frank Chang Reviewed-by: Bin Meng Signed-off-by: Bin Meng --- (no changes since v1) target/riscv/debug.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/target/riscv/debug.c b/target/riscv/debug.c index 7a8910f980..e16d5c070a 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -464,6 +464,11 @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs) switch (trigger_type) { case TRIGGER_TYPE_AD_MATCH: + /* type 2 trigger cannot be fired in VU/VS mode */ + if (riscv_cpu_virt_enabled(env)) { + return false; + } + ctrl = env->tdata1[i]; pc = env->tdata2[i]; @@ -499,6 +504,11 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp) switch (trigger_type) { case TRIGGER_TYPE_AD_MATCH: + /* type 2 trigger cannot be fired in VU/VS mode */ + if (riscv_cpu_virt_enabled(env)) { + return false; + } + ctrl = env->tdata1[i]; addr = env->tdata2[i]; flags = 0; From patchwork Fri Sep 9 13:42:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 12971834 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BD29BECAAD3 for ; Fri, 9 Sep 2022 13:52:30 +0000 (UTC) Received: from localhost ([::1]:43096 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oWeQn-0003E2-IJ for qemu-devel@archiver.kernel.org; Fri, 09 Sep 2022 09:52:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45212) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oWeHP-0007nZ-MF; Fri, 09 Sep 2022 09:42:47 -0400 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]:37466) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oWeHN-0003Jr-Ln; Fri, 09 Sep 2022 09:42:47 -0400 Received: by mail-pl1-x635.google.com with SMTP id s14so1835327plr.4; Fri, 09 Sep 2022 06:42:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=0snJnRa+N8kkM22PtyeEp2wNO5x5f1+D6KWxEK7uLRk=; b=kx5krN4cWDZ9WmuZ/Uv8qvXkSqFDIaJkiKrTdwzkPjsKn87HU2uJRcbH7ogWC3R0rQ RPjv/IlU7Om+DsqsvKX5ELZWJvBTNCYIT62eqi2Y7FBxYWg+vuup0K8A88l7jOh/Da0z 47+BqbAuaWYplrk381ZcGVrqmiyfjo7mWrXjeW/tl44bO7FSxPXUKj733ZpqgdYEiujp rG2VqqL3IVVSBcEmjtTPMkyoJKIpYyGAePT8QihGLZLHtuqpY4IbqdlR4OkM0aifuSUI 48BA1TGdr8lOvckPCA6EO/0UqionXn1j6ZMu0FWk2kQpzYamoYYJH9hSuxfaoizkwT/E dqRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=0snJnRa+N8kkM22PtyeEp2wNO5x5f1+D6KWxEK7uLRk=; b=P9GN6JMGosYBGbUYVyF7IK4x7TJav2P++HbymFhGeseJ+qU7CoxLw0ES38+ggcu6QT GKStlqDb6G8kY6xNKAwLGF8wBDNRCOJpwlibxTkOnSnYeL2hErqfvCoMFdWo+frW7HbC EkDOx8cS0hGL/31eCbXzgnaA7NNFxWW40OxBT1RGcUd2NCPVQPemhptM+ggNMma1c3PH 5du/oVl8jMMTMohYDV8iibQ9Vmf14zGzVJo4PVEU1zr1CYs3N4YslnSJo4HLLLz75+8a crgM6Pb0wqzh1LV80t+0CNM0Ejgx5dBuEpTNmZMTOvduW3WkJUNnefW5tqVrq87pgyQv RAsA== X-Gm-Message-State: ACgBeo0jv9GWYbA3h+fZcCm8YQdIr+UhiUVr+03sIhHYgrTWgRqgzVmH 2SW9Vld95Ms7br5auU59Y3SyA/RPAXg= X-Google-Smtp-Source: AA6agR4dqR+nbG3mqxakzT54WsS68830LjL6lCSZ9T+MnPhWu+bLm9CuJfM4pNz4MGpyfeY+EBQBFQ== X-Received: by 2002:a17:90b:1bc7:b0:202:52ce:a1d with SMTP id oa7-20020a17090b1bc700b0020252ce0a1dmr9939039pjb.110.1662730963828; Fri, 09 Sep 2022 06:42:43 -0700 (PDT) Received: from ubuntu.. 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[144.168.56.201]) by smtp.gmail.com with ESMTPSA id 196-20020a6306cd000000b0042a4612c07esm513172pgg.39.2022.09.09.06.42.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Sep 2022 06:42:43 -0700 (PDT) From: Bin Meng To: qemu-devel@nongnu.org Cc: Frank Chang , Alistair Francis , Bin Meng , Palmer Dabbelt , qemu-riscv@nongnu.org Subject: [PATCH v2 8/8] target/riscv: debug: Add initial support of type 6 trigger Date: Fri, 9 Sep 2022 21:42:15 +0800 Message-Id: <20220909134215.1843865-9-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220909134215.1843865-1-bmeng.cn@gmail.com> References: <20220909134215.1843865-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=bmeng.cn@gmail.com; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Frank Chang Type 6 trigger is similar to a type 2 trigger, but provides additional functionality and should be used instead of type 2 in newer implementations. Signed-off-by: Frank Chang Reviewed-by: Bin Meng Signed-off-by: Bin Meng --- (no changes since v1) target/riscv/debug.h | 18 +++++ target/riscv/debug.c | 174 ++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 188 insertions(+), 4 deletions(-) diff --git a/target/riscv/debug.h b/target/riscv/debug.h index 0e4859cf74..a1226b4d29 100644 --- a/target/riscv/debug.h +++ b/target/riscv/debug.h @@ -85,6 +85,24 @@ typedef enum { #define TYPE2_HIT BIT(20) #define TYPE2_SIZEHI (0x3 << 21) /* RV64 only */ +/* mcontrol6 field masks */ + +#define TYPE6_LOAD BIT(0) +#define TYPE6_STORE BIT(1) +#define TYPE6_EXEC BIT(2) +#define TYPE6_U BIT(3) +#define TYPE6_S BIT(4) +#define TYPE6_M BIT(6) +#define TYPE6_MATCH (0xf << 7) +#define TYPE6_CHAIN BIT(11) +#define TYPE6_ACTION (0xf << 12) +#define TYPE6_SIZE (0xf << 16) +#define TYPE6_TIMING BIT(20) +#define TYPE6_SELECT BIT(21) +#define TYPE6_HIT BIT(22) +#define TYPE6_VU BIT(23) +#define TYPE6_VS BIT(24) + /* access size */ enum { SIZE_ANY = 0, diff --git a/target/riscv/debug.c b/target/riscv/debug.c index e16d5c070a..26ea764407 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -39,7 +39,7 @@ * - tdata3 * - tinfo * - * The following triggers are implemented: + * The following triggers are initialized by default: * * Index | Type | tdata mapping | Description * ------+------+------------------------+------------ @@ -103,10 +103,12 @@ static trigger_action_t get_trigger_action(CPURISCVState *env, case TRIGGER_TYPE_AD_MATCH: action = (tdata1 & TYPE2_ACTION) >> 12; break; + case TRIGGER_TYPE_AD_MATCH6: + action = (tdata1 & TYPE6_ACTION) >> 12; + break; case TRIGGER_TYPE_INST_CNT: case TRIGGER_TYPE_INT: case TRIGGER_TYPE_EXCP: - case TRIGGER_TYPE_AD_MATCH6: case TRIGGER_TYPE_EXT_SRC: qemu_log_mask(LOG_UNIMP, "trigger type: %d is not supported\n", trigger_type); @@ -379,6 +381,123 @@ static void type2_reg_write(CPURISCVState *env, target_ulong index, return; } +/* type 6 trigger */ + +static inline bool type6_breakpoint_enabled(target_ulong ctrl) +{ + bool mode = !!(ctrl & (TYPE6_VU | TYPE6_VS | TYPE6_U | TYPE6_S | TYPE6_M)); + bool rwx = !!(ctrl & (TYPE6_LOAD | TYPE6_STORE | TYPE6_EXEC)); + + return mode && rwx; +} + +static target_ulong type6_mcontrol6_validate(CPURISCVState *env, + target_ulong ctrl) +{ + target_ulong val; + uint32_t size; + + /* validate the generic part first */ + val = tdata1_validate(env, ctrl, TRIGGER_TYPE_AD_MATCH6); + + /* validate unimplemented (always zero) bits */ + warn_always_zero_bit(ctrl, TYPE6_MATCH, "match"); + warn_always_zero_bit(ctrl, TYPE6_CHAIN, "chain"); + warn_always_zero_bit(ctrl, TYPE6_ACTION, "action"); + warn_always_zero_bit(ctrl, TYPE6_TIMING, "timing"); + warn_always_zero_bit(ctrl, TYPE6_SELECT, "select"); + warn_always_zero_bit(ctrl, TYPE6_HIT, "hit"); + + /* validate size encoding */ + size = extract32(ctrl, 16, 4); + if (access_size[size] == -1) { + qemu_log_mask(LOG_UNIMP, "access size %d is not supported, using SIZE_ANY\n", + size); + } else { + val |= (ctrl & TYPE6_SIZE); + } + + /* keep the mode and attribute bits */ + val |= (ctrl & (TYPE6_VU | TYPE6_VS | TYPE6_U | TYPE6_S | TYPE6_M | + TYPE6_LOAD | TYPE6_STORE | TYPE6_EXEC)); + + return val; +} + +static void type6_breakpoint_insert(CPURISCVState *env, target_ulong index) +{ + target_ulong ctrl = env->tdata1[index]; + target_ulong addr = env->tdata2[index]; + bool enabled = type6_breakpoint_enabled(ctrl); + CPUState *cs = env_cpu(env); + int flags = BP_CPU | BP_STOP_BEFORE_ACCESS; + uint32_t size; + + if (!enabled) { + return; + } + + if (ctrl & TYPE6_EXEC) { + cpu_breakpoint_insert(cs, addr, flags, &env->cpu_breakpoint[index]); + } + + if (ctrl & TYPE6_LOAD) { + flags |= BP_MEM_READ; + } + + if (ctrl & TYPE6_STORE) { + flags |= BP_MEM_WRITE; + } + + if (flags & BP_MEM_ACCESS) { + size = extract32(ctrl, 16, 4); + if (size != 0) { + cpu_watchpoint_insert(cs, addr, size, flags, + &env->cpu_watchpoint[index]); + } else { + cpu_watchpoint_insert(cs, addr, 8, flags, + &env->cpu_watchpoint[index]); + } + } +} + +static void type6_breakpoint_remove(CPURISCVState *env, target_ulong index) +{ + type2_breakpoint_remove(env, index); +} + +static void type6_reg_write(CPURISCVState *env, target_ulong index, + int tdata_index, target_ulong val) +{ + target_ulong new_val; + + switch (tdata_index) { + case TDATA1: + new_val = type6_mcontrol6_validate(env, val); + if (new_val != env->tdata1[index]) { + env->tdata1[index] = new_val; + type6_breakpoint_remove(env, index); + type6_breakpoint_insert(env, index); + } + break; + case TDATA2: + if (val != env->tdata2[index]) { + env->tdata2[index] = val; + type6_breakpoint_remove(env, index); + type6_breakpoint_insert(env, index); + } + break; + case TDATA3: + qemu_log_mask(LOG_UNIMP, + "tdata3 is not supported for type 6 trigger\n"); + break; + default: + g_assert_not_reached(); + } + + return; +} + target_ulong tdata_csr_read(CPURISCVState *env, int tdata_index) { switch (tdata_index) { @@ -407,10 +526,12 @@ void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val) case TRIGGER_TYPE_AD_MATCH: type2_reg_write(env, env->trigger_cur, tdata_index, val); break; + case TRIGGER_TYPE_AD_MATCH6: + type6_reg_write(env, env->trigger_cur, tdata_index, val); + break; case TRIGGER_TYPE_INST_CNT: case TRIGGER_TYPE_INT: case TRIGGER_TYPE_EXCP: - case TRIGGER_TYPE_AD_MATCH6: case TRIGGER_TYPE_EXT_SRC: qemu_log_mask(LOG_UNIMP, "trigger type: %d is not supported\n", trigger_type); @@ -428,7 +549,8 @@ void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val) target_ulong tinfo_csr_read(CPURISCVState *env) { /* assume all triggers support the same types of triggers */ - return BIT(TRIGGER_TYPE_AD_MATCH); + return BIT(TRIGGER_TYPE_AD_MATCH) | + BIT(TRIGGER_TYPE_AD_MATCH6); } void riscv_cpu_debug_excp_handler(CPUState *cs) @@ -479,6 +601,24 @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs) } } break; + case TRIGGER_TYPE_AD_MATCH6: + ctrl = env->tdata1[i]; + pc = env->tdata2[i]; + + if ((ctrl & TYPE6_EXEC) && (bp->pc == pc)) { + if (riscv_cpu_virt_enabled(env)) { + /* check VU/VS bit against current privilege level */ + if ((ctrl >> 23) & BIT(env->priv)) { + return true; + } + } else { + /* check U/S/M bit against current privilege level */ + if ((ctrl >> 3) & BIT(env->priv)) { + return true; + } + } + } + break; default: /* other trigger types are not supported or irrelevant */ break; @@ -527,6 +667,32 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp) } } break; + case TRIGGER_TYPE_AD_MATCH6: + ctrl = env->tdata1[i]; + addr = env->tdata2[i]; + flags = 0; + + if (ctrl & TYPE6_LOAD) { + flags |= BP_MEM_READ; + } + if (ctrl & TYPE6_STORE) { + flags |= BP_MEM_WRITE; + } + + if ((wp->flags & flags) && (wp->vaddr == addr)) { + if (riscv_cpu_virt_enabled(env)) { + /* check VU/VS bit against current privilege level */ + if ((ctrl >> 23) & BIT(env->priv)) { + return true; + } + } else { + /* check U/S/M bit against current privilege level */ + if ((ctrl >> 3) & BIT(env->priv)) { + return true; + } + } + } + break; default: /* other trigger types are not supported */ break;