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Miller" , Florian Fainelli , Vivien Didelot , Andrew Lunn , UNGLinuxDriver@microchip.com, Alexandre Belloni , Claudiu Manoil , Vladimir Oltean , Lee Jones Subject: [RFC v1 net-next 1/8] net: mscc: ocelot: expose ocelot wm functions Date: Sun, 11 Sep 2022 13:02:37 -0700 Message-Id: <20220911200244.549029-2-colin.foster@in-advantage.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220911200244.549029-1-colin.foster@in-advantage.com> References: <20220911200244.549029-1-colin.foster@in-advantage.com> X-ClientProxiedBy: MW4PR03CA0318.namprd03.prod.outlook.com (2603:10b6:303:dd::23) To MWHPR1001MB2351.namprd10.prod.outlook.com (2603:10b6:301:35::37) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 8ec766c8-008b-4cc5-cbf0-08da94309d8b X-MS-TrafficTypeDiagnostic: BN0PR10MB5335:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ICA9ww3eJ8tHZbENyAlqmth1FFDRm+V5LZRt0E8M1gnFAgLLq0BrPT57nI0jht79a6lPs2YbHL2SggnDwbE+G7zOZ+0PlLnrF0Mg8yXABx+hgnOkE6AM4xsUGU47YHrzIk21K41cdqiitZcthdfcZBnQ2mZAyGV3CfclmIra1jmU+aTndqQB2FZ9n70GoeTP6wjXSUQnBMTC0AKUrE9Lf67g70oX+jSOZ0ntdqR41VbOKGhwbsVz4nQgFqpq/NTE2pmbG6G0Km4z+R2TSoItcMvkwJfyqRjMsCVhq4dp9IeZczlE4vILy0kKwilC4NKVkXO6uKORLHswzHkRWuZQdTyQtyVeZjVNVd7o9RArzKx/vB7wrSdlPaA7SvTZNGT0Ju86r94pFmPltEOeM8j+R2oVRaHovxyR4b7BdSmd8Nm1eLdoDytkg9jQ9GY68Xm/e0qd9HDTz13H5vgRad9IubjfNpuAgCi/NGK1b/PDLufic8dlWBP6+YeuhM/Wt53k+G9F4VmF+HaQrCHrlx0dDrbMb8yC0llg24ZUM4+KfE4ecQrCotVXgaAu8Rj89Nzf1iYRzOJ064YnRrlGtM8hxQwPDHOwkc6D6XjKWWiNe214JUJkSHSNx4524t+3gXtlpIsbXuKdmxYe4AHy4iH8Det/KFNmk/v8v0gIH4S6Bp80wR8kiKmd9V+ac9Ib+cGpb9XU6VOx9Rd5paY6v7bUbss/QGSPDBO48pdWRLngMNkXlSy8dYq3lw5jjeZPikjzJ9umugfA9QrjV4b2KdaquA== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:MWHPR1001MB2351.namprd10.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230016)(396003)(136003)(366004)(39830400003)(376002)(346002)(38350700002)(38100700002)(8676002)(4326008)(66946007)(36756003)(86362001)(66556008)(66476007)(2906002)(83380400001)(186003)(2616005)(6512007)(6506007)(1076003)(52116002)(478600001)(6486002)(6666004)(26005)(316002)(54906003)(44832011)(41300700001)(8936002)(5660300002)(7416002);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: KW4Znoj6WvtNKZSFNFEzs84LfXtxg7JPuSMFi6gpSibVW55gVq88/PU+lEeJis+qiAYTJ51YXA5f8nymujCUGVnv6wF4v5pnxDAvEx57m49C2zMoX/rNZ0QVmosltOjfgrkCVftNn2MKOUGsT4hgzc8Gd+NnKPZI/qXHmh8YSvE9ePwytRqBI+jMEiVp3hhcCdiTGYMBlj0TrRHHbxyKtNP7/QcEtsBO4VEUwU6O94FpZBm+nkdmZmrZJsXsj4cz8auK3iXJzRG+hda4dMmzhTAGUJ9q5q3Yd5+Nbs/JVxAI5CvrckhYNNalKPheKwTQvdN02TZDmO0Ag1mkHYVgyzgVq5J/6+iFZSZuQ5w5dyVVMPX3M5Iq6vbEz8rXGNXdVKYhKDG42MD/QdyDuOTWYP9rqXR1KV02w0dUvywwNa6zlG1/yj1enJ01pPcw/NBME92TtvdC4ERTYn8gXg5r+e28fXPjP1jss4+boNXh2JXCiIA8Az+pt5ZzuMcGu9DSCBW+5EHF45uwgSphZQei+df+GsUFbGWIfzbqphdsNKJJ1X6LnkOHNLJDQAgOPkE15YDh73doh/uphVNF8b/LwrSImw8u4oDpVbQGeAEg4YkkzlD/juK2fPM+kD+/+QKrB22kNeBC0pqZn8P+x1GEFjhHiuWPw/G5Y3HFger+vLZmvTb4D7dzZszSR50kxQOS03OlIQTVlZ2kMkJo2GwrojbUN9aPYYRzXmykH2HZ5RywWPpdgKBLnv0zND00VKyD4QRVlNAeV8z3f08vldgS3IKdvuhl5l9xnA9uPQHRr/Okst4tM6/xym5FQYsYTIBarYQGd/X5jftuiEd12rCClZQsFK3MVudnVsHqZxgdqsLycXwOR9Ym3KrsdCmP3iaahqN7+QBfbRBVZHHVDkvRojlID7QcP6Bk6jnwx6jpF7vHTtivdtmnIHCuienxUi0T9rYNm2q7RvgjyULW5McqIFq+qTgCQ4giKbqP6eDEkGs5n6PCwk6ydlXz6gayIV+a64EGTNL0v7VOOhVjeA0x/eKP/m90JNbkOtNCsV+V7NEe0SUIuJqRU5VUjBi6U1fmI/rB53U2tdl8QshpaOemfBdZoOf+iXa5OCDyrVk//Yp6mtil8twwHiuly8Lhzq4jH1TPNlsqTMm7FYhOhm6zv2FCTuy7AvlwAwOg6vvR6ZG2E1mjX+u4L0LFYt1paLxVuIjmXOWPhukL2c52THzws+XLrGBSU/l0y/nIYS9eVF6vUwCx1dbE/sQVwXzG0GkrPoCqyaZ26gvDxHecusAHoH8x6xPdqYrsPYG5l5jnVmeaxSGWvZLAhEHTHEY48RARycO/yelLi646YU2Egkh482pxp0eG2qgRcXZRvrVm8trZJpSVPpxFR7ZGVW0UuG1DrKTZkJ8lQlwvJaZ6IhDp/h4P2gBKMTcvA+6iK5vrub/sEA67q+g9bDSArMZcx4kB43N6cN9Aa8C84umazc6mUyVHH+mSHbcm6aVsh1oT3tJN5ViWbNkMdaHeUoES59E9jwDMtWzXGvGvbnVG6DZDA38P42qyu6wvCuXrIaLhXZL19eAIWnFw2UoHXWHCkVZEVwDnNT5DtzWmKqC3CYAdyESUegQ419sNrpoEvHKxfqc= X-OriginatorOrg: in-advantage.com X-MS-Exchange-CrossTenant-Network-Message-Id: 8ec766c8-008b-4cc5-cbf0-08da94309d8b X-MS-Exchange-CrossTenant-AuthSource: MWHPR1001MB2351.namprd10.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Sep 2022 20:02:55.1059 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 48e842ca-fbd8-4633-a79d-0c955a7d3aae X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: ulclVo0JyinfMFATda+2yFdtq5VGIt1lH2W/iw8azRPsjmeDgGGsQyfvD56YwQTLcRhHOilxruWqbLQh8hTHcN4aff+I13S0HgBgzWRpY/E= X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN0PR10MB5335 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org X-Patchwork-State: RFC Expose ocelot_wm functions so they can be shared with other drivers. Signed-off-by: Colin Foster Reviewed-by: Vladimir Oltean --- v1: * No changes since previous RFC --- drivers/net/ethernet/mscc/ocelot_devlink.c | 31 ++++++++++++++++++++++ drivers/net/ethernet/mscc/ocelot_vsc7514.c | 28 ------------------- include/soc/mscc/ocelot.h | 5 ++++ 3 files changed, 36 insertions(+), 28 deletions(-) diff --git a/drivers/net/ethernet/mscc/ocelot_devlink.c b/drivers/net/ethernet/mscc/ocelot_devlink.c index b8737efd2a85..d9ea75a14f2f 100644 --- a/drivers/net/ethernet/mscc/ocelot_devlink.c +++ b/drivers/net/ethernet/mscc/ocelot_devlink.c @@ -487,6 +487,37 @@ static void ocelot_watermark_init(struct ocelot *ocelot) ocelot_setup_sharing_watermarks(ocelot); } +/* Watermark encode + * Bit 8: Unit; 0:1, 1:16 + * Bit 7-0: Value to be multiplied with unit + */ +u16 ocelot_wm_enc(u16 value) +{ + WARN_ON(value >= 16 * BIT(8)); + + if (value >= BIT(8)) + return BIT(8) | (value / 16); + + return value; +} +EXPORT_SYMBOL(ocelot_wm_enc); + +u16 ocelot_wm_dec(u16 wm) +{ + if (wm & BIT(8)) + return (wm & GENMASK(7, 0)) * 16; + + return wm; +} +EXPORT_SYMBOL(ocelot_wm_dec); + +void ocelot_wm_stat(u32 val, u32 *inuse, u32 *maxuse) +{ + *inuse = (val & GENMASK(23, 12)) >> 12; + *maxuse = val & GENMASK(11, 0); +} +EXPORT_SYMBOL(ocelot_wm_stat); + /* Pool size and type are fixed up at runtime. Keeping this structure to * look up the cell size multipliers. */ diff --git a/drivers/net/ethernet/mscc/ocelot_vsc7514.c b/drivers/net/ethernet/mscc/ocelot_vsc7514.c index ae42bbba5747..80e88bfd38ad 100644 --- a/drivers/net/ethernet/mscc/ocelot_vsc7514.c +++ b/drivers/net/ethernet/mscc/ocelot_vsc7514.c @@ -214,34 +214,6 @@ static int ocelot_reset(struct ocelot *ocelot) return 0; } -/* Watermark encode - * Bit 8: Unit; 0:1, 1:16 - * Bit 7-0: Value to be multiplied with unit - */ -static u16 ocelot_wm_enc(u16 value) -{ - WARN_ON(value >= 16 * BIT(8)); - - if (value >= BIT(8)) - return BIT(8) | (value / 16); - - return value; -} - -static u16 ocelot_wm_dec(u16 wm) -{ - if (wm & BIT(8)) - return (wm & GENMASK(7, 0)) * 16; - - return wm; -} - -static void ocelot_wm_stat(u32 val, u32 *inuse, u32 *maxuse) -{ - *inuse = (val & GENMASK(23, 12)) >> 12; - *maxuse = val & GENMASK(11, 0); -} - static const struct ocelot_ops ocelot_ops = { .reset = ocelot_reset, .wm_enc = ocelot_wm_enc, diff --git a/include/soc/mscc/ocelot.h b/include/soc/mscc/ocelot.h index 355cfdedc43b..17dd61f36563 100644 --- a/include/soc/mscc/ocelot.h +++ b/include/soc/mscc/ocelot.h @@ -1145,6 +1145,11 @@ void ocelot_port_assign_dsa_8021q_cpu(struct ocelot *ocelot, int port, int cpu); void ocelot_port_unassign_dsa_8021q_cpu(struct ocelot *ocelot, int port); u32 ocelot_port_assigned_dsa_8021q_cpu_mask(struct ocelot *ocelot, int port); +/* Watermark interface */ +u16 ocelot_wm_enc(u16 value); +u16 ocelot_wm_dec(u16 wm); +void ocelot_wm_stat(u32 val, u32 *inuse, u32 *maxuse); + /* DSA callbacks */ void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data); void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data); From patchwork Sun Sep 11 20:02:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Colin Foster X-Patchwork-Id: 12973041 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D9E06C6FA83 for ; Sun, 11 Sep 2022 20:03:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229660AbiIKUDG (ORCPT ); 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Miller" , Florian Fainelli , Vivien Didelot , Andrew Lunn , UNGLinuxDriver@microchip.com, Alexandre Belloni , Claudiu Manoil , Vladimir Oltean , Lee Jones Subject: [RFC v1 net-next 2/8] net: mscc: ocelot: expose regfield definition to be used by other drivers Date: Sun, 11 Sep 2022 13:02:38 -0700 Message-Id: <20220911200244.549029-3-colin.foster@in-advantage.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220911200244.549029-1-colin.foster@in-advantage.com> References: <20220911200244.549029-1-colin.foster@in-advantage.com> X-ClientProxiedBy: MW4PR03CA0318.namprd03.prod.outlook.com (2603:10b6:303:dd::23) To MWHPR1001MB2351.namprd10.prod.outlook.com (2603:10b6:301:35::37) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 054a6159-5515-4e26-3cce-08da94309ddf X-MS-TrafficTypeDiagnostic: BN0PR10MB5335:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: eUuXUWDksiGXLMBNQ64sEs8TviDdadZEBMds93G245aDz/+IUSlB551tz9X2X+Vfj+mFPyFQ/HXKdqpuVKU2+jilDoxZ0gfR0wxObAxiD4Vn6mbjg21CUgm6MOebVt1lUi1bokcKA/udTpKz7N9OVVkfwd7xZSyjYhNWz2WaD6wyrtl2xoberKOVc4Ii9LvUSyNO75VhxChmLS6ZifZ0rMq1oo/2G6PB+cEj6cFzUpE/6iiBS62Zgqmsqc7Ngl+GUWCinFQ0ro/0Z3PtsuNvoc9rfHMQAJhv0wD2vVJmfV155z6pNm7d5TDf3/3AmY7waQbUbI9AdwcOM+T6cDoQ4EVUMjnVzTBUN7FH/mGoColxCGf0ksZZPWd5hzPcVb+EfFXiPrtttNrb/S7o/MxwG2n3yjQM/qcUUpWN5RSKzIGUQfZ7JWaRRC9niUtm8KB37KINEhpKYdfKoYcMJ7Jr/yMxFZA4cZZsvLOIjdZF1zQ0BP1u+hZb1gBILp7aBlwZwFI1FkPvPcHLdiAvFOIvxOhOvka/ymxBsMypsQN4p0y7aDIINCKwrXI66NVXUFcBFTW79kkGmgIBoa4ZdY3I2jr/HGOxqcCFAXQYWksIL9YZ1YxMGw8DjS4iUkJI0/Fqbp2Q5i6Xztob4EByqA8Htsa95P/kk6H5naGNnEzDAxFDE2Yi4UmAb/Yw47HMgRAqtGMZhcKkUBZwimA/1kpgqLOsgEyZzze1vHslJyL4l0V7VHOc0GunNItTB/LJHdDZ3VfAIENdNacuwksWK52wPg== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:MWHPR1001MB2351.namprd10.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230016)(396003)(136003)(366004)(39830400003)(376002)(346002)(38350700002)(38100700002)(8676002)(4326008)(66946007)(36756003)(86362001)(66556008)(66476007)(2906002)(83380400001)(186003)(2616005)(6512007)(6506007)(1076003)(52116002)(478600001)(6486002)(6666004)(26005)(316002)(54906003)(30864003)(44832011)(41300700001)(8936002)(5660300002)(7416002);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: WrvwxI1+lDzim9bfL+18RHlWIAmdEwmeeiHh/BgEkYnvj4In72CJW+g05YJh/eCfgA66gQDi+3aJZZMxofOBHUDN0COMsUjCDqNV7FU2jbEzeM3BtkCTmzMkNJ8RIOKLyjGeFzSYb8x7kwBmEE9nXXB7LEk55tMCNFo2JvY1nB3FKYQS5DiZRcU/opSNLbJL7W6Ef1wZZhj3aPwdCNgRnEML30oy98OBQf6rqqhlBe2OJ0BlKlNIQhEeTv1l0LTYr0p2t4vohNchT5Izwc/ZjJAt2J8GPPKKtBWaap8sC68NIHjHvvQ44JY+9mh4+p/F8pNVICj2H3OD5Vruwf5AFl+edfXE0S6LMzVnwtShhAIjk/KHE7bfOzJiXXKlnzwNPpiji8Zy/GDBj0EBN7ZsHJgAx82ESXy2ZibjPdasvkoLmyibTylrb3Z2KyImzcW6bI077FoXILaGFWBTCCT2BBepbk+uRnusDGBxmxiK1Bt+Fcjsfyy0zgkrlPcTUMFIGUHaKFmWDqmKeWw1WPRBF2Dke+UIsEeT5lT9zbVRgXgAQGgmHXWdP+jWQTf9TOEnY/yuCcIFZ7tapepW58b908orMWkSBqHZh836LYjEzjh0VB1Ipz4WCyCqOGpFfcBSFIGCSjaoxPNC0aGvZE1RMRdpU96N19Y/i8ZL2GWZfxcJ0nUyybKye3TeeeV60AYK18QlKeUNCuLrqrI5ufjzWBtkcIKGZhpNFgbzP8LTO0AGTCVopMT3/o1u81U0OLXBtKe/pWZKgxrePSaEp7GXwJaxhSlT7iDsdGFhHRR7c3/Vr66L/KdsoX5eTvliJWhIuWduyO9OTw3QdWPCFkpwcGz91EmgoBxjgSGvb2Rfgb40HqL4EaWfNjio1flO/aNI6568zoBv9wMaS7n+UJmCodq1PoQOLV5M6u1yY85RQiQWr0Ls/cbCejoclpjVOMRs7VZYJ8Zw+V7F2GQgWzIsF2y+eIUom8HgnVVzu127aSjENjHjcPHbNF63tCwbdOR8MpL1NOFSD9lvjaYIUfLBnCLBJcAtwMPJIeKkR4F8xXuZp7hnHUtKFzMqyTe8BrBmnq3BAQpA2ZI1na8mFgXYKRs1wp8II0z6YXG9C/TkypjjtpTFW365c1OPXnRtU995TvBJI1GGi0ocC//qAkPGkbYBNKeHaCYbVCanVLwlUnFFtPD93RQ8gQ4HdH7i+ezeAN5hpS2cqO2IATbJLC9E7wJ9Bk7ZPUyQSSuouIwCpMugzf/9andekE+OFwgfyvRSfQ4YiBYtWdL7+iEdIaJMVcf0f7ddGcgRw1Oy8/xDExAWOnW/doZjz93/MFBYBCElU2qetbaSoVoReSiy6M1KK3TcI2pwl6ZE8thFjg6WGxera/EuBKmMnRYlqE3FyESrABL1NWraDi90yHgcgII0j0MF9CHLhdiEkMEM3LsLnNd8IUzC4BgdnECdOu1iHhyGoqcTUFMNdEskc5Hd4V81IcqNKWT+O7b0kQPsqRA0eCvih8HHTmbuEk77gxuBKjhFy/C+vHZiX15C37VymY9AM1+wlrWLk7JeF02Aa2YPpiTsGdmBAJWlbR4J64/H6fYMcNDs/34CPCm0IWIun3/4hUwxEw0exUcRdjYNDPGZQlA= X-OriginatorOrg: in-advantage.com X-MS-Exchange-CrossTenant-Network-Message-Id: 054a6159-5515-4e26-3cce-08da94309ddf X-MS-Exchange-CrossTenant-AuthSource: MWHPR1001MB2351.namprd10.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Sep 2022 20:02:55.5746 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 48e842ca-fbd8-4633-a79d-0c955a7d3aae X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: +zQ3TQinl6yxBxIQYYslFTIeTP3xHBlNBikzUO4jhhYCSzZFFiI7lawVF/PN8c881JHGj8axl4xI+0/EG8J6KXHfH1rntI6ubzMJemqQXzM= X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN0PR10MB5335 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org X-Patchwork-State: RFC The ocelot_regfields struct is common between several different chips, some of which can only be controlled externally. Export this structure so it doesn't have to be duplicated in these other drivers. Rename the structure as well, to follow the conventions of other shared resources. Signed-off-by: Colin Foster Reviewed-by: Vladimir Oltean --- v1 from previous RFC: * Remove GCB_SOFT_RST_SWC_RST entry from the regfields struct - it isn't used. * Export the vsc7514_regfields symbol so it can be used as a module. --- drivers/net/ethernet/mscc/ocelot_vsc7514.c | 60 +--------------------- drivers/net/ethernet/mscc/vsc7514_regs.c | 59 +++++++++++++++++++++ include/soc/mscc/vsc7514_regs.h | 2 + 3 files changed, 62 insertions(+), 59 deletions(-) diff --git a/drivers/net/ethernet/mscc/ocelot_vsc7514.c b/drivers/net/ethernet/mscc/ocelot_vsc7514.c index 80e88bfd38ad..e9c7740f20e9 100644 --- a/drivers/net/ethernet/mscc/ocelot_vsc7514.c +++ b/drivers/net/ethernet/mscc/ocelot_vsc7514.c @@ -38,64 +38,6 @@ static const u32 *ocelot_regmap[TARGET_MAX] = { [DEV_GMII] = vsc7514_dev_gmii_regmap, }; -static const struct reg_field ocelot_regfields[REGFIELD_MAX] = { - [ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 11, 11), - [ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 10), - [ANA_ANEVENTS_MSTI_DROP] = REG_FIELD(ANA_ANEVENTS, 27, 27), - [ANA_ANEVENTS_ACLKILL] = REG_FIELD(ANA_ANEVENTS, 26, 26), - [ANA_ANEVENTS_ACLUSED] = REG_FIELD(ANA_ANEVENTS, 25, 25), - [ANA_ANEVENTS_AUTOAGE] = REG_FIELD(ANA_ANEVENTS, 24, 24), - [ANA_ANEVENTS_VS2TTL1] = REG_FIELD(ANA_ANEVENTS, 23, 23), - [ANA_ANEVENTS_STORM_DROP] = REG_FIELD(ANA_ANEVENTS, 22, 22), - [ANA_ANEVENTS_LEARN_DROP] = REG_FIELD(ANA_ANEVENTS, 21, 21), - [ANA_ANEVENTS_AGED_ENTRY] = REG_FIELD(ANA_ANEVENTS, 20, 20), - [ANA_ANEVENTS_CPU_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 19, 19), - [ANA_ANEVENTS_AUTO_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 18, 18), - [ANA_ANEVENTS_LEARN_REMOVE] = REG_FIELD(ANA_ANEVENTS, 17, 17), - [ANA_ANEVENTS_AUTO_LEARNED] = REG_FIELD(ANA_ANEVENTS, 16, 16), - [ANA_ANEVENTS_AUTO_MOVED] = REG_FIELD(ANA_ANEVENTS, 15, 15), - [ANA_ANEVENTS_DROPPED] = REG_FIELD(ANA_ANEVENTS, 14, 14), - [ANA_ANEVENTS_CLASSIFIED_DROP] = REG_FIELD(ANA_ANEVENTS, 13, 13), - [ANA_ANEVENTS_CLASSIFIED_COPY] = REG_FIELD(ANA_ANEVENTS, 12, 12), - [ANA_ANEVENTS_VLAN_DISCARD] = REG_FIELD(ANA_ANEVENTS, 11, 11), - [ANA_ANEVENTS_FWD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 10, 10), - [ANA_ANEVENTS_MULTICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 9, 9), - [ANA_ANEVENTS_UNICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 8, 8), - [ANA_ANEVENTS_DEST_KNOWN] = REG_FIELD(ANA_ANEVENTS, 7, 7), - [ANA_ANEVENTS_BUCKET3_MATCH] = REG_FIELD(ANA_ANEVENTS, 6, 6), - [ANA_ANEVENTS_BUCKET2_MATCH] = REG_FIELD(ANA_ANEVENTS, 5, 5), - [ANA_ANEVENTS_BUCKET1_MATCH] = REG_FIELD(ANA_ANEVENTS, 4, 4), - [ANA_ANEVENTS_BUCKET0_MATCH] = REG_FIELD(ANA_ANEVENTS, 3, 3), - [ANA_ANEVENTS_CPU_OPERATION] = REG_FIELD(ANA_ANEVENTS, 2, 2), - [ANA_ANEVENTS_DMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 1, 1), - [ANA_ANEVENTS_SMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 0, 0), - [ANA_TABLES_MACACCESS_B_DOM] = REG_FIELD(ANA_TABLES_MACACCESS, 18, 18), - [ANA_TABLES_MACTINDX_BUCKET] = REG_FIELD(ANA_TABLES_MACTINDX, 10, 11), - [ANA_TABLES_MACTINDX_M_INDEX] = REG_FIELD(ANA_TABLES_MACTINDX, 0, 9), - [QSYS_TIMED_FRAME_ENTRY_TFRM_VLD] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 20, 20), - [QSYS_TIMED_FRAME_ENTRY_TFRM_FP] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 8, 19), - [QSYS_TIMED_FRAME_ENTRY_TFRM_PORTNO] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 4, 7), - [QSYS_TIMED_FRAME_ENTRY_TFRM_TM_SEL] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 1, 3), - [QSYS_TIMED_FRAME_ENTRY_TFRM_TM_T] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 0, 0), - [SYS_RESET_CFG_CORE_ENA] = REG_FIELD(SYS_RESET_CFG, 2, 2), - [SYS_RESET_CFG_MEM_ENA] = REG_FIELD(SYS_RESET_CFG, 1, 1), - [SYS_RESET_CFG_MEM_INIT] = REG_FIELD(SYS_RESET_CFG, 0, 0), - /* Replicated per number of ports (12), register size 4 per port */ - [QSYS_SWITCH_PORT_MODE_PORT_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 14, 14, 12, 4), - [QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 11, 13, 12, 4), - [QSYS_SWITCH_PORT_MODE_YEL_RSRVD] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 10, 10, 12, 4), - [QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 9, 9, 12, 4), - [QSYS_SWITCH_PORT_MODE_TX_PFC_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 1, 8, 12, 4), - [QSYS_SWITCH_PORT_MODE_TX_PFC_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 0, 0, 12, 4), - [SYS_PORT_MODE_DATA_WO_TS] = REG_FIELD_ID(SYS_PORT_MODE, 5, 6, 12, 4), - [SYS_PORT_MODE_INCL_INJ_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 3, 4, 12, 4), - [SYS_PORT_MODE_INCL_XTR_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 1, 2, 12, 4), - [SYS_PORT_MODE_INCL_HDR_ERR] = REG_FIELD_ID(SYS_PORT_MODE, 0, 0, 12, 4), - [SYS_PAUSE_CFG_PAUSE_START] = REG_FIELD_ID(SYS_PAUSE_CFG, 10, 18, 12, 4), - [SYS_PAUSE_CFG_PAUSE_STOP] = REG_FIELD_ID(SYS_PAUSE_CFG, 1, 9, 12, 4), - [SYS_PAUSE_CFG_PAUSE_ENA] = REG_FIELD_ID(SYS_PAUSE_CFG, 0, 1, 12, 4), -}; - static const struct ocelot_stat_layout ocelot_stats_layout[OCELOT_NUM_STATS] = { OCELOT_COMMON_STATS, }; @@ -138,7 +80,7 @@ static int ocelot_chip_init(struct ocelot *ocelot, const struct ocelot_ops *ops) ocelot->num_mact_rows = 1024; ocelot->ops = ops; - ret = ocelot_regfields_init(ocelot, ocelot_regfields); + ret = ocelot_regfields_init(ocelot, vsc7514_regfields); if (ret) return ret; diff --git a/drivers/net/ethernet/mscc/vsc7514_regs.c b/drivers/net/ethernet/mscc/vsc7514_regs.c index 9d2d3e13cacf..123175618251 100644 --- a/drivers/net/ethernet/mscc/vsc7514_regs.c +++ b/drivers/net/ethernet/mscc/vsc7514_regs.c @@ -9,6 +9,65 @@ #include #include "ocelot.h" +const struct reg_field vsc7514_regfields[REGFIELD_MAX] = { + [ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 11, 11), + [ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 10), + [ANA_ANEVENTS_MSTI_DROP] = REG_FIELD(ANA_ANEVENTS, 27, 27), + [ANA_ANEVENTS_ACLKILL] = REG_FIELD(ANA_ANEVENTS, 26, 26), + [ANA_ANEVENTS_ACLUSED] = REG_FIELD(ANA_ANEVENTS, 25, 25), + [ANA_ANEVENTS_AUTOAGE] = REG_FIELD(ANA_ANEVENTS, 24, 24), + [ANA_ANEVENTS_VS2TTL1] = REG_FIELD(ANA_ANEVENTS, 23, 23), + [ANA_ANEVENTS_STORM_DROP] = REG_FIELD(ANA_ANEVENTS, 22, 22), + [ANA_ANEVENTS_LEARN_DROP] = REG_FIELD(ANA_ANEVENTS, 21, 21), + [ANA_ANEVENTS_AGED_ENTRY] = REG_FIELD(ANA_ANEVENTS, 20, 20), + [ANA_ANEVENTS_CPU_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 19, 19), + [ANA_ANEVENTS_AUTO_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 18, 18), + [ANA_ANEVENTS_LEARN_REMOVE] = REG_FIELD(ANA_ANEVENTS, 17, 17), + [ANA_ANEVENTS_AUTO_LEARNED] = REG_FIELD(ANA_ANEVENTS, 16, 16), + [ANA_ANEVENTS_AUTO_MOVED] = REG_FIELD(ANA_ANEVENTS, 15, 15), + [ANA_ANEVENTS_DROPPED] = REG_FIELD(ANA_ANEVENTS, 14, 14), + [ANA_ANEVENTS_CLASSIFIED_DROP] = REG_FIELD(ANA_ANEVENTS, 13, 13), + [ANA_ANEVENTS_CLASSIFIED_COPY] = REG_FIELD(ANA_ANEVENTS, 12, 12), + [ANA_ANEVENTS_VLAN_DISCARD] = REG_FIELD(ANA_ANEVENTS, 11, 11), + [ANA_ANEVENTS_FWD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 10, 10), + [ANA_ANEVENTS_MULTICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 9, 9), + [ANA_ANEVENTS_UNICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 8, 8), + [ANA_ANEVENTS_DEST_KNOWN] = REG_FIELD(ANA_ANEVENTS, 7, 7), + [ANA_ANEVENTS_BUCKET3_MATCH] = REG_FIELD(ANA_ANEVENTS, 6, 6), + [ANA_ANEVENTS_BUCKET2_MATCH] = REG_FIELD(ANA_ANEVENTS, 5, 5), + [ANA_ANEVENTS_BUCKET1_MATCH] = REG_FIELD(ANA_ANEVENTS, 4, 4), + [ANA_ANEVENTS_BUCKET0_MATCH] = REG_FIELD(ANA_ANEVENTS, 3, 3), + [ANA_ANEVENTS_CPU_OPERATION] = REG_FIELD(ANA_ANEVENTS, 2, 2), + [ANA_ANEVENTS_DMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 1, 1), + [ANA_ANEVENTS_SMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 0, 0), + [ANA_TABLES_MACACCESS_B_DOM] = REG_FIELD(ANA_TABLES_MACACCESS, 18, 18), + [ANA_TABLES_MACTINDX_BUCKET] = REG_FIELD(ANA_TABLES_MACTINDX, 10, 11), + [ANA_TABLES_MACTINDX_M_INDEX] = REG_FIELD(ANA_TABLES_MACTINDX, 0, 9), + [QSYS_TIMED_FRAME_ENTRY_TFRM_VLD] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 20, 20), + [QSYS_TIMED_FRAME_ENTRY_TFRM_FP] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 8, 19), + [QSYS_TIMED_FRAME_ENTRY_TFRM_PORTNO] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 4, 7), + [QSYS_TIMED_FRAME_ENTRY_TFRM_TM_SEL] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 1, 3), + [QSYS_TIMED_FRAME_ENTRY_TFRM_TM_T] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 0, 0), + [SYS_RESET_CFG_CORE_ENA] = REG_FIELD(SYS_RESET_CFG, 2, 2), + [SYS_RESET_CFG_MEM_ENA] = REG_FIELD(SYS_RESET_CFG, 1, 1), + [SYS_RESET_CFG_MEM_INIT] = REG_FIELD(SYS_RESET_CFG, 0, 0), + /* Replicated per number of ports (12), register size 4 per port */ + [QSYS_SWITCH_PORT_MODE_PORT_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 14, 14, 12, 4), + [QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 11, 13, 12, 4), + [QSYS_SWITCH_PORT_MODE_YEL_RSRVD] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 10, 10, 12, 4), + [QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 9, 9, 12, 4), + [QSYS_SWITCH_PORT_MODE_TX_PFC_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 1, 8, 12, 4), + [QSYS_SWITCH_PORT_MODE_TX_PFC_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 0, 0, 12, 4), + [SYS_PORT_MODE_DATA_WO_TS] = REG_FIELD_ID(SYS_PORT_MODE, 5, 6, 12, 4), + [SYS_PORT_MODE_INCL_INJ_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 3, 4, 12, 4), + [SYS_PORT_MODE_INCL_XTR_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 1, 2, 12, 4), + [SYS_PORT_MODE_INCL_HDR_ERR] = REG_FIELD_ID(SYS_PORT_MODE, 0, 0, 12, 4), + [SYS_PAUSE_CFG_PAUSE_START] = REG_FIELD_ID(SYS_PAUSE_CFG, 10, 18, 12, 4), + [SYS_PAUSE_CFG_PAUSE_STOP] = REG_FIELD_ID(SYS_PAUSE_CFG, 1, 9, 12, 4), + [SYS_PAUSE_CFG_PAUSE_ENA] = REG_FIELD_ID(SYS_PAUSE_CFG, 0, 1, 12, 4), +}; +EXPORT_SYMBOL(vsc7514_regfields); + const u32 vsc7514_ana_regmap[] = { REG(ANA_ADVLEARN, 0x009000), REG(ANA_VLANMASK, 0x009004), diff --git a/include/soc/mscc/vsc7514_regs.h b/include/soc/mscc/vsc7514_regs.h index ceee26c96959..9b40e7d00ec5 100644 --- a/include/soc/mscc/vsc7514_regs.h +++ b/include/soc/mscc/vsc7514_regs.h @@ -10,6 +10,8 @@ #include +extern const struct reg_field vsc7514_regfields[REGFIELD_MAX]; + extern const u32 vsc7514_ana_regmap[]; extern const u32 vsc7514_qs_regmap[]; extern const u32 vsc7514_qsys_regmap[]; From patchwork Sun Sep 11 20:02:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Colin Foster X-Patchwork-Id: 12973042 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 572FAC6FA8A for ; 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Miller" , Florian Fainelli , Vivien Didelot , Andrew Lunn , UNGLinuxDriver@microchip.com, Alexandre Belloni , Claudiu Manoil , Vladimir Oltean , Lee Jones Subject: [RFC v1 net-next 3/8] net: mscc: ocelot: expose stats layout definition to be used by other drivers Date: Sun, 11 Sep 2022 13:02:39 -0700 Message-Id: <20220911200244.549029-4-colin.foster@in-advantage.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220911200244.549029-1-colin.foster@in-advantage.com> References: <20220911200244.549029-1-colin.foster@in-advantage.com> X-ClientProxiedBy: MW4PR03CA0318.namprd03.prod.outlook.com (2603:10b6:303:dd::23) To MWHPR1001MB2351.namprd10.prod.outlook.com (2603:10b6:301:35::37) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: baf7a9c2-e907-46fa-86ba-08da94309e2b X-MS-TrafficTypeDiagnostic: BN0PR10MB5335:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Ld8kMVkZRWNFaseb+wsWByY4vYFk+l4gZ4u6aEryoXWTejXVLs7ZYAbMZ2HKRmL7SVMoF50V+SLX94BqDukcl3SkNgE6Ul1PZ4hL+QbaY+Dui8iVrnExQRFdBq3Fd36swrVMzUe6CrV0maP1C/xzI/xNgax1yGXgSRIt090FV9zyqxIKH9/HDj3oGlns/67RDqB22IivTI/GJ6Lg5ovsYbRL4b5MF+dv0Spo3QSNda0syKnUB/+Jfya50xrLgonnYpeJKnv8LdUcr2TVXdb5zkrMHXpo1b6r1w1LdDNEycMI8lyjNr4W1tX1Om5+mLjLn174bK2KEb/X5b/gB6RK4RIPFxfb7KPqJIxSfJjUJIpUxgZxfSvprTPEYI4EPrDj5QRVAWKmqoPEvaV4qX/29n2FSQMI7eF1SK19nrlyyWrpxTgm3fbzZyiEW6ap6K3o0//ioBg/OZtZ9/A10b6ApW3qv8BT65jY6Hzoc3BHryvZ6cKfiAbKlXSMFqtbLfulowm+p921zXgHYxSyr4zQ6zy3MN2bjoVQzWSplHfzseI2fBLjuu0beIMZAzQDiTkoU80cfnp7+Z0tcVF8X4PqRdd51QpKDDhZe2wHGEegkkiM+0qoXKBw7TYVF40AaV6gLSIKhfPgs/TqIHkP8m9C4ZpEk2XpMMcq0D9eEilGsU4y3T/nlnKrjMmVdIRiGCJYjwbNRy7X9/RWldUwsmXXFjNBvMNDhSVyNcxfIqHGnm1rTYfa8mtNrH4TDdKJuvRv3FnmdDr06BMolB57ids5BA== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:MWHPR1001MB2351.namprd10.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230016)(396003)(136003)(366004)(39830400003)(376002)(346002)(38350700002)(38100700002)(8676002)(4326008)(66946007)(36756003)(86362001)(66556008)(66476007)(2906002)(83380400001)(186003)(2616005)(6512007)(6506007)(1076003)(52116002)(478600001)(6486002)(6666004)(26005)(316002)(54906003)(44832011)(41300700001)(8936002)(5660300002)(7416002);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: qM3MtDNie9Whn5JJYU6StPeY+W3jONDHaD2AiIR3tzDpqf1UeitRz6ZlG2xEINWxhiSZbKH2ABtMfk0z5pLpkYsApCsaZMTEg5vROMvImSFPArqbNBuot1p9hd2xshl2YoE6HHE/rAQxtZb/FazcFCAC8wbGiiTQhZED7Rc0Zs9HN/oxq9CD3pCs+RykknaC4nzc28eduRB7/eDTvKhenM+1T1nBuUvWFZIyUiG9os4pIG2V8AF0BnGUmggD03qflBitFx0wuBwfpzDtRReHUSNT+Y2DOvRlUF7MJjsNW379rjQTXbWz1WPdpK4Iu9jcUsnQVzsjXveN18mzG0MvKtZef/bNRLfLL2SymJllL3gBW7oEgsMIZbswoN9V8f7l1VWV7WJbXz18WNbRY84KZ68HNewROb19rrDpSQqg4M8sUQ19TBdXrCtN7cwYYnBLhJ1I3NhvjjG6T0siN+UGjGQ3ggZlX4ejknOdEPr/9SoVstcKGSkJT6OVRFfYDIKYecr2pGbX3dcEALH45lEJnpvVZRnPZiybq5e0mp7MfCjh6KydSb1G8VVrsUX7JMmSGhmvfziOvg2Fu1dk2N4jmokDGlM387KWwoc9XSqSFcB1+BanH3TmRhw8ST34ofUmg+PKBBuPpOUyCAZsx2svOnKWCkEY3hjreLNvOCaGhBLylX/TQlyR1SjNAUg62T2wgz1ZYvSqqDwpmjZ9mJTRVridxohc0hOVUJJQBoPHeDTAETYBnjUYRWoAHESCv+enrjI8XKNM+7M1U6EUgAA9OXDxD+9hEdt5sTka75quT/mg91FwS+PZg0QzQitlIvaAJpHiewcPZr997USNMkEFUG4B3p9C408hs7NZheOsiFr8Oc0UqJtoExDgxQkgBTRF3PWeVgoyT1HJdtDbXCDRveCF7l4NWIrH7zwwo6aaqjfY1w4LmhFScTJIz92UG+cwJOJyfK8Gd+XPI5mbMGP9CUZZkG4Fit+BMeuQ9c+wAzS/kFwvUwnhoFnFUpmxqL/WyNpGlzlA0PhwMWu7dVyPQncPEp+lsV8rpisFmO0hvOprciBlOolMrqNrh8wnrz1eua2Ykz/kruUb8H49StgVCE8uF+IYZTYG9Mto2ejGZwXMdDvj/jUicQ8v6FJOW7cA4MZFAI95/bWBcInE4b0VFivzNPI+dloN7L+/j/An1o41ryOt6+LQ70cFH1MuhrVhJhUHyQlJ1qar5BmWs33VeT1BgkEbCmS1ud8udisRRyePez7tKipikuwxhGTUaQqFUJ4i1iPeO0F3MJtQHyxYW17xjY6tQVeIVP6HLlEfk/QIN1+lwr16kq30n8aDBO0biIQktas8QLmk5x3dkrCTkRecfxkWL3EpmhS4n1q3y65fcbL2kBogdvnrXRbUHjTAkL8l7hVtMjeHeyH7MyFIe33U5G9Q/PG8rFqCyIkSYQSZgI/sookk2NuG1sgkuWYjt96UyllzXLrqEQD0zoaKqnDLeqo9VBQkrsssLfm2fME4/5Y9XtAOfAbVKTKBVYNEzjhCD1wn0aNgOEBxK/3DpWT9mbu7ibfG0yFBJboaPW/edjzYXlVNuPs7T/ZkWiLQiATHovwUx6KQZnwyM3W22Q== X-OriginatorOrg: in-advantage.com X-MS-Exchange-CrossTenant-Network-Message-Id: baf7a9c2-e907-46fa-86ba-08da94309e2b X-MS-Exchange-CrossTenant-AuthSource: MWHPR1001MB2351.namprd10.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Sep 2022 20:02:56.0902 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 48e842ca-fbd8-4633-a79d-0c955a7d3aae X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: QLJgeFwxVVCipsCm7e6yPcuwc8EIwvBZF+WKd/QNgJFR03PbUNHkFhu1n+VcGLwzq0IbgEF0AKSayrV0gQOgqsbrXBPymn5T7j50Fo+VZro= X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN0PR10MB5335 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org X-Patchwork-State: RFC The ocelot_stats_layout array is common between several different chips, some of which can only be controlled externally. Export this structure so it doesn't have to be duplicated in these other drivers. Rename the structure as well, to follow the conventions of other shared resources. Signed-off-by: Colin Foster --- v1 from previous RFC: * Utilize OCELOT_COMMON_STATS --- drivers/net/ethernet/mscc/ocelot_vsc7514.c | 6 +----- drivers/net/ethernet/mscc/vsc7514_regs.c | 5 +++++ include/soc/mscc/vsc7514_regs.h | 3 +++ 3 files changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/net/ethernet/mscc/ocelot_vsc7514.c b/drivers/net/ethernet/mscc/ocelot_vsc7514.c index e9c7740f20e9..7673ed76358b 100644 --- a/drivers/net/ethernet/mscc/ocelot_vsc7514.c +++ b/drivers/net/ethernet/mscc/ocelot_vsc7514.c @@ -38,10 +38,6 @@ static const u32 *ocelot_regmap[TARGET_MAX] = { [DEV_GMII] = vsc7514_dev_gmii_regmap, }; -static const struct ocelot_stat_layout ocelot_stats_layout[OCELOT_NUM_STATS] = { - OCELOT_COMMON_STATS, -}; - static void ocelot_pll5_init(struct ocelot *ocelot) { /* Configure PLL5. This will need a proper CCF driver @@ -76,7 +72,7 @@ static int ocelot_chip_init(struct ocelot *ocelot, const struct ocelot_ops *ops) int ret; ocelot->map = ocelot_regmap; - ocelot->stats_layout = ocelot_stats_layout; + ocelot->stats_layout = vsc7514_stats_layout; ocelot->num_mact_rows = 1024; ocelot->ops = ops; diff --git a/drivers/net/ethernet/mscc/vsc7514_regs.c b/drivers/net/ethernet/mscc/vsc7514_regs.c index 123175618251..d665522e18c6 100644 --- a/drivers/net/ethernet/mscc/vsc7514_regs.c +++ b/drivers/net/ethernet/mscc/vsc7514_regs.c @@ -9,6 +9,11 @@ #include #include "ocelot.h" +const struct ocelot_stat_layout vsc7514_stats_layout[OCELOT_NUM_STATS] = { + OCELOT_COMMON_STATS, +}; +EXPORT_SYMBOL(vsc7514_stats_layout); + const struct reg_field vsc7514_regfields[REGFIELD_MAX] = { [ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 11, 11), [ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 10), diff --git a/include/soc/mscc/vsc7514_regs.h b/include/soc/mscc/vsc7514_regs.h index 9b40e7d00ec5..d2b5b6b86aff 100644 --- a/include/soc/mscc/vsc7514_regs.h +++ b/include/soc/mscc/vsc7514_regs.h @@ -8,8 +8,11 @@ #ifndef VSC7514_REGS_H #define VSC7514_REGS_H +#include #include +extern const struct ocelot_stat_layout vsc7514_stats_layout[]; + extern const struct reg_field vsc7514_regfields[REGFIELD_MAX]; extern const u32 vsc7514_ana_regmap[]; From patchwork Sun Sep 11 20:02:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Colin Foster X-Patchwork-Id: 12973044 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A0DAEC6FA83 for ; Sun, 11 Sep 2022 20:03:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229586AbiIKUD0 (ORCPT ); Sun, 11 Sep 2022 16:03:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49464 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229748AbiIKUDF (ORCPT ); Sun, 11 Sep 2022 16:03:05 -0400 Received: from NAM02-SN1-obe.outbound.protection.outlook.com (mail-sn1anam02on2095.outbound.protection.outlook.com [40.107.96.95]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 454FE27DD9; Sun, 11 Sep 2022 13:03:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=WSIIW15Be6C9yxHYs010WpYsLzk6Y50d51VpgqDodT+ayO5RHoQ4XRYgKk59WQOVg6zJJ0aESV1YoKP9YTs0RpmVkeEf5qad6E7GEqMnsH+/r6mNTRx4UzqxzhZezWKCUR32M8TUDz2qVkfTpz9w4QNQc3xDrmE/uzCg3+hMG+GCv3/zVER9UQ4iiunFXBgkmbwDpKShh9CxxCR8QIQb5ZCg+9q6mDf4osEq0ACYSb50nRuj3zI+XEnIaVEaEus17qopB89vrkxbLStvuUkXvGu6Xr7QOXiu5gd1eoZWrfdWmIuh1/9R9+hBJkd711BirdxvKq8S4EK4UYW4kyjbQA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=z5az35p9O8xlhDt6pRnLRlMQ1zJXMFlctQDBw2XWpiw=; b=ewS0d4MFraBGvamYrVZFuMdiU/j82Xq/5s3ONbYQLYSTQn2KBTfiLo2G1LUqPKrmzR5zMbi/TzuszpbwpSzc076Hge4nT6qly5vThmgTSt2i4LhqKxKpJ9c49VLAWwc6MY6bzlezgsA4dpn0vgutzCm/bXU5wvu7AZn6+SF0pXl/ybBNiPgel87I4N6E9MjMlchp45htPCfHJUGGZID5DpWeMkgZY0hM9iNs+4gg5/b6RemZflPDzUd5nzzWRqDL3RoGt8MWG1KYeBP1raVzhsagmH9G0hWhMe0cQMafVDM0rRavy0cdgvxPZm/0q2vs4VD4f0Jnz33zUk3YLeD5VQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=in-advantage.com; dmarc=pass action=none header.from=in-advantage.com; dkim=pass header.d=in-advantage.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=inadvantage.onmicrosoft.com; s=selector2-inadvantage-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=z5az35p9O8xlhDt6pRnLRlMQ1zJXMFlctQDBw2XWpiw=; b=Ow8Xtn3kKw4Ky607q0Jyw0bJ2Uo9auMpz6D5HmJ9SD1wpU8r1R3cY5LRdkj7eIqdQ3sEtI5GWl5+QJHY7OSVEmxq8OpLwVPuhtoVALJfoJ8zjSC8/aS5NQFnqeIzORC9XRcg3tR5UorajTGvfupEvVdkSDBCx8iBP+sG2cLBuMY= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=in-advantage.com; Received: from MWHPR1001MB2351.namprd10.prod.outlook.com (2603:10b6:301:35::37) by BN0PR10MB5335.namprd10.prod.outlook.com (2603:10b6:408:127::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5612.14; Sun, 11 Sep 2022 20:02:57 +0000 Received: from MWHPR1001MB2351.namprd10.prod.outlook.com ([fe80::38ee:4bfb:c7b8:72e1]) by MWHPR1001MB2351.namprd10.prod.outlook.com ([fe80::38ee:4bfb:c7b8:72e1%7]) with mapi id 15.20.5588.020; Sun, 11 Sep 2022 20:02:57 +0000 From: Colin Foster To: netdev@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Russell King , Paolo Abeni , Jakub Kicinski , Eric Dumazet , "David S. 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Export this structure so it doesn't need to be recreated. Signed-off-by: Colin Foster --- v1 from previous RFC: * No changes --- drivers/net/ethernet/mscc/ocelot_vsc7514.c | 43 --------------------- drivers/net/ethernet/mscc/vsc7514_regs.c | 44 ++++++++++++++++++++++ include/soc/mscc/vsc7514_regs.h | 1 + 3 files changed, 45 insertions(+), 43 deletions(-) diff --git a/drivers/net/ethernet/mscc/ocelot_vsc7514.c b/drivers/net/ethernet/mscc/ocelot_vsc7514.c index 7673ed76358b..6191bca7a9c4 100644 --- a/drivers/net/ethernet/mscc/ocelot_vsc7514.c +++ b/drivers/net/ethernet/mscc/ocelot_vsc7514.c @@ -161,49 +161,6 @@ static const struct ocelot_ops ocelot_ops = { .netdev_to_port = ocelot_netdev_to_port, }; -static struct vcap_props vsc7514_vcap_props[] = { - [VCAP_ES0] = { - .action_type_width = 0, - .action_table = { - [ES0_ACTION_TYPE_NORMAL] = { - .width = 73, /* HIT_STICKY not included */ - .count = 1, - }, - }, - .target = S0, - .keys = vsc7514_vcap_es0_keys, - .actions = vsc7514_vcap_es0_actions, - }, - [VCAP_IS1] = { - .action_type_width = 0, - .action_table = { - [IS1_ACTION_TYPE_NORMAL] = { - .width = 78, /* HIT_STICKY not included */ - .count = 4, - }, - }, - .target = S1, - .keys = vsc7514_vcap_is1_keys, - .actions = vsc7514_vcap_is1_actions, - }, - [VCAP_IS2] = { - .action_type_width = 1, - .action_table = { - [IS2_ACTION_TYPE_NORMAL] = { - .width = 49, - .count = 2 - }, - [IS2_ACTION_TYPE_SMAC_SIP] = { - .width = 6, - .count = 4 - }, - }, - .target = S2, - .keys = vsc7514_vcap_is2_keys, - .actions = vsc7514_vcap_is2_actions, - }, -}; - static struct ptp_clock_info ocelot_ptp_clock_info = { .owner = THIS_MODULE, .name = "ocelot ptp", diff --git a/drivers/net/ethernet/mscc/vsc7514_regs.c b/drivers/net/ethernet/mscc/vsc7514_regs.c index d665522e18c6..c943da4dd1f1 100644 --- a/drivers/net/ethernet/mscc/vsc7514_regs.c +++ b/drivers/net/ethernet/mscc/vsc7514_regs.c @@ -644,3 +644,47 @@ const struct vcap_field vsc7514_vcap_is2_actions[] = { [VCAP_IS2_ACT_HIT_CNT] = { 49, 32 }, }; EXPORT_SYMBOL(vsc7514_vcap_is2_actions); + +struct vcap_props vsc7514_vcap_props[] = { + [VCAP_ES0] = { + .action_type_width = 0, + .action_table = { + [ES0_ACTION_TYPE_NORMAL] = { + .width = 73, /* HIT_STICKY not included */ + .count = 1, + }, + }, + .target = S0, + .keys = vsc7514_vcap_es0_keys, + .actions = vsc7514_vcap_es0_actions, + }, + [VCAP_IS1] = { + .action_type_width = 0, + .action_table = { + [IS1_ACTION_TYPE_NORMAL] = { + .width = 78, /* HIT_STICKY not included */ + .count = 4, + }, + }, + .target = S1, + .keys = vsc7514_vcap_is1_keys, + .actions = vsc7514_vcap_is1_actions, + }, + [VCAP_IS2] = { + .action_type_width = 1, + .action_table = { + [IS2_ACTION_TYPE_NORMAL] = { + .width = 49, + .count = 2 + }, + [IS2_ACTION_TYPE_SMAC_SIP] = { + .width = 6, + .count = 4 + }, + }, + .target = S2, + .keys = vsc7514_vcap_is2_keys, + .actions = vsc7514_vcap_is2_actions, + }, +}; +EXPORT_SYMBOL(vsc7514_vcap_props); diff --git a/include/soc/mscc/vsc7514_regs.h b/include/soc/mscc/vsc7514_regs.h index d2b5b6b86aff..a939849efd91 100644 --- a/include/soc/mscc/vsc7514_regs.h +++ b/include/soc/mscc/vsc7514_regs.h @@ -12,6 +12,7 @@ #include extern const struct ocelot_stat_layout vsc7514_stats_layout[]; +extern struct vcap_props vsc7514_vcap_props[]; extern const struct reg_field vsc7514_regfields[REGFIELD_MAX]; From patchwork Sun Sep 11 20:02:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Colin Foster X-Patchwork-Id: 12973046 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B5CEEC6FA83 for ; Sun, 11 Sep 2022 20:03:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229820AbiIKUDc (ORCPT ); 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Other devices (VSC7512 for example) don't require the same quirks, so they need to be configured on a per-device basis. Signed-off-by: Colin Foster Reviewed-by: Vladimir Oltean --- v1 from previous RFC: * No changes --- drivers/net/dsa/ocelot/felix.c | 7 +++++-- drivers/net/dsa/ocelot/felix.h | 1 + drivers/net/dsa/ocelot/felix_vsc9959.c | 1 + drivers/net/dsa/ocelot/seville_vsc9953.c | 1 + 4 files changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/net/dsa/ocelot/felix.c b/drivers/net/dsa/ocelot/felix.c index c73ef5f7aa64..95a5c5d0815c 100644 --- a/drivers/net/dsa/ocelot/felix.c +++ b/drivers/net/dsa/ocelot/felix.c @@ -990,9 +990,12 @@ static void felix_phylink_mac_link_down(struct dsa_switch *ds, int port, phy_interface_t interface) { struct ocelot *ocelot = ds->priv; + struct felix *felix; + + felix = ocelot_to_felix(ocelot); ocelot_phylink_mac_link_down(ocelot, port, link_an_mode, interface, - FELIX_MAC_QUIRKS); + felix->info->quirks); } static void felix_phylink_mac_link_up(struct dsa_switch *ds, int port, @@ -1007,7 +1010,7 @@ static void felix_phylink_mac_link_up(struct dsa_switch *ds, int port, ocelot_phylink_mac_link_up(ocelot, port, phydev, link_an_mode, interface, speed, duplex, tx_pause, rx_pause, - FELIX_MAC_QUIRKS); + felix->info->quirks); if (felix->info->port_sched_speed_set) felix->info->port_sched_speed_set(ocelot, port, speed); diff --git a/drivers/net/dsa/ocelot/felix.h b/drivers/net/dsa/ocelot/felix.h index deb8dde1fc19..12a1c03bfeb8 100644 --- a/drivers/net/dsa/ocelot/felix.h +++ b/drivers/net/dsa/ocelot/felix.h @@ -33,6 +33,7 @@ struct felix_info { u16 vcap_pol_base2; u16 vcap_pol_max2; const struct ptp_clock_info *ptp_caps; + unsigned long quirks; /* Some Ocelot switches are integrated into the SoC without the * extraction IRQ line connected to the ARM GIC. By enabling this diff --git a/drivers/net/dsa/ocelot/felix_vsc9959.c b/drivers/net/dsa/ocelot/felix_vsc9959.c index 459288d6222c..4adb109c2e77 100644 --- a/drivers/net/dsa/ocelot/felix_vsc9959.c +++ b/drivers/net/dsa/ocelot/felix_vsc9959.c @@ -2605,6 +2605,7 @@ static const struct felix_info felix_info_vsc9959 = { .num_mact_rows = 2048, .num_ports = VSC9959_NUM_PORTS, .num_tx_queues = OCELOT_NUM_TC, + .quirks = FELIX_MAC_QUIRKS, .quirk_no_xtr_irq = true, .ptp_caps = &vsc9959_ptp_caps, .mdio_bus_alloc = vsc9959_mdio_bus_alloc, diff --git a/drivers/net/dsa/ocelot/seville_vsc9953.c b/drivers/net/dsa/ocelot/seville_vsc9953.c index 3ce1cd1a8d4a..ba71e5fa5921 100644 --- a/drivers/net/dsa/ocelot/seville_vsc9953.c +++ b/drivers/net/dsa/ocelot/seville_vsc9953.c @@ -1071,6 +1071,7 @@ static const struct felix_info seville_info_vsc9953 = { .vcap_pol_max = VSC9953_VCAP_POLICER_MAX, .vcap_pol_base2 = VSC9953_VCAP_POLICER_BASE2, .vcap_pol_max2 = VSC9953_VCAP_POLICER_MAX2, + .quirks = FELIX_MAC_QUIRKS, .num_mact_rows = 2048, .num_ports = VSC9953_NUM_PORTS, .num_tx_queues = OCELOT_NUM_TC, From patchwork Sun Sep 11 20:02:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Colin Foster X-Patchwork-Id: 12973045 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E15F2ECAAD3 for ; Sun, 11 Sep 2022 20:03:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229799AbiIKUDa (ORCPT ); Sun, 11 Sep 2022 16:03:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49528 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229754AbiIKUDH (ORCPT ); Sun, 11 Sep 2022 16:03:07 -0400 Received: from NAM02-SN1-obe.outbound.protection.outlook.com (mail-sn1anam02on2095.outbound.protection.outlook.com [40.107.96.95]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DF33027FC9; Sun, 11 Sep 2022 13:03:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Aq4TlOSt8aiK6IV3VVuK/66Ayqo/Y7B2lbHzZkFxFVFQvFGi6p1JAX+jxRV0i44Lk24jYOx61CYpK+EmiR4O9iTt7dqAld5H8QDiigeQMRREqjZ4P59t0nIU/OIniucE4vqSqkWEyWh/wAZ4vRJqu5wKywlRSB/meoRxyJI5054adRmePIvlovonj/ZNKazmm0rVZTeno/oZP6JHsACJ/SNYeR9lpLCySF/5OWgVKKnamIKD9y+f7iYKTNBth5IrZ1aKlq3MEyq1Q03muU2aHpnbV9AkloNJHP1cpST0EPOL9aCFSwftfpn5l2EsD8ZqQpq9VRuMIolbd4R8HDCc2Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=dLzBU2dn6Sa+vdvgNRgichrqThsW4jBbOVCTX5P3wD0=; b=hOYfzFDfOEPqWJhzruluU+Wi1t03xr2nyfxBSkITXbIMHEG6oDdz1wGa0u65I7NPBrcwaXGDoYnTSqnhp1kuaUvdrGg/JFCakqlH0yia+rjTtBdcyousFNdnFor3ZNyMMvbnOyMnBIz9538zW1U/WRxypGpGGoYdJsI+YwlXdRQuKPuqLZsjJUkJEHJbsyFuGcBtiF6O37RdODMYimgVXE6BM1zDGVjYn7Ct48P879iawedndxu5vM2U8rWR5TeNYfKVNkrf39NH8L3eeqJoI6bruqBYI/LSxLDwPye2LqHwmQBCtn8siYiRomBCDpXKMHEp0GSv+tXLamXItSANKA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=in-advantage.com; dmarc=pass action=none header.from=in-advantage.com; dkim=pass header.d=in-advantage.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=inadvantage.onmicrosoft.com; s=selector2-inadvantage-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=dLzBU2dn6Sa+vdvgNRgichrqThsW4jBbOVCTX5P3wD0=; b=UE/27i+iLdc4d9pPmkykaCfs+j/veGnzFJARuGtyWRpqcy/1KzJ6l7nb4DSB41i0/QLsJnBlPXxNpZCVELvaHnIxERtwsbnrm51zuMUh//fzZZ6Urt4edvM7qxE9q/bl/z8HZAJccT98DAG6K9X1eKj3koIiVbhhCjZlxh06G0A= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=in-advantage.com; Received: from MWHPR1001MB2351.namprd10.prod.outlook.com (2603:10b6:301:35::37) by BN0PR10MB5335.namprd10.prod.outlook.com (2603:10b6:408:127::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5612.14; Sun, 11 Sep 2022 20:02:59 +0000 Received: from MWHPR1001MB2351.namprd10.prod.outlook.com ([fe80::38ee:4bfb:c7b8:72e1]) by MWHPR1001MB2351.namprd10.prod.outlook.com ([fe80::38ee:4bfb:c7b8:72e1%7]) with mapi id 15.20.5588.020; Sun, 11 Sep 2022 20:02:59 +0000 From: Colin Foster To: netdev@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Russell King , Paolo Abeni , Jakub Kicinski , Eric Dumazet , "David S. Miller" , Florian Fainelli , Vivien Didelot , Andrew Lunn , UNGLinuxDriver@microchip.com, Alexandre Belloni , Claudiu Manoil , Vladimir Oltean , Lee Jones Subject: [RFC v1 net-next 6/8] net: dsa: felix: populate mac_capabilities for all ports Date: Sun, 11 Sep 2022 13:02:42 -0700 Message-Id: <20220911200244.549029-7-colin.foster@in-advantage.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220911200244.549029-1-colin.foster@in-advantage.com> References: <20220911200244.549029-1-colin.foster@in-advantage.com> X-ClientProxiedBy: MW4PR03CA0318.namprd03.prod.outlook.com (2603:10b6:303:dd::23) To MWHPR1001MB2351.namprd10.prod.outlook.com (2603:10b6:301:35::37) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 5eacb02b-e21c-485c-648d-08da94309f10 X-MS-TrafficTypeDiagnostic: BN0PR10MB5335:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: +b+L7yLVTA3PlQy4cE653FTr3KEiErEeON8JdleANCkPihOUZmiOdvFQI59zjmHrM0D6IsdyQxLr/T+Tm6LmgkYi4EHpFK9EMKAGDrvnBm0jQyRcBm3cnRES0uqvTraw8ZBJpPBgaD2ACTcReJntq4807iMguHZlTRWtJWvf0AN9GpMXuH0AgphLcN4BYr9yrhkaveEBlIJnx3gsIegXFGWLH9ezYbEzRiQvxiPku/BvaBXcDmpdOiplWs6pAvuJJlSZDbiIP+TMXj7GGATMvUM1jB8MkqIBKpP6oOrsIO1s2/gPM/W5OFVX6b6IXrUgWl1G/3i9v7ViwXV2LjzmcZTxzXy5pRd9BSmc1kZT/GjG22V5d64AIfzt8FjeqPrIUs59rvjuyoCpS9sVaiYKEmpzqowFxjdgwd3ju/FmE74iXgb5/2sxgvqJ9bJ2jWEIGgkgt6x3zYtjoHIX7GKQfRQv9EjpxWujqInjAjIkRy4jiGRBTPhThRvfM/fUWsQE0fKsCrKQsmpeRYivVoaFng/YmNPNBOe51bbH5ii7KVcNVO0UC+D4/mF72kJijb15Y5Xi+i6NkgNWA316yeuO44jFQ9/2MHkUiEu1zBOxeeBWTWYVE1nUQ3RLZ7C2VbRDwMT4NS7wPMnnY5vnZcUh/XNFYocyBKlvM9nAJfx3jNVgbiLTJuV6E6VK+W0E26EcC9DQ2oKiP0ItAfDyM8I4S9SugtaEzB3ql5DjeQW3o0vIqkZWvo1BV9zV8uCDI21BvwB6hG0TQman88lpF2Q3EQ== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:MWHPR1001MB2351.namprd10.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230016)(396003)(136003)(366004)(39830400003)(376002)(346002)(38350700002)(38100700002)(8676002)(4326008)(66946007)(36756003)(86362001)(66556008)(66476007)(2906002)(83380400001)(186003)(2616005)(6512007)(6506007)(1076003)(52116002)(478600001)(6486002)(6666004)(26005)(316002)(54906003)(4744005)(44832011)(41300700001)(8936002)(5660300002)(7416002);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 8GT62Il9qja0vOQCC3bil2WAsBpgbRgd/AvUm5yW7/ASw9OGOk9xddKSi7IJap0/MaO7IWWXsqdCF/xXuqfW4gw8UkjGVdYobI3QCWVSDqWftASVX9pkKWnhNc7CKSzYDnBigDWBLdo9TR2H49kZNXEoiNDFFygnc3yNu6QyiU4JOX9Atn4vZs/Zvcuuj/hNPMNbyX/cpMIIcWCx7aM+9thFIecuePHfKedTaFPKeSnf7piAQCm50lrS9ki3+WYTVtScbAOZb+tp/eUICjFkdjaNO4XHD3e7GfUwtoefYW+P0kjN1baXHZebWxRBX0uumFq/cQiemqQ8iz8F2Rx0wttrTaQ78p89PzljA9sMcysyGd8raFDofx3TrnWdV6MQWygjWdWy0lQHWCApQkvXEYosjPfzTKaKlpSnSKeCzxFF1dG9mmRhROoTC/MXugoFBn+yjgHHspusLGN+wOFwJoMzvswmh/jqZkTn3HMgT15i8sv5EkuOH0K1SfXeZAGhPl/FCN2DPqgQsCQvX8m99bVXRQMrDL5HHxoJP1zel+nfQqDBCYx1ifQwzmH+0riCnF74kTHharqdGyTUqsnykdcPJxEsP/QSAJB+Jvg1J4HpVMcLWEGa780TILn1OU0AoTviahrq04S3acP3B5SBaY02WrjTTHE9gBbbXlhXyr699VMiTVrEq2PF4mHVnsRRe8zGoilSIurpT6ms+4I44WuBYz3kDTN5OhnoJdCtkuOKYHgGWCppYVDaeWxw+t+7+btsxMvmb4HBpK81BzZotVjNgqGLAdJXU0W+LgcxHfmv1eZEINnfZ3xNnI5Eo6sju4hrifDhI/wG5BhI3zKMGrHGOn93vSno/H3HnvjsgPI4DZ6NkElZ/m2Mani7HAX8EPENSxO8Dt2yVYfoPJwwhBGmo0xTgTF6imdJ1ejz/8ASsxFZuQ/VHsgyGtbt3UVqD8cdX2a4phzx3dSoorqvB/ef9seijnQkp/WtJFNNBgo1i0+DCZW/wEt8sNLLEMy2vsPP88GW3QLSSFVY6wYFTm2Lgmc/XuyqsMTIZzgKh2yjExW5AC9D9BCyAa/dVuAorhLeUYiQvtcCct4mduqCpbyaG9CsVPCLmFUgt65R+od7LiKJqHkm18BhvUF8W9l1IbSmgFSsPgXzh12cQV/jLu4G6Px+22SqAwSUF5n8myTtQxU5kOox2rlb/l90xkKCwrLG44gyXFPc4KNx2e4HHG+QzC51hyw8wnkqMF6fuZJSzjWhJ6Wbrbffp0lxvBfIbZ/XC9IxWWzmMPNRrL8R2dih1KVjM6eNOScDWDK7oHIfcLuer6z0QPZDLaptX1sTUTPVgjp/GOEvSNrwa8x3nZ68kC5t7OPmQNge831yjAyX5x0kYxxju+lQHyt1KhT3rED8Eo1Dj0nHJq7hMuqCAF/WNBe3EhqUv40Ef1oJQANO3UPlu1wxyRuRnujBPfwnH1eo+/Cryy91PIxFQgBHW7hAyYGm9kggLXYeXGNfMeHhIMZZ4of6qsU8xCCMMcaOH+aULYXg9qXs1K2VrkVU8puYHJkZ0fw9DVyPkwMZiQ7dv0nqz4t6J6aJY/kuuSoFElm2PuWLlDBz5jOhTHz4yg== X-OriginatorOrg: in-advantage.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5eacb02b-e21c-485c-648d-08da94309f10 X-MS-Exchange-CrossTenant-AuthSource: MWHPR1001MB2351.namprd10.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Sep 2022 20:02:57.5901 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 48e842ca-fbd8-4633-a79d-0c955a7d3aae X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: PiWjnK30hWU5kETeR2rm4SPeoa9D7QO1OZ+0C1djtkW3Ckw4iv4P71wyRnW9aLsSb3i1MThrYPV61AlVuTBLVKhRgWHDENBdFo6EC8WMsNw= X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN0PR10MB5335 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org X-Patchwork-State: RFC phylink_generic_validate() requires that mac_capabilities is correctly populated. While no existing drivers have used phylink_generic_validate(), the ocelot_ext.c driver will. Populate this element so the use of existing functions is possible. Signed-off-by: Colin Foster --- v1 from previous RFC: * New patch --- drivers/net/dsa/ocelot/felix.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/net/dsa/ocelot/felix.c b/drivers/net/dsa/ocelot/felix.c index 95a5c5d0815c..201bf3bdd67d 100644 --- a/drivers/net/dsa/ocelot/felix.c +++ b/drivers/net/dsa/ocelot/felix.c @@ -958,6 +958,9 @@ static void felix_phylink_get_caps(struct dsa_switch *ds, int port, __set_bit(ocelot->ports[port]->phy_mode, config->supported_interfaces); + + config->mac_capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE | MAC_10 | + MAC_100 | MAC_1000FD | MAC_2500FD; } static void felix_phylink_validate(struct dsa_switch *ds, int port, From patchwork Sun Sep 11 20:02:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Colin Foster X-Patchwork-Id: 12973048 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 189B8C6FA86 for ; Sun, 11 Sep 2022 20:03:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229846AbiIKUDi (ORCPT ); Sun, 11 Sep 2022 16:03:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50004 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229776AbiIKUDY (ORCPT ); Sun, 11 Sep 2022 16:03:24 -0400 Received: from NAM02-SN1-obe.outbound.protection.outlook.com (mail-sn1anam02on2095.outbound.protection.outlook.com [40.107.96.95]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 53D0827FEE; Sun, 11 Sep 2022 13:03:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=F4Dzs9PN0poK2bdW1Lizgd1NgG2BpzMKikJxr+0KycXByOd3YmR2c/pb24eIchERXmjhWWXxr5z6IU4xXDPheHb0/aHSsmG0sG55e/PFSm2XLHF88yaUykaGu3aUNU1UT/caaPNCTIf/273+nx1BbT9wZzoB2S4mpQAEtI6Sar0t9x1R3TUTXe6cGmHUVL0PrfO6Cw4eyofX+Brr2lnEgKZXqL9jfGhFV1Gc1iB04fmFxuSQxD5QWUZZEtOZYiNmvcRF8l5UNiPac2ZJJDfNVhEElQl8NlOu7IJHWW/quK7onlh7gwOKKgEdWGJ8mNJqIZHRd564Bhjx09NzyCNaJw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=toccuXRpC9GIrGKziX5sBEWXnnDtbF9gLspgZwGNLTk=; b=j0iGE08zlFDKuHPmGhT3uFOw8DsH6N5YTZgvXg4rJAYQsj07LvzaF4qW/ceP/j/AVhEgMatzt0+lwQMWozhck6DAgiGmh2eT5jnz5KDvzOVbElwiIk3fn05G2TEpe8gBTdx5kVAZx7P3cjTWiZWPIYW+D/kduX8tDeVfpnVa3tnTL7M/YWUeYjfmF90bYrRoUiwIf3S9yLqr8/qol2U2q6avuuFvH2qyiNxyXOfhE3Z+BGQWBKQRELOkwWX9h1ipugCoX2TdsByV05lXV+rrtYQlv1wzQKc4a32sdT8+J6jD4bKuGbLR+8WkMYG0aeLMa4048lDxmbR8CgXT6P4byA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=in-advantage.com; dmarc=pass action=none header.from=in-advantage.com; dkim=pass header.d=in-advantage.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=inadvantage.onmicrosoft.com; s=selector2-inadvantage-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=toccuXRpC9GIrGKziX5sBEWXnnDtbF9gLspgZwGNLTk=; b=VYhbE/SsIm0tfOBBlvnBLUvwvKa0/WiP611T5e5MFNTCedaqFBpF01s0mrlw3kj2lV7wWXU4PQZyicdK2cGUcu8ZQhSSPYMW6BcoIbOIq/1XZO4U08mCmHs9+VVcFZDtQxRBGF+dRsioVDY/CPKPb2epW+VgCKv4E9mkBKy114g= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=in-advantage.com; Received: from MWHPR1001MB2351.namprd10.prod.outlook.com (2603:10b6:301:35::37) by BN0PR10MB5335.namprd10.prod.outlook.com (2603:10b6:408:127::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5612.14; Sun, 11 Sep 2022 20:02:59 +0000 Received: from MWHPR1001MB2351.namprd10.prod.outlook.com ([fe80::38ee:4bfb:c7b8:72e1]) by MWHPR1001MB2351.namprd10.prod.outlook.com ([fe80::38ee:4bfb:c7b8:72e1%7]) with mapi id 15.20.5588.020; Sun, 11 Sep 2022 20:02:59 +0000 From: Colin Foster To: netdev@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Russell King , Paolo Abeni , Jakub Kicinski , Eric Dumazet , "David S. Miller" , Florian Fainelli , Vivien Didelot , Andrew Lunn , UNGLinuxDriver@microchip.com, Alexandre Belloni , Claudiu Manoil , Vladimir Oltean , Lee Jones Subject: [RFC v1 net-next 7/8] mfd: ocelot: add regmaps for ocelot_ext Date: Sun, 11 Sep 2022 13:02:43 -0700 Message-Id: <20220911200244.549029-8-colin.foster@in-advantage.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220911200244.549029-1-colin.foster@in-advantage.com> References: <20220911200244.549029-1-colin.foster@in-advantage.com> X-ClientProxiedBy: MW4PR03CA0318.namprd03.prod.outlook.com (2603:10b6:303:dd::23) To MWHPR1001MB2351.namprd10.prod.outlook.com (2603:10b6:301:35::37) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 411269ed-8e74-4608-ae74-08da94309f5c X-MS-TrafficTypeDiagnostic: BN0PR10MB5335:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: oZuCdRCmVBBXTgR0uWD7xyRAO40MryP/7D7XQsKb7gLKyghDXnvLo2jDtqS7sYgphJwf82Sj59I5B+6jy7PGiB7GN6wRf5nQ74E/EUCbXkrMfs+cHiPPyA51QvapR6+ShCEZRWm3qaEJVgPsPjIBgy4d3rMD4m+HfGTuPBuOLUv8RoUn9EG0uvQM1cnoNpf4U9rdJ1IxRWtndh+w7u7hFpyOJvEpeEg9Obml2JQoepmIAV4SWkebptod1Jw+IlxypjeQns1aFm3Hb1ZDKRMxpdosjy5uyfM9+QLXgsvprZMYj4hQ7xWLbaBxtJ8gQJRnL9/01Z+ooBHeUG73HqiBvsczRpXX2zbdKTwIXeUmUVnwXQntw5hpk0kagvUfAU0Q/ugbH9R87JxC8z2ZnVWHW2NE7lgQ5BvHOnoIiORKT5azZD/GHQ8ouRnTY4i+Xl3Mi9P7kheVMLa4+RG7mdG5pviONQPSR4Bwg7XinNzv0CkMaYA4/RkP7GhEB8bJfJ7FpPf97ja4illAHUDcKAa3ujlpiZueoivjts7jstUgEA3OamohaWgPHr/DhZLyQQAcxXpO52YhYgjG16Hu1tIi0rav/fVekDjyYWTfrIpJxNm+ZZvlSTSe+fbzND/szDW0XLFZ70hjcLF4cgRZ4yPJVNPGsjAKgrJuHZVIymUHY4iKatZ54bm1iQX/k8IUGeFy9n6+k82e5ABChhSlvWEr5MW0L7KRCUY7v59lgmTiXul5gWDXyB04jic1sa5v+YdHMtdlJKTL8cZytj0HTI5XOQ== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:MWHPR1001MB2351.namprd10.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230016)(396003)(136003)(366004)(39830400003)(376002)(346002)(38350700002)(38100700002)(8676002)(4326008)(66946007)(36756003)(86362001)(66556008)(66476007)(2906002)(83380400001)(186003)(2616005)(6512007)(6506007)(1076003)(52116002)(478600001)(6486002)(6666004)(26005)(316002)(54906003)(44832011)(41300700001)(8936002)(5660300002)(7416002);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: nZA4ZNXE/GHMPNx1Ms7D/onahZAodHQzvE+hcEzybbuUL9QdbPbLoVJAuKCc+SFOl6kQczvNKljlMz+JX+cXK1yT1OsXoEJ82LhAc11bKs/NMKkQzLcX7Q1VSTYhkX4jP82rlzGVUKcytZ22geARyikAdk/7+TO1GmnJ9xMIL0G3cV83IEXSirJNIaifosvpYfnJed42PUmInRz1mqcNF7175wVRBxMP3VbfjlKSNoAFL5kpRK1Iv+/rnJdypo+PtwLpF1OyVkw24JEfEpaBxKzfl+BKPS7M9ME78Phjojrw0shO1ShZGysX5Ji6Iq7OW+VIWFamMWYjXVZvZXFDddpf4XkqhR1VjYAmWBo72a4N9x+/TR0d6eKon31ricDZueAI7SoJJtK34wohraYueBWx/iD2FvEIg9R7fukgcpsFuexe7hYADCCu27FIkE1+IhUfexncpvE7No0/1LvRxFUD8SJNuuBaFk/WwWqb4kU6mv8AkWSWD4TY0F5kmroklQ0pPvg+v6z4sDKl/6gFZOaEqQkCjSdVJN/yeJKEwn6ZQBy/AxqxBU6nwxV0vnh/YeHhpKj9jbtFltLQeNlhbCWgG3CoqshVuR1h80n9rjHSZ+kxG+dZltq9vuoC0JO5w7dOHlVvB3xevE9/m+Vq9T3NUQmDYq7M93nvm0ZJg+JbB4Ig20SeEua1LhhUM5iX4aTZIbanguPdO0A0XFVt/ksAArxlyBnwYOrLG3SpwF8kFYodYo6b4mB3SE8WFAy3TQuGq64PRQQ2B/yIzMV6CQFXwD2kGR3pK0myazZlPyn+9KyKxBcssewDYEqFBSsnRbI1SiOrJYUEYCMqZ50uMUWuKojunDvXxaAHW1e3GSYT1cgXizrsz5QYzZcOOPtq5CAKyvwiBINlAfJOZf+Ke7J0CBuMEj7kMed+Safnm4rJ5Zrbu1qgQGGPWeMmOdo/L5cwPZMo1S3HojAMws2B17eZ1p/paM8dzePRZMXfxHsuckYviGtJbZiz5E0dLnJ/e3XpXu7jbZxrDZYnKkVlLfgtPRE/DRlP2SrkcxzoC8h+WfVTFsWbfi/wsW9LZSNs25PIsJcJ23idnwyzcytCnSpI8xtUEk1yT9JqSwl6Vfghn546K3ZBYWiKMDTiRNHuP0Z8NKmFGZUB9B30bYyzpRi8+Dwf+BdvinBOFY4e3ZHiArHqk+Wc90xoi+Wv/4O6m+h/HG7dWGzOGtdmtJRbR9aBsyhIMTg9v3Q0qsjqRXzeA3A9uOzYzmwv0kQ8v71QK7iUQyXRHYLd4XClVjoO/gSJGqF5W5eqw6PBIEsG6Cq9Jg2OiRK4bf9C409XUMKD8E1YV5XSrypYJwNQt6kpkVvRYzY1H4OL9b3hlaEP8hQWiVfkNpz+iSqsldg8YBoc391+NcUOGUQwKPk4do2M273PkYYukoj3jkoDTyDwQGmFJBi60M2toJchWxv4DR0Q2OY22lL2ll4P3ILDQ2cp3z8OHvTL9SaLNd3UBK5GWf4LmrvSpzW3KMBTyxHdJS9stBycwNYOR+c/ET8CONKAz8YwybN2kWeRzwc33SE3xN2vKE5i1YNz1n3TzlWdNaOSBAxkuk53XenhUWFx5IwmxQ== X-OriginatorOrg: in-advantage.com X-MS-Exchange-CrossTenant-Network-Message-Id: 411269ed-8e74-4608-ae74-08da94309f5c X-MS-Exchange-CrossTenant-AuthSource: MWHPR1001MB2351.namprd10.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Sep 2022 20:02:58.0901 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 48e842ca-fbd8-4633-a79d-0c955a7d3aae X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 2mZWWhUm8uZbRC6cESMlZK0/660TCP5rdXT6Ykc+PI67i82EOwjVyNJQK+qGDgzdQSqrzdPGlBoIq+4ncyZaUa0HqsLKVVLqXjRujSTbpOk= X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN0PR10MB5335 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org X-Patchwork-State: RFC The Ocelot switch core driver relies heavily on a fixed array of resources for both ports and peripherals. This is in contrast to existing peripherals - pinctrl for example - which have a one-to-one mapping of driver <> resource. As such, these regmaps must be created differently so that enumeration-based offsets are preserved. Register the regmaps to the core MFD device unconditionally so they can be referenced by the Ocelot switch / Felix DSA systems. Signed-off-by: Colin Foster --- v1 from previous RFC: * New patch --- drivers/mfd/ocelot-core.c | 88 +++++++++++++++++++++++++++++++++++--- include/linux/mfd/ocelot.h | 5 +++ 2 files changed, 88 insertions(+), 5 deletions(-) diff --git a/drivers/mfd/ocelot-core.c b/drivers/mfd/ocelot-core.c index 1816d52c65c5..aa7fa21b354c 100644 --- a/drivers/mfd/ocelot-core.c +++ b/drivers/mfd/ocelot-core.c @@ -34,16 +34,55 @@ #define VSC7512_MIIM0_RES_START 0x7107009c #define VSC7512_MIIM1_RES_START 0x710700c0 -#define VSC7512_MIIM_RES_SIZE 0x024 +#define VSC7512_MIIM_RES_SIZE 0x00000024 #define VSC7512_PHY_RES_START 0x710700f0 -#define VSC7512_PHY_RES_SIZE 0x004 +#define VSC7512_PHY_RES_SIZE 0x00000004 #define VSC7512_GPIO_RES_START 0x71070034 -#define VSC7512_GPIO_RES_SIZE 0x06c +#define VSC7512_GPIO_RES_SIZE 0x0000006c #define VSC7512_SIO_CTRL_RES_START 0x710700f8 -#define VSC7512_SIO_CTRL_RES_SIZE 0x100 +#define VSC7512_SIO_CTRL_RES_SIZE 0x00000100 + +#define VSC7512_HSIO_RES_START 0x710d0000 +#define VSC7512_HSIO_RES_SIZE 0x00000128 + +#define VSC7512_ANA_RES_START 0x71880000 +#define VSC7512_ANA_RES_SIZE 0x00010000 + +#define VSC7512_QS_RES_START 0x71080000 +#define VSC7512_QS_RES_SIZE 0x00000100 + +#define VSC7512_QSYS_RES_START 0x71800000 +#define VSC7512_QSYS_RES_SIZE 0x00200000 + +#define VSC7512_REW_RES_START 0x71030000 +#define VSC7512_REW_RES_SIZE 0x00010000 + +#define VSC7512_SYS_RES_START 0x71010000 +#define VSC7512_SYS_RES_SIZE 0x00010000 + +#define VSC7512_S0_RES_START 0x71040000 +#define VSC7512_S1_RES_START 0x71050000 +#define VSC7512_S2_RES_START 0x71060000 +#define VSC7512_S_RES_SIZE 0x00000400 + +#define VSC7512_GCB_RES_START 0x71070000 +#define VSC7512_GCB_RES_SIZE 0x0000022c + +#define VSC7512_PORT_0_RES_START 0x711e0000 +#define VSC7512_PORT_1_RES_START 0x711f0000 +#define VSC7512_PORT_2_RES_START 0x71200000 +#define VSC7512_PORT_3_RES_START 0x71210000 +#define VSC7512_PORT_4_RES_START 0x71220000 +#define VSC7512_PORT_5_RES_START 0x71230000 +#define VSC7512_PORT_6_RES_START 0x71240000 +#define VSC7512_PORT_7_RES_START 0x71250000 +#define VSC7512_PORT_8_RES_START 0x71260000 +#define VSC7512_PORT_9_RES_START 0x71270000 +#define VSC7512_PORT_10_RES_START 0x71280000 +#define VSC7512_PORT_RES_SIZE 0x00010000 #define VSC7512_GCB_RST_SLEEP_US 100 #define VSC7512_GCB_RST_TIMEOUT_US 100000 @@ -96,6 +135,34 @@ static const struct resource vsc7512_sgpio_resources[] = { DEFINE_RES_REG_NAMED(VSC7512_SIO_CTRL_RES_START, VSC7512_SIO_CTRL_RES_SIZE, "gcb_sio"), }; +const struct resource vsc7512_target_io_res[TARGET_MAX] = { + [ANA] = DEFINE_RES_REG_NAMED(VSC7512_ANA_RES_START, VSC7512_ANA_RES_SIZE, "ana"), + [QS] = DEFINE_RES_REG_NAMED(VSC7512_QS_RES_START, VSC7512_QS_RES_SIZE, "qs"), + [QSYS] = DEFINE_RES_REG_NAMED(VSC7512_QSYS_RES_START, VSC7512_QSYS_RES_SIZE, "qsys"), + [REW] = DEFINE_RES_REG_NAMED(VSC7512_REW_RES_START, VSC7512_REW_RES_SIZE, "rew"), + [SYS] = DEFINE_RES_REG_NAMED(VSC7512_SYS_RES_START, VSC7512_SYS_RES_SIZE, "sys"), + [S0] = DEFINE_RES_REG_NAMED(VSC7512_S0_RES_START, VSC7512_S_RES_SIZE, "s0"), + [S1] = DEFINE_RES_REG_NAMED(VSC7512_S1_RES_START, VSC7512_S_RES_SIZE, "s1"), + [S2] = DEFINE_RES_REG_NAMED(VSC7512_S2_RES_START, VSC7512_S_RES_SIZE, "s2"), + [GCB] = DEFINE_RES_REG_NAMED(VSC7512_GCB_RES_START, VSC7512_GCB_RES_SIZE, "devcpu_gcb"), + [HSIO] = DEFINE_RES_REG_NAMED(VSC7512_HSIO_RES_START, VSC7512_HSIO_RES_SIZE, "hsio"), +}; + +const struct resource vsc7512_port_io_res[] = { + DEFINE_RES_REG_NAMED(VSC7512_PORT_0_RES_START, VSC7512_PORT_RES_SIZE, "port0"), + DEFINE_RES_REG_NAMED(VSC7512_PORT_1_RES_START, VSC7512_PORT_RES_SIZE, "port1"), + DEFINE_RES_REG_NAMED(VSC7512_PORT_2_RES_START, VSC7512_PORT_RES_SIZE, "port2"), + DEFINE_RES_REG_NAMED(VSC7512_PORT_3_RES_START, VSC7512_PORT_RES_SIZE, "port3"), + DEFINE_RES_REG_NAMED(VSC7512_PORT_4_RES_START, VSC7512_PORT_RES_SIZE, "port4"), + DEFINE_RES_REG_NAMED(VSC7512_PORT_5_RES_START, VSC7512_PORT_RES_SIZE, "port5"), + DEFINE_RES_REG_NAMED(VSC7512_PORT_6_RES_START, VSC7512_PORT_RES_SIZE, "port6"), + DEFINE_RES_REG_NAMED(VSC7512_PORT_7_RES_START, VSC7512_PORT_RES_SIZE, "port7"), + DEFINE_RES_REG_NAMED(VSC7512_PORT_8_RES_START, VSC7512_PORT_RES_SIZE, "port8"), + DEFINE_RES_REG_NAMED(VSC7512_PORT_9_RES_START, VSC7512_PORT_RES_SIZE, "port9"), + DEFINE_RES_REG_NAMED(VSC7512_PORT_10_RES_START, VSC7512_PORT_RES_SIZE, "port10"), + {} +}; + static const struct mfd_cell vsc7512_devs[] = { { .name = "ocelot-pinctrl", @@ -127,7 +194,7 @@ static const struct mfd_cell vsc7512_devs[] = { static void ocelot_core_try_add_regmap(struct device *dev, const struct resource *res) { - if (dev_get_regmap(dev, res->name)) + if (!res->start || dev_get_regmap(dev, res->name)) return; ocelot_spi_init_regmap(dev, res); @@ -144,6 +211,7 @@ static void ocelot_core_try_add_regmaps(struct device *dev, int ocelot_core_init(struct device *dev) { + const struct resource *port_res; int i, ndevs; ndevs = ARRAY_SIZE(vsc7512_devs); @@ -151,6 +219,16 @@ int ocelot_core_init(struct device *dev) for (i = 0; i < ndevs; i++) ocelot_core_try_add_regmaps(dev, &vsc7512_devs[i]); + /* + * Both the target_io_res and tbe port_io_res structs need to be referenced directly by + * the ocelot_ext driver, so they can't be attached to the dev directly + */ + for (i = 0; i < TARGET_MAX; i++) + ocelot_core_try_add_regmap(dev, &vsc7512_target_io_res[i]); + + for (port_res = vsc7512_port_io_res; port_res->start; port_res++) + ocelot_core_try_add_regmap(dev, port_res); + return devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO, vsc7512_devs, ndevs, NULL, 0, NULL); } EXPORT_SYMBOL_NS(ocelot_core_init, MFD_OCELOT); diff --git a/include/linux/mfd/ocelot.h b/include/linux/mfd/ocelot.h index dd72073d2d4f..439ff5256cf0 100644 --- a/include/linux/mfd/ocelot.h +++ b/include/linux/mfd/ocelot.h @@ -11,8 +11,13 @@ #include #include +#include + struct resource; +extern const struct resource vsc7512_target_io_res[TARGET_MAX]; +extern const struct resource vsc7512_port_io_res[]; + static inline struct regmap * ocelot_regmap_from_resource_optional(struct platform_device *pdev, unsigned int index, From patchwork Sun Sep 11 20:02:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Colin Foster X-Patchwork-Id: 12973047 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 20EC6C6FA83 for ; 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Currently the four copper phy ports are fully functional. Communication to external phys is also functional, but the SGMII / QSGMII interfaces are currently non-functional. Signed-off-by: Colin Foster --- v1 from previous RFC: * Remove unnecessary byteorder and kconfig header includes. * Create OCELOT_EXT_PORT_MODE_SERDES macro to match vsc9959. * Utilize readx_poll_timeout for SYS_RESET_CFG_MEM_INIT. * *_io_res struct arrays have been moved to the MFD files. * Changes to utilize phylink_generic_validate() have been squashed. * dev_err_probe() is used in the probe function. * Make ocelot_ext_switch_of_match static. * Relocate ocelot_ext_ops structure to be next to vsc7512_info, to match what was done in other felix drivers. * Utilize dev_get_regmap() instead of the obsolete ocelot_init_regmap_from_resource() routine. --- drivers/mfd/ocelot-core.c | 3 + drivers/net/dsa/ocelot/Kconfig | 14 ++ drivers/net/dsa/ocelot/Makefile | 5 + drivers/net/dsa/ocelot/ocelot_ext.c | 254 ++++++++++++++++++++++++++++ include/soc/mscc/ocelot.h | 2 + 5 files changed, 278 insertions(+) create mode 100644 drivers/net/dsa/ocelot/ocelot_ext.c diff --git a/drivers/mfd/ocelot-core.c b/drivers/mfd/ocelot-core.c index aa7fa21b354c..b7b9f6855f74 100644 --- a/drivers/mfd/ocelot-core.c +++ b/drivers/mfd/ocelot-core.c @@ -188,6 +188,9 @@ static const struct mfd_cell vsc7512_devs[] = { .use_of_reg = true, .num_resources = ARRAY_SIZE(vsc7512_miim1_resources), .resources = vsc7512_miim1_resources, + }, { + .name = "ocelot-ext-switch", + .of_compatible = "mscc,vsc7512-ext-switch", }, }; diff --git a/drivers/net/dsa/ocelot/Kconfig b/drivers/net/dsa/ocelot/Kconfig index 08db9cf76818..d8b224f8dc97 100644 --- a/drivers/net/dsa/ocelot/Kconfig +++ b/drivers/net/dsa/ocelot/Kconfig @@ -1,4 +1,18 @@ # SPDX-License-Identifier: GPL-2.0-only +config NET_DSA_MSCC_OCELOT_EXT + tristate "Ocelot External Ethernet switch support" + depends on NET_DSA && SPI + depends on NET_VENDOR_MICROSEMI + select MDIO_MSCC_MIIM + select MFD_OCELOT_CORE + select MSCC_OCELOT_SWITCH_LIB + select NET_DSA_TAG_OCELOT_8021Q + select NET_DSA_TAG_OCELOT + help + This driver supports the VSC7511, VSC7512, VSC7513 and VSC7514 chips + when controlled through SPI. It can be used with the Microsemi dev + boards and an external CPU or custom hardware. + config NET_DSA_MSCC_FELIX tristate "Ocelot / Felix Ethernet switch support" depends on NET_DSA && PCI diff --git a/drivers/net/dsa/ocelot/Makefile b/drivers/net/dsa/ocelot/Makefile index f6dd131e7491..d7f3f5a4461c 100644 --- a/drivers/net/dsa/ocelot/Makefile +++ b/drivers/net/dsa/ocelot/Makefile @@ -1,11 +1,16 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_NET_DSA_MSCC_FELIX) += mscc_felix.o +obj-$(CONFIG_NET_DSA_MSCC_OCELOT_EXT) += mscc_ocelot_ext.o obj-$(CONFIG_NET_DSA_MSCC_SEVILLE) += mscc_seville.o mscc_felix-objs := \ felix.o \ felix_vsc9959.o +mscc_ocelot_ext-objs := \ + felix.o \ + ocelot_ext.o + mscc_seville-objs := \ felix.o \ seville_vsc9953.o diff --git a/drivers/net/dsa/ocelot/ocelot_ext.c b/drivers/net/dsa/ocelot/ocelot_ext.c new file mode 100644 index 000000000000..c821cc963787 --- /dev/null +++ b/drivers/net/dsa/ocelot/ocelot_ext.c @@ -0,0 +1,254 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2021-2022 Innovative Advantage Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "felix.h" + +#define VSC7512_NUM_PORTS 11 + +#define OCELOT_EXT_MEM_INIT_SLEEP_US 1000 +#define OCELOT_EXT_MEM_INIT_TIMEOUT_US 100000 + +#define OCELOT_EXT_PORT_MODE_SERDES (OCELOT_PORT_MODE_SGMII | \ + OCELOT_PORT_MODE_QSGMII) + +static const u32 vsc7512_port_modes[VSC7512_NUM_PORTS] = { + OCELOT_PORT_MODE_INTERNAL, + OCELOT_PORT_MODE_INTERNAL, + OCELOT_PORT_MODE_INTERNAL, + OCELOT_PORT_MODE_INTERNAL, + OCELOT_EXT_PORT_MODE_SERDES, + OCELOT_EXT_PORT_MODE_SERDES, + OCELOT_EXT_PORT_MODE_SERDES, + OCELOT_EXT_PORT_MODE_SERDES, + OCELOT_EXT_PORT_MODE_SERDES, + OCELOT_EXT_PORT_MODE_SERDES, + OCELOT_PORT_MODE_SGMII, + OCELOT_EXT_PORT_MODE_SERDES, +}; + +static const u32 vsc7512_gcb_regmap[] = { + REG(GCB_SOFT_RST, 0x0008), + REG(GCB_MIIM_MII_STATUS, 0x009c), + REG(GCB_PHY_PHY_CFG, 0x00f0), + REG(GCB_PHY_PHY_STAT, 0x00f4), +}; + +static const u32 *vsc7512_regmap[TARGET_MAX] = { + [ANA] = vsc7514_ana_regmap, + [QS] = vsc7514_qs_regmap, + [QSYS] = vsc7514_qsys_regmap, + [REW] = vsc7514_rew_regmap, + [SYS] = vsc7514_sys_regmap, + [S0] = vsc7514_vcap_regmap, + [S1] = vsc7514_vcap_regmap, + [S2] = vsc7514_vcap_regmap, + [PTP] = vsc7514_ptp_regmap, + [GCB] = vsc7512_gcb_regmap, + [DEV_GMII] = vsc7514_dev_gmii_regmap, +}; + +static void ocelot_ext_reset_phys(struct ocelot *ocelot) +{ + ocelot_write(ocelot, 0, GCB_PHY_PHY_CFG); + ocelot_write(ocelot, 0x1ff, GCB_PHY_PHY_CFG); + mdelay(500); +} + +static int ocelot_ext_mem_init_status(struct ocelot *ocelot) +{ + int val, err; + + err = regmap_field_read(ocelot->regfields[SYS_RESET_CFG_MEM_INIT], &val); + + return err ?: val; +} + +static int ocelot_ext_reset(struct ocelot *ocelot) +{ + int err, val; + + ocelot_ext_reset_phys(ocelot); + + /* Initialize chip memories */ + err = regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_ENA], 1); + if (err) + return err; + + err = regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_INIT], 1); + if (err) + return err; + + /* MEM_INIT is a self-clearing bit. Wait for it to be clear (should be + * 100us) before enabling the switch core + */ + err = readx_poll_timeout(ocelot_ext_mem_init_status, ocelot, val, !val, + OCELOT_EXT_MEM_INIT_SLEEP_US, + OCELOT_EXT_MEM_INIT_TIMEOUT_US); + + if (IS_ERR_VALUE(err)) + return err; + + return regmap_field_write(ocelot->regfields[SYS_RESET_CFG_CORE_ENA], 1); +} + +static void ocelot_ext_phylink_validate(struct ocelot *ocelot, int port, + unsigned long *supported, + struct phylink_link_state *state) +{ + struct felix *felix = ocelot_to_felix(ocelot); + struct dsa_switch *ds = felix->ds; + struct phylink_config *pl_config; + struct dsa_port *dp; + + dp = dsa_to_port(ds, port); + pl_config = &dp->pl_config; + + phylink_generic_validate(pl_config, supported, state); +} + +static struct regmap *ocelot_ext_regmap_init(struct ocelot *ocelot, + struct resource *res) +{ + return dev_get_regmap(ocelot->dev->parent, res->name); +} + +static const struct ocelot_ops ocelot_ext_ops = { + .reset = ocelot_ext_reset, + .wm_enc = ocelot_wm_enc, + .wm_dec = ocelot_wm_dec, + .wm_stat = ocelot_wm_stat, + .port_to_netdev = felix_port_to_netdev, + .netdev_to_port = felix_netdev_to_port, +}; + +static const struct felix_info vsc7512_info = { + .target_io_res = vsc7512_target_io_res, + .port_io_res = vsc7512_port_io_res, + .regfields = vsc7514_regfields, + .map = vsc7512_regmap, + .ops = &ocelot_ext_ops, + .stats_layout = vsc7514_stats_layout, + .vcap = vsc7514_vcap_props, + .num_mact_rows = 1024, + .num_ports = VSC7512_NUM_PORTS, + .num_tx_queues = OCELOT_NUM_TC, + .phylink_validate = ocelot_ext_phylink_validate, + .port_modes = vsc7512_port_modes, + .init_regmap = ocelot_ext_regmap_init, +}; + +static int ocelot_ext_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct dsa_switch *ds; + struct ocelot *ocelot; + struct felix *felix; + int err; + + felix = kzalloc(sizeof(*felix), GFP_KERNEL); + if (!felix) + return -ENOMEM; + + dev_set_drvdata(dev, felix); + + ocelot = &felix->ocelot; + ocelot->dev = dev; + + ocelot->num_flooding_pgids = 1; + + felix->info = &vsc7512_info; + + ds = kzalloc(sizeof(*ds), GFP_KERNEL); + if (!ds) { + err = -ENOMEM; + dev_err_probe(dev, err, "Failed to allocate DSA switch\n"); + goto err_free_felix; + } + + ds->dev = dev; + ds->num_ports = felix->info->num_ports; + ds->num_tx_queues = felix->info->num_tx_queues; + + ds->ops = &felix_switch_ops; + ds->priv = ocelot; + felix->ds = ds; + felix->tag_proto = DSA_TAG_PROTO_OCELOT; + + err = dsa_register_switch(ds); + if (err) { + dev_err_probe(dev, err, "Failed to register DSA switch\n"); + goto err_free_ds; + } + + return 0; + +err_free_ds: + kfree(ds); +err_free_felix: + kfree(felix); + return err; +} + +static int ocelot_ext_remove(struct platform_device *pdev) +{ + struct felix *felix = dev_get_drvdata(&pdev->dev); + + if (!felix) + return 0; + + dsa_unregister_switch(felix->ds); + + kfree(felix->ds); + kfree(felix); + + dev_set_drvdata(&pdev->dev, NULL); + + return 0; +} + +static void ocelot_ext_shutdown(struct platform_device *pdev) +{ + struct felix *felix = dev_get_drvdata(&pdev->dev); + + if (!felix) + return; + + dsa_switch_shutdown(felix->ds); + + dev_set_drvdata(&pdev->dev, NULL); +} + +static const struct of_device_id ocelot_ext_switch_of_match[] = { + { .compatible = "mscc,vsc7512-ext-switch" }, + { }, +}; +MODULE_DEVICE_TABLE(of, ocelot_ext_switch_of_match); + +static struct platform_driver ocelot_ext_switch_driver = { + .driver = { + .name = "ocelot-ext-switch", + .of_match_table = of_match_ptr(ocelot_ext_switch_of_match), + }, + .probe = ocelot_ext_probe, + .remove = ocelot_ext_remove, + .shutdown = ocelot_ext_shutdown, +}; +module_platform_driver(ocelot_ext_switch_driver); + +MODULE_DESCRIPTION("External Ocelot Switch driver"); +MODULE_LICENSE("GPL"); diff --git a/include/soc/mscc/ocelot.h b/include/soc/mscc/ocelot.h index 17dd61f36563..2ed38110a6cc 100644 --- a/include/soc/mscc/ocelot.h +++ b/include/soc/mscc/ocelot.h @@ -460,6 +460,8 @@ enum ocelot_reg { GCB_MIIM_MII_STATUS, GCB_MIIM_MII_CMD, GCB_MIIM_MII_DATA, + GCB_PHY_PHY_CFG, + GCB_PHY_PHY_STAT, DEV_CLOCK_CFG = DEV_GMII << TARGET_OFFSET, DEV_PORT_MISC, DEV_EVENTS,