From patchwork Mon Sep 12 01:29:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?SmFzb24tSkggTGluICjmnpfnnb/npaUp?= X-Patchwork-Id: 12973183 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CEA8DECAAD3 for ; Mon, 12 Sep 2022 01:30:37 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E840610E129; Mon, 12 Sep 2022 01:30:24 +0000 (UTC) Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by gabe.freedesktop.org (Postfix) with ESMTPS id 055B510E110 for ; Mon, 12 Sep 2022 01:30:17 +0000 (UTC) X-UUID: 08c7bde92ef34fa7851d464d2ab7c54e-20220912 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=O3LUqg31O+VB4iMjWdOGL0PoqlmvD6Jw/XCEotzP8UA=; b=SD3khOH5gft3LWYeG4NQOIhnEevMZyDrVdmiObQt9nL4bd0DIHgkO/H7FHkLywZWobjiO9NSXxD2fzdLvWc1QDZjc1OVOg7CC61oU0ZsLwjb1z6hv+YspJjDHAbgK32gXw+ykPHodOh1+89at++xQu9jbF7/WAfW8ubRWVom4I8=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.10, REQID:35ca6d8e-b803-4dcf-9999-dda8b71ada3e, OB:0, L OB:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_ Ham,ACTION:release,TS:0 X-CID-META: VersionHash:84eae18, CLOUDID:95e305f6-6e85-48d9-afd8-0504bbfe04cb, C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 08c7bde92ef34fa7851d464d2ab7c54e-20220912 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 524415163; Mon, 12 Sep 2022 09:30:12 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Mon, 12 Sep 2022 09:30:06 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Mon, 12 Sep 2022 09:30:06 +0800 From: Jason-JH.Lin To: Chun-Kuang Hu , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , AngeloGioacchino Del Regno Subject: [PATCH RESEND v3 1/9] dt-bindings: mediatek: modify item formatting for gamma Date: Mon, 12 Sep 2022 09:29:58 +0800 Message-ID: <20220912013006.27541-2-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220912013006.27541-1-jason-jh.lin@mediatek.com> References: <20220912013006.27541-1-jason-jh.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, "zheng-yan.chen" , Singo Chang , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Project_Global_Chrome_Upstream_Group@mediatek.com, Rex-BC Chen , linux-mediatek@lists.infradead.org, "Jason-JH . Lin" , linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: "zheng-yan.chen" Since the items with only one const should be dedicated as enum, merge all such items into one enum item. Fixes: 4ed545e7d100 ("dt-bindings: display: mediatek: disp: split each block to individual yaml") Signed-off-by: zheng-yan.chen Signed-off-by: Jason-JH.Lin Reviewed-by: Krzysztof Kozlowski --- .../bindings/display/mediatek/mediatek,gamma.yaml | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml index a89ea0ea7542..c3631a3e3f05 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml @@ -22,9 +22,9 @@ properties: compatible: oneOf: - items: - - const: mediatek,mt8173-disp-gamma - - items: - - const: mediatek,mt8183-disp-gamma + - enum: + - mediatek,mt8173-disp-gamma + - mediatek,mt8183-disp-gamma - items: - enum: - mediatek,mt8186-disp-gamma From patchwork Mon Sep 12 01:29:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?SmFzb24tSkggTGluICjmnpfnnb/npaUp?= X-Patchwork-Id: 12973189 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5B26DECAAD3 for ; Mon, 12 Sep 2022 01:31:02 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1171810E13E; Mon, 12 Sep 2022 01:30:32 +0000 (UTC) Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by gabe.freedesktop.org (Postfix) with ESMTPS id 18EA110E129 for ; Mon, 12 Sep 2022 01:30:14 +0000 (UTC) X-UUID: 91d39cd3bcb04ee9bda6f1fef05e00d5-20220912 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=IDXTI4k18EJfx3l923GepQjG7TruZcdsfijbeW9PjtI=; b=rOMSwu2F2psUj8ht/9jL979Lc9ODDdSy+hmH9vS4XGF43Ay2b/bnNzhXDwl9aaFxfQwWydRGykvZBvBFCXFqx6h5y9OVqe3vo3fGO7fehCF7K8Murvn4J0Ao5zqIhBEpNkabCJbbe8sZYJznL0IkBwZUovRaHRn5E51vHqzcV5Y=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.10, REQID:818b8dc5-ecb2-4208-8a0c-50848ab2bedd, OB:0, L OB:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_ Ham,ACTION:release,TS:0 X-CID-META: VersionHash:84eae18, CLOUDID:a1e305f6-6e85-48d9-afd8-0504bbfe04cb, C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 91d39cd3bcb04ee9bda6f1fef05e00d5-20220912 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 114593950; Mon, 12 Sep 2022 09:30:12 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Mon, 12 Sep 2022 09:30:06 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Mon, 12 Sep 2022 09:30:06 +0800 From: Jason-JH.Lin To: Chun-Kuang Hu , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , AngeloGioacchino Del Regno Subject: [PATCH RESEND v3 2/9] dt-bindings: mediatek: Add gamma compatible for mt8195 Date: Mon, 12 Sep 2022 09:29:59 +0800 Message-ID: <20220912013006.27541-3-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220912013006.27541-1-jason-jh.lin@mediatek.com> References: <20220912013006.27541-1-jason-jh.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, "zheng-yan.chen" , Singo Chang , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Project_Global_Chrome_Upstream_Group@mediatek.com, Rex-BC Chen , linux-mediatek@lists.infradead.org, "Jason-JH . Lin" , linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: "zheng-yan.chen" mt8195 uses 10bit-to-12bit gamma-LUT, which is not compatible with current 9bit-to-10bit gamma-LUT. This patch thus add constant compatible for mt8195, which means that mt8195 should only use specified mt8195 gamma driver data. Also, delete related compatible from enum, to ensure that mt8195 will not accidentally get others' gamma driver data and thus cause fatal error. Signed-off-by: zheng-yan.chen Signed-off-by: Jason-JH.Lin Reviewed-by: AngeloGioacchino Del Regno Acked-by: Krzysztof Kozlowski --- .../devicetree/bindings/display/mediatek/mediatek,gamma.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml index c3631a3e3f05..bc20160d6b68 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml @@ -25,11 +25,11 @@ properties: - enum: - mediatek,mt8173-disp-gamma - mediatek,mt8183-disp-gamma + - mediatek,mt8195-disp-gamma - items: - enum: - mediatek,mt8186-disp-gamma - mediatek,mt8192-disp-gamma - - mediatek,mt8195-disp-gamma - const: mediatek,mt8183-disp-gamma reg: From patchwork Mon Sep 12 01:30:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?SmFzb24tSkggTGluICjmnpfnnb/npaUp?= X-Patchwork-Id: 12973190 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 70487ECAAD3 for ; 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Mon, 12 Sep 2022 09:30:18 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Mon, 12 Sep 2022 09:30:07 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Mon, 12 Sep 2022 09:30:07 +0800 From: Jason-JH.Lin To: Chun-Kuang Hu , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , AngeloGioacchino Del Regno Subject: [PATCH RESEND v3 3/9] drm/mediatek: Adjust mtk_drm_gamma_set_common parameters Date: Mon, 12 Sep 2022 09:30:00 +0800 Message-ID: <20220912013006.27541-4-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220912013006.27541-1-jason-jh.lin@mediatek.com> References: <20220912013006.27541-1-jason-jh.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, "Jason-JH.Lin" , Singo Chang , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Project_Global_Chrome_Upstream_Group@mediatek.com, Rex-BC Chen , linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Adjust the parameters in mtk_drm_gamma_set_common() - add (struct device *dev) to get lut_diff from gamma's driver data - remove (bool lut_diff) and use false as default value in the function Fixes: 051524cbe62d ("FROMGIT: drm/mediatek: Add lut diff flag for new gamma hardware support") Signed-off-by: Jason-JH.Lin --- drivers/gpu/drm/mediatek/mtk_disp_aal.c | 2 +- drivers/gpu/drm/mediatek/mtk_disp_drv.h | 2 +- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 13 +++++++------ 3 files changed, 9 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_aal.c b/drivers/gpu/drm/mediatek/mtk_disp_aal.c index 0f9d7efb61d7..6517e0a5a7d8 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_aal.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_aal.c @@ -66,7 +66,7 @@ void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state) struct mtk_disp_aal *aal = dev_get_drvdata(dev); if (aal->data && aal->data->has_gamma) - mtk_gamma_set_common(aal->regs, state, false); + mtk_gamma_set_common(NULL, aal->regs, state); } void mtk_aal_start(struct device *dev) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h index 33e61a136bbc..a83e5fbc8724 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -52,7 +52,7 @@ void mtk_gamma_config(struct device *dev, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt); void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state); -void mtk_gamma_set_common(void __iomem *regs, struct drm_crtc_state *state, bool lut_diff); +void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crtc_state *state); void mtk_gamma_start(struct device *dev); void mtk_gamma_stop(struct device *dev); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c index bbd558a036ec..f54a6a618348 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -54,14 +54,19 @@ void mtk_gamma_clk_disable(struct device *dev) clk_disable_unprepare(gamma->clk); } -void mtk_gamma_set_common(void __iomem *regs, struct drm_crtc_state *state, bool lut_diff) +void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crtc_state *state) { + struct mtk_disp_gamma *gamma = dev_get_drvdata(dev); + bool lut_diff = false; unsigned int i, reg; struct drm_color_lut *lut; void __iomem *lut_base; u32 word; u32 diff[3] = {0}; + if (gamma && gamma->data) + lut_diff = gamma->data->lut_diff; + if (state->gamma_lut) { reg = readl(regs + DISP_GAMMA_CFG); reg = reg | GAMMA_LUT_EN; @@ -91,12 +96,8 @@ void mtk_gamma_set_common(void __iomem *regs, struct drm_crtc_state *state, bool void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state) { struct mtk_disp_gamma *gamma = dev_get_drvdata(dev); - bool lut_diff = false; - - if (gamma->data) - lut_diff = gamma->data->lut_diff; - mtk_gamma_set_common(gamma->regs, state, lut_diff); + mtk_gamma_set_common(dev, gamma->regs, state); } void mtk_gamma_config(struct device *dev, unsigned int w, From patchwork Mon Sep 12 01:30:01 2022 Content-Type: text/plain; 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Mon, 12 Sep 2022 09:30:07 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Mon, 12 Sep 2022 09:30:07 +0800 From: Jason-JH.Lin To: Chun-Kuang Hu , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , AngeloGioacchino Del Regno Subject: [PATCH RESEND v3 4/9] drm/mediatek: Add gamma support different lut_size for other SoC Date: Mon, 12 Sep 2022 09:30:01 +0800 Message-ID: <20220912013006.27541-5-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220912013006.27541-1-jason-jh.lin@mediatek.com> References: <20220912013006.27541-1-jason-jh.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, "Jason-JH.Lin" , Singo Chang , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Project_Global_Chrome_Upstream_Group@mediatek.com, Rex-BC Chen , linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" 1. Add mtk_drm_gamma_get_lut_size() and remove MTK_LUT_SIZE macro. 2. Add lut_size to gamma driver data for different SoC. Signed-off-by: Jason-JH.Lin --- drivers/gpu/drm/mediatek/mtk_disp_drv.h | 1 + drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 22 +++++++++++++++++++-- drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 4 ++-- drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 1 - drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 9 +++++++++ 5 files changed, 32 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h index a83e5fbc8724..6a05bb56e693 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -51,6 +51,7 @@ void mtk_gamma_clk_disable(struct device *dev); void mtk_gamma_config(struct device *dev, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt); +unsigned int mtk_gamma_get_lut_size(struct device *dev); void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state); void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crtc_state *state); void mtk_gamma_start(struct device *dev); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c index f54a6a618348..0a1022032b71 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -24,10 +24,12 @@ #define DISP_GAMMA_LUT 0x0700 #define LUT_10BIT_MASK 0x03ff +#define LUT_SIZE_DEFAULT 512 /* for setting gamma lut from AAL */ struct mtk_disp_gamma_data { bool has_dither; bool lut_diff; + u16 lut_size; }; /* @@ -54,18 +56,32 @@ void mtk_gamma_clk_disable(struct device *dev) clk_disable_unprepare(gamma->clk); } +unsigned int mtk_gamma_get_lut_size(struct device *dev) +{ + struct mtk_disp_gamma *gamma = dev_get_drvdata(dev); + unsigned int lut_size = LUT_SIZE_DEFAULT; + + if (gamma && gamma->data) + lut_size = gamma->data->lut_size; + + return lut_size; +} + void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crtc_state *state) { struct mtk_disp_gamma *gamma = dev_get_drvdata(dev); bool lut_diff = false; + u16 lut_size = LUT_SIZE_DEFAULT; unsigned int i, reg; struct drm_color_lut *lut; void __iomem *lut_base; u32 word; u32 diff[3] = {0}; - if (gamma && gamma->data) + if (gamma && gamma->data) { lut_diff = gamma->data->lut_diff; + lut_size = gamma->data->lut_size; + } if (state->gamma_lut) { reg = readl(regs + DISP_GAMMA_CFG); @@ -73,7 +89,7 @@ void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crt writel(reg, regs + DISP_GAMMA_CFG); lut_base = regs + DISP_GAMMA_LUT; lut = (struct drm_color_lut *)state->gamma_lut->data; - for (i = 0; i < MTK_LUT_SIZE; i++) { + for (i = 0; i < lut_size; i++) { if (!lut_diff || (i % 2 == 0)) { word = (((lut[i].red >> 6) & LUT_10BIT_MASK) << 20) + @@ -192,10 +208,12 @@ static int mtk_disp_gamma_remove(struct platform_device *pdev) static const struct mtk_disp_gamma_data mt8173_gamma_driver_data = { .has_dither = true, + .lut_size = 512, }; static const struct mtk_disp_gamma_data mt8183_gamma_driver_data = { .lut_diff = true, + .lut_size = 512, }; static const struct of_device_id mtk_disp_gamma_driver_dt_match[] = { diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c index 112615817dcb..fc845490fbb4 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c @@ -929,8 +929,8 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev, mtk_crtc->ddp_comp[i] = comp; if (comp->funcs) { - if (comp->funcs->gamma_set) - gamma_lut_size = MTK_LUT_SIZE; + if (comp->funcs->gamma_set && comp->funcs->gamma_get_lut_size) + gamma_lut_size = mtk_ddp_gamma_get_lut_size(comp); if (comp->funcs->ctm_set) has_ctm = true; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h index cb9a36c48d4f..1799853ef89a 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h @@ -10,7 +10,6 @@ #include "mtk_drm_ddp_comp.h" #include "mtk_drm_plane.h" -#define MTK_LUT_SIZE 512 #define MTK_MAX_BPC 10 #define MTK_MIN_BPC 3 diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index 2d0052c23dcb..ab589ea11ba7 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -65,6 +65,7 @@ struct mtk_ddp_comp_funcs { void (*layer_config)(struct device *dev, unsigned int idx, struct mtk_plane_state *state, struct cmdq_pkt *cmdq_pkt); + unsigned int (*gamma_get_lut_size)(struct device *dev); void (*gamma_set)(struct device *dev, struct drm_crtc_state *state); void (*bgclr_in_on)(struct device *dev); @@ -177,6 +178,14 @@ static inline void mtk_ddp_comp_layer_config(struct mtk_ddp_comp *comp, comp->funcs->layer_config(comp->dev, idx, state, cmdq_pkt); } +static inline unsigned int mtk_ddp_gamma_get_lut_size(struct mtk_ddp_comp *comp) +{ + if (comp->funcs && comp->funcs->gamma_get_lut_size) + return comp->funcs->gamma_get_lut_size(comp->dev); + + return 0; +} + static inline void mtk_ddp_gamma_set(struct mtk_ddp_comp *comp, struct drm_crtc_state *state) { From patchwork Mon Sep 12 01:30:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?SmFzb24tSkggTGluICjmnpfnnb/npaUp?= X-Patchwork-Id: 12973182 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EB79FECAAA1 for ; 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Mon, 12 Sep 2022 09:30:12 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Mon, 12 Sep 2022 09:30:07 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Mon, 12 Sep 2022 09:30:07 +0800 From: Jason-JH.Lin To: Chun-Kuang Hu , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , AngeloGioacchino Del Regno Subject: [PATCH RESEND v3 5/9] drm/mediatek: Add gamma support different lut_bits for other SoC Date: Mon, 12 Sep 2022 09:30:02 +0800 Message-ID: <20220912013006.27541-6-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220912013006.27541-1-jason-jh.lin@mediatek.com> References: <20220912013006.27541-1-jason-jh.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, "Jason-JH.Lin" , Singo Chang , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Project_Global_Chrome_Upstream_Group@mediatek.com, Rex-BC Chen , linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add lut_bits in gamma driver data for each SoC and adjust the usage of lut_bits in mtk_drm_gamma_set_common(). Signed-off-by: Jason-JH.Lin --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 36 ++++++++++++++++------- 1 file changed, 25 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c index 0a1022032b71..be82d15a5204 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -25,11 +25,14 @@ #define LUT_10BIT_MASK 0x03ff #define LUT_SIZE_DEFAULT 512 /* for setting gamma lut from AAL */ +#define LUT_BITS_DEFAULT 10 +#define LUT_INPUT_BITS 16 /* input lut bit from application */ struct mtk_disp_gamma_data { bool has_dither; bool lut_diff; u16 lut_size; + u8 lut_bits; }; /* @@ -72,17 +75,23 @@ void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crt struct mtk_disp_gamma *gamma = dev_get_drvdata(dev); bool lut_diff = false; u16 lut_size = LUT_SIZE_DEFAULT; + u8 lut_bits = LUT_BITS_DEFAULT; + u8 shift_bits; unsigned int i, reg; struct drm_color_lut *lut; void __iomem *lut_base; - u32 word; + u32 word, mask; u32 diff[3] = {0}; if (gamma && gamma->data) { lut_diff = gamma->data->lut_diff; lut_size = gamma->data->lut_size; + lut_bits = gamma->data->lut_bits; } + shift_bits = LUT_INPUT_BITS - lut_bits; + mask = GENMASK(lut_bits - 1, 0); + if (state->gamma_lut) { reg = readl(regs + DISP_GAMMA_CFG); reg = reg | GAMMA_LUT_EN; @@ -92,17 +101,20 @@ void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crt for (i = 0; i < lut_size; i++) { if (!lut_diff || (i % 2 == 0)) { - word = (((lut[i].red >> 6) & LUT_10BIT_MASK) << 20) + - (((lut[i].green >> 6) & LUT_10BIT_MASK) << 10) + - ((lut[i].blue >> 6) & LUT_10BIT_MASK); + word = (((lut[i].red >> shift_bits) & mask) << 20) + + (((lut[i].green >> shift_bits) & mask) << 10) + + ((lut[i].blue >> shift_bits) & mask); } else { - diff[0] = (lut[i].red >> 6) - (lut[i - 1].red >> 6); - diff[1] = (lut[i].green >> 6) - (lut[i - 1].green >> 6); - diff[2] = (lut[i].blue >> 6) - (lut[i - 1].blue >> 6); - - word = ((diff[0] & LUT_10BIT_MASK) << 20) + - ((diff[1] & LUT_10BIT_MASK) << 10) + - (diff[2] & LUT_10BIT_MASK); + diff[0] = (lut[i].red >> shift_bits) - + (lut[i - 1].red >> shift_bits); + diff[1] = (lut[i].green >> shift_bits) - + (lut[i - 1].green >> shift_bits); + diff[2] = (lut[i].blue >> shift_bits) - + (lut[i - 1].blue >> shift_bits); + + word = ((diff[0] & mask) << 20) + + ((diff[1] & mask) << 10) + + (diff[2] & mask); } writel(word, (lut_base + i * 4)); } @@ -209,11 +221,13 @@ static int mtk_disp_gamma_remove(struct platform_device *pdev) static const struct mtk_disp_gamma_data mt8173_gamma_driver_data = { .has_dither = true, .lut_size = 512, + .lut_bits = 10, }; static const struct mtk_disp_gamma_data mt8183_gamma_driver_data = { .lut_diff = true, .lut_size = 512, + .lut_bits = 10, }; static const struct of_device_id mtk_disp_gamma_driver_dt_match[] = { From patchwork Mon Sep 12 01:30:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?SmFzb24tSkggTGluICjmnpfnnb/npaUp?= X-Patchwork-Id: 12973188 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2C675ECAAA1 for ; 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Mon, 12 Sep 2022 09:30:12 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Mon, 12 Sep 2022 09:30:07 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Mon, 12 Sep 2022 09:30:07 +0800 From: Jason-JH.Lin To: Chun-Kuang Hu , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , AngeloGioacchino Del Regno Subject: [PATCH RESEND v3 6/9] drm/mediatek: Add gamma support different bank_size for other SoC Date: Mon, 12 Sep 2022 09:30:03 +0800 Message-ID: <20220912013006.27541-7-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220912013006.27541-1-jason-jh.lin@mediatek.com> References: <20220912013006.27541-1-jason-jh.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, "Jason-JH.Lin" , Singo Chang , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Project_Global_Chrome_Upstream_Group@mediatek.com, Rex-BC Chen , linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add multiple bank support for mt8195. If bank size is 0 which means no bank support. Signed-off-by: Jason-JH.Lin --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 45 +++++++++++++---------- 1 file changed, 26 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c index be82d15a5204..45da2b6206c8 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -21,6 +21,7 @@ #define GAMMA_LUT_EN BIT(1) #define GAMMA_DITHERING BIT(2) #define DISP_GAMMA_SIZE 0x0030 +#define DISP_GAMMA_BANK 0x0100 #define DISP_GAMMA_LUT 0x0700 #define LUT_10BIT_MASK 0x03ff @@ -33,6 +34,7 @@ struct mtk_disp_gamma_data { bool lut_diff; u16 lut_size; u8 lut_bits; + u16 bank_size; }; /* @@ -75,9 +77,10 @@ void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crt struct mtk_disp_gamma *gamma = dev_get_drvdata(dev); bool lut_diff = false; u16 lut_size = LUT_SIZE_DEFAULT; + u16 bank_size = lut_size; u8 lut_bits = LUT_BITS_DEFAULT; u8 shift_bits; - unsigned int i, reg; + unsigned int i, j, reg, bank_num; struct drm_color_lut *lut; void __iomem *lut_base; u32 word, mask; @@ -87,8 +90,10 @@ void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crt lut_diff = gamma->data->lut_diff; lut_size = gamma->data->lut_size; lut_bits = gamma->data->lut_bits; + bank_size = gamma->data->bank_size; } + bank_num = lut_size / bank_size; shift_bits = LUT_INPUT_BITS - lut_bits; mask = GENMASK(lut_bits - 1, 0); @@ -98,25 +103,27 @@ void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crt writel(reg, regs + DISP_GAMMA_CFG); lut_base = regs + DISP_GAMMA_LUT; lut = (struct drm_color_lut *)state->gamma_lut->data; - for (i = 0; i < lut_size; i++) { - - if (!lut_diff || (i % 2 == 0)) { - word = (((lut[i].red >> shift_bits) & mask) << 20) + - (((lut[i].green >> shift_bits) & mask) << 10) + - ((lut[i].blue >> shift_bits) & mask); - } else { - diff[0] = (lut[i].red >> shift_bits) - - (lut[i - 1].red >> shift_bits); - diff[1] = (lut[i].green >> shift_bits) - - (lut[i - 1].green >> shift_bits); - diff[2] = (lut[i].blue >> shift_bits) - - (lut[i - 1].blue >> shift_bits); - - word = ((diff[0] & mask) << 20) + - ((diff[1] & mask) << 10) + - (diff[2] & mask); + for (j = 0; j < bank_num; j++) { + writel(j, regs + DISP_GAMMA_BANK); + for (i = 0; i < bank_size; i++) { + if (!lut_diff || (i % 2 == 0)) { + word = (((lut[i].red >> shift_bits) & mask) << 20) + + (((lut[i].green >> shift_bits) & mask) << 10) + + ((lut[i].blue >> shift_bits) & mask); + } else { + diff[0] = (lut[i].red >> shift_bits) - + (lut[i - 1].red >> shift_bits); + diff[1] = (lut[i].green >> shift_bits) - + (lut[i - 1].green >> shift_bits); + diff[2] = (lut[i].blue >> shift_bits) - + (lut[i - 1].blue >> shift_bits); + + word = ((diff[0] & mask) << 20) + + ((diff[1] & mask) << 10) + + (diff[2] & mask); + } + writel(word, (lut_base + i * 4)); } - writel(word, (lut_base + i * 4)); } } } From patchwork Mon Sep 12 01:30:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?SmFzb24tSkggTGluICjmnpfnnb/npaUp?= X-Patchwork-Id: 12973184 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A2123ECAAD3 for ; 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Mon, 12 Sep 2022 09:30:12 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Mon, 12 Sep 2022 09:30:07 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Mon, 12 Sep 2022 09:30:07 +0800 From: Jason-JH.Lin To: Chun-Kuang Hu , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , AngeloGioacchino Del Regno Subject: [PATCH RESEND v3 7/9] drm/mediatek: Add gamma lut support for mt8195 Date: Mon, 12 Sep 2022 09:30:04 +0800 Message-ID: <20220912013006.27541-8-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220912013006.27541-1-jason-jh.lin@mediatek.com> References: <20220912013006.27541-1-jason-jh.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, "zheng-yan.chen" , Singo Chang , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Project_Global_Chrome_Upstream_Group@mediatek.com, Rex-BC Chen , linux-mediatek@lists.infradead.org, "Jason-JH . Lin" , linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: "zheng-yan.chen" Since the previous gamma_set_common() function is designed for 9bit-to-10bit conversion, which is not feasible for the 10bit-to-12bit conversion in mt8195. 1. Update the function to fit the need of mt8195. 2. Add gamma driver data for mt8195. Signed-off-by: zheng-yan.chen Signed-off-by: Jason-JH.Lin --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 57 ++++++++++++++++------- 1 file changed, 40 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c index 45da2b6206c8..d706f76fd30e 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -23,6 +23,7 @@ #define DISP_GAMMA_SIZE 0x0030 #define DISP_GAMMA_BANK 0x0100 #define DISP_GAMMA_LUT 0x0700 +#define DISP_GAMMA_LUT1 0x0b00 #define LUT_10BIT_MASK 0x03ff #define LUT_SIZE_DEFAULT 512 /* for setting gamma lut from AAL */ @@ -82,9 +83,8 @@ void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crt u8 shift_bits; unsigned int i, j, reg, bank_num; struct drm_color_lut *lut; - void __iomem *lut_base; - u32 word, mask; - u32 diff[3] = {0}; + void __iomem *lut_base, *lut1_base; + u32 word, word1, mask; if (gamma && gamma->data) { lut_diff = gamma->data->lut_diff; @@ -102,27 +102,41 @@ void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crt reg = reg | GAMMA_LUT_EN; writel(reg, regs + DISP_GAMMA_CFG); lut_base = regs + DISP_GAMMA_LUT; + lut1_base = regs + DISP_GAMMA_LUT1; lut = (struct drm_color_lut *)state->gamma_lut->data; for (j = 0; j < bank_num; j++) { writel(j, regs + DISP_GAMMA_BANK); for (i = 0; i < bank_size; i++) { - if (!lut_diff || (i % 2 == 0)) { - word = (((lut[i].red >> shift_bits) & mask) << 20) + - (((lut[i].green >> shift_bits) & mask) << 10) + - ((lut[i].blue >> shift_bits) & mask); + struct drm_color_lut input; + + input.red = (lut[i].red >> shift_bits) & mask; + input.green = (lut[i].green >> shift_bits) & mask; + input.blue = (lut[i].blue >> shift_bits) & mask; + if (!lut_diff || i % 2 == 0) { + word = (lut_bits == 12) ? + (input.red + (input.green << 12)) : + ((input.red << 20) + (input.green << 10) + + input.blue); + word1 = input.blue; } else { - diff[0] = (lut[i].red >> shift_bits) - - (lut[i - 1].red >> shift_bits); - diff[1] = (lut[i].green >> shift_bits) - - (lut[i - 1].green >> shift_bits); - diff[2] = (lut[i].blue >> shift_bits) - - (lut[i - 1].blue >> shift_bits); - - word = ((diff[0] & mask) << 20) + - ((diff[1] & mask) << 10) + - (diff[2] & mask); + struct drm_color_lut diff; + + diff.red = input.red - + ((lut[i - 1].red >> shift_bits) & mask); + diff.green = input.green - + ((lut[i - 1].green >> shift_bits & mask)); + diff.blue = input.blue - + ((lut[i - 1].blue >> shift_bits) & mask); + + word = (lut_bits == 12) ? + (input.red + (input.green << 12)) : + (diff.red << 20) + (diff.green << 10) + diff.blue; + word1 = input.blue; } + writel(word, (lut_base + i * 4)); + if (lut_bits == 12) + writel(word1, (lut1_base + i * 4)); } } } @@ -237,11 +251,20 @@ static const struct mtk_disp_gamma_data mt8183_gamma_driver_data = { .lut_bits = 10, }; +static const struct mtk_disp_gamma_data mt8195_gamma_driver_data = { + .lut_diff = true, + .lut_size = 512, + .lut_bits = 10, + .bank_size = 256, +}; + static const struct of_device_id mtk_disp_gamma_driver_dt_match[] = { { .compatible = "mediatek,mt8173-disp-gamma", .data = &mt8173_gamma_driver_data}, { .compatible = "mediatek,mt8183-disp-gamma", .data = &mt8183_gamma_driver_data}, + { .compatible = "mediatek,mt8195-disp-gamma", + .data = &mt8195_gamma_driver_data}, {}, }; MODULE_DEVICE_TABLE(of, mtk_disp_gamma_driver_dt_match); From patchwork Mon Sep 12 01:30:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?SmFzb24tSkggTGluICjmnpfnnb/npaUp?= X-Patchwork-Id: 12973187 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F2AF0ECAAA1 for ; Mon, 12 Sep 2022 01:30:55 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1A5F710E12E; Mon, 12 Sep 2022 01:30:27 +0000 (UTC) Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by gabe.freedesktop.org (Postfix) with ESMTPS id A443910E113 for ; Mon, 12 Sep 2022 01:30:18 +0000 (UTC) X-UUID: 2b062ff0721b42d29ca988c5a208dfd4-20220912 DKIM-Signature: v=1; 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Mon, 12 Sep 2022 09:30:12 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Mon, 12 Sep 2022 09:30:07 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Mon, 12 Sep 2022 09:30:07 +0800 From: Jason-JH.Lin To: Chun-Kuang Hu , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , AngeloGioacchino Del Regno Subject: [PATCH RESEND v3 8/9] drm/mediatek: Add clear RELAY_MODE bit to set gamma Date: Mon, 12 Sep 2022 09:30:05 +0800 Message-ID: <20220912013006.27541-9-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220912013006.27541-1-jason-jh.lin@mediatek.com> References: <20220912013006.27541-1-jason-jh.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, "Jason-JH.Lin" , Singo Chang , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Project_Global_Chrome_Upstream_Group@mediatek.com, Rex-BC Chen , linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Since the bootlaoder may set the RELAY_MODE to gamma be for the kerenl, we have to clear the RELAY_MODE bit to make sure that the gamma is enabled correctly. Fixes: b10023b03082 ("FROMGIT: drm/mediatek: Separate gamma module") Signed-off-by: Jason-JH.Lin --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c index d706f76fd30e..15fe2a4f98de 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -18,6 +18,7 @@ #define DISP_GAMMA_EN 0x0000 #define GAMMA_EN BIT(0) #define DISP_GAMMA_CFG 0x0020 +#define RELAY_MODE BIT(0) #define GAMMA_LUT_EN BIT(1) #define GAMMA_DITHERING BIT(2) #define DISP_GAMMA_SIZE 0x0030 @@ -99,6 +100,7 @@ void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crt if (state->gamma_lut) { reg = readl(regs + DISP_GAMMA_CFG); + reg = reg & ~RELAY_MODE; reg = reg | GAMMA_LUT_EN; writel(reg, regs + DISP_GAMMA_CFG); lut_base = regs + DISP_GAMMA_LUT; From patchwork Mon Sep 12 01:30:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?SmFzb24tSkggTGluICjmnpfnnb/npaUp?= X-Patchwork-Id: 12973185 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 41BCCECAAD3 for ; Mon, 12 Sep 2022 01:30:48 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0FDF410E113; Mon, 12 Sep 2022 01:30:27 +0000 (UTC) Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by gabe.freedesktop.org (Postfix) with ESMTPS id AE1D210E113 for ; Mon, 12 Sep 2022 01:30:23 +0000 (UTC) X-UUID: e026e9bb127f470fa98865c5ee66ee32-20220912 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=8dXiDlITRRdV1fryZ6x6Kqua0WndoPmtkLh2DFTBuNo=; b=RECw58PbpjLjC4648mEDrc9DrqAYf0USUY1Btx/xRUG5G4IaIE18QJoxRSVY9UUtiAPwMzD112TTq/RpkBG2FHhmBqDOl0OIElccAKolBcDPrhGriJqdCh5n0RduX0rO7poFJS5cL/MSqE2EOlXeD1nbkmEGr7LMXojxaawmIrk=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.10, REQID:ae809641-8582-46fb-ba29-d8b706af526e, OB:0, L OB:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_ Ham,ACTION:release,TS:0 X-CID-META: VersionHash:84eae18, CLOUDID:8ee405f6-6e85-48d9-afd8-0504bbfe04cb, C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: e026e9bb127f470fa98865c5ee66ee32-20220912 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1820718379; Mon, 12 Sep 2022 09:30:18 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Mon, 12 Sep 2022 09:30:07 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Mon, 12 Sep 2022 09:30:07 +0800 From: Jason-JH.Lin To: Chun-Kuang Hu , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , AngeloGioacchino Del Regno Subject: [PATCH RESEND v3 9/9] arm64: dts: Modify gamma compatible for mt8195 Date: Mon, 12 Sep 2022 09:30:06 +0800 Message-ID: <20220912013006.27541-10-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220912013006.27541-1-jason-jh.lin@mediatek.com> References: <20220912013006.27541-1-jason-jh.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, "zheng-yan.chen" , Singo Chang , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Project_Global_Chrome_Upstream_Group@mediatek.com, Rex-BC Chen , linux-mediatek@lists.infradead.org, "Jason-JH . Lin" , linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: "zheng-yan.chen" Modify gamma compatible for mt8195. This modification is because of that mt8183 gamma driver data is not compatible with mt8195 gamma. Thus, need to delete mt8183 gamma compatible from mt8195 gamma. Signed-off-by: zheng-yan.chen Signed-off-by: Jason-JH.Lin Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 905d1a90b406..6b01ebc0db8f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -2032,7 +2032,7 @@ }; gamma0: gamma@1c006000 { - compatible = "mediatek,mt8195-disp-gamma", "mediatek,mt8183-disp-gamma"; + compatible = "mediatek,mt8195-disp-gamma"; reg = <0 0x1c006000 0 0x1000>; interrupts = ; power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;