From patchwork Mon Sep 12 11:45:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 12973591 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 24BB4ECAAD5 for ; Mon, 12 Sep 2022 11:45:37 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6C67F10E3CF; Mon, 12 Sep 2022 11:45:36 +0000 (UTC) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id A8FD310E3CF for ; Mon, 12 Sep 2022 11:45:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1662983126; x=1694519126; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=sQXK5AWu/ap6CKmyprkccl2f5GCFfsIlCn8SytwAkgc=; b=Po7AK2c8Qyzfe0KNRLyt9CiSB7a+FRJCd+v4J51xsj21kse9yFygYknP C77s2B+jEuIIiXhBw89VN1BZ52wgeMyoNEsEdoakDCJeA7A50Z/5u1z0H IommIFLX9uzKMCZrf6fnwc1mmSXG4GjCJQo1XUZssMXYoQ35b8dBgQ6Sf O40MUcBZdxo8XRHPxky8YZwhTpcKDM9ZodR3vYPukfoZOMivWXTRSAMWC xyNEg97YG06PUKBOKukhUWcDvKUah7QsTnR7PF4koOtGsmeC0YNIapX3P cCsgTM0jedsBiXyh0+wbW68JWojE9ka+/ik7NFSX4jrCk3TWiGA3lNpd9 Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10467"; a="359568561" X-IronPort-AV: E=Sophos;i="5.93,310,1654585200"; d="scan'208";a="359568561" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Sep 2022 04:45:26 -0700 X-IronPort-AV: E=Sophos;i="5.93,310,1654585200"; d="scan'208";a="646426197" Received: from abijaz-mobl.ger.corp.intel.com (HELO localhost) ([10.252.58.140]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Sep 2022 04:45:25 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Date: Mon, 12 Sep 2022 14:45:12 +0300 Message-Id: <536237d5bc919e8c97a96796f235f5bb264ceff2.1662983005.git.jani.nikula@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Subject: [Intel-gfx] [PATCH 1/5] drm/i915/ipc: refactor and rename IPC functions X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Rename the IPC functions to have skl_watermark_ipc_ prefix, rename enable to update to reflect what the function actually does, and add enabled function to abstract direct ->ipc_enabled access for state query. Signed-off-by: Jani Nikula Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 6 ++--- .../drm/i915/display/intel_display_debugfs.c | 6 ++--- drivers/gpu/drm/i915/display/skl_watermark.c | 25 +++++++++++-------- drivers/gpu/drm/i915/display/skl_watermark.h | 5 ++-- drivers/gpu/drm/i915/i915_driver.c | 2 +- 5 files changed, 24 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 2d0018ae34b1..a0829dcfd6d3 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -4779,7 +4779,7 @@ static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state) /* Display WA #1135: BXT:ALL GLK:ALL */ if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && - dev_priv->ipc_enabled) + skl_watermark_ipc_enabled(dev_priv)) linetime_wm /= 2; return min(linetime_wm, 0x1ff); @@ -8782,7 +8782,7 @@ int intel_modeset_init(struct drm_i915_private *i915) intel_hpd_init(i915); intel_hpd_poll_disable(i915); - intel_init_ipc(i915); + skl_watermark_ipc_init(i915); return 0; } @@ -8913,7 +8913,7 @@ void intel_display_resume(struct drm_device *dev) if (!ret) ret = __intel_display_resume(i915, state, &ctx); - intel_enable_ipc(i915); + skl_watermark_ipc_update(i915); drm_modeset_drop_locks(&ctx); drm_modeset_acquire_fini(&ctx); diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c index fe40e2a226d6..d2139cf4f825 100644 --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c @@ -988,7 +988,7 @@ static int i915_ipc_status_show(struct seq_file *m, void *data) struct drm_i915_private *dev_priv = m->private; seq_printf(m, "Isochronous Priority Control: %s\n", - str_yes_no(dev_priv->ipc_enabled)); + str_yes_no(skl_watermark_ipc_enabled(dev_priv))); return 0; } @@ -1016,11 +1016,11 @@ static ssize_t i915_ipc_status_write(struct file *file, const char __user *ubuf, return ret; with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref) { - if (!dev_priv->ipc_enabled && enable) + if (!skl_watermark_ipc_enabled(dev_priv) && enable) drm_info(&dev_priv->drm, "Enabling IPC: WM will be proper only after next commit\n"); dev_priv->ipc_enabled = enable; - intel_enable_ipc(dev_priv); + skl_watermark_ipc_update(dev_priv); } return len; diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c index cb297725d5b9..df505ca6ef91 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.c +++ b/drivers/gpu/drm/i915/display/skl_watermark.c @@ -1837,10 +1837,8 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state, * WaIncreaseLatencyIPCEnabled: kbl,cfl * Display WA #1141: kbl,cfl */ - if ((IS_KABYLAKE(i915) || - IS_COFFEELAKE(i915) || - IS_COMETLAKE(i915)) && - i915->ipc_enabled) + if ((IS_KABYLAKE(i915) || IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) && + skl_watermark_ipc_enabled(i915)) latency += 4; if (skl_needs_memory_bw_wa(i915) && wp->x_tiled) @@ -2008,7 +2006,7 @@ static void skl_compute_transition_wm(struct drm_i915_private *i915, u16 wm0_blocks, trans_offset, blocks; /* Transition WM don't make any sense if ipc is disabled */ - if (!i915->ipc_enabled) + if (!skl_watermark_ipc_enabled(i915)) return; /* @@ -3116,7 +3114,12 @@ void intel_wm_state_verify(struct intel_crtc *crtc, kfree(hw); } -void intel_enable_ipc(struct drm_i915_private *i915) +bool skl_watermark_ipc_enabled(struct drm_i915_private *i915) +{ + return i915->ipc_enabled; +} + +void skl_watermark_ipc_update(struct drm_i915_private *i915) { u32 val; @@ -3125,7 +3128,7 @@ void intel_enable_ipc(struct drm_i915_private *i915) val = intel_uncore_read(&i915->uncore, DISP_ARB_CTL2); - if (i915->ipc_enabled) + if (skl_watermark_ipc_enabled(i915)) val |= DISP_IPC_ENABLE; else val &= ~DISP_IPC_ENABLE; @@ -3133,7 +3136,7 @@ void intel_enable_ipc(struct drm_i915_private *i915) intel_uncore_write(&i915->uncore, DISP_ARB_CTL2, val); } -static bool intel_can_enable_ipc(struct drm_i915_private *i915) +static bool skl_watermark_ipc_can_enable(struct drm_i915_private *i915) { /* Display WA #0477 WaDisableIPC: skl */ if (IS_SKYLAKE(i915)) @@ -3148,14 +3151,14 @@ static bool intel_can_enable_ipc(struct drm_i915_private *i915) return true; } -void intel_init_ipc(struct drm_i915_private *i915) +void skl_watermark_ipc_init(struct drm_i915_private *i915) { if (!HAS_IPC(i915)) return; - i915->ipc_enabled = intel_can_enable_ipc(i915); + i915->ipc_enabled = skl_watermark_ipc_can_enable(i915); - intel_enable_ipc(i915); + skl_watermark_ipc_update(i915); } static void diff --git a/drivers/gpu/drm/i915/display/skl_watermark.h b/drivers/gpu/drm/i915/display/skl_watermark.h index 50da05932750..7e5adef0c510 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.h +++ b/drivers/gpu/drm/i915/display/skl_watermark.h @@ -44,8 +44,9 @@ void skl_wm_sanitize(struct drm_i915_private *i915); void intel_wm_state_verify(struct intel_crtc *crtc, struct intel_crtc_state *new_crtc_state); -void intel_enable_ipc(struct drm_i915_private *i915); -void intel_init_ipc(struct drm_i915_private *i915); +void skl_watermark_ipc_init(struct drm_i915_private *i915); +void skl_watermark_ipc_update(struct drm_i915_private *i915); +bool skl_watermark_ipc_enabled(struct drm_i915_private *i915); void skl_wm_init(struct drm_i915_private *i915); diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c index 8262bfb2a2d9..c459eb362c47 100644 --- a/drivers/gpu/drm/i915/i915_driver.c +++ b/drivers/gpu/drm/i915/i915_driver.c @@ -1756,7 +1756,7 @@ static int intel_runtime_resume(struct device *kdev) intel_hpd_poll_disable(dev_priv); } - intel_enable_ipc(dev_priv); + skl_watermark_ipc_update(dev_priv); enable_rpm_wakeref_asserts(rpm); From patchwork Mon Sep 12 11:45:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 12973593 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CA68FECAAD5 for ; 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X-IronPort-AV: E=McAfee;i="6500,9779,10467"; a="284865108" X-IronPort-AV: E=Sophos;i="5.93,310,1654585200"; d="scan'208";a="284865108" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Sep 2022 04:45:30 -0700 X-IronPort-AV: E=Sophos;i="5.93,310,1654585200"; d="scan'208";a="593460164" Received: from abijaz-mobl.ger.corp.intel.com (HELO localhost) ([10.252.58.140]) by orsmga006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Sep 2022 04:45:29 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Date: Mon, 12 Sep 2022 14:45:13 +0300 Message-Id: <9d59b18f5dc06e86a48c1ce0f40d625f51e3e85a.1662983005.git.jani.nikula@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Subject: [Intel-gfx] [PATCH 2/5] drm/i915/ipc: move IPC debugfs to skl_watermark.c X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Follow the new direction for debugfs files, moving the details where the implementation is. It seems quite natural skl_watermark.c is the place that controls IPC details, even for debugfs, not intel_display_debugfs.c. Rename the functions and convert dev_priv->i915 while at it. Signed-off-by: Jani Nikula --- .../drm/i915/display/intel_display_debugfs.c | 54 +--------------- drivers/gpu/drm/i915/display/skl_watermark.c | 61 +++++++++++++++++++ drivers/gpu/drm/i915/display/skl_watermark.h | 1 + 3 files changed, 63 insertions(+), 53 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c index d2139cf4f825..338e92889ace 100644 --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c @@ -983,58 +983,6 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused) return 0; } -static int i915_ipc_status_show(struct seq_file *m, void *data) -{ - struct drm_i915_private *dev_priv = m->private; - - seq_printf(m, "Isochronous Priority Control: %s\n", - str_yes_no(skl_watermark_ipc_enabled(dev_priv))); - return 0; -} - -static int i915_ipc_status_open(struct inode *inode, struct file *file) -{ - struct drm_i915_private *dev_priv = inode->i_private; - - if (!HAS_IPC(dev_priv)) - return -ENODEV; - - return single_open(file, i915_ipc_status_show, dev_priv); -} - -static ssize_t i915_ipc_status_write(struct file *file, const char __user *ubuf, - size_t len, loff_t *offp) -{ - struct seq_file *m = file->private_data; - struct drm_i915_private *dev_priv = m->private; - intel_wakeref_t wakeref; - bool enable; - int ret; - - ret = kstrtobool_from_user(ubuf, len, &enable); - if (ret < 0) - return ret; - - with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref) { - if (!skl_watermark_ipc_enabled(dev_priv) && enable) - drm_info(&dev_priv->drm, - "Enabling IPC: WM will be proper only after next commit\n"); - dev_priv->ipc_enabled = enable; - skl_watermark_ipc_update(dev_priv); - } - - return len; -} - -static const struct file_operations i915_ipc_status_fops = { - .owner = THIS_MODULE, - .open = i915_ipc_status_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, - .write = i915_ipc_status_write -}; - static int i915_ddb_info(struct seq_file *m, void *unused) { struct drm_i915_private *dev_priv = node_to_i915(m->private); @@ -1911,7 +1859,6 @@ static const struct { {"i915_dp_test_active", &i915_displayport_test_active_fops}, {"i915_hpd_storm_ctl", &i915_hpd_storm_ctl_fops}, {"i915_hpd_short_storm_ctl", &i915_hpd_short_storm_ctl_fops}, - {"i915_ipc_status", &i915_ipc_status_fops}, {"i915_drrs_ctl", &i915_drrs_ctl_fops}, {"i915_edp_psr_debug", &i915_edp_psr_debug_fops}, }; @@ -1935,6 +1882,7 @@ void intel_display_debugfs_register(struct drm_i915_private *i915) intel_dmc_debugfs_register(i915); intel_fbc_debugfs_register(i915); + skl_watermark_ipc_debugfs_register(i915); } static int i915_panel_show(struct seq_file *m, void *data) diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c index df505ca6ef91..1f0efde29d96 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.c +++ b/drivers/gpu/drm/i915/display/skl_watermark.c @@ -3465,3 +3465,64 @@ void intel_mbus_dbox_update(struct intel_atomic_state *state) intel_de_write(i915, PIPE_MBUS_DBOX_CTL(crtc->pipe), val); } } + +static int skl_watermark_ipc_status_show(struct seq_file *m, void *data) +{ + struct drm_i915_private *i915 = m->private; + + seq_printf(m, "Isochronous Priority Control: %s\n", + str_yes_no(skl_watermark_ipc_enabled(i915))); + return 0; +} + +static int skl_watermark_ipc_status_open(struct inode *inode, struct file *file) +{ + struct drm_i915_private *i915 = inode->i_private; + + if (!HAS_IPC(i915)) + return -ENODEV; + + return single_open(file, skl_watermark_ipc_status_show, i915); +} + +static ssize_t skl_watermark_ipc_status_write(struct file *file, + const char __user *ubuf, + size_t len, loff_t *offp) +{ + struct seq_file *m = file->private_data; + struct drm_i915_private *i915 = m->private; + intel_wakeref_t wakeref; + bool enable; + int ret; + + ret = kstrtobool_from_user(ubuf, len, &enable); + if (ret < 0) + return ret; + + with_intel_runtime_pm(&i915->runtime_pm, wakeref) { + if (!skl_watermark_ipc_enabled(i915) && enable) + drm_info(&i915->drm, + "Enabling IPC: WM will be proper only after next commit\n"); + i915->ipc_enabled = enable; + skl_watermark_ipc_update(i915); + } + + return len; +} + +static const struct file_operations skl_watermark_ipc_status_fops = { + .owner = THIS_MODULE, + .open = skl_watermark_ipc_status_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, + .write = skl_watermark_ipc_status_write +}; + +void skl_watermark_ipc_debugfs_register(struct drm_i915_private *i915) +{ + struct drm_minor *minor = i915->drm.primary; + + debugfs_create_file("i915_ipc_status", 0644, minor->debugfs_root, i915, + &skl_watermark_ipc_status_fops); +} diff --git a/drivers/gpu/drm/i915/display/skl_watermark.h b/drivers/gpu/drm/i915/display/skl_watermark.h index 7e5adef0c510..7a5a4e67cd73 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.h +++ b/drivers/gpu/drm/i915/display/skl_watermark.h @@ -47,6 +47,7 @@ void intel_wm_state_verify(struct intel_crtc *crtc, void skl_watermark_ipc_init(struct drm_i915_private *i915); void skl_watermark_ipc_update(struct drm_i915_private *i915); bool skl_watermark_ipc_enabled(struct drm_i915_private *i915); +void skl_watermark_ipc_debugfs_register(struct drm_i915_private *i915); void skl_wm_init(struct drm_i915_private *i915); From patchwork Mon Sep 12 11:45:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 12973592 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B59F2ECAAD5 for ; Mon, 12 Sep 2022 11:45:42 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4C89710E3D6; Mon, 12 Sep 2022 11:45:41 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id B46EA10E3CF for ; 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d="scan'208";a="678052190" Received: from abijaz-mobl.ger.corp.intel.com (HELO localhost) ([10.252.58.140]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Sep 2022 04:45:33 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Date: Mon, 12 Sep 2022 14:45:14 +0300 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Subject: [Intel-gfx] [PATCH 3/5] drm/i915/ipc: register debugfs only if IPC available X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" It looks like trying to enable IPC via debugfs on platforms that don't have IPC resulted in dmesg info message about IPC being enabled, which is clearly not possible and would not happen. Seems sensible to register IPC debugfs only on platforms that have IPC. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/skl_watermark.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c index 1f0efde29d96..fd9552f08422 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.c +++ b/drivers/gpu/drm/i915/display/skl_watermark.c @@ -3479,9 +3479,6 @@ static int skl_watermark_ipc_status_open(struct inode *inode, struct file *file) { struct drm_i915_private *i915 = inode->i_private; - if (!HAS_IPC(i915)) - return -ENODEV; - return single_open(file, skl_watermark_ipc_status_show, i915); } @@ -3523,6 +3520,9 @@ void skl_watermark_ipc_debugfs_register(struct drm_i915_private *i915) { struct drm_minor *minor = i915->drm.primary; + if (!HAS_IPC(i915)) + return; + debugfs_create_file("i915_ipc_status", 0644, minor->debugfs_root, i915, &skl_watermark_ipc_status_fops); } From patchwork Mon Sep 12 11:45:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 12973594 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 12676ECAAD5 for ; Mon, 12 Sep 2022 11:45:56 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 95EB310E3D9; Mon, 12 Sep 2022 11:45:54 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id B16FB10E3D6 for ; Mon, 12 Sep 2022 11:45:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1662983139; x=1694519139; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=FneB0dSjYm2IOF/GQ9ee3SwHnM/TH/lCMnupFVi2L6I=; b=lsf3aQqkmoLUXuJgRIpqXZYVMToAzknC3qEr+nrl9WUD3Sqzs+abfkth OfwwFjJVOpitzu08XuLCzx/GOfpTp/hiEPf4hUkjnO8gPPeI5ZA2bw4g1 tHXBot+FMyh1zt/qrXohGKiFCOEQ1ODheENJwfj+lWlRXVVSulTomUGjd epJhKqEW1OnZ9eXMh/7qtWMEko5VjEXJ8haQp+GARyVcknMrXDBpUxQa9 u2Yc4NKkPA38y6rpNKlY2sqoOfRlfevj80IAxZnGM/mapfIueVLVy6obs D71t5hAEHysytm608Njk5O/xQNaw+okytVx4/Sqre4dDHGtZ/ymRF4BFX A==; X-IronPort-AV: E=McAfee;i="6500,9779,10467"; a="299184212" X-IronPort-AV: E=Sophos;i="5.93,310,1654585200"; d="scan'208";a="299184212" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Sep 2022 04:45:39 -0700 X-IronPort-AV: E=Sophos;i="5.93,310,1654585200"; d="scan'208";a="944600356" Received: from abijaz-mobl.ger.corp.intel.com (HELO localhost) ([10.252.58.140]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Sep 2022 04:45:37 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Date: Mon, 12 Sep 2022 14:45:15 +0300 Message-Id: <04ccaaceee9293e5a6c75761ba9d36792c36f095.1662983005.git.jani.nikula@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Subject: [Intel-gfx] [PATCH 4/5] drm/i915/display: move IPC under display wm sub-struct X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Move display IPC related member under drm_i915_private display sub-struct. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display_core.h | 2 ++ drivers/gpu/drm/i915/display/skl_watermark.c | 6 +++--- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h index 9086a612365e..96cf994b0ad1 100644 --- a/drivers/gpu/drm/i915/display/intel_display_core.h +++ b/drivers/gpu/drm/i915/display/intel_display_core.h @@ -239,6 +239,8 @@ struct intel_wm { * crtc_state->wm.need_postvbl_update. */ struct mutex wm_mutex; + + bool ipc_enabled; }; struct intel_display { diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c index fd9552f08422..ab7fc41d325a 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.c +++ b/drivers/gpu/drm/i915/display/skl_watermark.c @@ -3116,7 +3116,7 @@ void intel_wm_state_verify(struct intel_crtc *crtc, bool skl_watermark_ipc_enabled(struct drm_i915_private *i915) { - return i915->ipc_enabled; + return i915->display.wm.ipc_enabled; } void skl_watermark_ipc_update(struct drm_i915_private *i915) @@ -3156,7 +3156,7 @@ void skl_watermark_ipc_init(struct drm_i915_private *i915) if (!HAS_IPC(i915)) return; - i915->ipc_enabled = skl_watermark_ipc_can_enable(i915); + i915->display.wm.ipc_enabled = skl_watermark_ipc_can_enable(i915); skl_watermark_ipc_update(i915); } @@ -3500,7 +3500,7 @@ static ssize_t skl_watermark_ipc_status_write(struct file *file, if (!skl_watermark_ipc_enabled(i915) && enable) drm_info(&i915->drm, "Enabling IPC: WM will be proper only after next commit\n"); - i915->ipc_enabled = enable; + i915->display.wm.ipc_enabled = enable; skl_watermark_ipc_update(i915); } From patchwork Mon Sep 12 11:45:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 12973595 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2197EECAAD5 for ; Mon, 12 Sep 2022 11:45:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id EA1FD10E3E4; Mon, 12 Sep 2022 11:45:54 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 66B0F10E3DE for ; Mon, 12 Sep 2022 11:45:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1662983143; x=1694519143; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=J5ofhfZojjMlNq8hungrqo4vsFVnoLTfrW6RiLoIAQE=; b=DPxXq+JWFXJUSiMUSN3e2MpXmK3sMr1etBjgNlObYLmswW5wWC5imtq5 vAXrnKI/PE2pmirZSVeIveHstCmg2+8/BIfT3NI2sznrMAZSxxPnvvyD0 2p6+JWt5h+yGxpBuIWj3DlAbxTt8++faCNTNOi6uHF1Aa1DNkH1DfDtm9 Ra3Z2JKNGsTbWTlZBgLoZAjPvcgdFuRPL8y83qu6t9Oebfxvm0dJVk81p gii5Xw3Q6ytvuR80Lej4Ah6FU9V2bDcrGMqbWizFSkOiT/3BsHTbbT6/G aMauEy9NrFEn1I1v7BVCZyLNOkM4BeTNItkjE+nkz9lLgGnrxfgMeqVXp A==; X-IronPort-AV: E=McAfee;i="6500,9779,10467"; a="299184217" X-IronPort-AV: E=Sophos;i="5.93,310,1654585200"; d="scan'208";a="299184217" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Sep 2022 04:45:43 -0700 X-IronPort-AV: E=Sophos;i="5.93,310,1654585200"; d="scan'208";a="646426295" Received: from abijaz-mobl.ger.corp.intel.com (HELO localhost) ([10.252.58.140]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Sep 2022 04:45:41 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Date: Mon, 12 Sep 2022 14:45:16 +0300 Message-Id: <113a17cd18401b0e4c83396575b67aa6efb07346.1662983005.git.jani.nikula@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Subject: [Intel-gfx] [PATCH 5/5] drm/i915/ipc: use intel_uncore_rmw() to enable/disable X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Don't duplicate the rmw function. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/skl_watermark.c | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c index ab7fc41d325a..c70d811163f6 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.c +++ b/drivers/gpu/drm/i915/display/skl_watermark.c @@ -3121,19 +3121,11 @@ bool skl_watermark_ipc_enabled(struct drm_i915_private *i915) void skl_watermark_ipc_update(struct drm_i915_private *i915) { - u32 val; - if (!HAS_IPC(i915)) return; - val = intel_uncore_read(&i915->uncore, DISP_ARB_CTL2); - - if (skl_watermark_ipc_enabled(i915)) - val |= DISP_IPC_ENABLE; - else - val &= ~DISP_IPC_ENABLE; - - intel_uncore_write(&i915->uncore, DISP_ARB_CTL2, val); + intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL2, DISP_IPC_ENABLE, + skl_watermark_ipc_enabled(i915) ? DISP_IPC_ENABLE : 0); } static bool skl_watermark_ipc_can_enable(struct drm_i915_private *i915)