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Tue, 13 Sep 2022 01:24:54 -0700 From: Nicolin Chen To: , , , , , , , , , , , , , , , , , , CC: , , , , , , , , , , , , , , , , Subject: [PATCH 1/5] iommu/msm: Add missing __disable_clocks calls Date: Tue, 13 Sep 2022 01:24:44 -0700 Message-ID: <20220913082448.31120-2-nicolinc@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220913082448.31120-1-nicolinc@nvidia.com> References: <20220913082448.31120-1-nicolinc@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT032:EE_|DS0PR12MB6463:EE_ X-MS-Office365-Filtering-Correlation-Id: 2aab0ddb-ed9f-4596-e82e-08da9561716a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: /T5ilKBQ6RgvNbgtzksVs9px3xVmWgQMKCOi0OhstYeyHYRM8UaBxhnpiHcGrb/0wy4x7JJGrdKsPyHmrbW7W1/iZlOA38xS1zs4V+qbmdMNSAFXrBDLZ3wZX/+AHlvw2yGSo3MrgJjQnMPHlmLwWd4dyPNYsSFz4UQsFZrwXMY2LPWoPNgVtUvV3s4un5Fh1DaLLPiIQxbJBmPnVmSvpRmGB3pcedoUUZNu13mQKqrtnL0Wxx+ysRRQc8Rn9by6Fb4zRNoNoJHWC6ed9gpPcEZ5zF4t1gEVnjD0F+1FalUnyB8zf4WRRH8093hoX0seSj7TiU9Jldjs6bQ1VQXtm4ReIIiHQUUrHZcwFYBxHaB9A1lBVYGEGHhXysqr0JvbjO9TZipGLQRDPuZWfCZhN6gZPrOI262uVJx43YalzCmd6IEqm0waQ7+qCLEkx8dhANUL3rfJuCMTZuvvMb8L7DkDHwVSxCeZuVeY5hz41CJNaObmiyu9yZoqwmoG/Tsfry/50A1iIB3x2vXX3rg6jX81txHEs44e+ND8SRYkwJj3NoKNiGLjTJ/3UJQAt4y/yonsmomm5zIcwzhPDe3pZbeugP2rY3ld7ezMg159omcZimBD7aSnzoWh5WThzfhove8zTLLQTFCWx2NrH+OJzFZaM/dv4L2juPMZ7IGyasHfQhAItUOFi3FUlbY6H4BU5VpO9HP7SEhqSBR2GVZF9ylu7NHRyG67e6f1sIxu+2csJNBzS3Lbr7IGYPec632aXPwLBlH9ntiM6prBQIbeibODn4y6FSsz+PWy9Ux+kHQd5WxTVs09THGdYgFGAZDZ6beQvR9lvmNoNGa8Q6PSABIcSgEFv/ZpM6meJ5wbgqloRuwURswKQH66cdo/jf31 X-Forefront-Antispam-Report: CIP:12.22.5.236;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(13230022)(4636009)(39860400002)(376002)(346002)(396003)(136003)(451199015)(46966006)(40470700004)(36840700001)(186003)(83380400001)(86362001)(82740400003)(82310400005)(40460700003)(2616005)(8936002)(1076003)(7416002)(316002)(336012)(8676002)(40480700001)(36756003)(81166007)(356005)(4326008)(26005)(110136005)(41300700001)(7696005)(36860700001)(7406005)(921005)(2906002)(54906003)(6666004)(47076005)(426003)(70206006)(478600001)(70586007)(5660300002)(2101003)(36900700001)(83996005);DIR:OUT;SFP:1101; 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X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org The clock is not symmetrically disabled in the error-out routines. Fixes: 109bd48ea2e1 ("iommu/msm: Add DT adaptation") Cc: stable@vger.kernel.org Cc: Sricharan R Cc: Andy Gross Cc: Bjorn Andersson Cc: Konrad Dybcio Signed-off-by: Nicolin Chen --- drivers/iommu/msm_iommu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/iommu/msm_iommu.c b/drivers/iommu/msm_iommu.c index 6a24aa804ea3..a7d41ba4a47b 100644 --- a/drivers/iommu/msm_iommu.c +++ b/drivers/iommu/msm_iommu.c @@ -418,6 +418,7 @@ static int msm_iommu_attach_dev(struct iommu_domain *domain, struct device *dev) list_for_each_entry(master, &iommu->ctx_list, list) { if (master->num) { dev_err(dev, "domain already attached"); + __disable_clocks(iommu); ret = -EEXIST; goto fail; } @@ -425,6 +426,7 @@ static int msm_iommu_attach_dev(struct iommu_domain *domain, struct device *dev) msm_iommu_alloc_ctx(iommu->context_map, 0, iommu->ncb); if (IS_ERR_VALUE(master->num)) { + __disable_clocks(iommu); ret = -ENODEV; goto fail; } From patchwork Tue Sep 13 08:24:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 12974542 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 48B44C6FA82 for ; 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Tue, 13 Sep 2022 08:24:58 +0000 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail203.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Tue, 13 Sep 2022 01:24:57 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.11) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.986.29 via Frontend Transport; Tue, 13 Sep 2022 01:24:56 -0700 From: Nicolin Chen To: , , , , , , , , , , , , , , , , , , CC: , , , , , , , , , , , , , , , , Subject: [PATCH 2/5] iommu/amd: Drop unnecessary checks in amd_iommu_attach_device() Date: Tue, 13 Sep 2022 01:24:45 -0700 Message-ID: <20220913082448.31120-3-nicolinc@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220913082448.31120-1-nicolinc@nvidia.com> References: <20220913082448.31120-1-nicolinc@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000B8E9:EE_|DM4PR12MB5745:EE_ X-MS-Office365-Filtering-Correlation-Id: 730928f1-b9bc-43d6-0d14-08da9561728b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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If any of them fails there, then the device won't get a group, so there's no way for it to even reach amd_iommu_attach_device any more. Suggested-by: Robin Murphy Cc: Joerg Roedel Cc: Suravee Suthikulpanit Signed-off-by: Nicolin Chen --- drivers/iommu/amd/iommu.c | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 828672a46a3d..930d9946b9f7 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -2135,21 +2135,13 @@ static void amd_iommu_detach_device(struct iommu_domain *dom, static int amd_iommu_attach_device(struct iommu_domain *dom, struct device *dev) { + struct iommu_dev_data *dev_data = dev_iommu_priv_get(dev); struct protection_domain *domain = to_pdomain(dom); - struct iommu_dev_data *dev_data; - struct amd_iommu *iommu; + struct amd_iommu *iommu = rlookup_amd_iommu(dev); int ret; - if (!check_device(dev)) - return -EINVAL; - - dev_data = dev_iommu_priv_get(dev); dev_data->defer_attach = false; - iommu = rlookup_amd_iommu(dev); - if (!iommu) - return -EINVAL; - if (dev_data->domain) detach_device(dev); From patchwork Tue Sep 13 08:24:46 2022 Content-Type: text/plain; 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Tue, 13 Sep 2022 01:24:58 -0700 From: Nicolin Chen To: , , , , , , , , , , , , , , , , , , CC: , , , , , , , , , , , , , , , , Subject: [PATCH 3/5] iommu: Add return errno rules to ->attach_dev ops Date: Tue, 13 Sep 2022 01:24:46 -0700 Message-ID: <20220913082448.31120-4-nicolinc@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220913082448.31120-1-nicolinc@nvidia.com> References: <20220913082448.31120-1-nicolinc@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT087:EE_|BN9PR12MB5244:EE_ X-MS-Office365-Filtering-Correlation-Id: e4a303aa-49a3-482a-f547-08da956173cf X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: kQeY4K4dpFGNjBMs9GkjFgZblTv6JStd191oDA1OyxEwHYZRLkHwreiYt1rOEGixZ68HlvYkvUiST1b84fPa3sRVdsEAs274xg/BdDWUcy6hGdTcMOJjxJlzAR4MvcohcQkKZnDwSpE/35zpUCdLMg3w8BifWM4Uf5LZ9LuEBwMmwedOF5ORmUb3fj5iCY2TfDPFMsClgTRb2rMBpl3K9xY1iqi1fc5Lsv9MuPiIkJXtkHlk6bNA6MGFS91kd2VSKkj3C6pUPqpJ3oZxQ8l1z0+MLztocce3M5OvX+cQrFokG30JbaP2ikfid3RuLxDYvSAJSnzksEI0lZfiZ58C9dsTbS+mOOG+4XSeAR4ZvecmWp0iPSp7Zjv/MEG8x3ZjXP+JK/BH0TwW4JLrnt63IWX43xh0ex/VIxZdL+PS4REQMYSsPbsamu0sfPJYmJtO3XKqy1JIaUejc3tgjdLG49zI0fQd7Oqh6vfAWB1+apCEo5RM+TBXyFrcXK5AqRk3L+oA5gZd+9MOwwHoHlSC5wT/+EZYhBuBZffRE3rDSe2NImLI692oKXFzNVoOojjsmwMOs4vovfSOH0SDs5D7rd6jDGAma1KycCNx6eeKw0n2T0I78UnqdicE7cmfFytLBJR6+1K4JdQzJRpu6cPJ6Lw/DDF+tqhRko1pdrvyaYvDv7/CL+/ZjBfVRtOvsrzUV9q9XNtD84LfB1PqdgcICFjBlHOqxbnli03t0zu0US6nhjXlueO9DS+fpT7T2V+yMtzVqRMquGcNGUgR2KUtT7pOyqQu1kMDLIN5W32oeVK5P1Utmtywg0i8d3wTpDy3XOHtw4tmNbq9Og3vYGlvsDRMWu6IFR2U/t2AsgVUknrXdr0YftnTFlJoeEL8sSVa X-Forefront-Antispam-Report: CIP:12.22.5.234;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(13230022)(4636009)(136003)(376002)(346002)(39860400002)(396003)(451199015)(46966006)(40470700004)(36840700001)(316002)(5660300002)(70206006)(40460700003)(7416002)(186003)(426003)(7696005)(40480700001)(336012)(478600001)(36756003)(82310400005)(4326008)(110136005)(47076005)(921005)(83380400001)(1076003)(356005)(8676002)(7406005)(36860700001)(70586007)(2616005)(41300700001)(26005)(2906002)(86362001)(54906003)(82740400003)(6666004)(81166007)(8936002)(36900700001)(2101003)(83996005);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Sep 2022 08:25:01.1846 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e4a303aa-49a3-482a-f547-08da956173cf X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.234];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT087.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN9PR12MB5244 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220913_012508_122793_AAAF0EF3 X-CRM114-Status: GOOD ( 17.19 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Cases like VFIO wish to attach a device to an existing domain that was not allocated specifically from the device. This raises a condition where the IOMMU driver can fail the domain attach because the domain and device are incompatible with each other. This is a soft failure that can be resolved by using a different domain. Provide a dedicated errno EINVAL from the IOMMU driver during attach that the reason attached failed is because of domain incompatability. VFIO can use this to know attach is a soft failure and it should continue searching. Otherwise the attach will be a hard failure and VFIO will return the code to userspace. Update kdocs first to add rules of return errno to ->attach_dev ops. Suggested-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- include/linux/iommu.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/include/linux/iommu.h b/include/linux/iommu.h index ea30f00dc145..c5d7ec0187c7 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -266,6 +266,17 @@ struct iommu_ops { /** * struct iommu_domain_ops - domain specific operations * @attach_dev: attach an iommu domain to a device + * Rules of its return errno: + * EINVAL - Exclusively, device and domain are incompatible. Must + * avoid kernel prints along with this errno. Any EINVAL + * returned from kAPIs must be converted to ENODEV if it + * is device-specific, or to some other reasonable errno + * being listed below + * ENOMEM - Out of memory + * ENOSPC - No space left on device + * EBUSY - Device is attached to a domain and cannot be changed + * ENODEV - Device specific errors, not able to be attached + * - Treated as ENODEV by the caller. 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Tue, 13 Sep 2022 01:25:00 -0700 From: Nicolin Chen To: , , , , , , , , , , , , , , , , , , CC: , , , , , , , , , , , , , , , , Subject: [PATCH 4/5] iommu: Regulate errno in ->attach_dev callback functions Date: Tue, 13 Sep 2022 01:24:47 -0700 Message-ID: <20220913082448.31120-5-nicolinc@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220913082448.31120-1-nicolinc@nvidia.com> References: <20220913082448.31120-1-nicolinc@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT039:EE_|SN7PR12MB6768:EE_ X-MS-Office365-Filtering-Correlation-Id: d4f47266-f13c-409d-e7b2-08da956174b9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: zTMyQHbXTZYphVPHRK4ym81oC8rXwm3Pi3lVaiqgGwZA2hdjwD3k4Th4ti/kZ+Pb9JS5VhBnuBfbej/Yl6gWqVvAgiFKCO3dpr/1qNTgMzbV2DWO5WeEeSXbKudnDOdft0Y4mjPT9VACtDROmny0sgusIUTItfkbaSqrx52FRmFuvkyD6biQFaeoIl0mCXNbfHCqTDBddNKnGjGIXoc8jzreiryycQhAMHEX6fqv5j1o7ryII8QDxxo7XFdliVwhDh8mnqW5SfF5z9I5/481hySZ3svDyZMUq3WpBfpM23TUmmPe/wNmQlHh+f5MNn51PVFDGSyJD680ADHoQOjDc2vhYlK5N0ubTWoTdlosSoy/qTSMN3BF2GScC+/ynsPjLw7s4wZBqtQIQvzUVv2tdJXKkzTVWEZHtFVkVIN2cmj51NqmdaHafFBSeFSgNngyQmsiUgM5fQueiX9sYvHm23sqKO3qCTe+aTsU35od0Vm6CKDIJFARiqx8mWjok4L+Mq0vkkdFGZhCizm0b8OXwD9zhybzL8Gi/EKrIC2r3hAO6I+QcpTkoxYZEwLVXcFmwuDcEESa406Y8bLYUvvqr1IYwZZM5XwtApiyKOr2XZSukKaHTPcRr8pARE9jJ6Qq0oyyH76d1FCuidBWIVXvibvA0RDxbsr7DEjwzCciyShFQmEoyVv/x2BQ+66fwJy++rntOJXvUtzGgtC8/6uMXrgHeZG4mfJIuTJp+hou5A693F9JMM4GlpGo54Rc6rHlBzy9aziSGsNXssc16sCOJ1rE6ET2A9mKxw5L5mmkAncaSWYeaOwwmU4szAAplO54rJ//UqwftLueLWvZJmUEYwdtsM4DykISGlKplX0gnOU= X-Forefront-Antispam-Report: CIP:12.22.5.235;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(13230022)(4636009)(346002)(136003)(396003)(39860400002)(376002)(451199015)(40470700004)(46966006)(36840700001)(41300700001)(2616005)(336012)(426003)(186003)(82740400003)(7406005)(4326008)(110136005)(70586007)(8676002)(478600001)(7416002)(8936002)(40480700001)(70206006)(81166007)(54906003)(1076003)(36860700001)(6666004)(40460700003)(82310400005)(356005)(47076005)(316002)(26005)(83380400001)(7696005)(5660300002)(36756003)(2906002)(921005)(86362001)(83996005)(2101003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Sep 2022 08:25:02.7334 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d4f47266-f13c-409d-e7b2-08da956174b9 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.235];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT039.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB6768 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220913_012507_972797_B84C22A2 X-CRM114-Status: GOOD ( 19.12 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Following the new rules in include/linux/iommu.h kdocs, update all drivers ->attach_dev callback functions to return ENODEV error code for all device specific errors. It particularly excludes EINVAL from being used for such error cases. For the same purpose, also replace one EINVAL with ENOMEM in mtk_iommu driver. Note that the virtio-iommu does a viommu_domain_map_identity() call, which returns either 0 or ENOMEM at this moment. Change to "return ret" directly to allow it to pass an EINVAL in the future. Signed-off-by: Nicolin Chen Signed-off-by: Jean-Philippe Brucker --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 2 +- drivers/iommu/arm/arm-smmu/arm-smmu.c | 4 ++-- drivers/iommu/arm/arm-smmu/qcom_iommu.c | 2 +- drivers/iommu/fsl_pamu.c | 6 +++--- drivers/iommu/fsl_pamu_domain.c | 4 ++-- drivers/iommu/intel/pasid.c | 2 +- drivers/iommu/ipmmu-vmsa.c | 2 +- drivers/iommu/mtk_iommu.c | 9 ++++++--- drivers/iommu/omap-iommu.c | 4 ++-- drivers/iommu/rockchip-iommu.c | 4 +++- drivers/iommu/tegra-smmu.c | 2 +- drivers/iommu/virtio-iommu.c | 2 +- 12 files changed, 24 insertions(+), 19 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index d32b02336411..0186dfdf31fe 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2402,7 +2402,7 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) struct arm_smmu_master *master; if (!fwspec) - return -ENOENT; + return -ENODEV; master = dev_iommu_priv_get(dev); smmu = master->smmu; diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c index dfa82df00342..771dd161545c 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c @@ -1137,7 +1137,7 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) if (!fwspec || fwspec->ops != &arm_smmu_ops) { dev_err(dev, "cannot attach to SMMU, is it on the same bus?\n"); - return -ENXIO; + return -ENODEV; } /* @@ -1155,7 +1155,7 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) ret = arm_smmu_rpm_get(smmu); if (ret < 0) - return ret; + return -ENODEV; /* Ensure that the domain is finalised */ ret = arm_smmu_init_domain_context(domain, smmu, dev); diff --git a/drivers/iommu/arm/arm-smmu/qcom_iommu.c b/drivers/iommu/arm/arm-smmu/qcom_iommu.c index 17235116d3bb..49d40c80afd3 100644 --- a/drivers/iommu/arm/arm-smmu/qcom_iommu.c +++ b/drivers/iommu/arm/arm-smmu/qcom_iommu.c @@ -367,7 +367,7 @@ static int qcom_iommu_attach_dev(struct iommu_domain *domain, struct device *dev if (!qcom_iommu) { dev_err(dev, "cannot attach to IOMMU, is it on the same bus?\n"); - return -ENXIO; + return -ENODEV; } /* Ensure that the domain is finalized */ diff --git a/drivers/iommu/fsl_pamu.c b/drivers/iommu/fsl_pamu.c index 0d03f837a5d4..021ab3f9e6d2 100644 --- a/drivers/iommu/fsl_pamu.c +++ b/drivers/iommu/fsl_pamu.c @@ -126,7 +126,7 @@ int pamu_disable_liodn(int liodn) ppaace = pamu_get_ppaace(liodn); if (!ppaace) { pr_debug("Invalid primary paace entry\n"); - return -ENOENT; + return -ENODEV; } set_bf(ppaace->addr_bitfields, PAACE_AF_V, PAACE_V_INVALID); @@ -194,7 +194,7 @@ int pamu_config_ppaace(int liodn, u32 omi, u32 stashid, int prot) ppaace = pamu_get_ppaace(liodn); if (!ppaace) - return -ENOENT; + return -ENODEV; /* window size is 2^(WSE+1) bytes */ set_bf(ppaace->addr_bitfields, PPAACE_AF_WSE, @@ -211,7 +211,7 @@ int pamu_config_ppaace(int liodn, u32 omi, u32 stashid, int prot) ppaace->op_encode.index_ot.omi = omi; } else if (~omi != 0) { pr_debug("bad operation mapping index: %d\n", omi); - return -EINVAL; + return -ENODEV; } /* configure stash id */ diff --git a/drivers/iommu/fsl_pamu_domain.c b/drivers/iommu/fsl_pamu_domain.c index 011f9ab7f743..b4a1c0f79c3e 100644 --- a/drivers/iommu/fsl_pamu_domain.c +++ b/drivers/iommu/fsl_pamu_domain.c @@ -258,7 +258,7 @@ static int fsl_pamu_attach_device(struct iommu_domain *domain, liodn = of_get_property(dev->of_node, "fsl,liodn", &len); if (!liodn) { pr_debug("missing fsl,liodn property at %pOF\n", dev->of_node); - return -EINVAL; + return -ENODEV; } spin_lock_irqsave(&dma_domain->domain_lock, flags); @@ -267,7 +267,7 @@ static int fsl_pamu_attach_device(struct iommu_domain *domain, if (liodn[i] >= PAACE_NUMBER_ENTRIES) { pr_debug("Invalid liodn %d, attach device failed for %pOF\n", liodn[i], dev->of_node); - ret = -EINVAL; + ret = -ENODEV; break; } diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c index c5e7e8b020a5..712c7f3960e5 100644 --- a/drivers/iommu/intel/pasid.c +++ b/drivers/iommu/intel/pasid.c @@ -102,7 +102,7 @@ int intel_pasid_alloc_table(struct device *dev) might_sleep(); info = dev_iommu_priv_get(dev); if (WARN_ON(!info || !dev_is_pci(dev) || info->pasid_table)) - return -EINVAL; + return -ENODEV; pasid_table = kzalloc(sizeof(*pasid_table), GFP_KERNEL); if (!pasid_table) diff --git a/drivers/iommu/ipmmu-vmsa.c b/drivers/iommu/ipmmu-vmsa.c index 1d42084d0276..cb14abcfa43a 100644 --- a/drivers/iommu/ipmmu-vmsa.c +++ b/drivers/iommu/ipmmu-vmsa.c @@ -607,7 +607,7 @@ static int ipmmu_attach_device(struct iommu_domain *io_domain, if (!mmu) { dev_err(dev, "Cannot attach to IPMMU\n"); - return -ENXIO; + return -ENODEV; } mutex_lock(&domain->mutex); diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index 7e363b1f24df..dcfe728a4526 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -562,10 +562,12 @@ static int mtk_iommu_config(struct mtk_iommu_data *data, struct device *dev, peri_mmuen = enable ? peri_mmuen_msk : 0; ret = regmap_update_bits(data->pericfg, PERICFG_IOMMU_1, peri_mmuen_msk, peri_mmuen); - if (ret) + if (ret) { dev_err(dev, "%s iommu(%s) inframaster 0x%x fail(%d).\n", enable ? "enable" : "disable", dev_name(data->dev), peri_mmuen_msk, ret); + ret = -ENODEV; + } } } return ret; @@ -607,7 +609,7 @@ static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom, dom->iop = alloc_io_pgtable_ops(ARM_V7S, &dom->cfg, data); if (!dom->iop) { dev_err(data->dev, "Failed to alloc io pgtable\n"); - return -EINVAL; + return -ENOMEM; } /* Update our support page sizes bitmap */ @@ -655,7 +657,7 @@ static int mtk_iommu_attach_device(struct iommu_domain *domain, region_id = mtk_iommu_get_iova_region_id(dev, data->plat_data); if (region_id < 0) - return region_id; + return -ENODEV; bankid = mtk_iommu_get_bank_id(dev, data->plat_data); mutex_lock(&dom->mutex); @@ -678,6 +680,7 @@ static int mtk_iommu_attach_device(struct iommu_domain *domain, ret = pm_runtime_resume_and_get(m4udev); if (ret < 0) { dev_err(m4udev, "pm get fail(%d) in attach.\n", ret); + ret = -ENODEV; goto err_unlock; } diff --git a/drivers/iommu/omap-iommu.c b/drivers/iommu/omap-iommu.c index d9cf2820c02e..447e40d55918 100644 --- a/drivers/iommu/omap-iommu.c +++ b/drivers/iommu/omap-iommu.c @@ -1414,7 +1414,7 @@ static int omap_iommu_attach_init(struct device *dev, odomain->num_iommus = omap_iommu_count(dev); if (!odomain->num_iommus) - return -EINVAL; + return -ENODEV; odomain->iommus = kcalloc(odomain->num_iommus, sizeof(*iommu), GFP_ATOMIC); @@ -1464,7 +1464,7 @@ omap_iommu_attach_dev(struct iommu_domain *domain, struct device *dev) if (!arch_data || !arch_data->iommu_dev) { dev_err(dev, "device doesn't have an associated iommu\n"); - return -EINVAL; + return -ENODEV; } spin_lock(&omap_domain->lock); diff --git a/drivers/iommu/rockchip-iommu.c b/drivers/iommu/rockchip-iommu.c index ab57c4b8fade..de483b5532ed 100644 --- a/drivers/iommu/rockchip-iommu.c +++ b/drivers/iommu/rockchip-iommu.c @@ -1051,8 +1051,10 @@ static int rk_iommu_attach_device(struct iommu_domain *domain, return 0; ret = rk_iommu_enable(iommu); - if (ret) + if (ret) { rk_iommu_detach_device(iommu->domain, dev); + ret = -ENODEV; + } pm_runtime_put(iommu->dev); diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c index 2a8de975fe63..093c10db4cb4 100644 --- a/drivers/iommu/tegra-smmu.c +++ b/drivers/iommu/tegra-smmu.c @@ -487,7 +487,7 @@ static int tegra_smmu_attach_dev(struct iommu_domain *domain, int err; if (!fwspec) - return -ENOENT; + return -ENODEV; for (index = 0; index < fwspec->num_ids; index++) { err = tegra_smmu_as_prepare(smmu, as); diff --git a/drivers/iommu/virtio-iommu.c b/drivers/iommu/virtio-iommu.c index 80151176ba12..874c01634d2b 100644 --- a/drivers/iommu/virtio-iommu.c +++ b/drivers/iommu/virtio-iommu.c @@ -696,7 +696,7 @@ static int viommu_domain_finalise(struct viommu_endpoint *vdev, if (ret) { ida_free(&viommu->domain_ids, vdomain->id); vdomain->viommu = NULL; - return -EOPNOTSUPP; + return ret; } } From patchwork Tue Sep 13 08:24:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 12974545 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E0A2EC6FA82 for ; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Sep 2022 08:25:07.0978 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d3b1a77a-d97d-4e80-398d-08da95617794 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.235];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0000B073.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6668 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220913_012514_367943_90DF760F X-CRM114-Status: GOOD ( 17.67 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Following the new rules in include/linux/iommu.h kdocs, update all drivers ->attach_dev callback functions to return EINVAL in the failure paths that are related to domain incompatibility. Also drop adjacent error prints to prevent a kernel log spam, since EINVAL exclusively means an incompatibility error. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 11 +---------- drivers/iommu/arm/arm-smmu/arm-smmu.c | 3 --- drivers/iommu/arm/arm-smmu/qcom_iommu.c | 7 +------ drivers/iommu/intel/iommu.c | 10 +++------- drivers/iommu/ipmmu-vmsa.c | 2 -- drivers/iommu/omap-iommu.c | 2 +- drivers/iommu/sprd-iommu.c | 4 +--- drivers/iommu/tegra-gart.c | 2 +- drivers/iommu/virtio-iommu.c | 4 ++-- 9 files changed, 10 insertions(+), 35 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 0186dfdf31fe..8b5a2e8de7e2 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2429,23 +2429,14 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) goto out_unlock; } } else if (smmu_domain->smmu != smmu) { - dev_err(dev, - "cannot attach to SMMU %s (upstream of %s)\n", - dev_name(smmu_domain->smmu->dev), - dev_name(smmu->dev)); - ret = -ENXIO; + ret = -EINVAL; goto out_unlock; } else if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1 && master->ssid_bits != smmu_domain->s1_cfg.s1cdmax) { - dev_err(dev, - "cannot attach to incompatible domain (%u SSID bits != %u)\n", - smmu_domain->s1_cfg.s1cdmax, master->ssid_bits); ret = -EINVAL; goto out_unlock; } else if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1 && smmu_domain->stall_enabled != master->stall_enabled) { - dev_err(dev, "cannot attach to stall-%s domain\n", - smmu_domain->stall_enabled ? "enabled" : "disabled"); ret = -EINVAL; goto out_unlock; } diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c index 771dd161545c..63a488f2f16c 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c @@ -1167,9 +1167,6 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) * different SMMUs. */ if (smmu_domain->smmu != smmu) { - dev_err(dev, - "cannot attach to SMMU %s whilst already attached to domain on SMMU %s\n", - dev_name(smmu_domain->smmu->dev), dev_name(smmu->dev)); ret = -EINVAL; goto rpm_put; } diff --git a/drivers/iommu/arm/arm-smmu/qcom_iommu.c b/drivers/iommu/arm/arm-smmu/qcom_iommu.c index 49d40c80afd3..542fa8c4b6cb 100644 --- a/drivers/iommu/arm/arm-smmu/qcom_iommu.c +++ b/drivers/iommu/arm/arm-smmu/qcom_iommu.c @@ -381,13 +381,8 @@ static int qcom_iommu_attach_dev(struct iommu_domain *domain, struct device *dev * Sanity check the domain. We don't support domains across * different IOMMUs. */ - if (qcom_domain->iommu != qcom_iommu) { - dev_err(dev, "cannot attach to IOMMU %s while already " - "attached to domain on IOMMU %s\n", - dev_name(qcom_domain->iommu->dev), - dev_name(qcom_iommu->dev)); + if (qcom_domain->iommu != qcom_iommu) return -EINVAL; - } return 0; } diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index 1f2cd43cf9bc..51ef42b1bd4e 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -4158,19 +4158,15 @@ static int prepare_domain_attach_device(struct iommu_domain *domain, return -ENODEV; if (dmar_domain->force_snooping && !ecap_sc_support(iommu->ecap)) - return -EOPNOTSUPP; + return -EINVAL; /* check if this iommu agaw is sufficient for max mapped address */ addr_width = agaw_to_width(iommu->agaw); if (addr_width > cap_mgaw(iommu->cap)) addr_width = cap_mgaw(iommu->cap); - if (dmar_domain->max_addr > (1LL << addr_width)) { - dev_err(dev, "%s: iommu width (%d) is not " - "sufficient for the mapped address (%llx)\n", - __func__, addr_width, dmar_domain->max_addr); - return -EFAULT; - } + if (dmar_domain->max_addr > (1LL << addr_width)) + return -EINVAL; dmar_domain->gaw = addr_width; /* diff --git a/drivers/iommu/ipmmu-vmsa.c b/drivers/iommu/ipmmu-vmsa.c index cb14abcfa43a..cb8ce8af0bff 100644 --- a/drivers/iommu/ipmmu-vmsa.c +++ b/drivers/iommu/ipmmu-vmsa.c @@ -628,8 +628,6 @@ static int ipmmu_attach_device(struct iommu_domain *io_domain, * Something is wrong, we can't attach two devices using * different IOMMUs to the same domain. */ - dev_err(dev, "Can't attach IPMMU %s to domain on IPMMU %s\n", - dev_name(mmu->dev), dev_name(domain->mmu->dev)); ret = -EINVAL; } else dev_info(dev, "Reusing IPMMU context %u\n", domain->context_id); diff --git a/drivers/iommu/omap-iommu.c b/drivers/iommu/omap-iommu.c index 447e40d55918..be12f49140c7 100644 --- a/drivers/iommu/omap-iommu.c +++ b/drivers/iommu/omap-iommu.c @@ -1472,7 +1472,7 @@ omap_iommu_attach_dev(struct iommu_domain *domain, struct device *dev) /* only a single client device can be attached to a domain */ if (omap_domain->dev) { dev_err(dev, "iommu domain is already attached\n"); - ret = -EBUSY; + ret = -EINVAL; goto out; } diff --git a/drivers/iommu/sprd-iommu.c b/drivers/iommu/sprd-iommu.c index 511959c8a14d..945576039c9e 100644 --- a/drivers/iommu/sprd-iommu.c +++ b/drivers/iommu/sprd-iommu.c @@ -237,10 +237,8 @@ static int sprd_iommu_attach_device(struct iommu_domain *domain, struct sprd_iommu_domain *dom = to_sprd_domain(domain); size_t pgt_size = sprd_iommu_pgt_size(domain); - if (dom->sdev) { - pr_err("There's already a device attached to this domain.\n"); + if (dom->sdev) return -EINVAL; - } dom->pgt_va = dma_alloc_coherent(sdev->dev, pgt_size, &dom->pgt_pa, GFP_KERNEL); if (!dom->pgt_va) diff --git a/drivers/iommu/tegra-gart.c b/drivers/iommu/tegra-gart.c index e5ca3cf1a949..ed53279d1106 100644 --- a/drivers/iommu/tegra-gart.c +++ b/drivers/iommu/tegra-gart.c @@ -112,7 +112,7 @@ static int gart_iommu_attach_dev(struct iommu_domain *domain, spin_lock(&gart->dom_lock); if (gart->active_domain && gart->active_domain != domain) { - ret = -EBUSY; + ret = -EINVAL; } else if (dev_iommu_priv_get(dev) != domain) { dev_iommu_priv_set(dev, domain); gart->active_domain = domain; diff --git a/drivers/iommu/virtio-iommu.c b/drivers/iommu/virtio-iommu.c index 874c01634d2b..a252cd1daf70 100644 --- a/drivers/iommu/virtio-iommu.c +++ b/drivers/iommu/virtio-iommu.c @@ -733,8 +733,8 @@ static int viommu_attach_dev(struct iommu_domain *domain, struct device *dev) */ ret = viommu_domain_finalise(vdev, domain); } else if (vdomain->viommu != vdev->viommu) { - dev_err(dev, "cannot attach to foreign vIOMMU\n"); - ret = -EXDEV; + /* cannot attach to foreign vIOMMU */ + ret = -EINVAL; } mutex_unlock(&vdomain->mutex);