From patchwork Fri Sep 16 08:50:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Souradeep Chowdhury X-Patchwork-Id: 12978274 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E2D7EC6FA90 for ; Fri, 16 Sep 2022 08:51:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229787AbiIPIvX (ORCPT ); Fri, 16 Sep 2022 04:51:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58654 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229731AbiIPIvV (ORCPT ); Fri, 16 Sep 2022 04:51:21 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 65395A1D7F; Fri, 16 Sep 2022 01:51:20 -0700 (PDT) Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 28G8TkLt018965; Fri, 16 Sep 2022 08:51:11 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=6dAyzQe89u0mG11KpSWzWdayugn/QcfUtFtIUyj7M7Y=; b=XG9KbKTvy7r0BcYcOB6WHdB7a3IOcSdCGdoX6KpSdfCmM623018iz7+vvDr8W61YYnmh ouWUa6oTAvEw986ks6jhHDL65+ZtYr1s5e5bOkr2FIWs4SswukAsF3hGzPdwkZ+vOWt5 NfiZ88zXVBLKS63RVVyUa0oc00NE2EMSgTtKOn7TpnxAgLdIeT4cYF8mb/gJSF0KHZDE D8PCd5r42pTL71Lyc6Jza3g8okD4WIT2vkKLBxQgnH1/HqKboHl+nlmgb0+4GSZn5Sx7 xSHXYlCf97wVJUknNV4VCU5Re3W5NoaBvJ+Ex8Qs4L+8bSiEHnmjVhfIukk4x5u1DE+H eg== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3jm950tgfa-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 16 Sep 2022 08:51:11 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 28G8pAmC026317 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 16 Sep 2022 08:51:10 GMT Received: from blr-ubuntu-525.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Fri, 16 Sep 2022 01:51:06 -0700 From: Souradeep Chowdhury To: Andy Gross , Bjorn Andersson , Rob Herring , Alex Elder CC: , , , , "Sai Prakash Ranjan" , Sibi Sankar , Rajendra Nayak , , "Souradeep Chowdhury" Subject: [PATCH V11 1/7] dt-bindings: Added the yaml bindings for DCC Date: Fri, 16 Sep 2022 14:20:13 +0530 Message-ID: X-Mailer: git-send-email 2.7.4 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: h2XCBE60DIWnYcFbP03llsqiuBdOaAEF X-Proofpoint-ORIG-GUID: h2XCBE60DIWnYcFbP03llsqiuBdOaAEF X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-09-16_04,2022-09-14_04,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 suspectscore=0 impostorscore=0 malwarescore=0 adultscore=0 mlxscore=0 mlxlogscore=999 priorityscore=1501 spamscore=0 lowpriorityscore=0 bulkscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2209130000 definitions=main-2209160065 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Documentation for Data Capture and Compare(DCC) device tree bindings in yaml format. Reviewed-by: Rob Herring Signed-off-by: Souradeep Chowdhury Reviewed-by: Bjorn Andersson --- .../devicetree/bindings/arm/msm/qcom,dcc.yaml | 44 ++++++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml b/Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml new file mode 100644 index 0000000..8396b0c --- /dev/null +++ b/Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/msm/qcom,dcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Data Capture and Compare + +maintainers: + - Souradeep Chowdhury + +description: | + DCC (Data Capture and Compare) is a DMA engine which is used to save + configuration data or system memory contents during catastrophic failure + or SW trigger. DCC is used to capture and store data for debugging purpose + +properties: + compatible: + items: + - enum: + - qcom,sm8150-dcc + - qcom,sc7280-dcc + - qcom,sc7180-dcc + - qcom,sdm845-dcc + - const: qcom,dcc + + reg: + items: + - description: DCC base register region + - description: DCC RAM base register region + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + dma@10a2000{ + compatible = "qcom,sm8150-dcc","qcom,dcc"; + reg = <0x010a2000 0x1000>, + <0x010ad000 0x2000>; + }; From patchwork Fri Sep 16 08:50:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Souradeep Chowdhury X-Patchwork-Id: 12978277 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8B113ECAAD8 for ; Fri, 16 Sep 2022 08:51:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230516AbiIPIvu (ORCPT ); Fri, 16 Sep 2022 04:51:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58852 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230469AbiIPIvh (ORCPT ); Fri, 16 Sep 2022 04:51:37 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1C2EAA8966; Fri, 16 Sep 2022 01:51:31 -0700 (PDT) Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 28G8TTJQ005351; Fri, 16 Sep 2022 08:51:16 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=DZipOJ/hD73Owrv9so9Y12ICjdPmo0qmD6bz2C9YffM=; b=fd2vXHH7SDyDDfY+Rgevx5pPjATzv3wqgPMZeB+bfuxPMePO8HC6nh8RcQd2PWWZven8 KnhNE5c/6DTjbRJwD/LIzUC3wscie07MbuyPitbfPX0u7naCmyYCfYJ/3f8ZOesdGrN/ gmajgJWEPeF4XzsqwrbRvVqf8MNAF7xTeYl3szRbIYLEnJSznc5eYXveyuaEGi2W7CzO 9qzXmRR8RhLntmeK8Jf+JbsBLjcYTM1PXpfbVz7vjhui6k9lbyFfCgUjdF+5MeB2et+G 6rRHDrJ30oC/XGrm1c1DXCuCO0CBN8ExgTITjMSXtWt/5Q2SYs0Tr2yVsswnxETll1U1 HA== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3jm9m1aacr-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 16 Sep 2022 08:51:16 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 28G8pFAH019483 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 16 Sep 2022 08:51:15 GMT Received: from blr-ubuntu-525.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Fri, 16 Sep 2022 01:51:10 -0700 From: Souradeep Chowdhury To: Andy Gross , Bjorn Andersson , Rob Herring , Alex Elder CC: , , , , "Sai Prakash Ranjan" , Sibi Sankar , Rajendra Nayak , , "Souradeep Chowdhury" Subject: [PATCH V11 2/7] soc: qcom: dcc: Add driver support for Data Capture and Compare unit(DCC) Date: Fri, 16 Sep 2022 14:20:14 +0530 Message-ID: <453efd9a436868a125225226dad9cc28965b75c1.1663313821.git.quic_schowdhu@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 9ceok_WTztTh9PecgU6hnAlsbZlAepuO X-Proofpoint-GUID: 9ceok_WTztTh9PecgU6hnAlsbZlAepuO X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-09-16_04,2022-09-14_04,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 suspectscore=0 bulkscore=0 impostorscore=0 lowpriorityscore=0 malwarescore=0 adultscore=0 mlxlogscore=999 spamscore=0 mlxscore=0 phishscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2209130000 definitions=main-2209160065 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The DCC is a DMA Engine designed to capture and store data during system crash or software triggers. The DCC operates based on user inputs via the debugfs interface. The user gives addresses as inputs and these addresses are stored in the dcc sram. In case of a system crash or a manual software trigger by the user through the debugfs interface, the dcc captures and stores the values at these addresses. This patch contains the driver which has all the methods pertaining to the debugfs interface, auxiliary functions to support all the four fundamental operations of dcc namely read, write, read/modify/write and loop. The probe method here instantiates all the resources necessary for dcc to operate mainly the dedicated dcc sram where it stores the values. The DCC driver can be used for debugging purposes without going for a reboot since it can perform software triggers as well based on user inputs. Also added the documentation for debugfs entries and explained the functionalities of each debugfs file that has been created for dcc. The following is the justification of using debugfs interface over the other alternatives like sysfs/ioctls i) As can be seen from the debugfs attribute descriptions, some of the debugfs attribute files here contains multiple arguments which needs to be accepted from the user. This goes against the design style of sysfs. ii) The user input patterns have been made simple and convenient in this case with the use of debugfs interface as user doesn't need to shuffle between different files to execute one instruction as was the case on using other alternatives. Signed-off-by: Souradeep Chowdhury --- Documentation/ABI/testing/debugfs-driver-dcc | 98 ++ drivers/soc/qcom/Kconfig | 8 + drivers/soc/qcom/Makefile | 1 + drivers/soc/qcom/dcc.c | 1341 ++++++++++++++++++++++++++ 4 files changed, 1448 insertions(+) create mode 100644 Documentation/ABI/testing/debugfs-driver-dcc create mode 100644 drivers/soc/qcom/dcc.c -- 2.7.4 diff --git a/Documentation/ABI/testing/debugfs-driver-dcc b/Documentation/ABI/testing/debugfs-driver-dcc new file mode 100644 index 0000000..387f67e --- /dev/null +++ b/Documentation/ABI/testing/debugfs-driver-dcc @@ -0,0 +1,98 @@ +What: /sys/kernel/debug/dcc/.../ready +Date: September 2022 +Contact: Souradeep Chowdhury +Description: + This file is used to check the status of the dcc + hardware if it's ready to take the inputs. A 'Y' + here indicates dcc is in a ready condition. + Example: + cat /sys/kernel/debug/dcc/.../ready + +What: /sys/kernel/debug/dcc/.../trigger +Date: September 2022 +Contact: Souradeep Chowdhury +Description: + This is the debugfs interface for manual software + triggers. The user can simply enter a 1 against + the debugfs file and enable a manual trigger. + Example: + echo 1 > /sys/kernel/debug/dcc/.../trigger + +What: /sys/kernel/debug/dcc/.../config_reset +Date: September 2022 +Contact: Souradeep Chowdhury +Description: + This file is used to reset the configuration of + a dcc driver to the default configuration. This + means that all the previous addresses stored in + the driver gets removed and user needs to enter + the address values from the start. + Example: + echo 1 > /sys/kernel/debug/dcc/../config_reset + +What: /sys/kernel/debug/dcc/.../[list-number]/config +Date: September 2022 +Contact: Souradeep Chowdhury +Description: + This stores the addresses of the registers which + should be read in case of a hardware crash or + manual software triggers. The addresses entered here + are considered under all the 4 types of dcc + instructions Read type, Write type, Read Modify Write + type and Loop type. The lists need to be configured + sequentially and not in a overlapping manner. As an + example user can jump to list x only after list y is + configured and enabled. The format for entering all + types of instructions are explained in examples as + follows. + Example: + i)Read Type Instruction + echo R <1> <2> <3> >/sys/kernel/debug/dcc/../[list-number]/config + 1->Address to be considered for reading the value. + 2->The word count of the addresses, read n words + starting from address <1>. Each word is of 32 bits. + If not entered 1 is considered. + 3->Can be 'apb' or 'ahb' which indicates if it is apb or ahb + bus respectively. If not entered ahb is considered. + ii)Write Type Instruction + echo W <1> <2> <3> > /sys/kernel/debug/dcc/../[list-number]/config + 1->Address to be considered for writing the value. + 2->The value that needs to be written at the location. + 3->Can be a 'apb' or 'ahb' which indicates if it is apb or ahb + but respectively. + iii)Read Modify Write type instruction + echo RW <1> <2> <3> > /sys/kernel/debug/dcc/../[list-number]/config + 1->The address which needs to be considered for read then write. + 2->The value that needs to be written on the address. + 3->The mask of the value to be written. + iv)Loop Type Instruction + echo L <1> <2> <3> > /sys/kernel/debug/dcc/../[list-number]/config + 1->The loop count, the number of times the value of the addresses will be + captured. + 2->The address count, total number of addresses to be entered in this + instruction. + 3->The series of addresses to be entered separated by a space like + ... and so on. + +What: /sys/kernel/debug/dcc/.../[list-number]/enable +Date: September 2022 +Contact: Souradeep Chowdhury +Description: + This debugfs interface is used for enabling the + the dcc hardware. Enable file is kept under the + directory list number for which the user wants + to enable it. For example if the user wants to + enable list 1, then he should go for + echo 1 > /sys/kernel/debug/dcc/.../1/enable. + On enabling the dcc, all the addresses entered + by the user for the corresponding list is written + into dcc sram which is read by the dcc hardware + on manual or crash induced triggers. Lists should + be enabled sequentially.For example after configuring + addresses for list 1 and enabling it, a user can + proceed to enable list 2 or vice versa. + Example: + echo 0 > /sys/kernel/debug/dcc/.../[list-number]/enable + (disable dcc for the corresponding list number) + echo 1 > /sys/kernel/debug/dcc/.../[list-number]/enable + (enable dcc for the corresponding list number) diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig index 79b568f..5101912 100644 --- a/drivers/soc/qcom/Kconfig +++ b/drivers/soc/qcom/Kconfig @@ -69,6 +69,14 @@ config QCOM_LLCC SDM845. This provides interfaces to clients that use the LLCC. Say yes here to enable LLCC slice driver. +config QCOM_DCC + tristate "Qualcomm Technologies, Inc. Data Capture and Compare(DCC) engine driver" + depends on ARCH_QCOM || COMPILE_TEST + help + This option enables driver for Data Capture and Compare engine. DCC + driver provides interface to configure DCC block and read back + captured data from DCC's internal SRAM. + config QCOM_KRYO_L2_ACCESSORS bool depends on ARCH_QCOM && ARM64 || COMPILE_TEST diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile index ad675a6..0aaf82b 100644 --- a/drivers/soc/qcom/Makefile +++ b/drivers/soc/qcom/Makefile @@ -4,6 +4,7 @@ obj-$(CONFIG_QCOM_AOSS_QMP) += qcom_aoss.o obj-$(CONFIG_QCOM_GENI_SE) += qcom-geni-se.o obj-$(CONFIG_QCOM_COMMAND_DB) += cmd-db.o obj-$(CONFIG_QCOM_CPR) += cpr.o +obj-$(CONFIG_QCOM_DCC) += dcc.o obj-$(CONFIG_QCOM_GSBI) += qcom_gsbi.o obj-$(CONFIG_QCOM_MDT_LOADER) += mdt_loader.o obj-$(CONFIG_QCOM_OCMEM) += ocmem.o diff --git a/drivers/soc/qcom/dcc.c b/drivers/soc/qcom/dcc.c new file mode 100644 index 0000000..7e07f1a --- /dev/null +++ b/drivers/soc/qcom/dcc.c @@ -0,0 +1,1341 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copneight (c) 2015-2021, The Linex Fnendation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define STATUS_READY_TIMEOUT 5000 /*microseconds*/ + +#define DCC_SRAM_NODE "dcc_sram" + +/* DCC registers */ +#define DCC_HW_INFO 0x04 +#define DCC_LL_NUM_INFO 0x10 +#define DCC_STATUS(vers) ((vers) == 1 ? 0x0c : 0x1c) +#define DCC_LL_LOCK 0x00 +#define DCC_LL_CFG 0x04 +#define DCC_LL_BASE 0x08 +#define DCC_FD_BASE 0x0c +#define DCC_LL_TIMEOUT 0x10 +#define DCC_LL_INT_ENABLE 0x18 +#define DCC_LL_INT_STATUS 0x1c +#define DCC_LL_SW_TRIGGER 0x2c +#define DCC_LL_BUS_ACCESS_STATUS 0x30 + +#define DCC_MAP_LEVEL1 0x18 +#define DCC_MAP_LEVEL2 0x34 +#define DCC_MAP_LEVEL3 0x4C + +#define DCC_MAP_OFFSET1 0x10 +#define DCC_MAP_OFFSET2 0x18 +#define DCC_MAP_OFFSET3 0x1C +#define DCC_MAP_OFFSET4 0x8 + +/*Default value used if a bit 6 in the HW_INFO register is set.*/ +#define DCC_FIX_LOOP_OFFSET 16 + +/*Mask to find version info from HW_Info register*/ +#define DCC_VER_INFO_MASK BIT(9) + +#define DCC_READ 0 +#define DCC_WRITE 1 +#define DCC_LOOP 2 +#define DCC_READ_WRITE 3 + +#define MAX_DCC_OFFSET GENMASK(9, 2) +#define MAX_DCC_LEN GENMASK(6, 0) +#define MAX_LOOP_CNT GENMASK(7, 0) +#define MAX_LOOP_ADDR 10 + +#define DCC_ADDR_DESCRIPTOR 0x00 +#define DCC_ADDR_LIMIT 27 +#define DCC_ADDR_OFF_RANGE 8 +#define DCC_ADDR_RANGE_MASK GENMASK(31, 4) +#define DCC_LOOP_DESCRIPTOR BIT(30) +#define DCC_RD_MOD_WR_DESCRIPTOR BIT(31) +#define DCC_LINK_DESCRIPTOR GENMASK(31, 30) +#define DCC_STATUS_MASK GENMASK(1, 0) +#define DCC_LOCK_MASK BIT(0) +#define DCC_LOOP_OFFSET_MASK BIT(6) +#define DCC_TRIGGER_MASK BIT(9) + +#define DCC_READ_IND 0x00 +#define DCC_WRITE_IND (BIT(28)) + +#define DCC_AHB_IND 0x00 +#define DCC_APB_IND BIT(29) + +#define DCC_MAX_LINK_LIST 8 +#define DCC_INVALID_LINK_LIST GENMASK(7, 0) + +#define DCC_VER_MASK1 GENMASK(6, 0) +#define DCC_VER_MASK2 GENMASK(5, 0) + +#define DCC_RD_MOD_WR_ADDR 0xC105E + +/*DCC debugfs directory*/ +static struct dentry *dcc_dbg; + +enum dcc_descriptor_type { + DCC_READ_TYPE, + DCC_LOOP_TYPE, + DCC_READ_WRITE_TYPE, + DCC_WRITE_TYPE +}; + +struct dcc_config_entry { + u32 base; + u32 offset; + u32 len; + u32 loop_cnt; + u32 write_val; + u32 mask; + bool apb_bus; + enum dcc_descriptor_type desc_type; + struct list_head list; +}; + +/** + * struct dcc_drvdata - configuration information related to a dcc device + * @base: Base Address of the dcc device + * @dev: The device attached to the driver data + * @mutex: Lock to protect access and manipulation of dcc_drvdata + * @ram_base: Base address for the SRAM dedicated for the dcc device + * @ram_offset: Offset to the SRAM dedicated for dcc device + * @mem_map_ver: Memory map version of DCC hardware + * @ram_cfg: Used for address limit calculation for dcc + * @ram_start: Starting address of DCC SRAM + * @sram_dev: Micellaneous device equivalent of dcc SRAM + * @cfg_head: Points to the head of the linked list of addresses + * @dbg_dir: The dcc debugfs directory under which all the debugfs files are placed + * @nr_link_list: Total number of linkedlists supported by the DCC configuration + * @loopoff: Loop offset bits range for the addresses + * @enable: This contains an array of linkedlist enable flags + */ +struct dcc_drvdata { + void __iomem *base; + struct device *dev; + struct mutex mutex; + void __iomem *ram_base; + size_t ram_size; + size_t ram_offset; + int mem_map_ver; + phys_addr_t ram_cfg; + phys_addr_t ram_start; + struct miscdevice sram_dev; + struct list_head *cfg_head; + struct dentry *dbg_dir; + size_t nr_link_list; + u8 loopoff; + bool *enable; +}; + +struct dcc_cfg_attr { + u32 addr; + u32 prev_addr; + u32 prev_off; + u32 link; + u32 sram_offset; +}; + +struct dcc_cfg_loop_attr { + u32 loop; + u32 loop_cnt; + u32 loop_len; + u32 loop_off; + bool loop_start; +}; + +static size_t dcc_offset_conv(struct dcc_drvdata *drvdata, size_t off) +{ + /* If the memory map version is 1, adjust the offset based on + * the dcc version mask. If the memory map version is 2 + * adjust the offset if the dcc version mask is greater than + * map level 2.For other conditions, just return the offset. + */ + if (drvdata->mem_map_ver == 1) { + if (FIELD_GET(DCC_VER_MASK1, off) >= DCC_MAP_LEVEL3) + return off - DCC_MAP_OFFSET3; + if (FIELD_GET(DCC_VER_MASK1, off) >= DCC_MAP_LEVEL2) + return off - DCC_MAP_OFFSET2; + else if (FIELD_GET(DCC_VER_MASK1, off) >= DCC_MAP_LEVEL1) + return off - DCC_MAP_OFFSET1; + } else if (drvdata->mem_map_ver == 2) { + if (FIELD_GET(DCC_VER_MASK1, off) >= DCC_MAP_LEVEL2) + return off - DCC_MAP_OFFSET4; + } + + return off; +} + +static inline u32 dcc_ll_offset(int version) +{ + return version == 1 ? 0x1c : (version == 2 ? 0x2c : 0x34); +} + +static inline u32 dcc_readl(struct dcc_drvdata *drvdata, u32 off) +{ + return readl(drvdata->base + dcc_offset_conv(drvdata, off)); +} + +static inline void dcc_ll_writel(struct dcc_drvdata *drvdata, + u32 ll, u32 val, u32 off) +{ + u32 offset = dcc_ll_offset(drvdata->mem_map_ver) + off; + + writel(val, drvdata->base + ll * 0x80 + offset); +} + +static inline u32 dcc_ll_readl(struct dcc_drvdata *drvdata, u32 ll, u32 off) +{ + u32 offset = dcc_ll_offset(drvdata->mem_map_ver) + off; + + return readl(drvdata->base + ll * 0x80 + offset); +} + +static void dcc_sram_write_auto(struct dcc_drvdata *drvdata, + u32 val, u32 *off) +{ + writel(val, drvdata->ram_base + *off); + + *off += 4; +} + +static int dcc_read_and_clear(struct dcc_drvdata *drvdata) +{ + int i; + u32 bus_status; + u32 ll_cfg; + u32 tmp_ll_cfg; + + for (i = 0; i < drvdata->nr_link_list; i++) { + if (!drvdata->enable[i]) + continue; + + bus_status = dcc_ll_readl(drvdata, i, DCC_LL_BUS_ACCESS_STATUS); + if (!bus_status) + continue; + + dev_err(drvdata->dev, + "Read access error for list %d err: 0x%x.\n", i, bus_status); + ll_cfg = dcc_ll_readl(drvdata, i, DCC_LL_CFG); + tmp_ll_cfg = ll_cfg & ~DCC_TRIGGER_MASK; + dcc_ll_writel(drvdata, tmp_ll_cfg, i, DCC_LL_CFG); + dcc_ll_writel(drvdata, DCC_STATUS_MASK, i, + DCC_LL_BUS_ACCESS_STATUS); + dcc_ll_writel(drvdata, ll_cfg, i, DCC_LL_CFG); + return -ENODATA; + } + + return 0; +} + +static int dcc_sw_trigger(struct dcc_drvdata *drvdata) +{ + void __iomem *addr; + int ret; + int i; + u32 ll_cfg; + u32 tmp_ll_cfg; + u32 val; + + mutex_lock(&drvdata->mutex); + + for (i = 0; i < drvdata->nr_link_list; i++) { + if (!drvdata->enable[i]) + continue; + ll_cfg = dcc_ll_readl(drvdata, i, DCC_LL_CFG); + tmp_ll_cfg = ll_cfg & ~DCC_TRIGGER_MASK; + dcc_ll_writel(drvdata, tmp_ll_cfg, i, DCC_LL_CFG); + dcc_ll_writel(drvdata, 1, i, DCC_LL_SW_TRIGGER); + dcc_ll_writel(drvdata, ll_cfg, i, DCC_LL_CFG); + } + + addr = drvdata->base + DCC_STATUS(drvdata->mem_map_ver); + if (readl_poll_timeout(addr, val, (FIELD_GET(DCC_STATUS_MASK, val) == 0), + 1, STATUS_READY_TIMEOUT)) { + dev_err(drvdata->dev, + "DCC is busy after receiving sw tigger.\n"); + ret = -EBUSY; + goto out_unlock; + } + + ret = dcc_read_and_clear(drvdata); + +out_unlock: + mutex_unlock(&drvdata->mutex); + return ret; +} + +static void _dcc_ll_cfg_reset_link(struct dcc_cfg_attr *cfg) +{ + cfg->addr = 0x00; + cfg->link = 0; + cfg->prev_off = 0; + cfg->prev_addr = cfg->addr; +} + +static void _dcc_emit_read_write(struct dcc_drvdata *drvdata, + struct dcc_config_entry *entry, + struct dcc_cfg_attr *cfg) +{ + if (cfg->link) { + /* + * write new offset = 1 to continue + * processing the list + */ + + dcc_sram_write_auto(drvdata, cfg->link, &cfg->sram_offset); + + /* Reset link and prev_off */ + _dcc_ll_cfg_reset_link(cfg); + } + + cfg->addr = DCC_RD_MOD_WR_DESCRIPTOR; + dcc_sram_write_auto(drvdata, cfg->addr, &cfg->sram_offset); + + dcc_sram_write_auto(drvdata, entry->mask, &cfg->sram_offset); + + dcc_sram_write_auto(drvdata, entry->write_val, &cfg->sram_offset); + + cfg->addr = 0; +} + +static void _dcc_emit_loop(struct dcc_drvdata *drvdata, struct dcc_config_entry *entry, + struct dcc_cfg_attr *cfg, + struct dcc_cfg_loop_attr *cfg_loop, + u32 *total_len) +{ + /* Check if we need to write link of prev entry */ + if (cfg->link) + dcc_sram_write_auto(drvdata, cfg->link, &cfg->sram_offset); + + if (cfg_loop->loop_start) { + cfg_loop->loop = (cfg->sram_offset - cfg_loop->loop_off) / 4; + cfg_loop->loop |= (cfg_loop->loop_cnt << drvdata->loopoff) & + GENMASK(DCC_ADDR_LIMIT, drvdata->loopoff); + cfg_loop->loop |= DCC_LOOP_DESCRIPTOR; + *total_len += (*total_len - cfg_loop->loop_len) * cfg_loop->loop_cnt; + + dcc_sram_write_auto(drvdata, cfg_loop->loop, &cfg->sram_offset); + + cfg_loop->loop_start = false; + cfg_loop->loop_len = 0; + cfg_loop->loop_off = 0; + } else { + cfg_loop->loop_start = true; + cfg_loop->loop_cnt = entry->loop_cnt - 1; + cfg_loop->loop_len = *total_len; + cfg_loop->loop_off = cfg->sram_offset; + } + + /* Reset link and prev_off */ + _dcc_ll_cfg_reset_link(cfg); +} + +static void _dcc_emit_write(struct dcc_drvdata *drvdata, + struct dcc_config_entry *entry, + struct dcc_cfg_attr *cfg, + u32 *total_len) +{ + u32 off; + + if (cfg->link) { + /* + * write new offset = 1 to continue + * processing the list + */ + dcc_sram_write_auto(drvdata, cfg->link, &cfg->sram_offset); + + /* Reset link and prev_off */ + cfg->addr = 0x00; + cfg->prev_off = 0; + cfg->prev_addr = cfg->addr; + } + + off = entry->offset / 4; + /* write new offset-length pair to correct position */ + cfg->link |= ((off & GENMASK(7, 0)) | BIT(15) | ((entry->len << 8) & GENMASK(14, 8))); + cfg->link |= DCC_LINK_DESCRIPTOR; + + /* Address type */ + cfg->addr = (entry->base >> 4) & GENMASK(DCC_ADDR_LIMIT, 0); + if (entry->apb_bus) + cfg->addr |= DCC_ADDR_DESCRIPTOR | DCC_WRITE_IND | DCC_APB_IND; + else + cfg->addr |= DCC_ADDR_DESCRIPTOR | DCC_WRITE_IND | DCC_AHB_IND; + dcc_sram_write_auto(drvdata, cfg->addr, &cfg->sram_offset); + + dcc_sram_write_auto(drvdata, cfg->link, &cfg->sram_offset); + + dcc_sram_write_auto(drvdata, entry->write_val, &cfg->sram_offset); + + cfg->addr = 0x00; + cfg->link = 0; +} + +static int _dcc_emit_read(struct dcc_drvdata *drvdata, + struct dcc_config_entry *entry, + struct dcc_cfg_attr *cfg, + u32 *pos, u32 *total_len) +{ + u32 off; + u32 temp_off; + + cfg->addr = (entry->base >> 4) & GENMASK(27, 0); + + if (entry->apb_bus) + cfg->addr |= DCC_ADDR_DESCRIPTOR | DCC_READ_IND | DCC_APB_IND; + else + cfg->addr |= DCC_ADDR_DESCRIPTOR | DCC_READ_IND | DCC_AHB_IND; + + off = entry->offset / 4; + + *total_len += entry->len * 4; + + if (!cfg->prev_addr || cfg->prev_addr != cfg->addr || cfg->prev_off > off) { + /* Check if we need to write prev link entry */ + if (cfg->link) + dcc_sram_write_auto(drvdata, cfg->link, &cfg->sram_offset); + dev_dbg(drvdata->dev, "DCC: sram address 0x%x\n", cfg->sram_offset); + + /* Write address */ + dcc_sram_write_auto(drvdata, cfg->addr, &cfg->sram_offset); + + /* Reset link and prev_off */ + cfg->link = 0; + cfg->prev_off = 0; + } + + if ((off - cfg->prev_off) > 0xFF || entry->len > MAX_DCC_LEN) { + dev_err(drvdata->dev, "DCC: Programming error Base: 0x%x, offset 0x%x\n", + entry->base, entry->offset); + return -EINVAL; + } + + if (cfg->link) { + /* + * link already has one offset-length so new + * offset-length needs to be placed at + * bits [29:15] + */ + *pos = 15; + + /* Clear bits [31:16] */ + cfg->link &= GENMASK(14, 0); + } else { + /* + * link is empty, so new offset-length needs + * to be placed at bits [15:0] + */ + *pos = 0; + cfg->link = 1 << 15; + } + + /* write new offset-length pair to correct position */ + temp_off = (off - cfg->prev_off) & GENMASK(7, 0); + cfg->link |= temp_off | ((entry->len << 8) & GENMASK(14, 8)) << *pos; + + cfg->link |= DCC_LINK_DESCRIPTOR; + + if (*pos) { + dcc_sram_write_auto(drvdata, cfg->link, &cfg->sram_offset); + cfg->link = 0; + } + + cfg->prev_off = off + entry->len - 1; + cfg->prev_addr = cfg->addr; + return 0; +} + +static int __dcc_emit_config(struct dcc_drvdata *drvdata, int curr_list) +{ + int ret; + u32 total_len, pos; + struct dcc_config_entry *entry; + struct dcc_cfg_attr cfg; + struct dcc_cfg_loop_attr cfg_loop; + + memset(&cfg, 0, sizeof(cfg)); + memset(&cfg_loop, 0, sizeof(cfg_loop)); + cfg.sram_offset = drvdata->ram_cfg * 4; + total_len = 0; + + list_for_each_entry(entry, &drvdata->cfg_head[curr_list], list) { + switch (entry->desc_type) { + case DCC_READ_WRITE_TYPE: + _dcc_emit_read_write(drvdata, entry, &cfg); + break; + + case DCC_LOOP_TYPE: + _dcc_emit_loop(drvdata, entry, &cfg, &cfg_loop, &total_len); + break; + + case DCC_WRITE_TYPE: + _dcc_emit_write(drvdata, entry, &cfg, &total_len); + break; + + case DCC_READ_TYPE: + ret = _dcc_emit_read(drvdata, entry, &cfg, &pos, &total_len); + if (ret) + goto overstep; + break; + } + } + + if (cfg.link) + dcc_sram_write_auto(drvdata, cfg.link, &cfg.sram_offset); + + if (cfg_loop.loop_start) { + dev_err(drvdata->dev, "DCC: Programming error: Loop unterminated\n"); + ret = -EINVAL; + goto err; + } + + /* Handling special case of list ending with a rd_mod_wr */ + if (cfg.addr == DCC_RD_MOD_WR_DESCRIPTOR) { + cfg.addr = (DCC_RD_MOD_WR_ADDR) & GENMASK(27, 0); + cfg.addr |= DCC_ADDR_DESCRIPTOR; + dcc_sram_write_auto(drvdata, cfg.addr, &cfg.sram_offset); + } + + /* Setting zero to indicate end of the list */ + cfg.link = DCC_LINK_DESCRIPTOR; + dcc_sram_write_auto(drvdata, cfg.link, &cfg.sram_offset); + + /*Check if sram offset exceeds the ram size*/ + if (cfg.sram_offset > drvdata->ram_size) + goto overstep; + + /* Update ram_cfg and check if the data will overstep */ + drvdata->ram_cfg = (cfg.sram_offset + total_len) / 4; + + if (cfg.sram_offset + total_len > drvdata->ram_size) { + cfg.sram_offset += total_len; + goto overstep; + } + + drvdata->ram_start = cfg.sram_offset / 4; + return 0; +overstep: + ret = -EINVAL; + memset_io(drvdata->ram_base, 0, drvdata->ram_size); + +err: + return ret; +} + +static int dcc_valid_list(struct dcc_drvdata *drvdata, int curr_list) +{ + u32 lock_reg; + + if (list_empty(&drvdata->cfg_head[curr_list])) + return -EINVAL; + + if (drvdata->enable[curr_list]) { + dev_err(drvdata->dev, "List %d is already enabled\n", curr_list); + return -EINVAL; + } + + lock_reg = dcc_ll_readl(drvdata, curr_list, DCC_LL_LOCK); + if (lock_reg & DCC_LOCK_MASK) { + dev_err(drvdata->dev, "List %d is already locked\n", curr_list); + return -EINVAL; + } + + return 0; +} + +static bool is_dcc_enabled(struct dcc_drvdata *drvdata) +{ + int list; + + for (list = 0; list < DCC_MAX_LINK_LIST; list++) + if (drvdata->enable[list]) + return true; + + return false; +} + +static int dcc_enable(struct dcc_drvdata *drvdata, int curr_list) +{ + int ret; + u32 ram_cfg_base; + + mutex_lock(&drvdata->mutex); + + ret = dcc_valid_list(drvdata, curr_list); + if (ret) + goto out_unlock; + + /* Fill dcc sram with the poison value. + * This helps in understanding bus + * hang from registers returning a zero + */ + if (!is_dcc_enabled(drvdata)) + memset_io(drvdata->ram_base, 0xde, drvdata->ram_size); + + /* 1. Take ownership of the list */ + dcc_ll_writel(drvdata, DCC_LOCK_MASK, curr_list, DCC_LL_LOCK); + + /* 2. Program linked-list in the SRAM */ + ram_cfg_base = drvdata->ram_cfg; + ret = __dcc_emit_config(drvdata, curr_list); + if (ret) { + dcc_ll_writel(drvdata, 0, curr_list, DCC_LL_LOCK); + goto out_unlock; + } + + /* 3. Program DCC_RAM_CFG reg */ + dcc_ll_writel(drvdata, ram_cfg_base + + drvdata->ram_offset / 4, curr_list, DCC_LL_BASE); + dcc_ll_writel(drvdata, drvdata->ram_start + + drvdata->ram_offset / 4, curr_list, DCC_FD_BASE); + dcc_ll_writel(drvdata, 0xFFF, curr_list, DCC_LL_TIMEOUT); + + /* 4. Clears interrupt status register */ + dcc_ll_writel(drvdata, 0, curr_list, DCC_LL_INT_ENABLE); + dcc_ll_writel(drvdata, (BIT(0) | BIT(1) | BIT(2)), + curr_list, DCC_LL_INT_STATUS); + + drvdata->enable[curr_list] = true; + + /* 5. Configure trigger */ + dcc_ll_writel(drvdata, DCC_TRIGGER_MASK, + curr_list, DCC_LL_CFG); + +out_unlock: + mutex_unlock(&drvdata->mutex); + return ret; +} + +static void dcc_disable(struct dcc_drvdata *drvdata, int curr_list) +{ + mutex_lock(&drvdata->mutex); + + if (!drvdata->enable[curr_list]) + goto out_unlock; + dcc_ll_writel(drvdata, 0, curr_list, DCC_LL_CFG); + dcc_ll_writel(drvdata, 0, curr_list, DCC_LL_BASE); + dcc_ll_writel(drvdata, 0, curr_list, DCC_FD_BASE); + dcc_ll_writel(drvdata, 0, curr_list, DCC_LL_LOCK); + drvdata->enable[curr_list] = false; +out_unlock: + mutex_unlock(&drvdata->mutex); +} + +static u32 dcc_filp_curr_list(struct file *filp) +{ + struct dentry *dentry = file_dentry(filp); + int curr_list, ret; + + ret = kstrtoint(dentry->d_parent->d_name.name, 0, &curr_list); + if (ret) + return ret; + + return curr_list; +} + +static ssize_t enable_read(struct file *filp, char __user *userbuf, + size_t count, loff_t *ppos) +{ + char *buf; + struct dcc_drvdata *drvdata = filp->private_data; + + mutex_lock(&drvdata->mutex); + + if (is_dcc_enabled(drvdata)) + buf = "Y\n"; + else + buf = "N\n"; + + mutex_unlock(&drvdata->mutex); + + return simple_read_from_buffer(userbuf, count, ppos, buf, strlen(buf) + 1); +} + +static ssize_t enable_write(struct file *filp, const char __user *userbuf, + size_t count, loff_t *ppos) +{ + int ret = 0, curr_list; + bool val; + struct dcc_drvdata *drvdata = filp->private_data; + + curr_list = dcc_filp_curr_list(filp); + if (curr_list < 0) + return curr_list; + + ret = kstrtobool_from_user(userbuf, count, &val); + if (ret < 0) + return ret; + + if (val) { + ret = dcc_enable(drvdata, curr_list); + if (ret) + return ret; + } else { + dcc_disable(drvdata, curr_list); + } + + return count; +} + +static const struct file_operations enable_fops = { + .read = enable_read, + .write = enable_write, + .open = simple_open, + .llseek = generic_file_llseek, +}; + +static ssize_t trigger_write(struct file *filp, + const char __user *user_buf, size_t count, + loff_t *ppos) +{ + int ret; + unsigned int val; + struct dcc_drvdata *drvdata = filp->private_data; + + ret = kstrtouint_from_user(user_buf, count, 0, &val); + if (ret < 0) + return ret; + + if (val != 1) + return -EINVAL; + + ret = dcc_sw_trigger(drvdata); + if (ret < 0) + return ret; + + return count; +} + +static const struct file_operations trigger_fops = { + .write = trigger_write, + .open = simple_open, + .llseek = generic_file_llseek, +}; + +static int dcc_config_add(struct dcc_drvdata *drvdata, unsigned int addr, + unsigned int len, int apb_bus, int curr_list) +{ + int ret = 0; + struct dcc_config_entry *entry, *pentry; + unsigned int base, offset; + + mutex_lock(&drvdata->mutex); + + if (!len || len > drvdata->ram_size / DCC_ADDR_OFF_RANGE) { + dev_err(drvdata->dev, "DCC: Invalid length\n"); + ret = -EINVAL; + goto out_unlock; + } + + base = addr & DCC_ADDR_RANGE_MASK; + + if (!list_empty(&drvdata->cfg_head[curr_list])) { + pentry = list_last_entry(&drvdata->cfg_head[curr_list], + struct dcc_config_entry, list); + + if (pentry->desc_type == DCC_READ_TYPE && + addr >= (pentry->base + pentry->offset) && + addr <= (pentry->base + pentry->offset + MAX_DCC_OFFSET)) { + /* Re-use base address from last entry */ + base = pentry->base; + + if ((pentry->len * 4 + pentry->base + pentry->offset) + == addr) { + len += pentry->len; + + if (len > MAX_DCC_LEN) + pentry->len = MAX_DCC_LEN; + else + pentry->len = len; + + addr = pentry->base + pentry->offset + + pentry->len * 4; + len -= pentry->len; + } + } + } + + offset = addr - base; + + while (len) { + entry = devm_kzalloc(drvdata->dev, sizeof(*entry), GFP_KERNEL); + if (!entry) { + ret = -ENOMEM; + goto out_unlock; + } + + entry->base = base; + entry->offset = offset; + entry->len = min_t(u32, len, MAX_DCC_LEN); + entry->desc_type = DCC_READ_TYPE; + entry->apb_bus = apb_bus; + INIT_LIST_HEAD(&entry->list); + list_add_tail(&entry->list, + &drvdata->cfg_head[curr_list]); + + len -= entry->len; + offset += MAX_DCC_LEN * 4; + } + +out_unlock: + mutex_unlock(&drvdata->mutex); + return ret; +} + +static ssize_t dcc_config_add_read(struct dcc_drvdata *drvdata, char *buf, int curr_list) +{ + int len, nval, bus; + unsigned int base; + char apb_bus[4]; + + nval = sscanf(buf, "%x %i %s", &base, &len, apb_bus); + if (nval <= 0 || nval > 3) + return -EINVAL; + + if (nval == 1) { + len = 1; + bus = 0; + } else if (nval == 2) { + bus = 0; + } else if (!strcmp("apb", apb_bus)) { + bus = 1; + } else if (!strcmp("ahb", apb_bus)) { + bus = 0; + } else { + return -EINVAL; + } + + return dcc_config_add(drvdata, base, len, bus, curr_list); +} + +static void dcc_config_reset(struct dcc_drvdata *drvdata) +{ + struct dcc_config_entry *entry, *temp; + int curr_list; + + mutex_lock(&drvdata->mutex); + + for (curr_list = 0; curr_list < drvdata->nr_link_list; curr_list++) { + list_for_each_entry_safe(entry, temp, + &drvdata->cfg_head[curr_list], list) { + list_del(&entry->list); + } + } + drvdata->ram_start = 0; + drvdata->ram_cfg = 0; + mutex_unlock(&drvdata->mutex); +} + +static ssize_t config_reset_write(struct file *filp, + const char __user *user_buf, size_t count, + loff_t *ppos) +{ + unsigned int val, ret; + struct dcc_drvdata *drvdata = filp->private_data; + + ret = kstrtouint_from_user(user_buf, count, 0, &val); + if (ret < 0) + return ret; + + if (val) + dcc_config_reset(drvdata); + + return count; +} + +static const struct file_operations config_reset_fops = { + .write = config_reset_write, + .open = simple_open, + .llseek = generic_file_llseek, +}; + +static ssize_t ready_read(struct file *filp, char __user *userbuf, + size_t count, loff_t *ppos) +{ + int ret = 0; + char *buf; + struct dcc_drvdata *drvdata = filp->private_data; + + mutex_lock(&drvdata->mutex); + + if (!is_dcc_enabled(drvdata)) { + ret = -EINVAL; + goto out_unlock; + } + + if (!FIELD_GET(BIT(1), readl(drvdata->base + DCC_STATUS(drvdata->mem_map_ver)))) + buf = "Y\n"; + else + buf = "N\n"; +out_unlock: + mutex_unlock(&drvdata->mutex); + + if (ret < 0) + return -EINVAL; + else + return simple_read_from_buffer(userbuf, count, ppos, buf, strlen(buf) + 1); +} + +static const struct file_operations ready_fops = { + .read = ready_read, + .open = simple_open, + .llseek = generic_file_llseek, +}; + +static int dcc_add_loop(struct dcc_drvdata *drvdata, unsigned long loop_cnt, int curr_list) +{ + struct dcc_config_entry *entry; + + entry = devm_kzalloc(drvdata->dev, sizeof(*entry), GFP_KERNEL); + if (!entry) + return -ENOMEM; + + entry->loop_cnt = min_t(u32, loop_cnt, MAX_LOOP_CNT); + entry->desc_type = DCC_LOOP_TYPE; + INIT_LIST_HEAD(&entry->list); + list_add_tail(&entry->list, &drvdata->cfg_head[curr_list]); + + return 0; +} + +static ssize_t dcc_config_add_loop(struct dcc_drvdata *drvdata, char *buf, int curr_list) +{ + int ret, cnt = 2, i = 0; + char *token, *input; + char delim[2] = " "; + unsigned int val[MAX_LOOP_ADDR]; + + input = buf; + + token = strsep(&input, delim); + while (token) { + ret = kstrtoint(token, 0, &val[i++]); + if (ret) + return ret; + + token = strsep(&input, delim); + } + + ret = dcc_add_loop(drvdata, val[0], curr_list); + if (ret) + return ret; + + for (i = 0; i < val[1]; i++) + dcc_config_add(drvdata, val[cnt++], 1, 0, curr_list); + + return dcc_add_loop(drvdata, 1, curr_list); +} + +static int dcc_rd_mod_wr_add(struct dcc_drvdata *drvdata, unsigned int mask, + unsigned int val, int curr_list) +{ + int ret = 0; + struct dcc_config_entry *entry; + + mutex_lock(&drvdata->mutex); + + if (list_empty(&drvdata->cfg_head[curr_list])) { + dev_err(drvdata->dev, "DCC: No read address programmed\n"); + ret = -EPERM; + goto out_unlock; + } + + entry = devm_kzalloc(drvdata->dev, sizeof(*entry), GFP_KERNEL); + if (!entry) { + ret = -ENOMEM; + goto out_unlock; + } + + entry->desc_type = DCC_READ_WRITE_TYPE; + entry->mask = mask; + entry->write_val = val; + INIT_LIST_HEAD(&entry->list); + list_add_tail(&entry->list, &drvdata->cfg_head[curr_list]); +out_unlock: + mutex_unlock(&drvdata->mutex); + return ret; +} + +static ssize_t dcc_config_add_read_write(struct dcc_drvdata *drvdata, char *buf, int curr_list) +{ + int ret; + int nval; + unsigned int addr, mask, val; + + nval = sscanf(buf, "%x %x %x", &addr, &mask, &val); + + if (nval <= 1 || nval > 3) + return -EINVAL; + + ret = dcc_config_add(drvdata, addr, 1, 0, curr_list); + if (ret) + return ret; + + return dcc_rd_mod_wr_add(drvdata, mask, val, curr_list); +} + +static int dcc_add_write(struct dcc_drvdata *drvdata, unsigned int addr, + unsigned int write_val, int apb_bus, int curr_list) +{ + struct dcc_config_entry *entry; + + entry = devm_kzalloc(drvdata->dev, sizeof(*entry), GFP_KERNEL); + if (!entry) + return -ENOMEM; + + entry->desc_type = DCC_WRITE_TYPE; + entry->base = addr & GENMASK(31, 4); + entry->offset = addr - entry->base; + entry->write_val = write_val; + entry->len = 1; + entry->apb_bus = apb_bus; + INIT_LIST_HEAD(&entry->list); + list_add_tail(&entry->list, &drvdata->cfg_head[curr_list]); + + return 0; +} + +static ssize_t dcc_config_add_write(struct dcc_drvdata *drvdata, char *buf, int curr_list) +{ + int ret, bus; + int nval; + unsigned int addr, write_val; + char apb_bus[4]; + + nval = sscanf(buf, "%x %x %s", &addr, &write_val, apb_bus); + + if (nval <= 1 || nval > 3) + return -EINVAL; + + if (nval == 3) { + if (!strcmp("apb", apb_bus)) + bus = 1; + else if (!strcmp("apb", apb_bus)) + bus = 0; + else + return -EINVAL; + } + + ret = dcc_add_write(drvdata, addr, write_val, bus, curr_list); + + return ret; +} + +static ssize_t config_read(struct file *filp, char __user *userbuf, + size_t count, loff_t *ppos) +{ + struct dcc_drvdata *drvdata = filp->private_data; + struct dcc_config_entry *entry; + char local_buf[64], buf[100] = "\0"; + int len = 0, tot_len = 0, index = 0, curr_list; + + mutex_lock(&drvdata->mutex); + curr_list = dcc_filp_curr_list(filp); + if (curr_list < 0) + return curr_list; + + list_for_each_entry(entry, + &drvdata->cfg_head[curr_list], list) { + index++; + switch (entry->desc_type) { + case DCC_READ_WRITE_TYPE: + len = snprintf(local_buf, 64, + "Index: 0x%x, mask: 0x%x, val: 0x%x\n", + index, entry->mask, entry->write_val); + break; + case DCC_LOOP_TYPE: + len = snprintf(local_buf, 64, "Index: 0x%x, Loop: %d\n", + index, entry->loop_cnt); + break; + case DCC_WRITE_TYPE: + len = snprintf(local_buf, 64, + "Write Index: 0x%x, Base: 0x%x, Offset: 0x%x, len: 0x%x APB: %d\n", + index, entry->base, entry->offset, entry->len, + entry->apb_bus); + break; + case DCC_READ_TYPE: + len = snprintf(local_buf, 64, + "Read Index: 0x%x, Base: 0x%x, Offset: 0x%x, len: 0x%x APB: %d\n", + index, entry->base, entry->offset, + entry->len, entry->apb_bus); + } + tot_len += len; + strlcat(buf, local_buf, sizeof(local_buf)); + } + mutex_unlock(&drvdata->mutex); + return simple_read_from_buffer(userbuf, count, ppos, buf, tot_len); +} + +static ssize_t config_write(struct file *filp, + const char __user *user_buf, size_t count, + loff_t *ppos) +{ + int ret, curr_list; + char *token, buf[50]; + char *delim = " "; + struct dcc_drvdata *drvdata = filp->private_data; + + ret = copy_from_user(buf, user_buf, count); + if (ret) + return -EFAULT; + + curr_list = dcc_filp_curr_list(filp); + if (curr_list < 0) + return curr_list; + + if (buf[count - 1] == '\n') + buf[count - 1] = '\0'; + + token = strsep((char **)&buf, delim); + + if (!strcmp("R", token)) { + ret = dcc_config_add_read(drvdata, buf, curr_list); + } else if (!strcmp("W", token)) { + ret = dcc_config_add_write(drvdata, buf, curr_list); + } else if (!strcmp("RW", token)) { + ret = dcc_config_add_read_write(drvdata, buf, curr_list); + } else if (!strcmp("L", token)) { + ret = dcc_config_add_loop(drvdata, buf, curr_list); + } else { + dev_err(drvdata->dev, "%s is not a correct input\n", token); + return -EINVAL; + } + + if (ret) + return ret; + + return count; +} + +static const struct file_operations config_fops = { + .read = config_read, + .write = config_write, + .open = simple_open, + .llseek = generic_file_llseek, +}; + +void dcc_delete_debug_dir(struct dcc_drvdata *dcc) +{ + debugfs_remove_recursive(dcc->dbg_dir); +}; + +int dcc_create_debug_dir(struct dcc_drvdata *dcc) +{ + int i; + char list_num[10]; + struct dentry *list; + struct device *dev = dcc->dev; + + dcc_dbg = debugfs_create_dir(KBUILD_MODNAME, NULL); + if (!dcc_dbg) { + pr_err("can't create debugfs dir\n"); + return -1; + } + + dcc->dbg_dir = debugfs_create_dir(dev_name(dev), dcc_dbg); + if (!dcc->dbg_dir) + return -1; + for (i = 0; i <= dcc->nr_link_list; i++) { + sprintf(list_num, "%d", i); + list = debugfs_create_dir(list_num, dcc->dbg_dir); + debugfs_create_file("enable", 0600, list, dcc, &enable_fops); + debugfs_create_file("config", 0600, list, dcc, &config_fops); + } + + debugfs_create_file("trigger", 0200, dcc->dbg_dir, dcc, &trigger_fops); + debugfs_create_file("ready", 0400, dcc->dbg_dir, dcc, &ready_fops); + debugfs_create_file("config_reset", 0200, dcc->dbg_dir, + dcc, &config_reset_fops); + + return 0; +} + +static ssize_t dcc_sram_read(struct file *file, char __user *data, + size_t len, loff_t *ppos) +{ + unsigned char *buf; + struct dcc_drvdata *drvdata = container_of(file->private_data, + struct dcc_drvdata, + sram_dev); + + /* EOF check */ + if (*ppos > drvdata->ram_size) + return 0; + + if ((*ppos + len) > drvdata->ram_size) + len = (drvdata->ram_size - *ppos); + + buf = kzalloc(len, GFP_KERNEL); + if (!buf) + return -ENOMEM; + + memcpy_fromio(buf, drvdata->ram_base + *ppos, len); + + if (copy_to_user(data, buf, len)) { + kfree(buf); + return -EFAULT; + } + + *ppos += len; + + kfree(buf); + + return len; +} + +static const struct file_operations dcc_sram_fops = { + .owner = THIS_MODULE, + .read = dcc_sram_read, + .llseek = no_llseek, +}; + +static int dcc_sram_dev_init(struct dcc_drvdata *drvdata) +{ + drvdata->sram_dev.minor = MISC_DYNAMIC_MINOR; + drvdata->sram_dev.name = DCC_SRAM_NODE; + drvdata->sram_dev.fops = &dcc_sram_fops; + + return misc_register(&drvdata->sram_dev); +} + +static void dcc_sram_dev_exit(struct dcc_drvdata *drvdata) +{ + misc_deregister(&drvdata->sram_dev); +} + +static int dcc_probe(struct platform_device *pdev) +{ + u32 val; + int ret = 0, i, size; + struct device *dev = &pdev->dev; + struct dcc_drvdata *dcc; + struct resource *res; + + dcc = devm_kzalloc(dev, sizeof(*dcc), GFP_KERNEL); + if (!dcc) + return -ENOMEM; + + dcc->dev = &pdev->dev; + platform_set_drvdata(pdev, dcc); + + dcc->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(dcc->base)) + return PTR_ERR(dcc->base); + + dcc->ram_base = devm_platform_get_and_ioremap_resource(pdev, 1, &res); + if (IS_ERR(dcc->ram_base)) + return PTR_ERR(dcc->ram_base); + + dcc->ram_size = resource_size(res); + + dcc->ram_offset = (size_t)of_device_get_match_data(&pdev->dev); + + val = dcc_readl(dcc, DCC_HW_INFO); + + if (FIELD_GET(DCC_VER_INFO_MASK, val)) { + dcc->mem_map_ver = 3; + dcc->nr_link_list = dcc_readl(dcc, DCC_LL_NUM_INFO); + if (dcc->nr_link_list == 0) + return -EINVAL; + } else if ((val & DCC_VER_MASK2) == DCC_VER_MASK2) { + dcc->mem_map_ver = 2; + dcc->nr_link_list = dcc_readl(dcc, DCC_LL_NUM_INFO); + if (dcc->nr_link_list == 0) + return -EINVAL; + } else { + dcc->mem_map_ver = 1; + dcc->nr_link_list = DCC_MAX_LINK_LIST; + } + + /* Either set the fixed loop offset or calculate it + * from ram_size.Max consecutive addresses the + * dcc can loop is equivalent to the ram size + */ + if (val & DCC_LOOP_OFFSET_MASK) + dcc->loopoff = DCC_FIX_LOOP_OFFSET; + else + dcc->loopoff = get_bitmask_order((dcc->ram_size + + dcc->ram_offset) / 4 - 1); + + mutex_init(&dcc->mutex); + /* Allocate space for all entries at once */ + size = sizeof(*dcc->enable) + sizeof(*dcc->cfg_head); + + dcc->enable = devm_kcalloc(dev, dcc->nr_link_list, size, GFP_KERNEL); + if (!dcc->enable) + return -ENOMEM; + + dcc->cfg_head = (struct list_head *)(dcc->enable + dcc->nr_link_list); + + for (i = 0; i < dcc->nr_link_list; i++) + INIT_LIST_HEAD(&dcc->cfg_head[i]); + + ret = dcc_sram_dev_init(dcc); + if (ret) { + dev_err(dcc->dev, "DCC: sram node not registered.\n"); + return ret; + } + + ret = dcc_create_debug_dir(dcc); + if (ret) { + dev_err(dcc->dev, "DCC: debugfs files not created.\n"); + dcc_sram_dev_exit(dcc); + return ret; + } + + return 0; +} + +static int dcc_remove(struct platform_device *pdev) +{ + struct dcc_drvdata *drvdata = platform_get_drvdata(pdev); + + dcc_delete_debug_dir(drvdata); + + dcc_sram_dev_exit(drvdata); + + dcc_config_reset(drvdata); + + return 0; +} + +static const struct of_device_id dcc_match_table[] = { + { .compatible = "qcom,sm8150-dcc", .data = (void *)0x5000 }, + { .compatible = "qcom,sc7280-dcc", .data = (void *)0x12000 }, + { .compatible = "qcom,sc7180-dcc", .data = (void *)0x6000 }, + { .compatible = "qcom,sdm845-dcc", .data = (void *)0x6000 }, + { } +}; +MODULE_DEVICE_TABLE(of, dcc_match_table); + +static struct platform_driver dcc_driver = { + .probe = dcc_probe, + .remove = dcc_remove, + .driver = { + .name = "qcom-dcc", + .of_match_table = dcc_match_table, + }, +}; + +module_platform_driver(dcc_driver); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Qualcomm Technologies Inc. DCC driver"); + From patchwork Fri Sep 16 08:50:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Souradeep Chowdhury X-Patchwork-Id: 12978276 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2D3B5ECAAD8 for ; Fri, 16 Sep 2022 08:51:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230206AbiIPIvj (ORCPT ); Fri, 16 Sep 2022 04:51:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58756 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230465AbiIPIvf (ORCPT ); Fri, 16 Sep 2022 04:51:35 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A851FA895D; Fri, 16 Sep 2022 01:51:30 -0700 (PDT) Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 28G21PHe024433; Fri, 16 Sep 2022 08:51:20 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=ZbBNrxcBQwnBhSza745vP1mA930IbKsC4iuARxGi58o=; b=OqcPRJvYXbGnguX4KBk6mrMP8hB9nuCUX8PxcfMMbl7CejQg38HKYF8e46kncIJ4GIwr USntAzyvYBOonj8R0QTRY7NlwDRVWxyqh+YbFG9/GTAtSxmBKcpZJlEGj4yNC0izlx70 PFcMBikKloqf7Lwco8igrtLqQSZA7UIHThCRK8RED/DjqA0524MEBt4r+ZclahbooHSk 2oMABpzirjhUZMsU9x1FaB7E5LFHThg0FX+swDpadwNjA+UySMNwzn41MJWCaDS0gYNd 5OlgbJV6c7tcEerNTP58xffgH3BgNR09cL8us2ZvonQUPp+wdYOfoJoMgNCByJeRqV9u 3g== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3jm94pjesk-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 16 Sep 2022 08:51:19 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 28G8pJd3011141 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 16 Sep 2022 08:51:19 GMT Received: from blr-ubuntu-525.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Fri, 16 Sep 2022 01:51:15 -0700 From: Souradeep Chowdhury To: Andy Gross , Bjorn Andersson , Rob Herring , Alex Elder CC: , , , , "Sai Prakash Ranjan" , Sibi Sankar , Rajendra Nayak , , "Souradeep Chowdhury" Subject: [PATCH V11 3/7] MAINTAINERS: Add the entry for DCC(Data Capture and Compare) driver support Date: Fri, 16 Sep 2022 14:20:15 +0530 Message-ID: X-Mailer: git-send-email 2.7.4 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: J1R6G657BFiQWFw6wryxDT2DsEONbue9 X-Proofpoint-ORIG-GUID: J1R6G657BFiQWFw6wryxDT2DsEONbue9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-09-16_04,2022-09-14_04,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 malwarescore=0 lowpriorityscore=0 phishscore=0 spamscore=0 mlxlogscore=640 bulkscore=0 impostorscore=0 clxscore=1015 mlxscore=0 priorityscore=1501 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2209130000 definitions=main-2209160065 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Added the entries for all the files added as a part of driver support for DCC(Data Capture and Compare). Signed-off-by: Souradeep Chowdhury --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index a61f4f3..e57d927 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -5146,6 +5146,14 @@ F: include/linux/tfrc.h F: include/uapi/linux/dccp.h F: net/dccp/ +DCC QTI DRIVER +M: Souradeep Chowdhury +L: linux-arm-msm@vger.kernel.org +S: Maintained +F: Documentation/ABI/testing/debugfs-driver-dcc +F: Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml +F: drivers/soc/qcom/dcc.c + DECnet NETWORK LAYER L: linux-decnet-user@lists.sourceforge.net S: Orphan From patchwork Fri Sep 16 08:50:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Souradeep Chowdhury X-Patchwork-Id: 12978278 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1B236ECAAD8 for ; Fri, 16 Sep 2022 08:52:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231153AbiIPIwI (ORCPT ); Fri, 16 Sep 2022 04:52:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59070 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230512AbiIPIvu (ORCPT ); Fri, 16 Sep 2022 04:51:50 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D8A6EA8969; Fri, 16 Sep 2022 01:51:38 -0700 (PDT) Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 28G87iTI020542; Fri, 16 Sep 2022 08:51:24 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=PHw4Cp4v6vdGRb45xOMKdB4yRLnTQi+nswvzXGS9g5w=; b=pQoKqsoDMJmTbvLtSlN0aDrTybZ/9brPM546UNOr/xcWUPiGtUkv5aKFy4lMOz06QTHl cPkt5VCPA9/GQqoGJzpDD/xiZT2BAouM5uWl52C+JMNZ3w5sq5LgofxOsFrLbIJceDSf M/C5tUJiFA9UsIoRTxDYakEP83ihwTK5HzpszrESL/N2THDOnUDfK1ywuluZCNSMadgk 0aBKqoZUtbY3JXLl2qMXW6wTK3B6GlDChn6pSNkkM4H6HytoLjNRcWojlglp/0doYBda Eb/UdPbR9fUmwsFSAHfFDZ/pNRenoRz5MhHqf4cfSeQqRNM9e3O+tCCJz2BEw3tgPXQT 8w== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3jm9qct9kc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 16 Sep 2022 08:51:23 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 28G8pNQb025227 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 16 Sep 2022 08:51:23 GMT Received: from blr-ubuntu-525.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Fri, 16 Sep 2022 01:51:19 -0700 From: Souradeep Chowdhury To: Andy Gross , Bjorn Andersson , Rob Herring , Alex Elder CC: , , , , "Sai Prakash Ranjan" , Sibi Sankar , Rajendra Nayak , , "Souradeep Chowdhury" Subject: [PATCH V11 4/7] arm64: dts: qcom: sm8150: Add Data Capture and Compare(DCC) support node Date: Fri, 16 Sep 2022 14:20:16 +0530 Message-ID: X-Mailer: git-send-email 2.7.4 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: Vgc5LMbNOPAq5bQ52jO0_TGWS6FDjXSU X-Proofpoint-ORIG-GUID: Vgc5LMbNOPAq5bQ52jO0_TGWS6FDjXSU X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-09-16_04,2022-09-14_04,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 priorityscore=1501 adultscore=0 impostorscore=0 mlxscore=0 mlxlogscore=843 spamscore=0 phishscore=0 lowpriorityscore=0 clxscore=1015 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2209130000 definitions=main-2209160065 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the DCC(Data Capture and Compare) device tree node entry along with the addresses for register regions. Signed-off-by: Souradeep Chowdhury --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index d6d50b4..e0e1d3d 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1627,6 +1627,12 @@ interrupts = ; }; + dma@10a2000 { + compatible = "qcom,sm8150-dcc", "qcom,dcc"; + reg = <0x0 0x010a2000 0x0 0x1000>, + <0x0 0x010ad000 0x0 0x3000>; + }; + ufs_mem_hc: ufshc@1d84000 { compatible = "qcom,sm8150-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; From patchwork Fri Sep 16 08:50:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Souradeep Chowdhury X-Patchwork-Id: 12978280 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C2EE4ECAAD8 for ; Fri, 16 Sep 2022 08:52:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231124AbiIPIwS (ORCPT ); Fri, 16 Sep 2022 04:52:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59614 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230494AbiIPIvx (ORCPT ); Fri, 16 Sep 2022 04:51:53 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E0B0FA8CCA; Fri, 16 Sep 2022 01:51:41 -0700 (PDT) Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 28G8BQdT002491; Fri, 16 Sep 2022 08:51:28 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=c3ANqKgNRqh+v7KfiBpG3Aa7EDx2TG6fg+l2RcsFBps=; b=enYauOX4ldM/nH+FWKOyivn+Qk7VfvT6xMGsWRbz81cN0OAG0LQGwYS6UGMUtl/3ZTP+ jZfplL4v7/F7WHi1naeeigPDAg8wfwNbobTJPvF85pSoFC27PitO+Bnbzh2jzQ0Nlpoe USxkx85wzy69J6X+PmEvNjA57DbsMLsQL6Rul9amhnXEucS0gN9PTn5O49GFFHC6WAlq eUN+PxVNltqFYLyH3VcCXBhxBdFU3PBDET5QYWd9GfKLn2kUMOlp5PIj65/Zjs/PyTem 8FWiaj8mf18a859tK+F0e6LK0qTtjir3o2WdPIf84cKWWTYf2WDBEeUd36s6YEmxkjm/ yw== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3jm8yhhunu-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 16 Sep 2022 08:51:28 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 28G8pRko011186 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 16 Sep 2022 08:51:27 GMT Received: from blr-ubuntu-525.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Fri, 16 Sep 2022 01:51:23 -0700 From: Souradeep Chowdhury To: Andy Gross , Bjorn Andersson , Rob Herring , Alex Elder CC: , , , , "Sai Prakash Ranjan" , Sibi Sankar , Rajendra Nayak , , "Souradeep Chowdhury" Subject: [PATCH V11 5/7] arm64: dts: qcom: sc7280: Add Data Capture and Compare(DCC) support node Date: Fri, 16 Sep 2022 14:20:17 +0530 Message-ID: <118299aee0f83fca67b246f27d6f55004a972619.1663313821.git.quic_schowdhu@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: cV0mK2O0RHDmLK7F5SSivPTJl0DbgcgZ X-Proofpoint-ORIG-GUID: cV0mK2O0RHDmLK7F5SSivPTJl0DbgcgZ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-09-16_04,2022-09-14_04,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 phishscore=0 suspectscore=0 adultscore=0 mlxlogscore=811 mlxscore=0 impostorscore=0 malwarescore=0 spamscore=0 lowpriorityscore=0 clxscore=1015 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2209130000 definitions=main-2209160065 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the DCC(Data Capture and Compare) device tree node entry along with the address of the register region. Signed-off-by: Souradeep Chowdhury --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 53a21d0..54f1ec9 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -661,6 +661,12 @@ #power-domain-cells = <1>; }; + dma@117f000 { + compatible = "qcom,sc7280-dcc", "qcom,dcc"; + reg = <0x0 0x0117f000 0x0 0x1000>, + <0x0 0x01112000 0x0 0x6000>; + }; + stm@6002000 { compatible = "arm,coresight-stm", "arm,primecell"; reg = <0 0x06002000 0 0x1000>, From patchwork Fri Sep 16 08:50:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Souradeep Chowdhury X-Patchwork-Id: 12978279 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 16BD7C6FA8B for ; Fri, 16 Sep 2022 08:52:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231174AbiIPIwN (ORCPT ); Fri, 16 Sep 2022 04:52:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58818 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231124AbiIPIvw (ORCPT ); Fri, 16 Sep 2022 04:51:52 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D90F2A8CD5; Fri, 16 Sep 2022 01:51:42 -0700 (PDT) Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 28G8EZwP009420; Fri, 16 Sep 2022 08:51:32 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=gUkffy8YdmHv4JqQTQk1nv6bVvOjhDHBLpFC5cP2Zhc=; b=XgkWcidybXFOO03oVw3EKGXxtM4wKF6UeHWPJleCTJZJmzgDX1TTmdhfjuv7cN2EPwdH D/vLCUlkUGOQnWUEQHHk4rJkfOecPm1IM++3QiLEi5NM12KiRAJO/shSTCbSAaam9W02 /zOYydGKy1ccO6zWTlKkgdtCWTWyJvw3e2rHOM4HLuJAWOaqmr/Y8bQOcYgRSPtVum+I XIeEWNnN70coLgpOWVYtOP/IpdT0WRPEMTl3S1m07WKT18pJwHuGrOLreerOsmkDKAU0 7IZUatMluHhERz5Bx/XbXFiRWq8s56oPjtHKenrJTcl/fKUva28JBel1ceV8g2HA4ITH uQ== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3jm9umhmg3-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 16 Sep 2022 08:51:32 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 28G8pVEV019587 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 16 Sep 2022 08:51:31 GMT Received: from blr-ubuntu-525.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Fri, 16 Sep 2022 01:51:27 -0700 From: Souradeep Chowdhury To: Andy Gross , Bjorn Andersson , Rob Herring , Alex Elder CC: , , , , "Sai Prakash Ranjan" , Sibi Sankar , Rajendra Nayak , , "Souradeep Chowdhury" Subject: [PATCH V11 6/7] arm64: dts: qcom: sc7180: Add Data Capture and Compare(DCC) support node Date: Fri, 16 Sep 2022 14:20:18 +0530 Message-ID: <1c6510d950c909f4daa78b29fb270eeeb337d4d6.1663313821.git.quic_schowdhu@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 4-wjLfo7qX-JMPmZ5AHCHDgdpyY-CAHN X-Proofpoint-ORIG-GUID: 4-wjLfo7qX-JMPmZ5AHCHDgdpyY-CAHN X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-09-16_04,2022-09-14_04,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 lowpriorityscore=0 bulkscore=0 clxscore=1015 malwarescore=0 phishscore=0 mlxscore=0 mlxlogscore=811 adultscore=0 spamscore=0 suspectscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2209130000 definitions=main-2209160065 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the DCC(Data Capture and Compare) device tree node entry along with the address of the register region. Signed-off-by: Souradeep Chowdhury --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 47b20ba..6e7221d 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -2071,6 +2071,12 @@ #power-domain-cells = <1>; }; + dma@10a2000 { + compatible = "qcom,sc7180-dcc", "qcom,dcc"; + reg = <0x0 0x010a2000 0x0 0x1000>, + <0x0 0x010ae000 0x0 0x2000>; + }; + stm@6002000 { compatible = "arm,coresight-stm", "arm,primecell"; reg = <0 0x06002000 0 0x1000>, From patchwork Fri Sep 16 08:50:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Souradeep Chowdhury X-Patchwork-Id: 12978294 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 61560ECAAD8 for ; Fri, 16 Sep 2022 08:52:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231144AbiIPIwk (ORCPT ); Fri, 16 Sep 2022 04:52:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59498 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230509AbiIPIwH (ORCPT ); Fri, 16 Sep 2022 04:52:07 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F0812A8966; Fri, 16 Sep 2022 01:51:50 -0700 (PDT) Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 28G7w9v7027588; Fri, 16 Sep 2022 08:51:36 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=jgWfAwXuuu0RIdbapJx7yHndhKxVFwzMF8fPwOYRIh4=; b=S1uaTichPB3A61EJf5uwAr+ui3PBlWqSAceITqK17ezLVNep+kwFUklpbRwmqC9YMHfP 1yoMGDSEUnH9xEhNan7R+ok3vt+2N+uFhlVLUQPeghNAC8O/nuOp+HNZfxHB20mV1qIn ZEUKln5LpyJIYaj6JGnLpI7LqVg6pSWqB4c0SUUYFMQmxDZQN8mJ/v25+aifr0xzXbhz quDdc6N1T5Ahpbs6naGq2fS7Wyg7JpcoDih50ptefi9fSZDiGAIpNyHB2voW6fFISLRR oO2GZP5NFi3mQ5e1W2QJOpiPQSq7X6CwmNYMwBQbnH0QnpOt7Keeh9kZBJEquAiTnEYv lA== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3jm8ym9vvn-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 16 Sep 2022 08:51:36 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 28G8pZlb011212 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 16 Sep 2022 08:51:35 GMT Received: from blr-ubuntu-525.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Fri, 16 Sep 2022 01:51:31 -0700 From: Souradeep Chowdhury To: Andy Gross , Bjorn Andersson , Rob Herring , Alex Elder CC: , , , , "Sai Prakash Ranjan" , Sibi Sankar , Rajendra Nayak , , "Souradeep Chowdhury" Subject: [PATCH V11 7/7] arm64: dts: qcom: sdm845: Add Data Capture and Compare(DCC) support node Date: Fri, 16 Sep 2022 14:20:19 +0530 Message-ID: <1fe9f213f09be288be21705e919d4f6d642010f9.1663313821.git.quic_schowdhu@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: u2jc4cQoDhH5RjFLmWAw77WJyrWNlw-Y X-Proofpoint-GUID: u2jc4cQoDhH5RjFLmWAw77WJyrWNlw-Y X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-09-16_04,2022-09-14_04,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 mlxlogscore=815 impostorscore=0 phishscore=0 suspectscore=0 adultscore=0 mlxscore=0 spamscore=0 bulkscore=0 priorityscore=1501 malwarescore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2209130000 definitions=main-2209160065 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the DCC(Data Capture and Compare) device tree node entry along with the address of the register region. Signed-off-by: Souradeep Chowdhury --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index ff6bda1..ee13b5f 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -1968,6 +1968,12 @@ interrupts = ; }; + dma@10a2000 { + compatible = "qcom,sdm845-dcc", "qcom,dcc"; + reg = <0x0 0x010a2000 0x0 0x1000>, + <0x0 0x010ae000 0x0 0x2000>; + }; + pcie0: pci@1c00000 { compatible = "qcom,pcie-sdm845", "snps,dw-pcie"; reg = <0 0x01c00000 0 0x2000>,