From patchwork Tue Sep 20 10:22:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Chaitanya Chundru X-Patchwork-Id: 12981852 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A3437C6FA91 for ; Tue, 20 Sep 2022 10:23:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230197AbiITKXA (ORCPT ); Tue, 20 Sep 2022 06:23:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58298 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229561AbiITKW4 (ORCPT ); Tue, 20 Sep 2022 06:22:56 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3469C6DF8E; Tue, 20 Sep 2022 03:22:54 -0700 (PDT) Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 28K8SKwT018573; Tue, 20 Sep 2022 10:22:34 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references; s=qcppdkim1; bh=X3qxqlW+mUwvpjQqgoQXvawek5rXaIu94AJrsdYu/3E=; b=X+sYZ+vKnbiRTBGWvzXP1K2sbdLZS1/lBZ29t4RM6B8JavgIgE0SH7H4FVGI59PjS0gp EPzdPcW4IYfiu2XUT4dQFFAdU+RuliSQngqngfS+1vZzIGj0pvLXCu0mf1vzf175vJRe XBySWY7oqo19FGP/bc89vU08oiDVg9AqyBDka0NugILGQFRBy8kX3TlKVDog6hgY1xYL aUbQ7gwyRajwJtpHicFDTLCcAH1OCzz2z4tA7zRLwAW+daKrTOe3s+8/1ojwJBtyL1ex eAEC/7/uYtWIk+QZZ/4cUoZRzWTT7MhYVuzv8tSpIumrOvZJkr3UNCT7ZCeXZd5WDPNo dw== Received: from apblrppmta01.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3jqa1k8aqg-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 20 Sep 2022 10:22:34 +0000 Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 28KAMUt6016176; Tue, 20 Sep 2022 10:22:30 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 3jnqrbnbqn-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Tue, 20 Sep 2022 10:22:30 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 28KAMUqc016154; Tue, 20 Sep 2022 10:22:30 GMT Received: from hu-sgudaval-hyd.qualcomm.com (hu-krichai-hyd.qualcomm.com [10.213.110.37]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 28KAMTpQ016148; Tue, 20 Sep 2022 10:22:30 +0000 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 4058933) id 2CFEC19F8; Tue, 20 Sep 2022 15:52:29 +0530 (+0530) From: Krishna chaitanya chundru To: helgaas@kernel.org Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, mka@chromium.org, quic_vbadigan@quicinc.com, quic_hemantk@quicinc.com, quic_nitegupt@quicinc.com, quic_skananth@quicinc.com, quic_ramkri@quicinc.com, manivannan.sadhasivam@linaro.org, swboyd@chromium.org, dmitry.baryshkov@linaro.org, svarbanov@mm-sol.com, agross@kernel.org, andersson@kernel.org, konrad.dybcio@somainline.org, lpieralisi@kernel.org, robh@kernel.org, kw@linux.com, bhelgaas@google.com, linux-phy@lists.infradead.org, vkoul@kernel.org, kishon@ti.com, mturquette@baylibre.com, linux-clk@vger.kernel.org, Krishna chaitanya chundru , Bjorn Andersson Subject: [PATCH v7 1/5] PCI: qcom: Add system suspend and resume support Date: Tue, 20 Sep 2022 15:52:23 +0530 Message-Id: <1663669347-29308-2-git-send-email-quic_krichai@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1663669347-29308-1-git-send-email-quic_krichai@quicinc.com> References: <1663669347-29308-1-git-send-email-quic_krichai@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: iaPTJMpRgGCCFQQ5WkALV4p6-wWAKXRF X-Proofpoint-ORIG-GUID: iaPTJMpRgGCCFQQ5WkALV4p6-wWAKXRF X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-09-20_02,2022-09-16_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 malwarescore=0 adultscore=0 priorityscore=1501 suspectscore=0 bulkscore=0 phishscore=0 mlxscore=0 impostorscore=0 clxscore=1015 mlxlogscore=999 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2209130000 definitions=main-2209200062 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add suspend and resume syscore ops. Few PCIe endpoints like NVMe and WLANs are always expecting the device to be in D0 state and the link to be active (or in l1ss) all the time (including in S3 state). In qcom platform PCIe resources( clocks, phy etc..) can released when the link is in L1ss to reduce the power consumption. So if the link is in L1ss, release the PCIe resources. And when the system resumes, enable the PCIe resources if they released in the suspend path. is_suspended flag indicates if the PCIe resources are released or not in the suspend path. Its observed that access to Ep PCIe space to mask MSI/MSIX is happening at the very late stage of suspend path (access by affinity changes while making CPUs offline during suspend, this will happen after devices are suspended (after all phases of suspend ops)). If we turn off clocks in any PM callback, afterwards running into crashes due to un-clocked access due to above mentioned MSI/MSIx access. So, we are making use of syscore framework to turn off the PCIe clocks which will be called after making CPUs offline. Signed-off-by: Krishna chaitanya chundru --- changes since v6: - move the supports_system_suspend check to syscore ops. changes since v5: - Rebasing the code and replaced pm ops with syscore ops as we are getting access to pci region after pm ops. syscore ops will called after disabling non boot cpus and there is no pci access after that. Changes since v4: - Rebasing the code and removed the supports_system_suspend flag - in the resume path as is_suspended will serve its purpose. Changes since v3: - Powering down the phy in suspend and powering it on resume to achieve maximum power savings. Changes since v2: - Replaced the enable, disable clks ops with suspend and resume - Renamed support_pm_opsi flag with supports_system_suspend. Changes since v1: - Fixed compilation errors. --- drivers/pci/controller/dwc/pcie-qcom.c | 139 ++++++++++++++++++++++++++++++++- 1 file changed, 138 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 39ca06f..3f5424a 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -27,6 +27,7 @@ #include #include #include +#include #include "../../pci.h" #include "pcie-designware.h" @@ -44,6 +45,9 @@ #define PCIE20_PARF_PM_CTRL 0x20 #define REQ_NOT_ENTR_L1 BIT(5) +#define PCIE20_PARF_PM_STTS 0x24 +#define PCIE20_PARF_PM_STTS_LINKST_IN_L1SUB BIT(8) + #define PCIE20_PARF_PHY_CTRL 0x40 #define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK GENMASK(20, 16) #define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) ((x) << 16) @@ -122,6 +126,8 @@ #define QCOM_PCIE_CRC8_POLYNOMIAL (BIT(2) | BIT(1) | BIT(0)) +static LIST_HEAD(qcom_pcie_list); + struct qcom_pcie_resources_2_1_0 { struct clk_bulk_data clks[QCOM_PCIE_2_1_0_MAX_CLOCKS]; struct reset_control *pci_reset; @@ -211,13 +217,21 @@ struct qcom_pcie_ops { void (*post_deinit)(struct qcom_pcie *pcie); void (*ltssm_enable)(struct qcom_pcie *pcie); int (*config_sid)(struct qcom_pcie *pcie); + int (*suspend)(struct qcom_pcie *pcie); + int (*resume)(struct qcom_pcie *pcie); }; struct qcom_pcie_cfg { const struct qcom_pcie_ops *ops; + /* + * Flag ensures which devices will turn off clks, phy + * in system suspend. + */ + unsigned int supports_system_suspend:1; }; struct qcom_pcie { + struct list_head list; /* list to probed instances */ struct dw_pcie *pci; void __iomem *parf; /* DT parf */ void __iomem *elbi; /* DT elbi */ @@ -225,10 +239,14 @@ struct qcom_pcie { struct phy *phy; struct gpio_desc *reset; const struct qcom_pcie_cfg *cfg; + unsigned int is_suspended:1; }; #define to_qcom_pcie(x) dev_get_drvdata((x)->dev) +static int __maybe_unused qcom_pcie_syscore_op_suspend(void); +static void __maybe_unused qcom_pcie_syscore_op_resume(void); + static void qcom_ep_reset_assert(struct qcom_pcie *pcie) { gpiod_set_value_cansleep(pcie->reset, 1); @@ -1301,6 +1319,28 @@ static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie) regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); } +static int qcom_pcie_resume_2_7_0(struct qcom_pcie *pcie) +{ + struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; + int ret; + + ret = clk_bulk_prepare_enable(res->num_clks, res->clks); + + phy_power_on(pcie->phy); + + return ret; +} + +static int qcom_pcie_suspend_2_7_0(struct qcom_pcie *pcie) +{ + struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; + + phy_power_off(pcie->phy); + + clk_bulk_disable_unprepare(res->num_clks, res->clks); + return 0; +} + static int qcom_pcie_get_resources_2_9_0(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0; @@ -1594,6 +1634,8 @@ static const struct qcom_pcie_ops ops_1_9_0 = { .deinit = qcom_pcie_deinit_2_7_0, .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, .config_sid = qcom_pcie_config_sid_sm8250, + .suspend = qcom_pcie_suspend_2_7_0, + .resume = qcom_pcie_resume_2_7_0, }; /* Qcom IP rev.: 2.9.0 Synopsys IP rev.: 5.00a */ @@ -1613,6 +1655,11 @@ static const struct qcom_pcie_cfg cfg_1_9_0 = { .ops = &ops_1_9_0, }; +static const struct qcom_pcie_cfg sc7280_cfg = { + .ops = &ops_1_9_0, + .supports_system_suspend = true, +}; + static const struct qcom_pcie_cfg cfg_2_1_0 = { .ops = &ops_2_1_0, }; @@ -1642,6 +1689,23 @@ static const struct dw_pcie_ops dw_pcie_ops = { .start_link = qcom_pcie_start_link, }; +/* + * There is access to Ep PCIe space to mask MSI/MSIX after pm suspend + * ops.(getting hit by affinity changes while making CPUs offline during + * suspend, this will happen after devices are suspended + * (all phases of suspend ops)). + * + * When registered with pm ops there is a crash due to un-clocked access, + * as in the pm suspend op clocks are disabled. + * + * So, registering with syscore ops which will called after making + * CPU's offline. + */ +static struct syscore_ops qcom_pcie_syscore_ops = { + .suspend = qcom_pcie_syscore_op_suspend, + .resume = qcom_pcie_syscore_op_resume, +}; + static int qcom_pcie_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -1720,6 +1784,17 @@ static int qcom_pcie_probe(struct platform_device *pdev) goto err_phy_exit; } + /* Register for syscore ops only when first instance probed */ + if (list_empty(&qcom_pcie_list)) + register_syscore_ops(&qcom_pcie_syscore_ops); + + /* + * Add the qcom_pcie list of each PCIe instance probed to + * the global list so that we use it iterate through each PCIe + * instance in the syscore ops. + */ + list_add_tail(&pcie->list, &qcom_pcie_list); + return 0; err_phy_exit: @@ -1731,6 +1806,68 @@ static int qcom_pcie_probe(struct platform_device *pdev) return ret; } +static int __maybe_unused qcom_pcie_pm_suspend(struct qcom_pcie *pcie) +{ + u32 val; + struct dw_pcie *pci = pcie->pci; + struct device *dev = pci->dev; + + /* if the link is not active turn off clocks */ + if (!dw_pcie_link_up(pci)) { + dev_dbg(dev, "Link is not active\n"); + goto suspend; + } + + /* if the link is not in l1ss don't turn off clocks */ + val = readl(pcie->parf + PCIE20_PARF_PM_STTS); + if (!(val & PCIE20_PARF_PM_STTS_LINKST_IN_L1SUB)) { + dev_warn(dev, "Link is not in L1ss\n"); + return 0; + } + +suspend: + if (pcie->cfg->ops->suspend) + pcie->cfg->ops->suspend(pcie); + + pcie->is_suspended = true; + + return 0; +} + +static int __maybe_unused qcom_pcie_pm_resume(struct qcom_pcie *pcie) +{ + if (!pcie->is_suspended) + return 0; + + if (pcie->cfg->ops->resume) + pcie->cfg->ops->resume(pcie); + + pcie->is_suspended = false; + + return 0; +} + +static int __maybe_unused qcom_pcie_syscore_op_suspend(void) +{ + struct qcom_pcie *qcom_pcie; + + list_for_each_entry(qcom_pcie, &qcom_pcie_list, list) { + + if (qcom_pcie->cfg->supports_system_suspend) + qcom_pcie_pm_suspend(qcom_pcie); + } + return 0; +} + +static void __maybe_unused qcom_pcie_syscore_op_resume(void) +{ + struct qcom_pcie *qcom_pcie; + + list_for_each_entry(qcom_pcie, &qcom_pcie_list, list) { + qcom_pcie_pm_resume(qcom_pcie); + } +} + static const struct of_device_id qcom_pcie_match[] = { { .compatible = "qcom,pcie-apq8064", .data = &cfg_2_1_0 }, { .compatible = "qcom,pcie-apq8084", .data = &cfg_1_0_0 }, @@ -1742,7 +1879,7 @@ static const struct of_device_id qcom_pcie_match[] = { { .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 }, { .compatible = "qcom,pcie-qcs404", .data = &cfg_2_4_0 }, { .compatible = "qcom,pcie-sa8540p", .data = &cfg_1_9_0 }, - { .compatible = "qcom,pcie-sc7280", .data = &cfg_1_9_0 }, + { .compatible = "qcom,pcie-sc7280", .data = &sc7280_cfg }, { .compatible = "qcom,pcie-sc8180x", .data = &cfg_1_9_0 }, { .compatible = "qcom,pcie-sc8280xp", .data = &cfg_1_9_0 }, { .compatible = "qcom,pcie-sdm845", .data = &cfg_2_7_0 }, From patchwork Tue Sep 20 10:22:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Chaitanya Chundru X-Patchwork-Id: 12981850 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 99F9CC6FA95 for ; Tue, 20 Sep 2022 10:23:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229596AbiITKW7 (ORCPT ); Tue, 20 Sep 2022 06:22:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58300 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229928AbiITKW4 (ORCPT ); Tue, 20 Sep 2022 06:22:56 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C21B850194; Tue, 20 Sep 2022 03:22:54 -0700 (PDT) Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 28KAMYCJ030209; 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Tue, 20 Sep 2022 10:22:30 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 3jnqrbnbqq-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Tue, 20 Sep 2022 10:22:30 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 28KAMUG8016159; Tue, 20 Sep 2022 10:22:30 GMT Received: from hu-sgudaval-hyd.qualcomm.com (hu-krichai-hyd.qualcomm.com [10.213.110.37]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 28KAMTb4016149; Tue, 20 Sep 2022 10:22:30 +0000 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 4058933) id 5E18D19F9; Tue, 20 Sep 2022 15:52:29 +0530 (+0530) From: Krishna chaitanya chundru To: helgaas@kernel.org Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, mka@chromium.org, quic_vbadigan@quicinc.com, quic_hemantk@quicinc.com, quic_nitegupt@quicinc.com, quic_skananth@quicinc.com, quic_ramkri@quicinc.com, manivannan.sadhasivam@linaro.org, swboyd@chromium.org, dmitry.baryshkov@linaro.org, svarbanov@mm-sol.com, agross@kernel.org, andersson@kernel.org, konrad.dybcio@somainline.org, lpieralisi@kernel.org, robh@kernel.org, kw@linux.com, bhelgaas@google.com, linux-phy@lists.infradead.org, vkoul@kernel.org, kishon@ti.com, mturquette@baylibre.com, linux-clk@vger.kernel.org, Krishna chaitanya chundru , Bjorn Andersson Subject: [PATCH v7 2/5] PCI: qcom: Add retry logic for link to be stable in either L1.1 or L1.2 Date: Tue, 20 Sep 2022 15:52:24 +0530 Message-Id: <1663669347-29308-3-git-send-email-quic_krichai@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1663669347-29308-1-git-send-email-quic_krichai@quicinc.com> References: <1663669347-29308-1-git-send-email-quic_krichai@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: MVX-zVMiMf09preCe-06zwyqS_L4eeRU X-Proofpoint-ORIG-GUID: MVX-zVMiMf09preCe-06zwyqS_L4eeRU X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-09-20_02,2022-09-16_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 malwarescore=0 adultscore=0 priorityscore=1501 suspectscore=0 bulkscore=0 phishscore=0 mlxscore=0 impostorscore=0 clxscore=1015 mlxlogscore=951 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2209130000 definitions=main-2209200062 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org When link is in L1ss(L1.1 or L1.2), all the clocks will gate off and there will be no activity on the link. At that point clocks and phy can be turned off. If clocks got disabled before link enters L1ss the PCIe link goes down. Few endpoints are taking time more time to settle the link in L1 substates. When we check the traffic in protocol analyzer, we see some DLLP packets going on still. So Wait for max time of 200ms for the link to be stable in L1 substates. Signed-off-by: Krishna chaitanya chundru --- changes since v6: - updated comments. --- drivers/pci/controller/dwc/pcie-qcom.c | 46 ++++++++++++++++++++++++++-------- 1 file changed, 35 insertions(+), 11 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 3f5424a..7a6f69e 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1809,23 +1809,47 @@ static int qcom_pcie_probe(struct platform_device *pdev) static int __maybe_unused qcom_pcie_pm_suspend(struct qcom_pcie *pcie) { u32 val; + ktime_t timeout, start; struct dw_pcie *pci = pcie->pci; struct device *dev = pci->dev; - /* if the link is not active turn off clocks */ - if (!dw_pcie_link_up(pci)) { - dev_dbg(dev, "Link is not active\n"); - goto suspend; - } + /* + * When link is in L1ss, all the clocks will gate off and + * there will be no activity on the link. At that point clocks + * and phy can be turned off. If clocks got disabled before + * link enters L1ss the PCIe link goes down. + * + * Few endpoints are taking time more time to settle the link + * in L1ss. Wait for max of 200ms for the link to be stable in + * L1ss. + */ + start = ktime_get(); + /* Wait max 200 ms */ + timeout = ktime_add_ms(start, 200); + + while (1) { + /* if the liink is not active turn off clocks */ + if (!dw_pcie_link_up(pci)) { + dev_dbg(dev, "Link is not active\n"); + break; + } - /* if the link is not in l1ss don't turn off clocks */ - val = readl(pcie->parf + PCIE20_PARF_PM_STTS); - if (!(val & PCIE20_PARF_PM_STTS_LINKST_IN_L1SUB)) { - dev_warn(dev, "Link is not in L1ss\n"); - return 0; + /* if the link is not in l1ss don't turn off clocks */ + val = readl(pcie->parf + PCIE20_PARF_PM_STTS); + if ((val & PCIE20_PARF_PM_STTS_LINKST_IN_L1SUB)) { + dev_dbg(dev, "Link enters L1ss after %lld ms\n", + ktime_to_ms(ktime_get() - start)); + break; + } + + if (ktime_after(ktime_get(), timeout)) { + dev_warn(dev, "Link is not in L1ss\n"); + return 0; + } + + udelay(1000); } -suspend: if (pcie->cfg->ops->suspend) pcie->cfg->ops->suspend(pcie); From patchwork Tue Sep 20 10:22:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Chaitanya Chundru X-Patchwork-Id: 12981851 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5CB44C6FA99 for ; Tue, 20 Sep 2022 10:23:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230252AbiITKXB (ORCPT ); Tue, 20 Sep 2022 06:23:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58302 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229939AbiITKW4 (ORCPT ); Tue, 20 Sep 2022 06:22:56 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0B4AE6AA0B; Tue, 20 Sep 2022 03:22:54 -0700 (PDT) Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 28K7xs7Y009306; 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Tue, 20 Sep 2022 10:22:30 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 3jnqrbnbqv-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Tue, 20 Sep 2022 10:22:30 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 28KAMUYx016171; Tue, 20 Sep 2022 10:22:30 GMT Received: from hu-sgudaval-hyd.qualcomm.com (hu-krichai-hyd.qualcomm.com [10.213.110.37]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 28KAMUNg016162; Tue, 20 Sep 2022 10:22:30 +0000 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 4058933) id 9CFAA19FB; Tue, 20 Sep 2022 15:52:29 +0530 (+0530) From: Krishna chaitanya chundru To: helgaas@kernel.org Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, mka@chromium.org, quic_vbadigan@quicinc.com, quic_hemantk@quicinc.com, quic_nitegupt@quicinc.com, quic_skananth@quicinc.com, quic_ramkri@quicinc.com, manivannan.sadhasivam@linaro.org, swboyd@chromium.org, dmitry.baryshkov@linaro.org, svarbanov@mm-sol.com, agross@kernel.org, andersson@kernel.org, konrad.dybcio@somainline.org, lpieralisi@kernel.org, robh@kernel.org, kw@linux.com, bhelgaas@google.com, linux-phy@lists.infradead.org, vkoul@kernel.org, kishon@ti.com, mturquette@baylibre.com, linux-clk@vger.kernel.org, Krishna chaitanya chundru Subject: [PATCH v7 3/5] phy: core: Add support for phy suspend & resume Date: Tue, 20 Sep 2022 15:52:25 +0530 Message-Id: <1663669347-29308-4-git-send-email-quic_krichai@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1663669347-29308-1-git-send-email-quic_krichai@quicinc.com> References: <1663669347-29308-1-git-send-email-quic_krichai@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: iG49z6pzG43hKAh5IJjwaeck3CKweXNZ X-Proofpoint-GUID: iG49z6pzG43hKAh5IJjwaeck3CKweXNZ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-09-20_02,2022-09-16_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 clxscore=1015 impostorscore=0 phishscore=0 adultscore=0 mlxscore=0 bulkscore=0 malwarescore=0 priorityscore=1501 suspectscore=0 spamscore=0 mlxlogscore=779 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2209130000 definitions=main-2209200062 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Introducing phy power suspend and resume callbacks for allowing to park the link-state in L1ss without holding any PCIe resources during system suspend. If we use phy_suspend & phy_resume API's we are getting compilation issue as same function is present in drivers/net/phy/phy_device.c. So creating phy_pm_suspend & phy_pm_resume API's. Signed-off-by: Krishna chaitanya chundru --- changes since v6: - change names from power_down, power_up to suspend & resume respectively. --- drivers/phy/phy-core.c | 30 ++++++++++++++++++++++++++++++ include/linux/phy/phy.h | 20 ++++++++++++++++++++ 2 files changed, 50 insertions(+) diff --git a/drivers/phy/phy-core.c b/drivers/phy/phy-core.c index d93ddf1..ca3e423 100644 --- a/drivers/phy/phy-core.c +++ b/drivers/phy/phy-core.c @@ -441,6 +441,36 @@ int phy_set_speed(struct phy *phy, int speed) } EXPORT_SYMBOL_GPL(phy_set_speed); +int phy_pm_suspend(struct phy *phy) +{ + int ret; + + if (!phy || !phy->ops->suspend) + return 0; + + mutex_lock(&phy->mutex); + ret = phy->ops->suspend(phy); + mutex_unlock(&phy->mutex); + + return ret; +} +EXPORT_SYMBOL_GPL(phy_pm_suspend); + +int phy_pm_resume(struct phy *phy) +{ + int ret; + + if (!phy || !phy->ops->resume) + return 0; + + mutex_lock(&phy->mutex); + ret = phy->ops->resume(phy); + mutex_unlock(&phy->mutex); + + return ret; +} +EXPORT_SYMBOL_GPL(phy_pm_resume); + int phy_reset(struct phy *phy) { int ret; diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h index b141375..e312028 100644 --- a/include/linux/phy/phy.h +++ b/include/linux/phy/phy.h @@ -76,6 +76,8 @@ union phy_configure_opts { * @set_mode: set the mode of the phy * @set_media: set the media type of the phy (optional) * @set_speed: set the speed of the phy (optional) + * @suspend: suspending the phy + * @resume: resuming the phy * @reset: resetting the phy * @calibrate: calibrate the phy * @release: ops to be performed while the consumer relinquishes the PHY @@ -89,6 +91,8 @@ struct phy_ops { int (*set_mode)(struct phy *phy, enum phy_mode mode, int submode); int (*set_media)(struct phy *phy, enum phy_media media); int (*set_speed)(struct phy *phy, int speed); + int (*suspend)(struct phy *phy); + int (*resume)(struct phy *phy); /** * @configure: @@ -226,6 +230,8 @@ int phy_init(struct phy *phy); int phy_exit(struct phy *phy); int phy_power_on(struct phy *phy); int phy_power_off(struct phy *phy); +int phy_pm_suspend(struct phy *phy); +int phy_pm_resume(struct phy *phy); int phy_set_mode_ext(struct phy *phy, enum phy_mode mode, int submode); #define phy_set_mode(phy, mode) \ phy_set_mode_ext(phy, mode, 0) @@ -349,6 +355,20 @@ static inline int phy_power_off(struct phy *phy) return -ENOSYS; } +static inline int phy_pm_suspend(struct phy *phy) +{ + if (!phy) + return 0; + return -ENOSYS; +} + +static inline int phy_pm_resume(struct phy *phy) +{ + if (!phy) + return 0; + return -ENOSYS; +} + static inline int phy_set_mode_ext(struct phy *phy, enum phy_mode mode, int submode) { From patchwork Tue Sep 20 10:22:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Chaitanya Chundru X-Patchwork-Id: 12981848 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 71592C6FA92 for ; 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Tue, 20 Sep 2022 10:22:34 +0000 Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 28KAMUpv016172; Tue, 20 Sep 2022 10:22:31 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 3jnqrbnbqy-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Tue, 20 Sep 2022 10:22:31 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 28KAMUgh016182; Tue, 20 Sep 2022 10:22:30 GMT Received: from hu-sgudaval-hyd.qualcomm.com (hu-krichai-hyd.qualcomm.com [10.213.110.37]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 28KAMUL2016169; Tue, 20 Sep 2022 10:22:30 +0000 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 4058933) id DDF7E1A07; Tue, 20 Sep 2022 15:52:29 +0530 (+0530) From: Krishna chaitanya chundru To: helgaas@kernel.org Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, mka@chromium.org, quic_vbadigan@quicinc.com, quic_hemantk@quicinc.com, quic_nitegupt@quicinc.com, quic_skananth@quicinc.com, quic_ramkri@quicinc.com, manivannan.sadhasivam@linaro.org, swboyd@chromium.org, dmitry.baryshkov@linaro.org, svarbanov@mm-sol.com, agross@kernel.org, andersson@kernel.org, konrad.dybcio@somainline.org, lpieralisi@kernel.org, robh@kernel.org, kw@linux.com, bhelgaas@google.com, linux-phy@lists.infradead.org, vkoul@kernel.org, kishon@ti.com, mturquette@baylibre.com, linux-clk@vger.kernel.org, Krishna chaitanya chundru , Bjorn Andersson Subject: [PATCH v7 4/5] phy: qcom: Add power suspend & resume callbacks to PCIe phy Date: Tue, 20 Sep 2022 15:52:26 +0530 Message-Id: <1663669347-29308-5-git-send-email-quic_krichai@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1663669347-29308-1-git-send-email-quic_krichai@quicinc.com> References: <1663669347-29308-1-git-send-email-quic_krichai@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: Sjn5LIsd3PAAGUkv95Ma8gS-WHXmhmjc X-Proofpoint-GUID: Sjn5LIsd3PAAGUkv95Ma8gS-WHXmhmjc X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-09-20_02,2022-09-16_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 mlxlogscore=693 malwarescore=0 suspectscore=0 spamscore=0 lowpriorityscore=0 clxscore=1015 impostorscore=0 mlxscore=0 bulkscore=0 priorityscore=1501 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2209130000 definitions=main-2209200062 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add phy power suspend & resume callbacks to PCIe phy. Using these callbacks we can release phy resources like phy specific clocks but continue maintain PCIe link in l1ss state. This can help in parking PCIe link in l1ss state during system suspend (S3). Instead of this if we add suspend & resume pm ops, phy will suspend first instead of PCIe driver, it will cause link down as phy will be down before controller goes down. Signed-off-by: Krishna chaitanya chundru --- changes since v6: - Change names from phy_power_down and phy_power_up to phy_pm_suspend and phy_pm_resume respectively. --- drivers/pci/controller/dwc/pcie-qcom.c | 4 +-- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 50 ++++++++++++++++++++++++++++++++ 2 files changed, 52 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 7a6f69e..672a9be 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1326,7 +1326,7 @@ static int qcom_pcie_resume_2_7_0(struct qcom_pcie *pcie) ret = clk_bulk_prepare_enable(res->num_clks, res->clks); - phy_power_on(pcie->phy); + phy_pm_resume(pcie->phy); return ret; } @@ -1335,7 +1335,7 @@ static int qcom_pcie_suspend_2_7_0(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; - phy_power_off(pcie->phy); + phy_pm_suspend(pcie->phy); clk_bulk_disable_unprepare(res->num_clks, res->clks); return 0; diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 2d65e1f..69220dd 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -2145,6 +2145,54 @@ static int qcom_qmp_phy_pcie_exit(struct phy *phy) return 0; } +static int qcom_qmp_phy_pcie_resume(struct phy *phy) +{ + struct qmp_phy *qphy = phy_get_drvdata(phy); + struct qcom_qmp *qmp = qphy->qmp; + const struct qmp_phy_cfg *cfg = qphy->cfg; + int ret; + + ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); + if (ret) + return ret; + + ret = clk_prepare_enable(qphy->pipe_clk); + if (ret) + return ret; + + /* Pull out PHY from POWER DOWN state */ + if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) { + qphy_setbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], + cfg->pwrdn_ctrl); + } else { + qphy_setbits(qphy->pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, + cfg->pwrdn_ctrl); + } + + return 0; +} + +static int qcom_qmp_phy_pcie_suspend(struct phy *phy) +{ + struct qmp_phy *qphy = phy_get_drvdata(phy); + struct qcom_qmp *qmp = qphy->qmp; + const struct qmp_phy_cfg *cfg = qphy->cfg; + + clk_disable_unprepare(qphy->pipe_clk); + clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); + + /* Put PHY into POWER DOWN state: active low */ + if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) { + qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], + cfg->pwrdn_ctrl); + } else { + qphy_clrbits(qphy->pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, + cfg->pwrdn_ctrl); + } + + return 0; +} + static int qcom_qmp_phy_pcie_enable(struct phy *phy) { int ret; @@ -2304,6 +2352,8 @@ static const struct phy_ops qcom_qmp_phy_pcie_ops = { .power_on = qcom_qmp_phy_pcie_enable, .power_off = qcom_qmp_phy_pcie_disable, .set_mode = qcom_qmp_phy_pcie_set_mode, + .suspend = qcom_qmp_phy_pcie_suspend, + .resume = qcom_qmp_phy_pcie_resume, .owner = THIS_MODULE, }; From patchwork Tue Sep 20 10:22:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Chaitanya Chundru X-Patchwork-Id: 12981847 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 12DA5ECAAD8 for ; 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Tue, 20 Sep 2022 10:22:34 +0000 Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 28KAMVlW016209; Tue, 20 Sep 2022 10:22:31 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 3jnqrbnbr6-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Tue, 20 Sep 2022 10:22:31 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 28KAJDH9014240; Tue, 20 Sep 2022 10:22:31 GMT Received: from hu-sgudaval-hyd.qualcomm.com (hu-krichai-hyd.qualcomm.com [10.213.110.37]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 28KAMUcX016193; Tue, 20 Sep 2022 10:22:31 +0000 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 4058933) id 18FE31A0A; Tue, 20 Sep 2022 15:52:30 +0530 (+0530) From: Krishna chaitanya chundru To: helgaas@kernel.org Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, mka@chromium.org, quic_vbadigan@quicinc.com, quic_hemantk@quicinc.com, quic_nitegupt@quicinc.com, quic_skananth@quicinc.com, quic_ramkri@quicinc.com, manivannan.sadhasivam@linaro.org, swboyd@chromium.org, dmitry.baryshkov@linaro.org, svarbanov@mm-sol.com, agross@kernel.org, andersson@kernel.org, konrad.dybcio@somainline.org, lpieralisi@kernel.org, robh@kernel.org, kw@linux.com, bhelgaas@google.com, linux-phy@lists.infradead.org, vkoul@kernel.org, kishon@ti.com, mturquette@baylibre.com, linux-clk@vger.kernel.org, Krishna chaitanya chundru , Bjorn Andersson , Stephen Boyd Subject: [PATCH v7 5/5] clk: qcom: gcc-sc7280: Update the .pwrsts for PCIe GDSC Date: Tue, 20 Sep 2022 15:52:27 +0530 Message-Id: <1663669347-29308-6-git-send-email-quic_krichai@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1663669347-29308-1-git-send-email-quic_krichai@quicinc.com> References: <1663669347-29308-1-git-send-email-quic_krichai@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: i22Kw6cglr45nfDrZ8fX6cgxsUowuBmL X-Proofpoint-GUID: i22Kw6cglr45nfDrZ8fX6cgxsUowuBmL X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-09-20_02,2022-09-16_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 clxscore=1015 impostorscore=0 phishscore=0 adultscore=0 mlxscore=0 bulkscore=0 malwarescore=0 priorityscore=1501 suspectscore=0 spamscore=0 mlxlogscore=802 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2209130000 definitions=main-2209200062 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Enabling PCIe GDSC retention to ensure controller and its dependent clocks won't go down during system suspend. Update the .pwrsts for PCIe GDSC so it only transitions to RET in low power. Signed-off-by: Krishna chaitanya chundru --- changes since v6: - Instead of marking as ALWAYS_ON setting .pwrsts to RET in low power. --- drivers/clk/qcom/gcc-sc7280.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/qcom/gcc-sc7280.c b/drivers/clk/qcom/gcc-sc7280.c index 7ff64d4..e66069c 100644 --- a/drivers/clk/qcom/gcc-sc7280.c +++ b/drivers/clk/qcom/gcc-sc7280.c @@ -3108,7 +3108,7 @@ static struct gdsc gcc_pcie_1_gdsc = { .pd = { .name = "gcc_pcie_1_gdsc", }, - .pwrsts = PWRSTS_OFF_ON, + .pwrsts = PWRSTS_RET_ON, .flags = VOTABLE, };