From patchwork Tue Sep 20 14:01:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?SmFzb24tSkggTGluICjmnpfnnb/npaUp?= X-Patchwork-Id: 12982236 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 97B2DECAAD8 for ; Tue, 20 Sep 2022 14:02:11 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C3C8710E5C2; Tue, 20 Sep 2022 14:01:59 +0000 (UTC) Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3730D10E5C9 for ; Tue, 20 Sep 2022 14:01:54 +0000 (UTC) X-UUID: b7d757cb1c8949b29160afe94bfc0a26-20220920 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=TyVFTKI2N/4V5RXql18bi63eq9DUhb732RoGa9fikGk=; b=NTbx35PUcdDuiVdHtJss2GFOQmAxI3r02kjCco1HYIZ03LdTsApAiuCmAtfCBd5vvbLxVEFzmrqxwnkmcsXyaLsCn/IAHmyirhiplptgxkBNBY0UD5cgAWCnLV+DQTyJsK/Tvr+cukdpPVTNJcgaGV7Y+SXgCGGkbB0lnxbOoOo=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.11, REQID:33bd7ee0-550f-4b49-91bb-6db838b8cc4a, IP:0, U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTI ON:release,TS:70 X-CID-INFO: VERSION:1.1.11, REQID:33bd7ee0-550f-4b49-91bb-6db838b8cc4a, IP:0, URL :0,TC:0,Content:-25,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTI ON:quarantine,TS:70 X-CID-META: VersionHash:39a5ff1, CLOUDID:f3766e70-dafa-4a42-b716-cf2cd4845592, B ulkID:220920220151RGUGSRWU,BulkQuantity:0,Recheck:0,SF:28|17|19|48|823|824 ,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL :0 X-UUID: b7d757cb1c8949b29160afe94bfc0a26-20220920 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 465838816; Tue, 20 Sep 2022 22:01:48 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Tue, 20 Sep 2022 22:01:46 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Tue, 20 Sep 2022 22:01:46 +0800 From: Jason-JH.Lin To: Matthias Brugger , Chun-Kuang Hu , Rob Herring , Krzysztof Kozlowski , AngeloGioacchino Del Regno Subject: [PATCH v3 1/6] dt-bindings: arm: mediatek: mmsys: change compatible for MT8195 Date: Tue, 20 Sep 2022 22:01:40 +0800 Message-ID: <20220920140145.19973-2-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220920140145.19973-1-jason-jh.lin@mediatek.com> References: <20220920140145.19973-1-jason-jh.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, "Jason-JH.Lin" , Singo Chang , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Project_Global_Chrome_Upstream_Group@mediatek.com, Rex-BC Chen , Nancy Lin , linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" For previous MediaTek SoCs, such as MT8173, there are 2 display HW pipelines binding to 1 mmsys with the same power domain, the same clock driver and the same mediatek-drm driver. For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines binding to 2 different power domains, different clock drivers and different mediatek-drm drivers. Moreover, Hardware pipeline of VDOSYS0 has these components: COLOR, CCORR, AAL, GAMMA, DITHER. They are related to the PQ (Picture Quality) and they makes VDOSYS0 supports PQ function while they are not including in VDOSYS1. Hardware pipeline of VDOSYS1 has the component ETHDR (HDR related component). It makes VDOSYS1 supports the HDR function while it's not including in VDOSYS0. To summarize0: Only VDOSYS0 can support PQ adjustment. Only VDOSYS1 can support HDR adjustment. Therefore, we need to separate these two different mmsys hardwares to 2 different compatibles for MT8195. Fixes: 81c5a41d10b9 ("dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding") Signed-off-by: Jason-JH.Lin Signed-off-by: Bo-Chen Chen --- .../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml index 6ad023eec193..df9184b6772c 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml @@ -38,6 +38,10 @@ properties: - const: mediatek,mt7623-mmsys - const: mediatek,mt2701-mmsys - const: syscon + - items: + - const: mediatek,mt8195-vdosys0 + - const: mediatek,mt8195-mmsys + - const: syscon reg: maxItems: 1 From patchwork Tue Sep 20 14:01:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?SmFzb24tSkggTGluICjmnpfnnb/npaUp?= X-Patchwork-Id: 12982238 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1E9BBC54EE9 for ; Tue, 20 Sep 2022 14:02:44 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D911E10E6C4; Tue, 20 Sep 2022 14:02:41 +0000 (UTC) Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by gabe.freedesktop.org (Postfix) with ESMTPS id 75F8A10E5C2 for ; Tue, 20 Sep 2022 14:01:55 +0000 (UTC) X-UUID: a49bb29bf47a4cd0bbe1caabbd068f10-20220920 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=1/1Ku4TKTJIecK9KwoQZ4UL0RtHBi42vComhWuhRuFs=; b=Y2iUn5WwPhcFtFSxn4arH+s80HRe9RWw4mZWJGmMgeSgijjPjhxh/4q6uAOLeOjd9KwvlaQhsF8FLINN/W9BbRpCj+gacfhVtILxcN3G50Eb6fTRflAreIebZXzkpfMS6+BF7Vxh+MtCxTfvqjpOyAaYC4hTJG0VE6jf6MZtRQo=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.11, REQID:584b2f45-8ebc-4e3c-9c32-03e2657cfe34, IP:0, U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:39a5ff1, CLOUDID:ed766e70-dafa-4a42-b716-cf2cd4845592, B ulkID:nil,BulkQuantity:0,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: a49bb29bf47a4cd0bbe1caabbd068f10-20220920 Received: from mtkmbs11n2.mediatek.inc [(172.21.101.187)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1693444552; Tue, 20 Sep 2022 22:01:48 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Tue, 20 Sep 2022 22:01:47 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Tue, 20 Sep 2022 22:01:47 +0800 From: Jason-JH.Lin To: Matthias Brugger , Chun-Kuang Hu , Rob Herring , "Krzysztof Kozlowski" , AngeloGioacchino Del Regno Subject: [PATCH v3 2/6] Revert "soc: mediatek: add mtk-mmsys support for mt8195 vdosys0" Date: Tue, 20 Sep 2022 22:01:41 +0800 Message-ID: <20220920140145.19973-3-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220920140145.19973-1-jason-jh.lin@mediatek.com> References: <20220920140145.19973-1-jason-jh.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, "Jason-JH.Lin" , Singo Chang , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Project_Global_Chrome_Upstream_Group@mediatek.com, Rex-BC Chen , Nancy Lin , linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" This reverts commit b804923b7ccb9c9629703364e927b48cd02a9254. Due to the compatible changing of mt8195 from "mediatek,mt8195-mmsys" to "mediatek,mt8195-vdosys0", we have to revert this patch and send a new patch with the new compatible. Signed-off-by: Jason-JH.Lin --- drivers/soc/mediatek/mt8195-mmsys.h | 370 ---------------------------- drivers/soc/mediatek/mtk-mmsys.c | 152 +----------- drivers/soc/mediatek/mtk-mmsys.h | 6 - 3 files changed, 11 insertions(+), 517 deletions(-) delete mode 100644 drivers/soc/mediatek/mt8195-mmsys.h diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h deleted file mode 100644 index abfe94a30248..000000000000 --- a/drivers/soc/mediatek/mt8195-mmsys.h +++ /dev/null @@ -1,370 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __SOC_MEDIATEK_MT8195_MMSYS_H -#define __SOC_MEDIATEK_MT8195_MMSYS_H - -#define MT8195_VDO0_OVL_MOUT_EN 0xf14 -#define MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0 BIT(0) -#define MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0 BIT(1) -#define MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1 BIT(2) -#define MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1 BIT(4) -#define MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1 BIT(5) -#define MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0 BIT(6) - -#define MT8195_VDO0_SEL_IN 0xf34 -#define MT8195_SEL_IN_VPP_MERGE_FROM_MASK GENMASK(1, 0) -#define MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT (0 << 0) -#define MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1 (1 << 0) -#define MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0 (2 << 0) -#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK GENMASK(4, 4) -#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 (0 << 4) -#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE (1 << 4) -#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK GENMASK(5, 5) -#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1 (0 << 5) -#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE (1 << 5) -#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK GENMASK(8, 8) -#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE (0 << 8) -#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT (1 << 8) -#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK GENMASK(9, 9) -#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT (0 << 9) -#define MT8195_SEL_IN_DP_INTF0_FROM_MASK GENMASK(13, 12) -#define MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT (0 << 0) -#define MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE (1 << 12) -#define MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0 (2 << 12) -#define MT8195_SEL_IN_DSI0_FROM_MASK GENMASK(16, 16) -#define MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT (0 << 16) -#define MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0 (1 << 16) -#define MT8195_SEL_IN_DSI1_FROM_MASK GENMASK(17, 17) -#define MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT (0 << 17) -#define MT8195_SEL_IN_DSI1_FROM_VPP_MERGE (1 << 17) -#define MT8195_SEL_IN_DISP_WDMA1_FROM_MASK GENMASK(20, 20) -#define MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1 (0 << 20) -#define MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE (1 << 20) -#define MT8195_SEL_IN_DSC_WRAP1_FROM_MASK GENMASK(21, 21) -#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN (0 << 21) -#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 (1 << 21) -#define MT8195_SEL_IN_DISP_WDMA0_FROM_MASK GENMASK(22, 22) -#define MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0 (0 << 22) - -#define MT8195_VDO0_SEL_OUT 0xf38 -#define MT8195_SOUT_DISP_DITHER0_TO_MASK BIT(0) -#define MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN (0 << 0) -#define MT8195_SOUT_DISP_DITHER0_TO_DSI0 (1 << 0) -#define MT8195_SOUT_DISP_DITHER1_TO_MASK GENMASK(2, 1) -#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN (0 << 1) -#define MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE (1 << 1) -#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT (2 << 1) -#define MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK GENMASK(4, 4) -#define MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE (0 << 4) -#define MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0 (1 << 4) -#define MT8195_SOUT_VPP_MERGE_TO_MASK GENMASK(10, 8) -#define MT8195_SOUT_VPP_MERGE_TO_DSI1 (0 << 8) -#define MT8195_SOUT_VPP_MERGE_TO_DP_INTF0 (1 << 8) -#define MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 (2 << 8) -#define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1 (3 << 8) -#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN (4 << 8) -#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK GENMASK(11, 11) -#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN (0 << 11) -#define MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK GENMASK(13, 12) -#define MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0 (0 << 12) -#define MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 (1 << 12) -#define MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE (2 << 12) -#define MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK GENMASK(17, 16) -#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1 (0 << 16) -#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0 (1 << 16) -#define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 << 16) -#define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE (3 << 16) - -static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = { - { - DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, - MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0, - MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0 - }, { - DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0, - MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0, - MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0 - }, { - DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL1, - MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1, - MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1 - }, { - DDP_COMPONENT_OVL1, DDP_COMPONENT_RDMA1, - MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1, - MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1 - }, { - DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1, - MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1, - MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1 - }, { - DDP_COMPONENT_OVL1, DDP_COMPONENT_OVL0, - MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0, - MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0 - }, { - DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK, - MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT - }, { - DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK, - MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1 - }, { - DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK, - MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0 - }, { - DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSC0, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK, - MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 - }, { - DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK, - MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE - }, { - DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK, - MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1 - }, { - DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK, - MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE - }, { - DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK, - MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE - }, { - DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK, - MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE - }, { - DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK, - MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE - }, { - DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK, - MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT - }, { - DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK, - MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT - }, { - DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK, - MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT - }, { - DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK, - MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT - }, { - DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK, - MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT - }, { - DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK, - MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT - }, { - DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK, - MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT - }, { - DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK, - MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE - }, { - DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK, - MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0 - }, { - DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK, - MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT - }, { - DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK, - MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0 - }, { - DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK, - MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT - }, { - DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK, - MT8195_SEL_IN_DSI1_FROM_VPP_MERGE - }, { - DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK, - MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1 - }, { - DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK, - MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE - }, { - DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, - MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN - }, { - DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, - MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN - }, { - DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, - MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN - }, { - DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, - MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN - }, { - DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, - MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN - }, { - DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, - MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN - }, { - DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, - MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 - }, { - DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, - MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 - }, { - DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, - MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 - }, { - DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, - MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 - }, { - DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0, - MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA0_FROM_MASK, - MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0 - }, { - DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSC0, - MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK, - MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN - }, { - DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0, - MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK, - MT8195_SOUT_DISP_DITHER0_TO_DSI0 - }, { - DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1, - MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, - MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN - }, { - DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0, - MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, - MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE - }, { - DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1, - MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, - MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT - }, { - DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0, - MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, - MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT - }, { - DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF1, - MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, - MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT - }, { - DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0, - MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, - MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT - }, { - DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1, - MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, - MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT - }, { - DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0, - MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK, - MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE - }, { - DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0, - MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK, - MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0 - }, { - DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1, - MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, - MT8195_SOUT_VPP_MERGE_TO_DSI1 - }, { - DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0, - MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, - MT8195_SOUT_VPP_MERGE_TO_DP_INTF0 - }, { - DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1, - MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, - MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 - }, { - DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0, - MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, - MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 - }, { - DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1, - MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, - MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 - }, { - DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1, - MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, - MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1 - }, { - DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0, - MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, - MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN - }, { - DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1, - MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK, - MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN - }, { - DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0, - MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK, - MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0 - }, { - DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1, - MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK, - MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 - }, { - DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0, - MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK, - MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 - }, { - DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1, - MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK, - MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 - }, { - DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0, - MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK, - MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE - }, { - DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1, - MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK, - MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1 - }, { - DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0, - MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK, - MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0 - }, { - DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1, - MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK, - MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 - }, { - DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0, - MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK, - MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 - }, { - DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1, - MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK, - MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 - }, { - DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0, - MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK, - MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE - } -}; - -#endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */ diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index d2c7a87aab87..2dd626945e58 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -17,7 +17,6 @@ #include "mt8183-mmsys.h" #include "mt8186-mmsys.h" #include "mt8192-mmsys.h" -#include "mt8195-mmsys.h" #include "mt8365-mmsys.h" static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { @@ -26,61 +25,26 @@ static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { .num_routes = ARRAY_SIZE(mmsys_default_routing_table), }; -static const struct mtk_mmsys_match_data mt2701_mmsys_match_data = { - .num_drv_data = 1, - .drv_data = { - &mt2701_mmsys_driver_data, - }, -}; - static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { .clk_driver = "clk-mt2712-mm", .routes = mmsys_default_routing_table, .num_routes = ARRAY_SIZE(mmsys_default_routing_table), }; -static const struct mtk_mmsys_match_data mt2712_mmsys_match_data = { - .num_drv_data = 1, - .drv_data = { - &mt2712_mmsys_driver_data, - }, -}; - static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = { .clk_driver = "clk-mt6779-mm", }; -static const struct mtk_mmsys_match_data mt6779_mmsys_match_data = { - .num_drv_data = 1, - .drv_data = { - &mt6779_mmsys_driver_data, - }, -}; - static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = { .clk_driver = "clk-mt6797-mm", }; -static const struct mtk_mmsys_match_data mt6797_mmsys_match_data = { - .num_drv_data = 1, - .drv_data = { - &mt6797_mmsys_driver_data, - }, -}; - static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = { .clk_driver = "clk-mt8167-mm", .routes = mt8167_mmsys_routing_table, .num_routes = ARRAY_SIZE(mt8167_mmsys_routing_table), }; -static const struct mtk_mmsys_match_data mt8167_mmsys_match_data = { - .num_drv_data = 1, - .drv_data = { - &mt8167_mmsys_driver_data, - }, -}; - static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { .clk_driver = "clk-mt8173-mm", .routes = mmsys_default_routing_table, @@ -88,13 +52,6 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B, }; -static const struct mtk_mmsys_match_data mt8173_mmsys_match_data = { - .num_drv_data = 1, - .drv_data = { - &mt8173_mmsys_driver_data, - }, -}; - static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { .clk_driver = "clk-mt8183-mm", .routes = mmsys_mt8183_routing_table, @@ -102,13 +59,6 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B, }; -static const struct mtk_mmsys_match_data mt8183_mmsys_match_data = { - .num_drv_data = 1, - .drv_data = { - &mt8183_mmsys_driver_data, - }, -}; - static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = { .clk_driver = "clk-mt8186-mm", .routes = mmsys_mt8186_routing_table, @@ -116,13 +66,6 @@ static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = { .sw0_rst_offset = MT8186_MMSYS_SW0_RST_B, }; -static const struct mtk_mmsys_match_data mt8186_mmsys_match_data = { - .num_drv_data = 1, - .drv_data = { - &mt8186_mmsys_driver_data, - }, -}; - static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { .clk_driver = "clk-mt8192-mm", .routes = mmsys_mt8192_routing_table, @@ -130,66 +73,19 @@ static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { .sw0_rst_offset = MT8186_MMSYS_SW0_RST_B, }; -static const struct mtk_mmsys_match_data mt8192_mmsys_match_data = { - .num_drv_data = 1, - .drv_data = { - &mt8192_mmsys_driver_data, - }, -}; - -static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = { - .io_start = 0x1c01a000, - .clk_driver = "clk-mt8195-vdo0", - .routes = mmsys_mt8195_routing_table, - .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table), -}; - -static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = { - .io_start = 0x1c100000, - .clk_driver = "clk-mt8195-vdo1", -}; - -static const struct mtk_mmsys_match_data mt8195_mmsys_match_data = { - .num_drv_data = 2, - .drv_data = { - &mt8195_vdosys0_driver_data, - &mt8195_vdosys1_driver_data, - }, -}; - static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = { .clk_driver = "clk-mt8365-mm", .routes = mt8365_mmsys_routing_table, .num_routes = ARRAY_SIZE(mt8365_mmsys_routing_table), }; -static const struct mtk_mmsys_match_data mt8365_mmsys_match_data = { - .num_drv_data = 1, - .drv_data = { - &mt8365_mmsys_driver_data, - }, -}; - struct mtk_mmsys { void __iomem *regs; const struct mtk_mmsys_driver_data *data; spinlock_t lock; /* protects mmsys_sw_rst_b reg */ struct reset_controller_dev rcdev; - phys_addr_t io_start; }; -static int mtk_mmsys_find_match_drvdata(struct mtk_mmsys *mmsys, - const struct mtk_mmsys_match_data *match) -{ - int i; - - for (i = 0; i < match->num_drv_data; i++) - if (mmsys->io_start == match->drv_data[i]->io_start) - return i; - - return -EINVAL; -} - void mtk_mmsys_ddp_connect(struct device *dev, enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next) @@ -304,9 +200,7 @@ static int mtk_mmsys_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct platform_device *clks; struct platform_device *drm; - const struct mtk_mmsys_match_data *match_data; struct mtk_mmsys *mmsys; - struct resource *res; int ret; mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL); @@ -332,27 +226,7 @@ static int mtk_mmsys_probe(struct platform_device *pdev) return ret; } - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) { - dev_err(dev, "Couldn't get mmsys resource\n"); - return -EINVAL; - } - mmsys->io_start = res->start; - - match_data = of_device_get_match_data(dev); - if (match_data->num_drv_data > 1) { - /* This SoC has multiple mmsys channels */ - ret = mtk_mmsys_find_match_drvdata(mmsys, match_data); - if (ret < 0) { - dev_err(dev, "Couldn't get match driver data\n"); - return ret; - } - mmsys->data = match_data->drv_data[ret]; - } else { - dev_dbg(dev, "Using single mmsys channel\n"); - mmsys->data = match_data->drv_data[0]; - } - + mmsys->data = of_device_get_match_data(&pdev->dev); platform_set_drvdata(pdev, mmsys); clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver, @@ -373,47 +247,43 @@ static int mtk_mmsys_probe(struct platform_device *pdev) static const struct of_device_id of_match_mtk_mmsys[] = { { .compatible = "mediatek,mt2701-mmsys", - .data = &mt2701_mmsys_match_data, + .data = &mt2701_mmsys_driver_data, }, { .compatible = "mediatek,mt2712-mmsys", - .data = &mt2712_mmsys_match_data, + .data = &mt2712_mmsys_driver_data, }, { .compatible = "mediatek,mt6779-mmsys", - .data = &mt6779_mmsys_match_data, + .data = &mt6779_mmsys_driver_data, }, { .compatible = "mediatek,mt6797-mmsys", - .data = &mt6797_mmsys_match_data, + .data = &mt6797_mmsys_driver_data, }, { .compatible = "mediatek,mt8167-mmsys", - .data = &mt8167_mmsys_match_data, + .data = &mt8167_mmsys_driver_data, }, { .compatible = "mediatek,mt8173-mmsys", - .data = &mt8173_mmsys_match_data, + .data = &mt8173_mmsys_driver_data, }, { .compatible = "mediatek,mt8183-mmsys", - .data = &mt8183_mmsys_match_data, + .data = &mt8183_mmsys_driver_data, }, { .compatible = "mediatek,mt8186-mmsys", - .data = &mt8186_mmsys_match_data, + .data = &mt8186_mmsys_driver_data, }, { .compatible = "mediatek,mt8192-mmsys", - .data = &mt8192_mmsys_match_data, - }, - { - .compatible = "mediatek,mt8195-mmsys", - .data = &mt8195_mmsys_match_data, + .data = &mt8192_mmsys_driver_data, }, { .compatible = "mediatek,mt8365-mmsys", - .data = &mt8365_mmsys_match_data, + .data = &mt8365_mmsys_driver_data, }, { } }; diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h index f01ba206481d..77f37f8c715b 100644 --- a/drivers/soc/mediatek/mtk-mmsys.h +++ b/drivers/soc/mediatek/mtk-mmsys.h @@ -87,18 +87,12 @@ struct mtk_mmsys_routes { }; struct mtk_mmsys_driver_data { - const resource_size_t io_start; const char *clk_driver; const struct mtk_mmsys_routes *routes; const unsigned int num_routes; const u16 sw0_rst_offset; }; -struct mtk_mmsys_match_data { - unsigned short num_drv_data; - const struct mtk_mmsys_driver_data *drv_data[]; -}; - /* * Routes in mt8173, mt2701, mt2712 are different. That means * in the same register address, it controls different input/output From patchwork Tue Sep 20 14:01:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?SmFzb24tSkggTGluICjmnpfnnb/npaUp?= X-Patchwork-Id: 12982240 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9BE67C54EE9 for ; Tue, 20 Sep 2022 14:02:53 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 95B9810E6C8; Tue, 20 Sep 2022 14:02:43 +0000 (UTC) Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by gabe.freedesktop.org (Postfix) with ESMTPS id B10BA10E54C for ; Tue, 20 Sep 2022 14:01:54 +0000 (UTC) X-UUID: 17016db4ca864cd494e2a542d46fd8f5-20220920 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=IfULUsGyjFzBH1kGw7s+1slRJ5leY0sOaPBLXJOyWH0=; b=e+m+LIGYV6LQFhvPkkIksVb8O4UFHXoD0sPkcCy2PC8LXDyEcDkkYte98eOvCFl6e3bsXQJefI5BTWKsuGzoLQSzC3LiFKvKiReC4tDt17+b/6/glMwo2ZDtVfdfQT8/w8l8ncTBZkq8pEr4YZWCok7y4Ub0uAlLAlTbDzmF0cg=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.11, REQID:f8ba1ecb-f4de-44df-9c23-e145d8d51efc, IP:0, U RL:0,TC:0,Content:36,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:36 X-CID-META: VersionHash:39a5ff1, CLOUDID:eb766e70-dafa-4a42-b716-cf2cd4845592, B ulkID:nil,BulkQuantity:0,Recheck:0,SF:nil,TC:nil,Content:4,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 17016db4ca864cd494e2a542d46fd8f5-20220920 Received: from mtkmbs11n2.mediatek.inc [(172.21.101.187)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1560109628; Tue, 20 Sep 2022 22:01:48 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Tue, 20 Sep 2022 22:01:47 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Tue, 20 Sep 2022 22:01:47 +0800 From: Jason-JH.Lin To: Matthias Brugger , Chun-Kuang Hu , Rob Herring , "Krzysztof Kozlowski" , AngeloGioacchino Del Regno Subject: [PATCH v3 3/6] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0 Date: Tue, 20 Sep 2022 22:01:42 +0800 Message-ID: <20220920140145.19973-4-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220920140145.19973-1-jason-jh.lin@mediatek.com> References: <20220920140145.19973-1-jason-jh.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, "Jason-JH.Lin" , Singo Chang , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Project_Global_Chrome_Upstream_Group@mediatek.com, Rex-BC Chen , Nancy Lin , linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" 1. Add mt8195 driver data with compatible "mediatek-mt8195-vdosys0". 2. Add mt8195 routing table settings of vdosys0. Signed-off-by: Jason-JH.Lin --- drivers/soc/mediatek/mt8195-mmsys.h | 370 ++++++++++++++++++++++++++++ drivers/soc/mediatek/mtk-mmsys.c | 11 + 2 files changed, 381 insertions(+) create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h new file mode 100644 index 000000000000..abfe94a30248 --- /dev/null +++ b/drivers/soc/mediatek/mt8195-mmsys.h @@ -0,0 +1,370 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8195_MMSYS_H +#define __SOC_MEDIATEK_MT8195_MMSYS_H + +#define MT8195_VDO0_OVL_MOUT_EN 0xf14 +#define MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0 BIT(0) +#define MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0 BIT(1) +#define MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1 BIT(2) +#define MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1 BIT(4) +#define MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1 BIT(5) +#define MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0 BIT(6) + +#define MT8195_VDO0_SEL_IN 0xf34 +#define MT8195_SEL_IN_VPP_MERGE_FROM_MASK GENMASK(1, 0) +#define MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT (0 << 0) +#define MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1 (1 << 0) +#define MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0 (2 << 0) +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK GENMASK(4, 4) +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 (0 << 4) +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE (1 << 4) +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK GENMASK(5, 5) +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1 (0 << 5) +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE (1 << 5) +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK GENMASK(8, 8) +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE (0 << 8) +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT (1 << 8) +#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK GENMASK(9, 9) +#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT (0 << 9) +#define MT8195_SEL_IN_DP_INTF0_FROM_MASK GENMASK(13, 12) +#define MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT (0 << 0) +#define MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE (1 << 12) +#define MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0 (2 << 12) +#define MT8195_SEL_IN_DSI0_FROM_MASK GENMASK(16, 16) +#define MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT (0 << 16) +#define MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0 (1 << 16) +#define MT8195_SEL_IN_DSI1_FROM_MASK GENMASK(17, 17) +#define MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT (0 << 17) +#define MT8195_SEL_IN_DSI1_FROM_VPP_MERGE (1 << 17) +#define MT8195_SEL_IN_DISP_WDMA1_FROM_MASK GENMASK(20, 20) +#define MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1 (0 << 20) +#define MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE (1 << 20) +#define MT8195_SEL_IN_DSC_WRAP1_FROM_MASK GENMASK(21, 21) +#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN (0 << 21) +#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 (1 << 21) +#define MT8195_SEL_IN_DISP_WDMA0_FROM_MASK GENMASK(22, 22) +#define MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0 (0 << 22) + +#define MT8195_VDO0_SEL_OUT 0xf38 +#define MT8195_SOUT_DISP_DITHER0_TO_MASK BIT(0) +#define MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN (0 << 0) +#define MT8195_SOUT_DISP_DITHER0_TO_DSI0 (1 << 0) +#define MT8195_SOUT_DISP_DITHER1_TO_MASK GENMASK(2, 1) +#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN (0 << 1) +#define MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE (1 << 1) +#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT (2 << 1) +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK GENMASK(4, 4) +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE (0 << 4) +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0 (1 << 4) +#define MT8195_SOUT_VPP_MERGE_TO_MASK GENMASK(10, 8) +#define MT8195_SOUT_VPP_MERGE_TO_DSI1 (0 << 8) +#define MT8195_SOUT_VPP_MERGE_TO_DP_INTF0 (1 << 8) +#define MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 (2 << 8) +#define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1 (3 << 8) +#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN (4 << 8) +#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK GENMASK(11, 11) +#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN (0 << 11) +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK GENMASK(13, 12) +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0 (0 << 12) +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 (1 << 12) +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE (2 << 12) +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK GENMASK(17, 16) +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1 (0 << 16) +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0 (1 << 16) +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 << 16) +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE (3 << 16) + +static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = { + { + DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, + MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0, + MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0 + }, { + DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0, + MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0, + MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0 + }, { + DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL1, + MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1, + MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1 + }, { + DDP_COMPONENT_OVL1, DDP_COMPONENT_RDMA1, + MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1, + MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1 + }, { + DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1, + MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1, + MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1 + }, { + DDP_COMPONENT_OVL1, DDP_COMPONENT_OVL0, + MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0, + MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0 + }, { + DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK, + MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT + }, { + DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK, + MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1 + }, { + DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK, + MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0 + }, { + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSC0, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK, + MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 + }, { + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK, + MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE + }, { + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK, + MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1 + }, { + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK, + MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE + }, { + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK, + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE + }, { + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK, + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE + }, { + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK, + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE + }, { + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK, + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT + }, { + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK, + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT + }, { + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK, + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT + }, { + DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK, + MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT + }, { + DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK, + MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT + }, { + DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK, + MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT + }, { + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK, + MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT + }, { + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK, + MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE + }, { + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK, + MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0 + }, { + DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK, + MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT + }, { + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK, + MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0 + }, { + DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK, + MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT + }, { + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK, + MT8195_SEL_IN_DSI1_FROM_VPP_MERGE + }, { + DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK, + MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1 + }, { + DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK, + MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE + }, { + DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN + }, { + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN + }, { + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN + }, { + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN + }, { + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN + }, { + DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN + }, { + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 + }, { + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 + }, { + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 + }, { + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 + }, { + DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0, + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA0_FROM_MASK, + MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0 + }, { + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSC0, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK, + MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN + }, { + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK, + MT8195_SOUT_DISP_DITHER0_TO_DSI0 + }, { + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN + }, { + DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, + MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE + }, { + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT + }, { + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT + }, { + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF1, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT + }, { + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT + }, { + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT + }, { + DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK, + MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE + }, { + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK, + MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0 + }, { + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, + MT8195_SOUT_VPP_MERGE_TO_DSI1 + }, { + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, + MT8195_SOUT_VPP_MERGE_TO_DP_INTF0 + }, { + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, + MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 + }, { + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, + MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 + }, { + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, + MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 + }, { + DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, + MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1 + }, { + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, + MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN + }, { + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK, + MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN + }, { + DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK, + MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0 + }, { + DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK, + MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 + }, { + DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK, + MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 + }, { + DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK, + MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 + }, { + DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK, + MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE + }, { + DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK, + MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1 + }, { + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK, + MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0 + }, { + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK, + MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 + }, { + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK, + MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 + }, { + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK, + MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 + }, { + DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0, + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK, + MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE + } +}; + +#endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */ diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index 2dd626945e58..146a78ba06c1 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -17,6 +17,7 @@ #include "mt8183-mmsys.h" #include "mt8186-mmsys.h" #include "mt8192-mmsys.h" +#include "mt8195-mmsys.h" #include "mt8365-mmsys.h" static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { @@ -73,6 +74,12 @@ static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { .sw0_rst_offset = MT8186_MMSYS_SW0_RST_B, }; +static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = { + .clk_driver = "clk-mt8195-vdo0", + .routes = mmsys_mt8195_routing_table, + .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table), +}; + static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = { .clk_driver = "clk-mt8365-mm", .routes = mt8365_mmsys_routing_table, @@ -281,6 +288,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = { .compatible = "mediatek,mt8192-mmsys", .data = &mt8192_mmsys_driver_data, }, + { + .compatible = "mediatek,mt8195-vdosys0", + .data = &mt8195_vdosys0_driver_data, + }, { .compatible = "mediatek,mt8365-mmsys", .data = &mt8365_mmsys_driver_data, From patchwork Tue Sep 20 14:01:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?SmFzb24tSkggTGluICjmnpfnnb/npaUp?= X-Patchwork-Id: 12982241 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9D689ECAAD8 for ; Tue, 20 Sep 2022 14:03:18 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0A17F10E5C9; Tue, 20 Sep 2022 14:03:17 +0000 (UTC) Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by gabe.freedesktop.org (Postfix) with ESMTPS id B802B10E5C9 for ; Tue, 20 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ulkID:220920220151KIJ37W8C,BulkQuantity:0,Recheck:0,SF:28|17|19|48|823|824 ,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL :0 X-UUID: 10ace3caeb9c48baa00f902e1d059059-20220920 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 657572787; Tue, 20 Sep 2022 22:01:49 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Tue, 20 Sep 2022 22:01:47 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Tue, 20 Sep 2022 22:01:47 +0800 From: Jason-JH.Lin To: Matthias Brugger , Chun-Kuang Hu , Rob Herring , Krzysztof Kozlowski , AngeloGioacchino Del Regno Subject: [PATCH v3 4/6] Revert "drm/mediatek: Add mediatek-drm of vdosys0 support for mt8195" Date: Tue, 20 Sep 2022 22:01:43 +0800 Message-ID: <20220920140145.19973-5-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220920140145.19973-1-jason-jh.lin@mediatek.com> References: <20220920140145.19973-1-jason-jh.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, "Jason-JH.Lin" , Singo Chang , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Project_Global_Chrome_Upstream_Group@mediatek.com, Rex-BC Chen , Nancy Lin , linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" This reverts commit 7266e90a51a32722a94daa3cb5b8fa278059e49e. Due to the compatible changing of mt8195 from "mediatek,mt8195-mmsys" to "mediatek,mt8195-vdosys0", we have to revert this patch and send a new patch with the new compatible. Signed-off-by: Jason-JH.Lin --- drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 8 +- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 150 ++--------------------- drivers/gpu/drm/mediatek/mtk_drm_drv.h | 6 - 3 files changed, 14 insertions(+), 150 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c index 0ec2e4049e07..2cb90466798c 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c @@ -370,8 +370,8 @@ static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = { .fifo_size = 5 * SZ_1K, }; -static const struct mtk_disp_rdma_data mt8195_rdma_driver_data = { - .fifo_size = 1920, +static const struct mtk_disp_rdma_data mt8192_rdma_driver_data = { + .fifo_size = 5 * SZ_1K, }; static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = { @@ -381,8 +381,8 @@ static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = { .data = &mt8173_rdma_driver_data}, { .compatible = "mediatek,mt8183-disp-rdma", .data = &mt8183_rdma_driver_data}, - { .compatible = "mediatek,mt8195-disp-rdma", - .data = &mt8195_rdma_driver_data}, + { .compatible = "mediatek,mt8192-disp-rdma", + .data = &mt8192_rdma_driver_data}, {}, }; MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match); diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index 5f02f8d0e4fc..adc9a4f4085b 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -4,8 +4,6 @@ * Author: YT SHEN */ -#include -#include #include #include #include @@ -197,19 +195,6 @@ static const enum mtk_ddp_comp_id mt8192_mtk_ddp_ext[] = { DDP_COMPONENT_DPI0, }; -static const enum mtk_ddp_comp_id mt8195_mtk_ddp_main[] = { - DDP_COMPONENT_OVL0, - DDP_COMPONENT_RDMA0, - DDP_COMPONENT_COLOR0, - DDP_COMPONENT_CCORR, - DDP_COMPONENT_AAL0, - DDP_COMPONENT_GAMMA, - DDP_COMPONENT_DITHER0, - DDP_COMPONENT_DSC0, - DDP_COMPONENT_MERGE0, - DDP_COMPONENT_DP_INTF0, -}; - static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { .main_path = mt2701_mtk_ddp_main, .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main), @@ -218,13 +203,6 @@ static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { .shadow_register = true, }; -static const struct mtk_mmsys_match_data mt2701_mmsys_match_data = { - .num_drv_data = 1, - .drv_data = { - &mt2701_mmsys_driver_data, - }, -}; - static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = { .main_path = mt7623_mtk_ddp_main, .main_len = ARRAY_SIZE(mt7623_mtk_ddp_main), @@ -233,13 +211,6 @@ static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = { .shadow_register = true, }; -static const struct mtk_mmsys_match_data mt7623_mmsys_match_data = { - .num_drv_data = 1, - .drv_data = { - &mt7623_mmsys_driver_data, - }, -}; - static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { .main_path = mt2712_mtk_ddp_main, .main_len = ARRAY_SIZE(mt2712_mtk_ddp_main), @@ -249,25 +220,11 @@ static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { .third_len = ARRAY_SIZE(mt2712_mtk_ddp_third), }; -static const struct mtk_mmsys_match_data mt2712_mmsys_match_data = { - .num_drv_data = 1, - .drv_data = { - &mt2712_mmsys_driver_data, - }, -}; - static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = { .main_path = mt8167_mtk_ddp_main, .main_len = ARRAY_SIZE(mt8167_mtk_ddp_main), }; -static const struct mtk_mmsys_match_data mt8167_mmsys_match_data = { - .num_drv_data = 1, - .drv_data = { - &mt8167_mmsys_driver_data, - }, -}; - static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { .main_path = mt8173_mtk_ddp_main, .main_len = ARRAY_SIZE(mt8173_mtk_ddp_main), @@ -275,13 +232,6 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { .ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext), }; -static const struct mtk_mmsys_match_data mt8173_mmsys_match_data = { - .num_drv_data = 1, - .drv_data = { - &mt8173_mmsys_driver_data, - }, -}; - static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { .main_path = mt8183_mtk_ddp_main, .main_len = ARRAY_SIZE(mt8183_mtk_ddp_main), @@ -289,13 +239,6 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext), }; -static const struct mtk_mmsys_match_data mt8183_mmsys_match_data = { - .num_drv_data = 1, - .drv_data = { - &mt8183_mmsys_driver_data, - }, -}; - static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = { .main_path = mt8186_mtk_ddp_main, .main_len = ARRAY_SIZE(mt8186_mtk_ddp_main), @@ -303,13 +246,6 @@ static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = { .ext_len = ARRAY_SIZE(mt8186_mtk_ddp_ext), }; -static const struct mtk_mmsys_match_data mt8186_mmsys_match_data = { - .num_drv_data = 1, - .drv_data = { - &mt8186_mmsys_driver_data, - }, -}; - static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { .main_path = mt8192_mtk_ddp_main, .main_len = ARRAY_SIZE(mt8192_mtk_ddp_main), @@ -317,31 +253,6 @@ static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { .ext_len = ARRAY_SIZE(mt8192_mtk_ddp_ext), }; -static const struct mtk_mmsys_match_data mt8192_mmsys_match_data = { - .num_drv_data = 1, - .drv_data = { - &mt8192_mmsys_driver_data, - }, -}; - -static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = { - .io_start = 0x1c01a000, - .main_path = mt8195_mtk_ddp_main, - .main_len = ARRAY_SIZE(mt8195_mtk_ddp_main), -}; - -static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = { - .io_start = 0x1c100000, -}; - -static const struct mtk_mmsys_match_data mt8195_mmsys_match_data = { - .num_drv_data = 1, - .drv_data = { - &mt8195_vdosys0_driver_data, - &mt8195_vdosys1_driver_data, - }, -}; - static int mtk_drm_kms_init(struct drm_device *drm) { struct mtk_drm_private *private = drm->dev_private; @@ -559,16 +470,12 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { .data = (void *)MTK_DISP_DITHER }, { .compatible = "mediatek,mt8183-disp-dither", .data = (void *)MTK_DISP_DITHER }, - { .compatible = "mediatek,mt8195-disp-dsc", - .data = (void *)MTK_DISP_DSC }, { .compatible = "mediatek,mt8167-disp-gamma", .data = (void *)MTK_DISP_GAMMA, }, { .compatible = "mediatek,mt8173-disp-gamma", .data = (void *)MTK_DISP_GAMMA, }, { .compatible = "mediatek,mt8183-disp-gamma", .data = (void *)MTK_DISP_GAMMA, }, - { .compatible = "mediatek,mt8195-disp-merge", - .data = (void *)MTK_DISP_MERGE }, { .compatible = "mediatek,mt2701-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt2712-disp-mutex", @@ -583,8 +490,6 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt8192-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, - { .compatible = "mediatek,mt8195-disp-mutex", - .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt8173-disp-od", .data = (void *)MTK_DISP_OD }, { .compatible = "mediatek,mt2701-disp-ovl", @@ -617,7 +522,7 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { .data = (void *)MTK_DISP_RDMA }, { .compatible = "mediatek,mt8183-disp-rdma", .data = (void *)MTK_DISP_RDMA }, - { .compatible = "mediatek,mt8195-disp-rdma", + { .compatible = "mediatek,mt8192-disp-rdma", .data = (void *)MTK_DISP_RDMA }, { .compatible = "mediatek,mt8173-disp-ufoe", .data = (void *)MTK_DISP_UFOE }, @@ -648,53 +553,30 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { static const struct of_device_id mtk_drm_of_ids[] = { { .compatible = "mediatek,mt2701-mmsys", - .data = &mt2701_mmsys_match_data}, + .data = &mt2701_mmsys_driver_data}, { .compatible = "mediatek,mt7623-mmsys", - .data = &mt7623_mmsys_match_data}, + .data = &mt7623_mmsys_driver_data}, { .compatible = "mediatek,mt2712-mmsys", - .data = &mt2712_mmsys_match_data}, + .data = &mt2712_mmsys_driver_data}, { .compatible = "mediatek,mt8167-mmsys", - .data = &mt8167_mmsys_match_data}, + .data = &mt8167_mmsys_driver_data}, { .compatible = "mediatek,mt8173-mmsys", - .data = &mt8173_mmsys_match_data}, + .data = &mt8173_mmsys_driver_data}, { .compatible = "mediatek,mt8183-mmsys", - .data = &mt8183_mmsys_match_data}, + .data = &mt8183_mmsys_driver_data}, { .compatible = "mediatek,mt8186-mmsys", - .data = &mt8186_mmsys_match_data}, + .data = &mt8186_mmsys_driver_data}, { .compatible = "mediatek,mt8192-mmsys", - .data = &mt8192_mmsys_match_data}, - { .compatible = "mediatek,mt8195-mmsys", - .data = &mt8195_mmsys_match_data}, + .data = &mt8192_mmsys_driver_data}, { } }; MODULE_DEVICE_TABLE(of, mtk_drm_of_ids); -static int mtk_drm_find_match_data(struct device *dev, - const struct mtk_mmsys_match_data *match_data) -{ - int i; - struct platform_device *pdev = of_find_device_by_node(dev->parent->of_node); - struct resource *res; - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) { - dev_err(dev, "failed to get parent resource\n"); - return -EINVAL; - } - - for (i = 0; i < match_data->num_drv_data; i++) - if (match_data->drv_data[i]->io_start == res->start) - return i; - - return -EINVAL; -} - static int mtk_drm_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct device_node *phandle = dev->parent->of_node; const struct of_device_id *of_id; - const struct mtk_mmsys_match_data *match_data; struct mtk_drm_private *private; struct device_node *node; struct component_match *match = NULL; @@ -715,19 +597,7 @@ static int mtk_drm_probe(struct platform_device *pdev) if (!of_id) return -ENODEV; - match_data = of_id->data; - if (match_data->num_drv_data > 1) { - /* This SoC has multiple mmsys channels */ - ret = mtk_drm_find_match_data(dev, match_data); - if (ret < 0) { - dev_err(dev, "Couldn't get match driver data\n"); - return ret; - } - private->data = match_data->drv_data[ret]; - } else { - dev_dbg(dev, "Using single mmsys channel\n"); - private->data = match_data->drv_data[0]; - } + private->data = of_id->data; /* Iterate over sibling DISP function blocks */ for_each_child_of_node(phandle->parent, node) { diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h index 7b37b5cf9629..64a1f66df26a 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h @@ -21,7 +21,6 @@ struct drm_property; struct regmap; struct mtk_mmsys_driver_data { - const resource_size_t io_start; const enum mtk_ddp_comp_id *main_path; unsigned int main_len; const enum mtk_ddp_comp_id *ext_path; @@ -32,11 +31,6 @@ struct mtk_mmsys_driver_data { bool shadow_register; }; -struct mtk_mmsys_match_data { - unsigned short num_drv_data; - const struct mtk_mmsys_driver_data *drv_data[]; -}; - struct mtk_drm_private { struct drm_device *drm; struct device *dma_dev; From patchwork Tue Sep 20 14:01:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?SmFzb24tSkggTGluICjmnpfnnb/npaUp?= X-Patchwork-Id: 12982239 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AFD43C6FA8E for ; Tue, 20 Sep 2022 14:02:48 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8C55410E6C6; Tue, 20 Sep 2022 14:02:42 +0000 (UTC) Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by gabe.freedesktop.org (Postfix) with ESMTPS id B7D0610E5CA for ; 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Tue, 20 Sep 2022 22:01:49 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Tue, 20 Sep 2022 22:01:47 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Tue, 20 Sep 2022 22:01:47 +0800 From: Jason-JH.Lin To: Matthias Brugger , Chun-Kuang Hu , Rob Herring , Krzysztof Kozlowski , AngeloGioacchino Del Regno Subject: [PATCH v3 5/6] drm/mediatek: add mediatek-drm of vdosys0 support for mt8195 Date: Tue, 20 Sep 2022 22:01:44 +0800 Message-ID: <20220920140145.19973-6-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220920140145.19973-1-jason-jh.lin@mediatek.com> References: <20220920140145.19973-1-jason-jh.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, "Jason-JH.Lin" , Singo Chang , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Project_Global_Chrome_Upstream_Group@mediatek.com, Rex-BC Chen , Nancy Lin , linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add driver data of mt8195 vdosys0 to mediatek-drm and the sub driver. Signed-off-by: Jason-JH.Lin --- drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 +++++ drivers/gpu/drm/mediatek/mtk_drm_drv.c | 28 ++++++++++++++++++++++++ 2 files changed, 34 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c index 2cb90466798c..66cdd0bc1311 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c @@ -374,6 +374,10 @@ static const struct mtk_disp_rdma_data mt8192_rdma_driver_data = { .fifo_size = 5 * SZ_1K, }; +static const struct mtk_disp_rdma_data mt8195_rdma_driver_data = { + .fifo_size = 1920, +}; + static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = { { .compatible = "mediatek,mt2701-disp-rdma", .data = &mt2701_rdma_driver_data}, @@ -383,6 +387,8 @@ static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = { .data = &mt8183_rdma_driver_data}, { .compatible = "mediatek,mt8192-disp-rdma", .data = &mt8192_rdma_driver_data}, + { .compatible = "mediatek,mt8195-disp-rdma", + .data = &mt8195_rdma_driver_data}, {}, }; MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match); diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index adc9a4f4085b..9b5a7a7ddde0 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -195,6 +195,19 @@ static const enum mtk_ddp_comp_id mt8192_mtk_ddp_ext[] = { DDP_COMPONENT_DPI0, }; +static const enum mtk_ddp_comp_id mt8195_mtk_ddp_main[] = { + DDP_COMPONENT_OVL0, + DDP_COMPONENT_RDMA0, + DDP_COMPONENT_COLOR0, + DDP_COMPONENT_CCORR, + DDP_COMPONENT_AAL0, + DDP_COMPONENT_GAMMA, + DDP_COMPONENT_DITHER0, + DDP_COMPONENT_DSC0, + DDP_COMPONENT_MERGE0, + DDP_COMPONENT_DP_INTF0, +}; + static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { .main_path = mt2701_mtk_ddp_main, .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main), @@ -253,6 +266,11 @@ static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { .ext_len = ARRAY_SIZE(mt8192_mtk_ddp_ext), }; +static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = { + .main_path = mt8195_mtk_ddp_main, + .main_len = ARRAY_SIZE(mt8195_mtk_ddp_main), +}; + static int mtk_drm_kms_init(struct drm_device *drm) { struct mtk_drm_private *private = drm->dev_private; @@ -470,12 +488,16 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { .data = (void *)MTK_DISP_DITHER }, { .compatible = "mediatek,mt8183-disp-dither", .data = (void *)MTK_DISP_DITHER }, + { .compatible = "mediatek,mt8195-disp-dsc", + .data = (void *)MTK_DISP_DSC }, { .compatible = "mediatek,mt8167-disp-gamma", .data = (void *)MTK_DISP_GAMMA, }, { .compatible = "mediatek,mt8173-disp-gamma", .data = (void *)MTK_DISP_GAMMA, }, { .compatible = "mediatek,mt8183-disp-gamma", .data = (void *)MTK_DISP_GAMMA, }, + { .compatible = "mediatek,mt8195-disp-merge", + .data = (void *)MTK_DISP_MERGE }, { .compatible = "mediatek,mt2701-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt2712-disp-mutex", @@ -490,6 +512,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt8192-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, + { .compatible = "mediatek,mt8195-disp-mutex", + .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt8173-disp-od", .data = (void *)MTK_DISP_OD }, { .compatible = "mediatek,mt2701-disp-ovl", @@ -524,6 +548,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { .data = (void *)MTK_DISP_RDMA }, { .compatible = "mediatek,mt8192-disp-rdma", .data = (void *)MTK_DISP_RDMA }, + { .compatible = "mediatek,mt8195-disp-rdma", + .data = (void *)MTK_DISP_RDMA }, { .compatible = "mediatek,mt8173-disp-ufoe", .data = (void *)MTK_DISP_UFOE }, { .compatible = "mediatek,mt8173-disp-wdma", @@ -568,6 +594,8 @@ static const struct of_device_id mtk_drm_of_ids[] = { .data = &mt8186_mmsys_driver_data}, { .compatible = "mediatek,mt8192-mmsys", .data = &mt8192_mmsys_driver_data}, + { .compatible = "mediatek,mt8195-vdosys0", + .data = &mt8195_vdosys0_driver_data}, { } }; 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Tue, 20 Sep 2022 22:01:49 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Tue, 20 Sep 2022 22:01:47 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Tue, 20 Sep 2022 22:01:47 +0800 From: Jason-JH.Lin To: Matthias Brugger , Chun-Kuang Hu , Rob Herring , Krzysztof Kozlowski , AngeloGioacchino Del Regno Subject: [PATCH v3 6/6] soc: mediatek: remove DDP_DOMPONENT_DITHER from enum Date: Tue, 20 Sep 2022 22:01:45 +0800 Message-ID: <20220920140145.19973-7-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220920140145.19973-1-jason-jh.lin@mediatek.com> References: <20220920140145.19973-1-jason-jh.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, "Jason-JH.Lin" , Singo Chang , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Project_Global_Chrome_Upstream_Group@mediatek.com, Rex-BC Chen , Nancy Lin , linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" After mmsys and drm change DITHER enum to DDP_COMPONENT_DITHER0, mmsys header can remove the useless DDP_COMPONENT_DITHER enum. Signed-off-by: Jason-JH.Lin Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Rex-BC Chen Acked-by: Matthias Brugger --- include/linux/soc/mediatek/mtk-mmsys.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index d2b02bb43768..16ac0e5847f0 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -16,8 +16,7 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_CCORR, DDP_COMPONENT_COLOR0, DDP_COMPONENT_COLOR1, - DDP_COMPONENT_DITHER, - DDP_COMPONENT_DITHER0 = DDP_COMPONENT_DITHER, + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0, DDP_COMPONENT_DP_INTF1,