From patchwork Wed Sep 21 08:22:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 12983347 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C9420C6FA8B for ; Wed, 21 Sep 2022 08:24:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231357AbiIUIXg (ORCPT ); Wed, 21 Sep 2022 04:23:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46726 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229626AbiIUIXa (ORCPT ); Wed, 21 Sep 2022 04:23:30 -0400 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2043.outbound.protection.outlook.com [40.107.244.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1185C83049; Wed, 21 Sep 2022 01:23:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=l3j6l1jWaFdiYWiKvv1nl0TkpM/iy5DsmqQmJR/hldPBCIaAXz7MBGoCLX5tUF0rILc7Vy8ROYaRTlhVQo8xkZVWqveEre6opRr8TEUE4ZhkSAmlFL+hfQb0maGGmylnuszAovEIwD7ePN1zPzHIThzMkhd4n9cnf4SJMGozoX8kB2+KUvRq3G9z5eLKj0IZPAk4Lv/ZsU+8iLSIgs3ruRrCIUSc6yII2BxM5jggOwZMs3BSZhLXzAU7pY9/D843XrcRoLT45iWii/+0FHrKvxLZXuVCPvqwdC/e6xVRYQYg7OZFfzN901p0oJbQuRATOYGGpAnAaqzknA9PTWaxvg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=sVWuaU1xhsyPp0FldJ+R6UJIQ/awjc7dyDtFiRvl6jY=; b=RcsTFJ7td2VjW2SwOuRgwQINX+xTwiw1OM97AS9fBaQFKxrmyi887xdtoeCQDAtz1l/6yLxZ84CjaU7IK6IzpKY6c2bH3XsxgSCoutnazo4rLjlDXJwqgDXivuBlP4Swt+PM4haO2S8g/Z5anyQLVCYW47hKrZrtiyDwVZDj1gGdHUn6SEYu0ocP3p5xYGa3GMNpswdwUzBFKQyPMaO09mKe1xbiq2wVFU24oJdSMX6aTveTwG/kJZRogEs+OUNyyesjUfbON7ZWtmA3TH66CoHOrc9yVxnVlDSHouLC5DxFPH7/0ZPnVmab3N1mnwiaY0YnYr5mNCAlT6cP8EyHmA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=sVWuaU1xhsyPp0FldJ+R6UJIQ/awjc7dyDtFiRvl6jY=; b=ipwFkZuwiUfU3lKQATOOxY+t8sf3oCHScGZWrtQKMfpCOS/RTEF7IZ2qtt/Xcckbn/ifz2FKzssQwkdvHtTNAT5S5KqVxXt3rD9C5Quc9Jdn4ZAyO2cXN1zFFPwBx+HzLXdmJQJC9vYWRMUa1OtMgBpN6UFEOHBOX7cOTdu60OwxCPAVxo6fvECNgIg2vZDJBeUxDe1mJ6nHW9dL9y7WvkGbSWV0ruHECDU9QiZW9yBGtb21AblbNXVvuVMMqXr2IYeh7+odvIZ8PVBj8y7u6sWZfiWFIysgkoM1ZA+nfyIruGyiDJD7EE8CMmgWsWWs2OEbjOrd61RSuFHNUApaHQ== Received: from MW4PR04CA0309.namprd04.prod.outlook.com (2603:10b6:303:82::14) by DM6PR12MB4299.namprd12.prod.outlook.com (2603:10b6:5:223::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5632.21; Wed, 21 Sep 2022 08:23:17 +0000 Received: from CO1NAM11FT089.eop-nam11.prod.protection.outlook.com (2603:10b6:303:82:cafe::ea) by MW4PR04CA0309.outlook.office365.com (2603:10b6:303:82::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5654.17 via Frontend Transport; Wed, 21 Sep 2022 08:23:17 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by CO1NAM11FT089.mail.protection.outlook.com (10.13.175.179) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5654.14 via Frontend Transport; Wed, 21 Sep 2022 08:23:17 +0000 Received: from rnnvmail205.nvidia.com (10.129.68.10) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.26; Wed, 21 Sep 2022 01:22:58 -0700 Received: from rnnvmail202.nvidia.com (10.129.68.7) by rnnvmail205.nvidia.com (10.129.68.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Wed, 21 Sep 2022 01:22:58 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.14) by mail.nvidia.com (10.129.68.7) with Microsoft SMTP Server id 15.2.986.29 via Frontend Transport; Wed, 21 Sep 2022 01:22:57 -0700 From: Nicolin Chen To: , , , , , , CC: , , , , Subject: [PATCH v4 1/6] iommu/msm: Fix error-out routine in msm_iommu_attach_dev() Date: Wed, 21 Sep 2022 01:22:53 -0700 Message-ID: <0ec6d333a98bb6a11e254ba49ecb385e50a52588.1663744983.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT089:EE_|DM6PR12MB4299:EE_ X-MS-Office365-Filtering-Correlation-Id: c28e9011-e55b-4d93-a295-08da9baa8926 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: LkGi3iElH8VO5hBbcX+MmSaUhOs23Lit7EgYWINzSEOP3P3vyuYdQFq5igkdtzHcc9D+PaJ0GL7F3PUDdla5dn+sCmbuxxVo9Po9KzZ8Kxh8UA0k4rDuaWH+y7bcsds770IilHEZqKJr9caOQ71w5AFrHYj6n4SVMt/1ZsNDAFOj3nbxQgRyzJMRlGODlOlHZLNP/Q/y5KXFsSxY/9MJXAfLgj8m5fuRVIWzgdiCKyjL0I9pzVG/YPqov2VvL2rcHkiTAjrX40o3ShaQ85Rpt77g9CllZBafGACKzTH0l53Pzb6dCj2z7Tt604/T15QRh8HRJTEENexf4K1P2fBdr78D8k00Hv18C8uNruPX7CcmV4odNSsx1WiZx3l3NmxDBI27d+AuNXHbfOnmAyN0otSx6gdOq33eQN5jWL945TbA63Ntr4ylLokLJ3XuztBZrJAlolv21bVhvDY88Q3NzbyhOP4RJy7DNGyGyw6QCZDQj3yhvMWvm6WomRUROWfA7qU9+ZeVmjCWTUGBxb/5/8+LoRv4rVOl4GhFI+uSXFhBsUSwcUp9QPoRpMju07qlyLgEEoL4h08bz2PzI3vgZDvq1Atl2SaobLNGX4RXO936TBQqkIxbhkc97BnsHrhWx9LGc78KQ6J6rwU7wRxKxp7O/Kf3ufL64MaPXj3hb2UytWnV1ZdjqCbzJRCI16spMST/80eRj3pjOrC03yfG6LHsKdMl470vIrrIpHSyF0IKnq/gtiXPK+kcE1S9IxtxpjQRRMGwses/kntGCEEOzg== X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230022)(4636009)(376002)(396003)(346002)(136003)(39860400002)(451199015)(46966006)(40470700004)(36840700001)(36860700001)(7416002)(5660300002)(82740400003)(83380400001)(47076005)(40480700001)(26005)(2906002)(110136005)(478600001)(8936002)(54906003)(40460700003)(316002)(426003)(86362001)(336012)(82310400005)(356005)(186003)(7636003)(2616005)(41300700001)(6666004)(36756003)(70206006)(70586007)(8676002)(4326008)(7696005);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Sep 2022 08:23:17.2540 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c28e9011-e55b-4d93-a295-08da9baa8926 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT089.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4299 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The error-out routine is missing all the reverting pieces for the iop and attached-ctx allocations. And clock enable/disable is unbalanced too. Fix it by adding __disable_clocks() and calling msm_iommu_detach_dev() at the end of the msm_iommu_attach_dev() if "ret" is non-zero. Also set the master->num to 0 in the detach_dev() since attach_dev() would check it. Fixes: 109bd48ea2e1 ("iommu/msm: Add DT adaptation") Cc: stable@vger.kernel.org Cc: Sricharan R Cc: Andy Gross Cc: Bjorn Andersson Cc: Konrad Dybcio Signed-off-by: Nicolin Chen Reviewed-by: Kevin Tian --- drivers/iommu/msm_iommu.c | 59 +++++++++++++++++++++------------------ 1 file changed, 32 insertions(+), 27 deletions(-) diff --git a/drivers/iommu/msm_iommu.c b/drivers/iommu/msm_iommu.c index 6a24aa804ea3..14df722f0060 100644 --- a/drivers/iommu/msm_iommu.c +++ b/drivers/iommu/msm_iommu.c @@ -394,6 +394,34 @@ static struct iommu_device *msm_iommu_probe_device(struct device *dev) return &iommu->iommu; } +static void msm_iommu_detach_dev(struct iommu_domain *domain, + struct device *dev) +{ + struct msm_priv *priv = to_msm_priv(domain); + unsigned long flags; + struct msm_iommu_dev *iommu; + struct msm_iommu_ctx_dev *master; + int ret; + + free_io_pgtable_ops(priv->iop); + + spin_lock_irqsave(&msm_iommu_lock, flags); + list_for_each_entry(iommu, &priv->list_attached, dom_node) { + ret = __enable_clocks(iommu); + if (ret) + goto fail; + + list_for_each_entry(master, &iommu->ctx_list, list) { + msm_iommu_free_ctx(iommu->context_map, master->num); + __reset_context(iommu->base, master->num); + master->num = 0; + } + __disable_clocks(iommu); + } +fail: + spin_unlock_irqrestore(&msm_iommu_lock, flags); +} + static int msm_iommu_attach_dev(struct iommu_domain *domain, struct device *dev) { int ret = 0; @@ -418,6 +446,7 @@ static int msm_iommu_attach_dev(struct iommu_domain *domain, struct device *dev) list_for_each_entry(master, &iommu->ctx_list, list) { if (master->num) { dev_err(dev, "domain already attached"); + __disable_clocks(iommu); ret = -EEXIST; goto fail; } @@ -425,6 +454,7 @@ static int msm_iommu_attach_dev(struct iommu_domain *domain, struct device *dev) msm_iommu_alloc_ctx(iommu->context_map, 0, iommu->ncb); if (IS_ERR_VALUE(master->num)) { + __disable_clocks(iommu); ret = -ENODEV; goto fail; } @@ -439,37 +469,12 @@ static int msm_iommu_attach_dev(struct iommu_domain *domain, struct device *dev) fail: spin_unlock_irqrestore(&msm_iommu_lock, flags); + if (ret) + msm_iommu_detach_dev(domain, dev); return ret; } -static void msm_iommu_detach_dev(struct iommu_domain *domain, - struct device *dev) -{ - struct msm_priv *priv = to_msm_priv(domain); - unsigned long flags; - struct msm_iommu_dev *iommu; - struct msm_iommu_ctx_dev *master; - int ret; - - free_io_pgtable_ops(priv->iop); - - spin_lock_irqsave(&msm_iommu_lock, flags); - list_for_each_entry(iommu, &priv->list_attached, dom_node) { - ret = __enable_clocks(iommu); - if (ret) - goto fail; - - list_for_each_entry(master, &iommu->ctx_list, list) { - msm_iommu_free_ctx(iommu->context_map, master->num); - __reset_context(iommu->base, master->num); - } - __disable_clocks(iommu); - } -fail: - spin_unlock_irqrestore(&msm_iommu_lock, flags); -} - static int msm_iommu_map(struct iommu_domain *domain, unsigned long iova, phys_addr_t pa, size_t len, int prot, gfp_t gfp) { From patchwork Wed Sep 21 08:23:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 12983348 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 47A66C32771 for ; Wed, 21 Sep 2022 08:24:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230325AbiIUIYI (ORCPT ); Wed, 21 Sep 2022 04:24:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47306 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231463AbiIUIXl (ORCPT ); Wed, 21 Sep 2022 04:23:41 -0400 Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2067.outbound.protection.outlook.com [40.107.237.67]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 514AE564E3; Wed, 21 Sep 2022 01:23:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=V6K2oTMt5OZPr5xUZOfWGl819xgS0AESm9Kz+IeC96CBgsnvJkgAyx5UKU3ZFNfpG8FNDgJgyD73V3xiaTbb86zANLqYncJpThaxCEOmtd18oiTouvxAWJE3rZGCShwDgac25ZUTRHiZBMw+jQyDFHWzgtsrF+duGALkVSo5FtP40qog5i2qkOPB0B9BXAhMdfZdTCLkhWz0WdpY0GEVxqkWHhapQZ8IMuQhnKsNFyERPc68VdZjUROnALNRsx56LYgcQiKOtRe6NinOEyx4uwLRgfOOIJ/HXpNfEPzs190CBfVtCNRA8Bo5LkSK5+FD+0sJrS54iRI3mZvLPD8z/A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=ZUuZ+Zjpj5ybs1qjjUFFijxxk0TQIcq4LwJzlyUIp4g=; b=Un2/d8KBs+lxo5yycHGWsKHVI2BHgV8pkt87O4okfME6PHoFF4yGLPAaNp0N0WACv/IsEC3t9v8vbUPW49rEu2/rKzy9mYuWSQAP5olwYjn/0w3lV306Fl5bhrcu0Nkq8+JcUjtqKw9fmle9R5LLeixxuG9oGm+e45CBICGpKiYCBjJHZ1B/acGnlblLCoKSdRGArYtVhfCTjtJCDYioidDo+TChfEC1wkDF0wK2s097YuFXKWajWUDBKfYumTNs7TGLN3qeekw48HQFMEp+KpaUG2IG/xWzLLZGrtMr7/AI+O+ScMV9nSfJ2AGRY41JBm8CcA1oeR3BIY2VdeWRIQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=8bytes.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ZUuZ+Zjpj5ybs1qjjUFFijxxk0TQIcq4LwJzlyUIp4g=; b=FXqUDEd10koWHazMUSx+uCMF+YL74FCOOJVNiQRoZ0C09w4UsCijoKPuRnXX3JVnzeO24CPC0Q1sGBzq0GtplNdwHfcnLuz7/MesaiL5q/LUtTqzCNkqB6/zEQ6JInnmGwKFEX5VsrFXHcib6Yc+GzjkQ2CUzMK5Re8l9JTNS6Qwqal0kcc0JvE1yZVv04KRYN+/w0iDr0n6Qm69A71dQljoMA55mx8MlK+IBCRxKXwyKLEVq7Lcf6XXKMt2yWtRTLWIi0jK74Aw0fasq7K5QZHcMZHo8dY0YRWgp6Lxpsv3abVea3y1xFVhDPAwnihTiYszf4KWo0bUYOlsBd9sBw== Received: from DM5PR07CA0062.namprd07.prod.outlook.com (2603:10b6:4:ad::27) by MN0PR12MB5883.namprd12.prod.outlook.com (2603:10b6:208:37b::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5632.18; Wed, 21 Sep 2022 08:23:36 +0000 Received: from DS1PEPF0000B076.namprd05.prod.outlook.com (2603:10b6:4:ad:cafe::4) by DM5PR07CA0062.outlook.office365.com (2603:10b6:4:ad::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5654.16 via Frontend Transport; Wed, 21 Sep 2022 08:23:36 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by DS1PEPF0000B076.mail.protection.outlook.com (10.167.17.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5654.11 via Frontend Transport; Wed, 21 Sep 2022 08:23:36 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.26; Wed, 21 Sep 2022 01:23:21 -0700 Received: from rnnvmail204.nvidia.com (10.129.68.6) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Wed, 21 Sep 2022 01:23:21 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.14) by mail.nvidia.com (10.129.68.6) with Microsoft SMTP Server id 15.2.986.29 via Frontend Transport; Wed, 21 Sep 2022 01:23:19 -0700 From: Nicolin Chen To: , , , , , , , , , , , , , , CC: , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v4 3/6] iommu: Add return value rules to attach_dev op and APIs Date: Wed, 21 Sep 2022 01:23:16 -0700 Message-ID: <8c3dbf153b63a3002a46bab6e707c63fd8635bb8.1663744983.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0000B076:EE_|MN0PR12MB5883:EE_ X-MS-Office365-Filtering-Correlation-Id: 6dfc07d9-8227-4586-7575-08da9baa9480 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: FWxKC9JyW260RPU5WFEiQ68d3Ok5wDXiJ7dFoRBsy8ug2yu6L6a2GQIuWGZU5qd/vbbsQS3HCtH5BBVHHqgw2l60z3SzoiD6/H5QH4/8yEYvNhA8Xq+MiUERYYNR6uHjIx8q1VjQc/wOYmlCD738oCIZnXBx6DayUBiIoEfA8+wjwAey5Fc1M0RWi43aMYIfijvJ506/5zQ7S0T9HF/YhyBIPi5VzjV5cOmxY+nAW/bEWibJkIpbDGB9NNUOa9WpaCLNkcFhkn6vOHUQ+zMKMGtIzyBqO2ktp/XwXaBjIg5pGGpBl28Ap/eXP+dFvGEOudZ5vROXz0Z2b/oZ8GS7glitMA2dTyk/bTAgqBt7CmSKpqH3sajpoFSoCv2/yMaMrcLGeqZWQSnpN9u6c2oADLjLMirOGZFOPfW12kBy+Vyi3WtYHu7dTsXJVmlB5jCOuHLPqh+J5IFYNuiWowx5IlelZZ10hMOT3tmjR5iKL8iOb0ORwd5c+7pP/kZAfGB3jd2juek9IYUA+tcec25vC+SC8IdoHjX2SXKvKnkYySH4QCIOlNLsJsnKE6x2voXuw+g4tTJFZ6FLKGXaYD5tyOuCY/1JtvZW9U1q2pF68jcK1Qtf54CQH9uFrUk2U8CskK2A/fB2QzTKCTl2Nz7p5TeOF9p+7xNe6bzVGa16zKkQsAR47cmOIRghvFY6bq6kdwPpZfIBJAvFgDK6F3dmG47AgtA3tyRND4YpYhYDypfjEkJnb+h65BU1FDgTPNDsCQZIA/EN5LeXhy3qGzAwr8Jp68HPrADRnso7PzIsg1NdKKQ8RFVM7pmoJrznNbbWO2a708BYIAbBlj2OLpEpEQ== X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230022)(4636009)(376002)(39860400002)(346002)(136003)(396003)(451199015)(40470700004)(36840700001)(46966006)(478600001)(110136005)(54906003)(316002)(41300700001)(7406005)(5660300002)(47076005)(6666004)(40460700003)(70206006)(8936002)(83380400001)(7416002)(8676002)(82310400005)(86362001)(7636003)(7696005)(4326008)(70586007)(26005)(36756003)(336012)(356005)(186003)(921005)(2906002)(426003)(40480700001)(82740400003)(36860700001)(2616005)(2101003)(83996005);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Sep 2022 08:23:36.2976 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6dfc07d9-8227-4586-7575-08da9baa9480 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0000B076.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5883 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Cases like VFIO wish to attach a device to an existing domain that was not allocated specifically from the device. This raises a condition where the IOMMU driver can fail the domain attach because the domain and device are incompatible with each other. This is a soft failure that can be resolved by using a different domain. Provide a dedicated errno EINVAL from the IOMMU driver during attach that the reason why the attach failed is because of domain incompatibility. VFIO can use this to know that the attach is a soft failure and it should continue searching. Otherwise, the attach will be a hard failure and VFIO will return the code to userspace. Update kdocs to add rules of return value to the attach_dev op and APIs. Suggested-by: Jason Gunthorpe Signed-off-by: Nicolin Chen Reviewed-by: Kevin Tian --- drivers/iommu/iommu.c | 22 ++++++++++++++++++++++ include/linux/iommu.h | 12 ++++++++++++ 2 files changed, 34 insertions(+) diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index 3a808146b50f..1d1e32aeaae6 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -1975,6 +1975,17 @@ static int __iommu_attach_device(struct iommu_domain *domain, return ret; } +/** + * iommu_attach_device - Attach a device to an IOMMU domain + * @domain: IOMMU domain to attach + * @dev: Device that will be attached + * + * Returns 0 on success and error code on failure + * + * Note that EINVAL may be returned as a soft failure if the domain and device + * are incompatible due to some previous configuration of the domain, in which + * case attaching the same device to a different domain may succeed. + */ int iommu_attach_device(struct iommu_domain *domain, struct device *dev) { struct iommu_group *group; @@ -2101,6 +2112,17 @@ static int __iommu_attach_group(struct iommu_domain *domain, return ret; } +/** + * iommu_attach_group - Attach an IOMMU group to an IOMMU domain + * @domain: IOMMU domain to attach + * @group: IOMMU group that will be attached + * + * Returns 0 on success and error code on failure + * + * Note that EINVAL may be returned as a soft failure if the domain and group + * are incompatible due to some previous configuration of the domain, in which + * case attaching the same group to a different domain may succeed. + */ int iommu_attach_group(struct iommu_domain *domain, struct iommu_group *group) { int ret; diff --git a/include/linux/iommu.h b/include/linux/iommu.h index ea30f00dc145..13a33b04e867 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -266,6 +266,18 @@ struct iommu_ops { /** * struct iommu_domain_ops - domain specific operations * @attach_dev: attach an iommu domain to a device + * Return: + * * 0 - success + * * EINVAL - can indicate that device and domain are incompatible due to + * some previous configuration of the domain, in which case the + * driver shouldn't log an error, since it is legitimate for a + * caller to test reuse of existing domains. Otherwise, it may + * still represent some other fundamental problem + * * ENOMEM - out of memory + * * ENOSPC - non-ENOMEM type of resource allocation failures + * * EBUSY - device is attached to a domain and cannot be changed + * * ENODEV - device specific errors, not able to be attached + * * - treated as ENODEV by the caller. Use is discouraged * @detach_dev: detach an iommu domain from a device * @map: map a physically contiguous memory region to an iommu domain * @map_pages: map a physically contiguous set of pages of the same size to From patchwork Wed Sep 21 08:23:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 12983349 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 23187ECAAD8 for ; Wed, 21 Sep 2022 08:24:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229880AbiIUIYK (ORCPT ); Wed, 21 Sep 2022 04:24:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47572 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231526AbiIUIXy (ORCPT ); Wed, 21 Sep 2022 04:23:54 -0400 Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2082.outbound.protection.outlook.com [40.107.237.82]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5457A883ED; Wed, 21 Sep 2022 01:23:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Dpb6mvB1iMGzd8g8dohRZy+NqAiihxMuCS2xBpoWDM42oHfZbJJkxaBIV6ofwRuG2V2Z2o1ltHqIpT/oLyU/I624SVnfFzzCDdOuMMhsHqvbD/zjx3Uyj6Beq73D2TVFGetdj0pm5Pb9bk1i2CREjN6CDbsOpUIxtlgwhe4eCNz01oRbIPtBpdho0qsEeI5Bx7m+J0RCaNwB0Pndy40dNn8s+2JpyfhJ2HRq7BqAQIXCTNMoIsAsdwo1LdKPo36hn+5oLcskkYBnpM/LwC2rnJylnlrHPcJ5ig/mmZqvfnUcKgrGNsu37QyccUijCZScbuv4tIs52dXYO5Ec5wy5IA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=++uoO3LawFXul3U/9kiNYyLITdupVpuzSrdELGwdTdw=; b=MkNSaeYeWA79zpjV2JBJm4q4lK30FrHkujnqR9PwRF7FIPFWoFQbSfsia7QzF3zwyGGMU+XJTNo7p8pVZbzaIv0KJGnUvOhRlcqG9hkXxwG/sqIdQMh/iLKyrpJlQzjsEajdrNiEFKNqf/37I4rQRt+LrGRFVRaZAzWnNRPcs9wf1H/gZKPuhs8tsrd3up7pX4FyHQPeIkK0aryH3LO7pcwfH5qTMLNI+tmWvnQSHX3Ny89tx8GXbTuCuvy6cjjOKFFu+PQQnGJ4kXfCWQcHvnvVvaU2YM87Jw5KfNlp7DWDD+wgzftskBao4kxcn3vT2EMe/flsETOB6PsGAYChJQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=8bytes.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=++uoO3LawFXul3U/9kiNYyLITdupVpuzSrdELGwdTdw=; b=nf6kJ0ACGRu+PyHKoxvndDnmBh8f+0huwPr9dAHLzs1HflMg6wWlbRDOhQfPsnebfypw38Xh3XygPA8G8GQwvP66dy1MJ232nH+SSa27/y+wGTL1gZESq6hGhhAN9IJrXpMAJpALPz5zArHCDaC7oyd8/Ejyo8t+CnJLdN+VNjg3d4DmxMe+jCXkLjttZrDgtiLpMKvh+zjQx2U2PM1rH0qdIsSXvB1Oaz7tKYDRVYUfK1W5qW4WHbMUd9JYMDsNhgiL3q7ICUK/ca9CcjSy9ZcN8CK+kgF4VujoCJE9+wR51HOSUDr1/Al+3naqOCLUCGa1Zm8OnPmJBCMj5onCAg== Received: from DS7PR05CA0038.namprd05.prod.outlook.com (2603:10b6:8:2f::23) by SN7PR12MB7156.namprd12.prod.outlook.com (2603:10b6:806:2a7::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5654.14; Wed, 21 Sep 2022 08:23:51 +0000 Received: from DS1PEPF0000B075.namprd05.prod.outlook.com (2603:10b6:8:2f:cafe::c) by DS7PR05CA0038.outlook.office365.com (2603:10b6:8:2f::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5654.6 via Frontend Transport; Wed, 21 Sep 2022 08:23:51 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by DS1PEPF0000B075.mail.protection.outlook.com (10.167.17.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5654.11 via Frontend Transport; Wed, 21 Sep 2022 08:23:51 +0000 Received: from rnnvmail204.nvidia.com (10.129.68.6) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.26; Wed, 21 Sep 2022 01:23:43 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by rnnvmail204.nvidia.com (10.129.68.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Wed, 21 Sep 2022 01:23:43 -0700 Received: from drhqmail203.nvidia.com (10.126.190.182) by drhqmail202.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Wed, 21 Sep 2022 01:23:42 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.14) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server id 15.2.986.29 via Frontend Transport; Wed, 21 Sep 2022 01:23:40 -0700 From: Nicolin Chen To: , , , , , , , , , , , , , , CC: , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v4 5/6] iommu: Use EINVAL for incompatible device/domain in ->attach_dev Date: Wed, 21 Sep 2022 01:23:39 -0700 Message-ID: <4469b88b4460fc230b8c394f806c134e627aa5bd.1663744983.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0000B075:EE_|SN7PR12MB7156:EE_ X-MS-Office365-Filtering-Correlation-Id: bf644beb-214b-47f1-829f-08da9baa9d59 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 8fDJj9PvhhCdGRkkGOg5mZ7ZS1SoiRf5gp19Uz79DMqoOo6k/p7iUK7+PB+K/Dnzn65HqCC6r0Opfiu2Z0FVh/txTIV5cmgTcbXkkJX8wxiag2NQZ/oa2awcw2xdt46WnvgWkfA3DiI/wKc8xHTMUcWWPleHkjCf6uCwroeEKS3OEdCl4vE5Gi1s7v2uwBO5j8WDfaRydi+ClH+S/RV5+QtZerDtTZU0dWCm9DL5jH+4ZN/v/sBpK8yBJHPc1BdPu4DXlyTbGxp1rFWoA+c8DMwISp0Qre9lZCib6v04lNlwPnooFgdAJ77Z1M4ntnMm9jMRCm70sOVXd9BgsoNgI6fAYipNvVlxdJlXWWdmX6vQ2sHs9OemvUeekvizfJcKS2tRxnXp5JTWJ/6QQKf3fKxJ1SOoDPK0Jjg32v3Ykg4wfRYL802uOYIyThDqZsqzwHm1FbhjQ7rMxD9d0VDgrU55OO1Tw6FqYSq+DyRJO+XNBRcomflvNBqdzDiUiEGOoo3sfA+1Fq+NgYe4LhfGZAgNYxePOcoKaF8/tEbgdXcPN2OAQ3QrOnl4vUMVt2eLZlvYc499KmG9j7tHTFX4aziFtvzB+uiNyNa1Y4vvgb+5ZjHKZ/KbFhnAurJSgQ8ZM+oRN9BLSDBS+0ynEWWarKSoZZ5bd+J+7Y4i4TwRlouOUlbX9Y+1XNen+BHQIZ7MRhF7mXRqavqJu6GnC22bLk6N86LjXeqMdFfS93wYk0k4IPT+eUIvKHwOfLUcp3tX6/2+EURC9AzwHSO5Yavsf5E2ylHxqhJW5etS8PA3ADo7upKouCgumCaRvSy+WXDsLiAAlutB9+qI1O39TWiyQAbSPxMxrtI4O9CiSxS4DPg= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230022)(4636009)(39860400002)(136003)(376002)(396003)(346002)(451199015)(40470700004)(46966006)(36840700001)(478600001)(2616005)(426003)(186003)(26005)(336012)(47076005)(7696005)(2906002)(86362001)(54906003)(40460700003)(8936002)(7406005)(7416002)(5660300002)(82310400005)(40480700001)(110136005)(36756003)(70206006)(8676002)(316002)(41300700001)(4326008)(70586007)(82740400003)(356005)(83380400001)(7636003)(921005)(36860700001)(83996005)(2101003)(473944003);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Sep 2022 08:23:51.1418 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bf644beb-214b-47f1-829f-08da9baa9d59 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0000B075.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7156 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Following the new rules in include/linux/iommu.h kdocs, update all drivers ->attach_dev callback functions to return EINVAL in the failure paths that are related to domain incompatibility. Also, drop adjacent error prints to prevent a kernel log spam. Signed-off-by: Nicolin Chen Reviewed-by: Lu Baolu Reviewed-by: Kevin Tian --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 11 +---------- drivers/iommu/arm/arm-smmu/arm-smmu.c | 3 --- drivers/iommu/arm/arm-smmu/qcom_iommu.c | 7 +------ drivers/iommu/intel/iommu.c | 10 +++------- drivers/iommu/ipmmu-vmsa.c | 2 -- drivers/iommu/omap-iommu.c | 2 +- drivers/iommu/sprd-iommu.c | 4 +--- drivers/iommu/tegra-gart.c | 2 +- drivers/iommu/virtio-iommu.c | 3 +-- 9 files changed, 9 insertions(+), 35 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index d32b02336411..f96f8aad8280 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2429,23 +2429,14 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) goto out_unlock; } } else if (smmu_domain->smmu != smmu) { - dev_err(dev, - "cannot attach to SMMU %s (upstream of %s)\n", - dev_name(smmu_domain->smmu->dev), - dev_name(smmu->dev)); - ret = -ENXIO; + ret = -EINVAL; goto out_unlock; } else if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1 && master->ssid_bits != smmu_domain->s1_cfg.s1cdmax) { - dev_err(dev, - "cannot attach to incompatible domain (%u SSID bits != %u)\n", - smmu_domain->s1_cfg.s1cdmax, master->ssid_bits); ret = -EINVAL; goto out_unlock; } else if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1 && smmu_domain->stall_enabled != master->stall_enabled) { - dev_err(dev, "cannot attach to stall-%s domain\n", - smmu_domain->stall_enabled ? "enabled" : "disabled"); ret = -EINVAL; goto out_unlock; } diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c index dfa82df00342..dbd12da31707 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c @@ -1167,9 +1167,6 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) * different SMMUs. */ if (smmu_domain->smmu != smmu) { - dev_err(dev, - "cannot attach to SMMU %s whilst already attached to domain on SMMU %s\n", - dev_name(smmu_domain->smmu->dev), dev_name(smmu->dev)); ret = -EINVAL; goto rpm_put; } diff --git a/drivers/iommu/arm/arm-smmu/qcom_iommu.c b/drivers/iommu/arm/arm-smmu/qcom_iommu.c index 17235116d3bb..37c5ddc212c1 100644 --- a/drivers/iommu/arm/arm-smmu/qcom_iommu.c +++ b/drivers/iommu/arm/arm-smmu/qcom_iommu.c @@ -381,13 +381,8 @@ static int qcom_iommu_attach_dev(struct iommu_domain *domain, struct device *dev * Sanity check the domain. We don't support domains across * different IOMMUs. */ - if (qcom_domain->iommu != qcom_iommu) { - dev_err(dev, "cannot attach to IOMMU %s while already " - "attached to domain on IOMMU %s\n", - dev_name(qcom_domain->iommu->dev), - dev_name(qcom_iommu->dev)); + if (qcom_domain->iommu != qcom_iommu) return -EINVAL; - } return 0; } diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index 1f2cd43cf9bc..51ef42b1bd4e 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -4158,19 +4158,15 @@ static int prepare_domain_attach_device(struct iommu_domain *domain, return -ENODEV; if (dmar_domain->force_snooping && !ecap_sc_support(iommu->ecap)) - return -EOPNOTSUPP; + return -EINVAL; /* check if this iommu agaw is sufficient for max mapped address */ addr_width = agaw_to_width(iommu->agaw); if (addr_width > cap_mgaw(iommu->cap)) addr_width = cap_mgaw(iommu->cap); - if (dmar_domain->max_addr > (1LL << addr_width)) { - dev_err(dev, "%s: iommu width (%d) is not " - "sufficient for the mapped address (%llx)\n", - __func__, addr_width, dmar_domain->max_addr); - return -EFAULT; - } + if (dmar_domain->max_addr > (1LL << addr_width)) + return -EINVAL; dmar_domain->gaw = addr_width; /* diff --git a/drivers/iommu/ipmmu-vmsa.c b/drivers/iommu/ipmmu-vmsa.c index 1d42084d0276..f5217a4cb9b3 100644 --- a/drivers/iommu/ipmmu-vmsa.c +++ b/drivers/iommu/ipmmu-vmsa.c @@ -628,8 +628,6 @@ static int ipmmu_attach_device(struct iommu_domain *io_domain, * Something is wrong, we can't attach two devices using * different IOMMUs to the same domain. */ - dev_err(dev, "Can't attach IPMMU %s to domain on IPMMU %s\n", - dev_name(mmu->dev), dev_name(domain->mmu->dev)); ret = -EINVAL; } else dev_info(dev, "Reusing IPMMU context %u\n", domain->context_id); diff --git a/drivers/iommu/omap-iommu.c b/drivers/iommu/omap-iommu.c index 447e40d55918..be12f49140c7 100644 --- a/drivers/iommu/omap-iommu.c +++ b/drivers/iommu/omap-iommu.c @@ -1472,7 +1472,7 @@ omap_iommu_attach_dev(struct iommu_domain *domain, struct device *dev) /* only a single client device can be attached to a domain */ if (omap_domain->dev) { dev_err(dev, "iommu domain is already attached\n"); - ret = -EBUSY; + ret = -EINVAL; goto out; } diff --git a/drivers/iommu/sprd-iommu.c b/drivers/iommu/sprd-iommu.c index 511959c8a14d..945576039c9e 100644 --- a/drivers/iommu/sprd-iommu.c +++ b/drivers/iommu/sprd-iommu.c @@ -237,10 +237,8 @@ static int sprd_iommu_attach_device(struct iommu_domain *domain, struct sprd_iommu_domain *dom = to_sprd_domain(domain); size_t pgt_size = sprd_iommu_pgt_size(domain); - if (dom->sdev) { - pr_err("There's already a device attached to this domain.\n"); + if (dom->sdev) return -EINVAL; - } dom->pgt_va = dma_alloc_coherent(sdev->dev, pgt_size, &dom->pgt_pa, GFP_KERNEL); if (!dom->pgt_va) diff --git a/drivers/iommu/tegra-gart.c b/drivers/iommu/tegra-gart.c index e5ca3cf1a949..ed53279d1106 100644 --- a/drivers/iommu/tegra-gart.c +++ b/drivers/iommu/tegra-gart.c @@ -112,7 +112,7 @@ static int gart_iommu_attach_dev(struct iommu_domain *domain, spin_lock(&gart->dom_lock); if (gart->active_domain && gart->active_domain != domain) { - ret = -EBUSY; + ret = -EINVAL; } else if (dev_iommu_priv_get(dev) != domain) { dev_iommu_priv_set(dev, domain); gart->active_domain = domain; diff --git a/drivers/iommu/virtio-iommu.c b/drivers/iommu/virtio-iommu.c index 4c652773fd6c..87128266b6e3 100644 --- a/drivers/iommu/virtio-iommu.c +++ b/drivers/iommu/virtio-iommu.c @@ -733,8 +733,7 @@ static int viommu_attach_dev(struct iommu_domain *domain, struct device *dev) */ ret = viommu_domain_finalise(vdev, domain); } else if (vdomain->viommu != vdev->viommu) { - dev_err(dev, "cannot attach to foreign vIOMMU\n"); - ret = -EXDEV; + ret = -EINVAL; } mutex_unlock(&vdomain->mutex);