From patchwork Wed Sep 21 21:15:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 12984177 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A1DFAC32771 for ; Wed, 21 Sep 2022 21:15:40 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C4FE110E522; Wed, 21 Sep 2022 21:15:38 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9D8D210E522 for ; Wed, 21 Sep 2022 21:15:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1663794932; x=1695330932; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Y21G8aODXAxDyN808S6adrXRds/zry2e2XBK/AUwDzQ=; b=K852tB2G+hKcGGuDaJU3qGEV2LjbaB54tqh0Uf31+pup5K3+EcOLMNc6 4V03ZcQIZ2lKM+4YXExKbYGWRzos+yQ6sdt04jqx12rzgSMfZrXk0zajE NmEBs/oufrRCmZp76DmbjGPFzrF/464hAysSCZ/uqrN3mIPKlFonR0ePo DUMrCSXQSqTFZZ/sEiNnaghx5ngCG3dJ2xcBcvuS6RDMQUpl5tINc9wQ7 eCf2cOmvDVU1FRXm9Y2j/5ZohH4v/fj687qHLXnZe4R24GPrnck4s2Xm5 LmGHktPTf63NdfgIomWbm0853sYl3INriP9dQ8n0hyoxS7QtvYqFZ0TFu g==; X-IronPort-AV: E=McAfee;i="6500,9779,10477"; a="283176171" X-IronPort-AV: E=Sophos;i="5.93,334,1654585200"; d="scan'208";a="283176171" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Sep 2022 14:15:31 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,334,1654585200"; d="scan'208";a="681938199" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.191]) by fmsmga008.fm.intel.com with SMTP; 21 Sep 2022 14:15:29 -0700 Received: by stinkbox (sSMTP sendmail emulation); Thu, 22 Sep 2022 00:15:28 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Thu, 22 Sep 2022 00:15:22 +0300 Message-Id: <20220921211525.10675-2-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220921211525.10675-1-ville.syrjala@linux.intel.com> References: <20220921211525.10675-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 1/4] drm/i915: Force DPLL calculation for TC ports after readout X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä We always allocate two DPLLs (TC and TBT) for TC ports. This is because we can't know ahead of time wherher we need to put the PHY into DP-Alt or TBT mode. However during readout we can obviously only read out the state of the DPLL that the port is actually using. Thus the state after readout will not have both DPLLs populated. We run into problems if during readout the TC port is in DP-Alt mode, but we then perform a modeset on the port without going through the full .compute_config() machinery, and during said modeset the port cannot be switched back into DP-Alt mode and we need to take the TBT fallback path. Such a modeset can happen eg. due to cdclk reprogramming. This wasn't a problem earlier because we did all the DPLL calculations much later in the modeset. So even if flagged a modeset very late we'd still have gone through the DPLL calculations. But now all the DPLL calculations happen much earlier and so we need to deal with it, or else we'll attempt a modeset without a DPLL. To guarantee that we always have both DPLLs fully cal/ulated for TC ports force a full modeset computation during the initial commit. Reported-by: Lee Shawn C Fixes: b000abd3b3d2 ("drm/i915: Do .crtc_compute_clock() earlier") Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_ddi.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 643832d55c28..6278b8ea5bf1 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3600,10 +3600,21 @@ static void intel_ddi_sync_state(struct intel_encoder *encoder, static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state) { + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + enum phy phy = intel_port_to_phy(i915, encoder->port); + bool ret = true; + + if (intel_phy_is_tc(i915, phy)) { + drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset to compute TC port DPLLs\n", + encoder->base.base.id, encoder->base.name); + crtc_state->uapi.mode_changed = true; + ret = false; + } + if (intel_crtc_has_dp_encoder(crtc_state)) - return intel_dp_initial_fastset_check(encoder, crtc_state); + ret &= intel_dp_initial_fastset_check(encoder, crtc_state); - return true; + return ret; } static enum intel_output_type From patchwork Wed Sep 21 21:15:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 12984178 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CE2A6ECAAD8 for ; Wed, 21 Sep 2022 21:15:44 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5A50210E886; Wed, 21 Sep 2022 21:15:41 +0000 (UTC) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1E71810E522 for ; Wed, 21 Sep 2022 21:15:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1663794935; x=1695330935; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=APw7YQuR9FJ4aQ/HELpmZyra/e0tJ+1Lw4368e75IKU=; b=m3+NAKFDefO5ueKOwUL4nzAqGpGWVK/APa3RPzxVqj1IqzbNHD2HZRtS OYW+3Tm5Rorb6AiuyCezcvPGpozZxYJ/3mLHuEENe+89tz04YJUwouztd /BpYJ9SKrhztGBsQlBq9Z3XpfCDk9TLyZw76q9sPnVtMurGslMJvsqyf5 urPi5gbsqbx3r/mqM3muhRFCog1DwN0RjzYSsM3YrHA6FVDevBpgMWfZM sXi6JMqZXzeVwf3fyiqjOKwZEBeat99nmF3OIqWjyG8EK0FyrAjLuQtgR UayLT6j4Cq9cPBQJQE1FAycFkYPfHe/t5RX4zLkbRuE8TiabP52GhBq+y Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10477"; a="280499015" X-IronPort-AV: E=Sophos;i="5.93,334,1654585200"; d="scan'208";a="280499015" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Sep 2022 14:15:34 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,334,1654585200"; d="scan'208";a="650241931" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.191]) by orsmga008.jf.intel.com with SMTP; 21 Sep 2022 14:15:32 -0700 Received: by stinkbox (sSMTP sendmail emulation); Thu, 22 Sep 2022 00:15:31 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Thu, 22 Sep 2022 00:15:23 +0300 Message-Id: <20220921211525.10675-3-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220921211525.10675-1-ville.syrjala@linux.intel.com> References: <20220921211525.10675-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 2/4] drm/i915: Don't bail early from intel_dp_initial_fastset_check() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Do all the checks in intel_dp_initial_fastset_check() instead of bailing out on the first condition that triggers. This makes for better debug logs since we see all the reasons why the full modeset computation is forced. Also avoid the risk of someone accidentally adding a check later in the function that would require connectors_changed=true (ie. no fastset at all), but an earlier check may have already bailed out with just mode_changed=true (ie. fastset is still possible). Pimp the debugs with the encoder id+name while at it. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dp.c | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index c9be61d2348e..73c4db4db20b 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2306,6 +2306,7 @@ bool intel_dp_initial_fastset_check(struct intel_encoder *encoder, { struct drm_i915_private *i915 = to_i915(encoder->base.dev); struct intel_dp *intel_dp = enc_to_intel_dp(encoder); + bool ret = true; /* * If BIOS has set an unsupported or non-standard link rate for some @@ -2313,9 +2314,10 @@ bool intel_dp_initial_fastset_check(struct intel_encoder *encoder, */ if (intel_dp_rate_index(intel_dp->source_rates, intel_dp->num_source_rates, crtc_state->port_clock) < 0) { - drm_dbg_kms(&i915->drm, "Forcing full modeset due to unsupported link rate\n"); + drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset due to unsupported link rate\n", + encoder->base.base.id, encoder->base.name); crtc_state->uapi.connectors_changed = true; - return false; + ret = false; } /* @@ -2326,18 +2328,20 @@ bool intel_dp_initial_fastset_check(struct intel_encoder *encoder, * Remove once we have readout for DSC. */ if (crtc_state->dsc.compression_enable) { - drm_dbg_kms(&i915->drm, "Forcing full modeset due to DSC being enabled\n"); + drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset due to DSC being enabled\n", + encoder->base.base.id, encoder->base.name); crtc_state->uapi.mode_changed = true; - return false; + ret = false; } if (CAN_PSR(intel_dp)) { - drm_dbg_kms(&i915->drm, "Forcing full modeset to compute PSR state\n"); + drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset to compute PSR state\n", + encoder->base.base.id, encoder->base.name); crtc_state->uapi.mode_changed = true; - return false; + ret = false; } - return true; + return ret; } static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp) From patchwork Wed Sep 21 21:15:24 2022 Content-Type: text/plain; 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h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=3Xj6EMj+s7IpqQlq1XUQgrdDm/Kbi7JWIypr656nIJ0=; b=MWlr+AsTiYmUG7u9b3eLEclMCsATL/+mG+4CevnQQI8e9Jh3kO11w1n4 TN41DoAic1YBQWzl14zhtq5iCe0GwGd2Ht5cyLdplaunYkW0XvQMZkh8n Vgj7Sq7WSZ7EJUGv36idyd+6job0WUce8ynvwIvGU4zkIsZjCyqyvUi3v n3o49tb40tD3IH/t353av8nh9GohbMJ2xcfGlJGfg0u3PfbctGlV/EJQL r2jpq3gDXnfANnSLjEvHnK2vsSlx3xei0DLs+ZocRqXmIq7/7RaMbvQz+ Ru2tAMcj2EDK72rauD8Z3W3HFVmemy8bwPjmnwkglJaY1rZ2Gi+AbVG2J A==; X-IronPort-AV: E=McAfee;i="6500,9779,10477"; a="300969856" X-IronPort-AV: E=Sophos;i="5.93,334,1654585200"; d="scan'208";a="300969856" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Sep 2022 14:15:37 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,334,1654585200"; d="scan'208";a="597160965" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.191]) by orsmga006.jf.intel.com with SMTP; 21 Sep 2022 14:15:35 -0700 Received: by stinkbox (sSMTP sendmail emulation); Thu, 22 Sep 2022 00:15:34 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Thu, 22 Sep 2022 00:15:24 +0300 Message-Id: <20220921211525.10675-4-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220921211525.10675-1-ville.syrjala@linux.intel.com> References: <20220921211525.10675-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 3/4] drm/i915: Pimp DPLL ref/unref debugs X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä We currently have a debug message in intel_reference_shared_dpll() but no counterpart in intel_unreference_shared_dpll(). Add one. Switch to the [CRTC:...] notation for the pipe name while at it. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index e5fb66a5dd02..c21818cb6fe2 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -384,20 +384,25 @@ intel_reference_shared_dpll(struct intel_atomic_state *state, if (shared_dpll[id].pipe_mask == 0) shared_dpll[id].hw_state = *pll_state; - drm_dbg(&i915->drm, "using %s for pipe %c\n", pll->info->name, - pipe_name(crtc->pipe)); - shared_dpll[id].pipe_mask |= BIT(crtc->pipe); + + drm_dbg(&i915->drm, "[CRTC:%d:%s] reserving %s\n", + crtc->base.base.id, crtc->base.name, pll->info->name); } static void intel_unreference_shared_dpll(struct intel_atomic_state *state, const struct intel_crtc *crtc, const struct intel_shared_dpll *pll) { + struct drm_i915_private *i915 = to_i915(state->base.dev); struct intel_shared_dpll_state *shared_dpll; shared_dpll = intel_atomic_get_shared_dpll_state(&state->base); + shared_dpll[pll->info->id].pipe_mask &= ~BIT(crtc->pipe); + + drm_dbg(&i915->drm, "[CRTC:%d:%s] releasing %s\n", + crtc->base.base.id, crtc->base.name, pll->info->name); } static void intel_put_dpll(struct intel_atomic_state *state, From patchwork Wed Sep 21 21:15:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 12984179 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0B18EC32771 for ; Wed, 21 Sep 2022 21:15:57 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F180B10E895; Wed, 21 Sep 2022 21:15:56 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 92AF610E88F for ; Wed, 21 Sep 2022 21:15:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1663794941; x=1695330941; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=ZdAJyVvEe+hxH/OOFq8bxzeJs5eepYcW5wMBIaly6BE=; b=GSUPrdHX4LOWUNEH9qGwWpUjbh01bBGDPye5RrAgIHYU81v4vUUZgepG z1d7IwpuxunhQ4SxLdtvgIBJAtfgS05d+f6jLW9zxC29xUD80xKlJzzqg jeHxu9RQMFVzcmBN5xPOGBKfEyBn6qTKQ7Pe+QTGeUh4sP2jHqy08V95e aP6FSIOcbwLjVHcbMKdPOpivdBn9GI3vN07CwP68zysxTQc1je67uhaC5 rD8hcvP7P2D9yqRuwvJRz2d5y5gRWRjUvX5XkVc8RHmf+VxwcTAoVCUSB BfeT7pra7DVeCYj1xQbKZd64Ihpt0T8l/4LRUKc5cIRvaX/DluaAYww66 A==; X-IronPort-AV: E=McAfee;i="6500,9779,10477"; a="283176189" X-IronPort-AV: E=Sophos;i="5.93,334,1654585200"; d="scan'208";a="283176189" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Sep 2022 14:15:40 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,334,1654585200"; d="scan'208";a="652702975" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.191]) by orsmga001.jf.intel.com with SMTP; 21 Sep 2022 14:15:38 -0700 Received: by stinkbox (sSMTP sendmail emulation); Thu, 22 Sep 2022 00:15:37 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Thu, 22 Sep 2022 00:15:25 +0300 Message-Id: <20220921211525.10675-5-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220921211525.10675-1-ville.syrjala@linux.intel.com> References: <20220921211525.10675-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 4/4] drm/i915: WARN if PLL ref/unref got messed up X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Spew a WARN if we try to ref/unref the same DPLL multiple times for the same pipe. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index c21818cb6fe2..2a6ef1398c84 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -384,6 +384,8 @@ intel_reference_shared_dpll(struct intel_atomic_state *state, if (shared_dpll[id].pipe_mask == 0) shared_dpll[id].hw_state = *pll_state; + drm_WARN_ON(&i915->drm, (shared_dpll[id].pipe_mask & BIT(crtc->pipe)) != 0); + shared_dpll[id].pipe_mask |= BIT(crtc->pipe); drm_dbg(&i915->drm, "[CRTC:%d:%s] reserving %s\n", @@ -396,10 +398,13 @@ static void intel_unreference_shared_dpll(struct intel_atomic_state *state, { struct drm_i915_private *i915 = to_i915(state->base.dev); struct intel_shared_dpll_state *shared_dpll; + const enum intel_dpll_id id = pll->info->id; shared_dpll = intel_atomic_get_shared_dpll_state(&state->base); - shared_dpll[pll->info->id].pipe_mask &= ~BIT(crtc->pipe); + drm_WARN_ON(&i915->drm, (shared_dpll[id].pipe_mask & BIT(crtc->pipe)) == 0); + + shared_dpll[id].pipe_mask &= ~BIT(crtc->pipe); drm_dbg(&i915->drm, "[CRTC:%d:%s] releasing %s\n", crtc->base.base.id, crtc->base.name, pll->info->name);