From patchwork Thu Sep 22 05:19:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Like Xu X-Patchwork-Id: 12984553 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 12F7DC6FA82 for ; Thu, 22 Sep 2022 05:19:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229828AbiIVFTy (ORCPT ); Thu, 22 Sep 2022 01:19:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35236 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229788AbiIVFTv (ORCPT ); Thu, 22 Sep 2022 01:19:51 -0400 Received: from mail-pj1-x1030.google.com (mail-pj1-x1030.google.com [IPv6:2607:f8b0:4864:20::1030]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 05C81474DF; Wed, 21 Sep 2022 22:19:51 -0700 (PDT) Received: by mail-pj1-x1030.google.com with SMTP id o99-20020a17090a0a6c00b002039c4fce53so1054293pjo.2; Wed, 21 Sep 2022 22:19:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date; bh=GMkU1fcxIyUL21eoHYe2jKHkE16Hr771WCkqjLcwYtQ=; b=a/O4rKKT7Kv3eslRbh+88BtpBD0P8l4ruNM3RRxvb6HZGewie2O3XXjTpv6THavl8t q0ro46K08595GLN2FI/Ecc+9Kkp5eFswR5hsKMiDIfHD+kaiEP/biv8JF33TRPJsFHnB SF3eIyTpAb3YGoCx+t5QSwGVa/0un+b12HG/sRV2C+Te/DiaunPMC2MbaoHXR1XqoKWY IXHgN0aIGoJC1CDwDGe8SoGcn0ymBAhwQeyiecI9NMzxDUCXAbvJWmV5GlbokXfabJjf y75/5rENdR2VVDHRtE/N1BpfgBXGh4Wdg6j/NPmAKMweRMcnLPoc+1vDJA4zBv8exuHs Gwng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date; bh=GMkU1fcxIyUL21eoHYe2jKHkE16Hr771WCkqjLcwYtQ=; b=kFe0wCdAl+OtMkNmMZzUbbYWttUe38me5wn6FnJBI1/ujH1LfNl1mM417fZcun/Ulj G7ac6ON+Xclm3yl4SbuQZ819ZkYHEEicZtPn7/5FiOynjBS/XgWvPWxf+McXjjpWsQZF JzCD6k5t4o9tGd6ZB726ZTQACFhtC20qeMZYq6Mg5mdGUqAZSPclp6JnIUS7N8PLW34x 2nXJIHljo3mdQ3S3jqJB2yUQJVstyMnd8CIz/zzLGaw8SU6ACOlS5svwmK/zJUSo/wtz cPYiG0iUP2AsXKw6P5VPWOL0a7aXspotHx1LEKjUCcvwJaG1F5at4obFe+fffwDI7Bx4 2otw== X-Gm-Message-State: ACrzQf3Un6/+XxEQSwEWWjc5LgRmHWDEUF1nF84M8UjiMvzgCMtXSTMB P9+Pp8nMy9X8CBwMviy3eYAD4UfA0mS3fQ== X-Google-Smtp-Source: AMsMyM574gPz7vjNosZQoXrztx9lPl1MgEp7iRPI9JGASkpN+LI/pxLffmg8+/92XqFPR6iFooH7Pw== X-Received: by 2002:a17:90a:4502:b0:202:7a55:558f with SMTP id u2-20020a17090a450200b002027a55558fmr13175584pjg.108.1663823990416; Wed, 21 Sep 2022 22:19:50 -0700 (PDT) Received: from localhost.localdomain ([103.7.29.32]) by smtp.gmail.com with ESMTPSA id b7-20020a170903228700b001780a528540sm3045067plh.93.2022.09.21.22.19.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Sep 2022 22:19:49 -0700 (PDT) From: Like Xu X-Google-Original-From: Like Xu To: Sean Christopherson , Paolo Bonzini Cc: Peter Zijlstra , Jim Mattson , linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, Kan Liang Subject: [PATCH v2 1/2] perf/x86/intel: Expose EPT-friendly PEBS for SPR and future models Date: Thu, 22 Sep 2022 13:19:28 +0800 Message-Id: <20220922051929.89484-1-likexu@tencent.com> X-Mailer: git-send-email 2.37.3 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Like Xu According to Intel SDM, the EPT-friendly PEBS is supported by all the platforms after ICX, ADL and the future platforms with PEBS format 5. Currently the only in-kernel user of this capability is KVM, which has very limited support for hybrid core pmu, so ADL and its successors do not currently expose this capability. When both hybrid core and PEBS format 5 are present, KVM will decide on its own merits. Cc: Peter Zijlstra Cc: linux-perf-users@vger.kernel.org Suggested-by: Kan Liang Signed-off-by: Like Xu Reviewed-by: Kan Liang --- V1 -> V2 Changelog: - the perf part should be a separate patch; (Kan) - apply PEBS format 5 to avoid patching every future model; (Kan) arch/x86/events/intel/core.c | 1 + arch/x86/events/intel/ds.c | 4 +++- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 2db93498ff71..804540ba4599 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -6288,6 +6288,7 @@ __init int intel_pmu_init(void) x86_pmu.pebs_constraints = intel_spr_pebs_event_constraints; x86_pmu.extra_regs = intel_spr_extra_regs; x86_pmu.limit_period = spr_limit_period; + x86_pmu.pebs_ept = 1; x86_pmu.pebs_aliases = NULL; x86_pmu.pebs_prec_dist = true; x86_pmu.pebs_block = true; diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c index ba60427caa6d..4e937f685cdc 100644 --- a/arch/x86/events/intel/ds.c +++ b/arch/x86/events/intel/ds.c @@ -2253,8 +2253,10 @@ void __init intel_ds_init(void) x86_pmu.large_pebs_flags |= PERF_SAMPLE_TIME; break; - case 4: case 5: + x86_pmu.pebs_ept = 1; + fallthrough; + case 4: x86_pmu.drain_pebs = intel_pmu_drain_pebs_icl; x86_pmu.pebs_record_size = sizeof(struct pebs_basic); if (x86_pmu.intel_cap.pebs_baseline) { From patchwork Thu Sep 22 05:19:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Like Xu X-Patchwork-Id: 12984554 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5E6A5ECAAD8 for ; Thu, 22 Sep 2022 05:19:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230268AbiIVFT4 (ORCPT ); Thu, 22 Sep 2022 01:19:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35338 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230081AbiIVFTy (ORCPT ); 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Wed, 21 Sep 2022 22:19:52 -0700 (PDT) From: Like Xu X-Google-Original-From: Like Xu To: Sean Christopherson , Paolo Bonzini Cc: Peter Zijlstra , Jim Mattson , linux-kernel@vger.kernel.org, kvm@vger.kernel.org Subject: [PATCH v2 2/2] KVM: x86/pmu: Add PEBS support for SPR and future non-hybird models Date: Thu, 22 Sep 2022 13:19:29 +0800 Message-Id: <20220922051929.89484-2-likexu@tencent.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220922051929.89484-1-likexu@tencent.com> References: <20220922051929.89484-1-likexu@tencent.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Like Xu Virtualization support for SPR PEBS has officially available in the Intel SDM (June 2022) and has been validated on late stepping machines: Compared to Ice Lake Server, the PDIR counter available (Fixed 0) on SPR is unchanged, but the capability is enhanced to Instruction-Accurate PDIR (PDIR++), where PEBS is taken on the next instruction after the one that caused the overflow. Also, it introduces a new Precise Distribution (PDist) facility that eliminates the skid when a precise event is programmed on general programmable counter 0. For guest usage, KVM will require the max precise level in both cases mentioned above (other conditions may apply later), requesting the correct hardware counter (PRIR++ or PDist) from host perf as usual. Signed-off-by: Like Xu --- Previous: https://lore.kernel.org/kvm/20220921064827.936-1-likexu@tencent.com/ V1 -> V2 Changelog: - move the check into a function; (Kan) arch/x86/kvm/pmu.c | 25 ++++++++++++++++++++++--- arch/x86/kvm/vmx/capabilities.h | 4 +++- 2 files changed, 25 insertions(+), 4 deletions(-) diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index 02f9e4f245bd..5e9b0b3ea42d 100644 --- a/arch/x86/kvm/pmu.c +++ b/arch/x86/kvm/pmu.c @@ -28,9 +28,18 @@ struct x86_pmu_capability __read_mostly kvm_pmu_cap; EXPORT_SYMBOL_GPL(kvm_pmu_cap); -static const struct x86_cpu_id vmx_icl_pebs_cpu[] = { +/* Precise Distribution of Instructions Retired (PDIR) */ +static const struct x86_cpu_id vmx_pebs_pdir_cpu[] = { X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, NULL), X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, NULL), + /* Instruction-Accurate PDIR (PDIR++) */ + X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, NULL), + {} +}; + +/* Precise Distribution (PDist) */ +static const struct x86_cpu_id vmx_pebs_pdist_cpu[] = { + X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, NULL), {} }; @@ -140,6 +149,16 @@ static void kvm_perf_overflow(struct perf_event *perf_event, __kvm_perf_overflow(pmc, true); } +static bool need_max_precise(struct kvm_pmc *pmc) +{ + if (pmc->idx == 0 && x86_match_cpu(vmx_pebs_pdist_cpu)) + return true; + if (pmc->idx == 32 && x86_match_cpu(vmx_pebs_pdir_cpu)) + return true; + + return false; +} + static void pmc_reprogram_counter(struct kvm_pmc *pmc, u32 type, u64 config, bool exclude_user, bool exclude_kernel, bool intr) @@ -181,11 +200,11 @@ static void pmc_reprogram_counter(struct kvm_pmc *pmc, u32 type, * the accuracy of the PEBS profiling result, because the "event IP" * in the PEBS record is calibrated on the guest side. * - * On Icelake everything is fine. Other hardware (GLC+, TNT+) that + * On Icelake everything is fine. Other hardware (TNT+) that * could possibly care here is unsupported and needs changes. */ attr.precise_ip = 1; - if (x86_match_cpu(vmx_icl_pebs_cpu) && pmc->idx == 32) + if (need_max_precise(pmc)) attr.precise_ip = 3; } diff --git a/arch/x86/kvm/vmx/capabilities.h b/arch/x86/kvm/vmx/capabilities.h index c5e5dfef69c7..4dc4bbe18821 100644 --- a/arch/x86/kvm/vmx/capabilities.h +++ b/arch/x86/kvm/vmx/capabilities.h @@ -398,7 +398,9 @@ static inline bool vmx_pt_mode_is_host_guest(void) static inline bool vmx_pebs_supported(void) { - return boot_cpu_has(X86_FEATURE_PEBS) && kvm_pmu_cap.pebs_ept; + return boot_cpu_has(X86_FEATURE_PEBS) && + !boot_cpu_has(X86_FEATURE_HYBRID_CPU) && + kvm_pmu_cap.pebs_ept; } static inline u64 vmx_get_perf_capabilities(void)