From patchwork Thu Sep 22 08:41:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tommy Wu X-Patchwork-Id: 12984752 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 07808C6FA8B for ; Thu, 22 Sep 2022 08:50:56 +0000 (UTC) Received: from localhost ([::1]:59076 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1obHv5-0003OW-O2 for qemu-devel@archiver.kernel.org; Thu, 22 Sep 2022 04:50:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35770) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1obHlw-00083i-6u for qemu-devel@nongnu.org; Thu, 22 Sep 2022 04:41:28 -0400 Received: from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435]:41724) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1obHlr-0000LY-U3 for qemu-devel@nongnu.org; Thu, 22 Sep 2022 04:41:27 -0400 Received: by mail-pf1-x435.google.com with SMTP id l65so8590527pfl.8 for ; Thu, 22 Sep 2022 01:41:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=FSSYQLFV1VvTNy6n9rnrntuKIbdmESb1brATI/jw0D4=; b=jIPGdf7atn+5cmrKS0tcVbY1ADbb6fODx3ArxpeIaWINiO9sT6Thke5RBe/NbKXDN3 8t2xgv/3KzihxjFj5VAHhqOxTI+s5Ac7dowL6+idLoEHvkCr/mbOASihLkyZMrgje9Kk 6YCP1H9nBeZyE5OtjmRl786WVtQL6h2KnVwPC52QhxN3z7kQRVP5zkxSzB6GE/r08HHR NEFAGMLqZslYFJ3UIte+/wZHkAgZSECoMIQY+lwaQrIuIzOrx7Lo9WNODwzF4ESSFuze +2jOKqulKjzFJjZyv9igso1zybA5/fIht1F7A6Df4XnDyGcTc3O2IlXZQ7q2anhV9GMD SwqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=FSSYQLFV1VvTNy6n9rnrntuKIbdmESb1brATI/jw0D4=; b=SugfEwgmfY6jbNfqGaAEaDtMDZfvzInRmCXS+mZSeAL9S3qNipaWhpOIXwXlIToMSZ ISUhqoNZV9hABUvy459vG7JdZ6RxhjXX7W5I2eTI1sWjie6rQC0afi32LqfGothE/gYe 3rFEOiXKQTZEzBz4+AZZdJjyRQJduzdsPty4jKDgKlI+eDHTPpqLq3aRzNjeoZ5FCl6o wdfYNnNUgB0GF3kSlQWD/TEc+HyTEcPdJh0uHMqbZXX870FWQYURIGNNiyeqGHjLvMdh h3vEtS2jbl7bkYghs9CXzb47pvY8lYiLuBEwGUPGk4ylOJrjbrKkcicd3uLIPI0y6pMY y3Kg== X-Gm-Message-State: ACrzQf2MnFgSm5H9di34Oc4kkRa4pdEosL4oP6bckKHhCjGtFSknxLW0 wy0Z+YH4V88L0T7GvaLkXlqU4d0q1ojFDlfm7gi+3gobzgzTXl6aerNw3WVw+Ta2io2qyKPdUHa 6nZgOcfuqGHVL0d4JLk8G6e1T71seJhDusolxnoRJeSzJRz5G8ZLgOhK3wlCPKYNT94s7NyE= X-Google-Smtp-Source: AMsMyM62XkQxjZRz4VInXr3PqSW3cgkthu4G9ojlut0Gx+j6dCtMnqeL3vjjW0mO471jPFBfi6XKag== X-Received: by 2002:a05:6a00:1253:b0:546:3d50:3284 with SMTP id u19-20020a056a00125300b005463d503284mr2463119pfi.72.1663836078633; Thu, 22 Sep 2022 01:41:18 -0700 (PDT) Received: from sw06.internal.sifive.com ([64.62.193.194]) by smtp.gmail.com with ESMTPSA id x2-20020a17090a1f8200b0020379616053sm3239202pja.57.2022.09.22.01.41.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Sep 2022 01:41:18 -0700 (PDT) From: Tommy Wu To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: alistair.francis@wdc.com, palmer@dabbelt.com, bin.meng@windriver.com, jim.shu@sifive.com, frank.chang@sifive.com, Tommy Wu Subject: [PATCH 1/3] hw/misc: sifive_e_aon: Support the watchdog timer of HiFive 1 rev b. Date: Thu, 22 Sep 2022 01:41:05 -0700 Message-Id: <20220922084107.2834285-2-tommy.wu@sifive.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220922084107.2834285-1-tommy.wu@sifive.com> References: <20220922084107.2834285-1-tommy.wu@sifive.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=tommy.wu@sifive.com; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The watchdog timer is in the always-on domain device of HiFive 1 rev b, so this patch added the AON device to the sifive_e machine. This patch only implemented the functionality of the watchdog timer. Signed-off-by: Tommy Wu Reviewed-by: Frank Chang --- hw/misc/Kconfig | 3 + hw/misc/meson.build | 1 + hw/misc/sifive_e_aon.c | 330 +++++++++++++++++++++++++++++++++ include/hw/misc/sifive_e_aon.h | 87 +++++++++ 4 files changed, 421 insertions(+) create mode 100644 hw/misc/sifive_e_aon.c create mode 100644 include/hw/misc/sifive_e_aon.h diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig index cbabe9f78c..7d1247822e 100644 --- a/hw/misc/Kconfig +++ b/hw/misc/Kconfig @@ -162,6 +162,9 @@ config SIFIVE_TEST config SIFIVE_E_PRCI bool +config SIFIVE_E_AON + bool + config SIFIVE_U_OTP bool diff --git a/hw/misc/meson.build b/hw/misc/meson.build index 95268eddc0..1536a0cc2e 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -30,6 +30,7 @@ softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_DMC', if_true: files('mchp_pfsoc_dmc.c') softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_IOSCB', if_true: files('mchp_pfsoc_ioscb.c')) softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_SYSREG', if_true: files('mchp_pfsoc_sysreg.c')) softmmu_ss.add(when: 'CONFIG_SIFIVE_TEST', if_true: files('sifive_test.c')) +softmmu_ss.add(when: 'CONFIG_SIFIVE_E_AON', if_true: files('sifive_e_aon.c')) softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c')) softmmu_ss.add(when: 'CONFIG_SIFIVE_U_OTP', if_true: files('sifive_u_otp.c')) softmmu_ss.add(when: 'CONFIG_SIFIVE_U_PRCI', if_true: files('sifive_u_prci.c')) diff --git a/hw/misc/sifive_e_aon.c b/hw/misc/sifive_e_aon.c new file mode 100644 index 0000000000..7773dfb168 --- /dev/null +++ b/hw/misc/sifive_e_aon.c @@ -0,0 +1,330 @@ +/* + * SiFive HiFive1 AON (Always On Domain) for QEMU. + * + * Copyright (c) 2022 SiFive, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "qemu/timer.h" +#include "qemu/log.h" +#include "hw/irq.h" +#include "sysemu/watchdog.h" +#include "qapi/visitor.h" +#include "hw/misc/sifive_e_aon.h" + +static void sifive_e_aon_wdt_update_wdogcount(SiFiveEAONState *r) +{ + if (0 == r->wdogcfg.wdogenalways && + 0 == r->wdogcfg.wdogencoreawake) { + return; + } + int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + r->wdogcount += muldiv64(now - r->wdog_restart_time, + r->wdogclk_freq, NANOSECONDS_PER_SECOND); + /* Clean the most significant bit. */ + r->wdogcount = ((r->wdogcount << 1) >> 1); + r->wdog_restart_time = now; +} + +static void sifive_e_aon_wdt_update_state(SiFiveEAONState *r) +{ + sifive_e_aon_wdt_update_wdogcount(r); + uint16_t wdogs = (uint16_t)(r->wdogcount >> r->wdogcfg.wdogscale); + bool cmp_signal = false; + if (wdogs >= r->wdogcmp0) { + cmp_signal = true; + if (1 == r->wdogcfg.wdogzerocmp) { + r->wdogcount = 0; + wdogs = 0; + } + } + + if (cmp_signal) { + if (1 == r->wdogcfg.wdogrsten) { + watchdog_perform_action(); + } + r->wdogcfg.wdogip0 = 1; + } + + qemu_set_irq(r->wdog_irq, r->wdogcfg.wdogip0); + + if (wdogs < r->wdogcmp0 && + (r->wdogcfg.wdogenalways || + r->wdogcfg.wdogencoreawake)) { + int64_t next = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + next += muldiv64((r->wdogcmp0 - wdogs) << r->wdogcfg.wdogscale, + NANOSECONDS_PER_SECOND, r->wdogclk_freq); + timer_mod(r->wdog_timer, next); + } else { + timer_mod(r->wdog_timer, INT64_MAX); + } +} + +/* + * Callback used when the timer set using timer_mod expires. + */ +static void sifive_e_aon_wdt_expired_cb(void *opaque) +{ + SiFiveEAONState *r = SIFIVE_E_AON(opaque); + sifive_e_aon_wdt_update_state(r); +} + +static uint64_t +sifive_e_aon_wdt_read(void *opaque, hwaddr addr, unsigned int size) +{ + SiFiveEAONState *r = SIFIVE_E_AON(opaque); + + switch (addr) { + case SIFIVE_E_AON_WDT_WDOGCFG: + return r->wdogcfg.value; + case SIFIVE_E_AON_WDT_WDOGCOUNT: + sifive_e_aon_wdt_update_wdogcount(r); + return r->wdogcount; + case SIFIVE_E_AON_WDT_WDOGS: + sifive_e_aon_wdt_update_wdogcount(r); + return r->wdogcount >> r->wdogcfg.wdogscale; + case SIFIVE_E_AON_WDT_WDOGFEED: + return 0; + case SIFIVE_E_AON_WDT_WDOGKEY: + return r->wdogunlock; + case SIFIVE_E_AON_WDT_WDOGCMP0: + return r->wdogcmp0; + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: bad read: addr=0x%x\n", + __func__, (int)addr); + } + + return 0; +} + +static void +sifive_e_aon_wdt_write(void *opaque, hwaddr addr, + uint64_t val64, unsigned int size) +{ + SiFiveEAONState *r = SIFIVE_E_AON(opaque); + uint32_t value = val64; + + switch (addr) { + case SIFIVE_E_AON_WDT_WDOGCFG: + if (0 == r->wdogunlock) { + return; + } + wdogcfg_s new_wdogcfg; + new_wdogcfg.value = value; + if (1 == (r->wdogcfg.wdogenalways || + r->wdogcfg.wdogencoreawake) && + 0 == (new_wdogcfg.wdogenalways || + new_wdogcfg.wdogencoreawake)) { + sifive_e_aon_wdt_update_wdogcount(r); + } else if (0 == (r->wdogcfg.wdogenalways || + r->wdogcfg.wdogencoreawake) && + 1 == (new_wdogcfg.wdogenalways || + new_wdogcfg.wdogencoreawake)) { + r->wdog_restart_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + } + r->wdogcfg.value = value; + r->wdogunlock = 0; + break; + case SIFIVE_E_AON_WDT_WDOGCOUNT: + if (0 == r->wdogunlock) { + return; + } + r->wdogcount = ((value << 1) >> 1); + r->wdog_restart_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + r->wdogunlock = 0; + break; + case SIFIVE_E_AON_WDT_WDOGS: + return; + case SIFIVE_E_AON_WDT_WDOGFEED: + if (0 == r->wdogunlock) { + return; + } + if (SIFIVE_E_AON_WDOGFEED == value) { + r->wdogcount = 0; + r->wdog_restart_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + } + r->wdogunlock = 0; + break; + case SIFIVE_E_AON_WDT_WDOGKEY: + if (SIFIVE_E_AON_WDOGKEY == value) { + r->wdogunlock = 1; + } + break; + case SIFIVE_E_AON_WDT_WDOGCMP0: + if (0 == r->wdogunlock) { + return; + } + r->wdogcmp0 = (uint16_t) value; + r->wdogunlock = 0; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=0x%x v=0x%x\n", + __func__, (int)addr, (int)value); + } + + sifive_e_aon_wdt_update_state(r); +} + +static uint64_t +sifive_e_aon_read(void *opaque, hwaddr addr, unsigned int size) +{ + if (addr < SIFIVE_E_AON_RTC_RTCCFG) { + /* AON WDT */ + return sifive_e_aon_wdt_read(opaque, addr, size); + } else if (addr < SIFIVE_E_AON_LFROSC_LFROSCCFG) { + /* AON RTC */ + } else if (addr < SIFIVE_E_AON_BACKUP_BACKUP0) { + /* AON LFROSC */ + } else if (addr < SIFIVE_E_AON_PMU_PMUWAKEUP0) { + /* AON BACKUP */ + } else if (addr < SIFIVE_E_AON_MAX) { + /* AON PMU */ + } else { + qemu_log_mask(LOG_GUEST_ERROR, "%s: bad read: addr=0x%x\n", + __func__, (int)addr); + } + + return 0; +} + +static void +sifive_e_aon_write(void *opaque, hwaddr addr, + uint64_t val64, unsigned int size) +{ + if (addr < SIFIVE_E_AON_RTC_RTCCFG) { + /* AON WDT */ + sifive_e_aon_wdt_write(opaque, addr, val64, size); + } else if (addr < SIFIVE_E_AON_LFROSC_LFROSCCFG) { + /* AON RTC */ + } else if (addr < SIFIVE_E_AON_BACKUP_BACKUP0) { + /* AON LFROSC */ + } else if (addr < SIFIVE_E_AON_PMU_PMUWAKEUP0) { + /* AON BACKUP */ + } else if (addr < SIFIVE_E_AON_MAX) { + /* AON PMU */ + } else { + qemu_log_mask(LOG_GUEST_ERROR, "%s: bad read: addr=0x%x\n", + __func__, (int)addr); + } +} + +static const MemoryRegionOps sifive_e_aon_ops = { + .read = sifive_e_aon_read, + .write = sifive_e_aon_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .impl = { + .min_access_size = 4, + .max_access_size = 4 + }, + .valid = { + .min_access_size = 4, + .max_access_size = 4 + } +}; + +SiFiveEAONState *sifive_e_aon_create(MemoryRegion *mr, hwaddr base, + qemu_irq wdt_irq) +{ + DeviceState *dev; + SysBusDevice *s; + SiFiveEAONState *r; + + dev = qdev_new(TYPE_SIFIVE_E_AON); + s = SYS_BUS_DEVICE(dev); + + sysbus_realize_and_unref(s, &error_fatal); + + memory_region_add_subregion(mr, base, + sysbus_mmio_get_region(s, 0)); + sysbus_connect_irq(s, 0, wdt_irq); + + r = SIFIVE_E_AON(dev); + return r; +} + +static void sifive_e_aon_reset(DeviceState *dev) +{ + SiFiveEAONState *s = SIFIVE_E_AON(dev); + + s->wdogcfg.wdogrsten = 0; + s->wdogcfg.wdogenalways = 0; + s->wdogcfg.wdogencoreawake = 0; + s->wdogcmp0 = 0xbeef; +} + +static void sifive_e_aon_wdt_update_wdogclk_freq(Object *obj, Visitor *v, + const char *name, + void *opaque, + Error **errp) { + SiFiveEAONState *r = SIFIVE_E_AON(opaque); + uint64_t value; + if (!visit_type_uint64(v, name, &value, errp)) { + return; + } + + r->wdogclk_freq = value; + sifive_e_aon_wdt_update_state(r); +} + +static void sifive_e_aon_init(Object *obj) +{ + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); + SiFiveEAONState *s = SIFIVE_E_AON(obj); + + memory_region_init_io(&s->mmio, OBJECT(s), &sifive_e_aon_ops, s, + TYPE_SIFIVE_E_AON, SIFIVE_E_AON_MAX); + sysbus_init_mmio(sbd, &s->mmio); + + /* watchdog timer */ + s->wdogclk_freq = SIFIVE_E_LFCLK_DEFAULT_FREQ; + sysbus_init_irq(sbd, &s->wdog_irq); + object_property_add(obj, "wdogclk-frequency", "uint64", + NULL, + sifive_e_aon_wdt_update_wdogclk_freq, + NULL, s); +} + +static void sifive_e_aon_realize(DeviceState *dev, Error **errp) +{ + SiFiveEAONState *s = SIFIVE_E_AON(dev); + + /* watchdog timer */ + s->wdog_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, + sifive_e_aon_wdt_expired_cb, s); +} + +static void sifive_e_aon_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + + dc->realize = sifive_e_aon_realize; + dc->reset = sifive_e_aon_reset; +} + +static const TypeInfo sifive_e_aon_info = { + .name = TYPE_SIFIVE_E_AON, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(SiFiveEAONState), + .instance_init = sifive_e_aon_init, + .class_init = sifive_e_aon_class_init, +}; + +static void sifive_e_aon_register_types(void) +{ + type_register_static(&sifive_e_aon_info); +} + +type_init(sifive_e_aon_register_types) diff --git a/include/hw/misc/sifive_e_aon.h b/include/hw/misc/sifive_e_aon.h new file mode 100644 index 0000000000..ee4134bd25 --- /dev/null +++ b/include/hw/misc/sifive_e_aon.h @@ -0,0 +1,87 @@ +/* + * SiFive HiFive1 AON (Always On Domain) interface. + * + * Copyright (c) 2022 SiFive, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#ifndef HW_SIFIVE_AON_H +#define HW_SIFIVE_AON_H + +#include "hw/sysbus.h" +#include "qom/object.h" + +#define TYPE_SIFIVE_E_AON "riscv.sifive.e.aon" +OBJECT_DECLARE_SIMPLE_TYPE(SiFiveEAONState, SIFIVE_E_AON) + +#define SIFIVE_E_AON_WDOGKEY (0x51F15E) +#define SIFIVE_E_AON_WDOGFEED (0xD09F00D) +#define SIFIVE_E_LFCLK_DEFAULT_FREQ (32768) + +enum { + SIFIVE_E_AON_WDT_WDOGCFG = 0, + SIFIVE_E_AON_WDT_WDOGCOUNT = 0x8, + SIFIVE_E_AON_WDT_WDOGS = 0x10, + SIFIVE_E_AON_WDT_WDOGFEED = 0x18, + SIFIVE_E_AON_WDT_WDOGKEY = 0x1c, + SIFIVE_E_AON_WDT_WDOGCMP0 = 0x20, + SIFIVE_E_AON_RTC_RTCCFG = 0x40, + SIFIVE_E_AON_LFROSC_LFROSCCFG = 0x70, + SIFIVE_E_AON_BACKUP_BACKUP0 = 0x80, + SIFIVE_E_AON_PMU_PMUWAKEUP0 = 0x100, + SIFIVE_E_AON_MAX = 0x150 +}; + +typedef struct wdogcfg_s wdogcfg_s; +struct wdogcfg_s { + union { + uint32_t value; + struct { + uint32_t wdogscale:4; + uint32_t reserved:4; + uint8_t wdogrsten:1; + uint8_t wdogzerocmp:1; + uint8_t reserved2:2; + uint8_t wdogenalways:1; + uint8_t wdogencoreawake:1; + uint32_t reserved3:14; + uint8_t wdogip0:1; + uint8_t reserved4:3; + }; + }; +}; + +struct SiFiveEAONState { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + MemoryRegion mmio; + + /*< watchdog timer >*/ + QEMUTimer *wdog_timer; + qemu_irq wdog_irq; + uint64_t wdog_restart_time; + uint64_t wdogclk_freq; + + wdogcfg_s wdogcfg; + uint16_t wdogcmp0; + uint32_t wdogcount; + uint8_t wdogunlock; +}; + +SiFiveEAONState *sifive_e_aon_create(MemoryRegion *mr, hwaddr base, + qemu_irq irq); + +#endif From patchwork Thu Sep 22 08:41:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tommy Wu X-Patchwork-Id: 12984750 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1346EC6FA8B for ; Thu, 22 Sep 2022 08:48:24 +0000 (UTC) Received: from localhost ([::1]:33620 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1obHsd-0002lF-Nl for qemu-devel@archiver.kernel.org; Thu, 22 Sep 2022 04:48:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35766) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1obHlv-00083B-QG for qemu-devel@nongnu.org; Thu, 22 Sep 2022 04:41:27 -0400 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]:41633) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1obHlr-0000PH-W8 for qemu-devel@nongnu.org; Thu, 22 Sep 2022 04:41:27 -0400 Received: by mail-pl1-x633.google.com with SMTP id d11so723083pll.8 for ; Thu, 22 Sep 2022 01:41:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=4BjXTJQeqxBw/YQt7EauQLCNg+bbYoI2T6boosefcnI=; b=UpgjIeNU16Wbs0q+bkTg1aT+qDkbuYsvWh9BU+VwKKICtF7RdMU9G6+CXY8WD8mqbw Bsht5ntN6nWcgFfqGFlKflGAGSgzKbgOTWJayAmu/BC1tvCerolhf9gu/9E96YkecwgK jTqOVBS9yKhY1k1eFVwyUpBVE7SM/ZuvR2M6yGlpXmEE1Veem7cj+7kEbGUHCyJWfA4X ukwhO5qaU+dhdVUlFRdsTrYnVH1MwU6eVIwfbOt/zRNtSD6K4J0R5D+bOWYez+QcktOk qmR4esMiiNFrfz/Oy3RNSk9fDkC7SWn5JbND+bk2c/LMwiHI8uOEoG5AOLj5I77CWy43 w6Jg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=4BjXTJQeqxBw/YQt7EauQLCNg+bbYoI2T6boosefcnI=; b=7wcDt8+b6OrepHcLBIa8nSsMlfcduIZBnxmzhni2QM5t71ngHfI6P/3ODAoRWDrk0V UnKFK9wB/Az8Da1yiK048C2NcsJlI75m2yjA7gBfYaQEttkByWj+j77pJnTl5ewHA9UK xbE8hK5ahm/HzIpMNez/c9v4zrT0mdtgTEmJL4j6iMAexY29PqTs49Ubsvou3eLGKOrD OyRihHfu1OVbjRuKWBHl1019aeXSK8/reZVrb9Su7NewsbLXoW6XJ/FRLd92JLzKsRdD XZa9FIc5iJJF24N2X68Lt1Em3ujNBCYwjzZtvJm/XXx6X8qIcNjxNmEj+nWQOxfUFfwF c7cA== X-Gm-Message-State: ACrzQf12uCW/4VA5wz2R/egd9MVsf5FLIapOA+8A2s+EUj+1FCjoBFb1 VWWQL7byqfj4r7xSjm/+FuYA6BRx9Utv2aGDBLDyELGtMGWkt1u7uNMQtDT9zuDfGtSIvwPIWwf JZduRdAC/t4rbTHxc4crHmCZL19mTsJ001cmNNxLl+v6sCPoX2TH5AupGd1AJs/Z2xFlI5uI= X-Google-Smtp-Source: AMsMyM5w5Qvmbrt0RNr8aAsAnFMOCO/fD/kDkd77lRPmSHO8/X466dZLYU79dx/DFXiVvcN8gdNYeA== X-Received: by 2002:a17:903:41c2:b0:178:5ddd:c75b with SMTP id u2-20020a17090341c200b001785dddc75bmr2388882ple.22.1663836081101; Thu, 22 Sep 2022 01:41:21 -0700 (PDT) Received: from sw06.internal.sifive.com ([64.62.193.194]) by smtp.gmail.com with ESMTPSA id x2-20020a17090a1f8200b0020379616053sm3239202pja.57.2022.09.22.01.41.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Sep 2022 01:41:20 -0700 (PDT) From: Tommy Wu To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: alistair.francis@wdc.com, palmer@dabbelt.com, bin.meng@windriver.com, jim.shu@sifive.com, frank.chang@sifive.com, Tommy Wu Subject: [PATCH 2/3] hw/riscv: sifive_e: Support the watchdog timer of HiFive 1 rev b. Date: Thu, 22 Sep 2022 01:41:06 -0700 Message-Id: <20220922084107.2834285-3-tommy.wu@sifive.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220922084107.2834285-1-tommy.wu@sifive.com> References: <20220922084107.2834285-1-tommy.wu@sifive.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=tommy.wu@sifive.com; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Create the AON device when we realize the sifive_e machine. This patch only implemented the functionality of the watchdog timer, not all the functionality of the AON device. Signed-off-by: Tommy Wu Reviewed-by: Frank Chang Reviewed-by: Alistair Francis --- hw/riscv/Kconfig | 1 + hw/riscv/sifive_e.c | 5 +++-- include/hw/riscv/sifive_e.h | 7 ++++--- 3 files changed, 8 insertions(+), 5 deletions(-) diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index 79ff61c464..50890b1b75 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -59,6 +59,7 @@ config SIFIVE_E select SIFIVE_PLIC select SIFIVE_UART select SIFIVE_E_PRCI + select SIFIVE_E_AON select UNIMP config SIFIVE_U diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index d65d2fd869..f9c05cfd3a 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -45,6 +45,7 @@ #include "hw/intc/riscv_aclint.h" #include "hw/intc/sifive_plic.h" #include "hw/misc/sifive_e_prci.h" +#include "hw/misc/sifive_e_aon.h" #include "chardev/char.h" #include "sysemu/sysemu.h" @@ -222,8 +223,8 @@ static void sifive_e_soc_realize(DeviceState *dev, Error **errp) RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, ms->smp.cpus, RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, false); - create_unimplemented_device("riscv.sifive.e.aon", - memmap[SIFIVE_E_DEV_AON].base, memmap[SIFIVE_E_DEV_AON].size); + sifive_e_aon_create(sys_mem, memmap[SIFIVE_E_DEV_AON].base, + qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_AON_WDT_IRQ)); sifive_e_prci_create(memmap[SIFIVE_E_DEV_PRCI].base); /* GPIO */ diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h index 83604da805..7de2221564 100644 --- a/include/hw/riscv/sifive_e.h +++ b/include/hw/riscv/sifive_e.h @@ -75,9 +75,10 @@ enum { }; enum { - SIFIVE_E_UART0_IRQ = 3, - SIFIVE_E_UART1_IRQ = 4, - SIFIVE_E_GPIO0_IRQ0 = 8 + SIFIVE_E_AON_WDT_IRQ = 1, + SIFIVE_E_UART0_IRQ = 3, + SIFIVE_E_UART1_IRQ = 4, + SIFIVE_E_GPIO0_IRQ0 = 8 }; #define SIFIVE_E_PLIC_HART_CONFIG "M" From patchwork Thu Sep 22 08:41:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tommy Wu X-Patchwork-Id: 12984753 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1AE5FC6FA8B for ; Thu, 22 Sep 2022 08:51:20 +0000 (UTC) Received: from localhost ([::1]:56088 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1obHvT-0003qv-0x for qemu-devel@archiver.kernel.org; Thu, 22 Sep 2022 04:51:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35774) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1obHly-00083w-2A for qemu-devel@nongnu.org; Thu, 22 Sep 2022 04:41:30 -0400 Received: from mail-pg1-x533.google.com ([2607:f8b0:4864:20::533]:39447) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1obHls-0000PV-O6 for qemu-devel@nongnu.org; Thu, 22 Sep 2022 04:41:29 -0400 Received: by mail-pg1-x533.google.com with SMTP id b5so303882pgb.6 for ; Thu, 22 Sep 2022 01:41:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=HvuMTW94+hFSQqzauz4aeVbKjUjPDqFiwXpARMEgMMY=; b=JSLWeu1CVqE96Twxs7Wxo8zCKgsuEuMPm8+jiBJn+HXBpNXXQiCcsFuMmgpSGNnPDR Fgcqa0APPsN1D1+h71D5LEnUNfSr2PTMCZTujNiAPKNOk0+q6XLw4ar1FVsYFwiTYbK6 NTDFOMUjbqugYdqDpvgn35kJEsk2j4Fe8uNCIP3C3Yy2ik+Dg+UqWObRjYqN1egghwMW tu6tMtIee0Z/xMOVnr/Vtln6RDhTqcWloIpHrTqR789QH86zQN+AA3ER4OkUaxA2NNgS JaV2LjIlkBVyhYfRLYQf4QjbFsnVNrR+3tco4cF1XfkWP1BZXXX0WcJ89mQUyN5JAP+6 5Olg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=HvuMTW94+hFSQqzauz4aeVbKjUjPDqFiwXpARMEgMMY=; b=y3Aee3fWghUpGQ0OIoblFwhseHDaBZ1tMaDpgDgs5D38/2S4F2e1AtxLP1eoScFwjo h0n5hdH0+6NLT9ohQ7EXpeFiCQ6P7cd35sdhXkYaHLk/OzM9fxvjKZwkyTm0gX3voKUx i+pnqswLH+cGiV5kd0JehESD/4yVH2+X+qCJdzNfVFSF83u+7lBu8vEhaMIXoE4vrlnC YwlilvaxYZMA7XZet77F162oRLHVWKJYxp6JPNXHv35UHpSb8XL430gNZZlWlpr8ihHp 2ji5i++rOIOzr7eNmNe0zNRD54VVd196tHVsH7nvOQ370QJ4+PhU6bcu4EC046heCXDq YoWg== X-Gm-Message-State: ACrzQf23E7J5053QF3ZawlnRbLKDSmlcYx1qX0gFxR7bHz/VjVz8uaTc l5xCvqlo5tbd5dYKq8kN+RZX3cpwQqszsYQf4DjRBts+9zL5e0p4NtseZAZgX2fIXlV84tsYfPz WuhRD6D78BGFV5wQzQrpFYiLGclN9Pc6+fy30/t3kQqmSbYcTdUBBSt5a1W0y8J84EtC7xlU= X-Google-Smtp-Source: AMsMyM4r5bGfiM7j0M51h2Kyokh3JWWZX6fBAPCKLGAdnvdEzdcTc06TXoN2NwNW/TdyuegtDsc1uw== X-Received: by 2002:a05:6a00:1946:b0:54d:bdea:e159 with SMTP id s6-20020a056a00194600b0054dbdeae159mr2538828pfk.47.1663836082911; Thu, 22 Sep 2022 01:41:22 -0700 (PDT) Received: from sw06.internal.sifive.com ([64.62.193.194]) by smtp.gmail.com with ESMTPSA id x2-20020a17090a1f8200b0020379616053sm3239202pja.57.2022.09.22.01.41.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Sep 2022 01:41:22 -0700 (PDT) From: Tommy Wu To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: alistair.francis@wdc.com, palmer@dabbelt.com, bin.meng@windriver.com, jim.shu@sifive.com, frank.chang@sifive.com, Tommy Wu Subject: [PATCH 3/3] tests/qtest: sifive-e-aon-watchdog-test.c : Add QTest of watchdog of sifive_e Date: Thu, 22 Sep 2022 01:41:07 -0700 Message-Id: <20220922084107.2834285-4-tommy.wu@sifive.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220922084107.2834285-1-tommy.wu@sifive.com> References: <20220922084107.2834285-1-tommy.wu@sifive.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=tommy.wu@sifive.com; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Add some simple tests of the watchdog timer in the always-on domain device of HiFive 1 rev b. Signed-off-by: Tommy Wu Reviewed-by: Frank Chang --- tests/qtest/meson.build | 3 + tests/qtest/sifive-e-aon-watchdog-test.c | 400 +++++++++++++++++++++++ 2 files changed, 403 insertions(+) create mode 100644 tests/qtest/sifive-e-aon-watchdog-test.c diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index e910cb32ca..446115ea34 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -234,6 +234,9 @@ qtests_s390x = \ 'cpu-plug-test', 'migration-test'] +qtests_riscv32 = \ + (config_all_devices.has_key('CONFIG_SIFIVE_E_AON') ? ['sifive-e-aon-watchdog-test'] : []) + qos_test_ss = ss.source_set() qos_test_ss.add( 'ac97-test.c', diff --git a/tests/qtest/sifive-e-aon-watchdog-test.c b/tests/qtest/sifive-e-aon-watchdog-test.c new file mode 100644 index 0000000000..a583539346 --- /dev/null +++ b/tests/qtest/sifive-e-aon-watchdog-test.c @@ -0,0 +1,400 @@ +#include "qemu/osdep.h" +#include "qemu/timer.h" +#include "qemu/bitops.h" +#include "libqtest-single.h" +#include "hw/misc/sifive_e_aon.h" + +#define WDOG_BASE (0x10000000) +#define WDOGCFG (0x0) +#define WDOGCOUNT (0x8) +#define WDOGS (0x10) +#define WDOGFEED (0x18) +#define WDOGKEY (0x1c) +#define WDOGCMP0 (0x20) + +#define SIFIVE_E_AON_WDOGKEY (0x51F15E) +#define SIFIVE_E_AON_WDOGFEED (0xD09F00D) +#define SIFIVE_E_LFCLK_DEFAULT_FREQ (32768) + +static void test_init(void) +{ + writel(WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); + writel(WDOG_BASE + WDOGCOUNT, 0); + + writel(WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); + writel(WDOG_BASE + WDOGCFG, 0); + + writel(WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); + writel(WDOG_BASE + WDOGCMP0, 0xBEEF); +} + +static void test_wdogcount(void) +{ + test_init(); + + uint64_t tmp; + tmp = readl(WDOG_BASE + WDOGCOUNT); + writel(WDOG_BASE + WDOGCOUNT, 0xBEEF); + g_assert(readl(WDOG_BASE + WDOGCOUNT) == tmp); + + writel(WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); + writel(WDOG_BASE + WDOGCOUNT, 0xBEEF); + g_assert(0xBEEF == readl(WDOG_BASE + WDOGCOUNT)); + + writel(WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); + writel(WDOG_BASE + WDOGCOUNT, 0xAAAAAAAA); + g_assert(0x2AAAAAAA == readl(WDOG_BASE + WDOGCOUNT)); + + writel(WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); + writel(WDOG_BASE + WDOGFEED, 0xAAAAAAAA); + g_assert(0x2AAAAAAA == readl(WDOG_BASE + WDOGCOUNT)); + + writel(WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); + writel(WDOG_BASE + WDOGFEED, SIFIVE_E_AON_WDOGFEED); + g_assert(0 == readl(WDOG_BASE + WDOGCOUNT)); +} + +static void test_wdogcfg(void) +{ + test_init(); + + wdogcfg_s tmp; + tmp.value = readl(WDOG_BASE + WDOGCFG); + writel(WDOG_BASE + WDOGCFG, 0xFFFFFFFF); + g_assert(readl(WDOG_BASE + WDOGCFG) == tmp.value); + + writel(WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); + writel(WDOG_BASE + WDOGCFG, 0xFFFFFFFF); + g_assert(0xFFFFFFFF == readl(WDOG_BASE + WDOGCFG)); + + tmp.value = readl(WDOG_BASE + WDOGCFG); + g_assert(15 == tmp.wdogscale); + g_assert(1 == tmp.wdogrsten); + g_assert(1 == tmp.wdogzerocmp); + g_assert(1 == tmp.wdogenalways); + g_assert(1 == tmp.wdogencoreawake); + g_assert(1 == tmp.wdogip0); + + writel(WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); + writel(WDOG_BASE + WDOGCFG, 0); + g_assert(0 == readl(WDOG_BASE + WDOGCFG)); + + tmp.value = readl(WDOG_BASE + WDOGCFG); + g_assert(0 == tmp.wdogscale); + g_assert(0 == tmp.wdogrsten); + g_assert(0 == tmp.wdogzerocmp); + g_assert(0 == tmp.wdogenalways); + g_assert(0 == tmp.wdogencoreawake); + g_assert(0 == tmp.wdogip0); +} + +static void test_wdogcmp0(void) +{ + test_init(); + + wdogcfg_s tmp; + tmp.value = readl(WDOG_BASE + WDOGCMP0); + writel(WDOG_BASE + WDOGCMP0, 0xBEEF); + g_assert(readl(WDOG_BASE + WDOGCMP0) == tmp.value); + + writel(WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); + writel(WDOG_BASE + WDOGCMP0, 0xBEEF); + g_assert(0xBEEF == readl(WDOG_BASE + WDOGCMP0)); +} + +static void test_wdogkey(void) +{ + test_init(); + + g_assert(0 == readl(WDOG_BASE + WDOGKEY)); + + writel(WDOG_BASE + WDOGKEY, 0xFFFF); + g_assert(0 == readl(WDOG_BASE + WDOGKEY)); + + writel(WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); + g_assert(1 == readl(WDOG_BASE + WDOGKEY)); + + writel(WDOG_BASE + WDOGFEED, 0xAAAAAAAA); + g_assert(0 == readl(WDOG_BASE + WDOGKEY)); +} + +static void test_wdogfeed(void) +{ + test_init(); + + g_assert(0 == readl(WDOG_BASE + WDOGFEED)); + + writel(WDOG_BASE + WDOGFEED, 0xFFFF); + g_assert(0 == readl(WDOG_BASE + WDOGFEED)); +} + +static void test_scaled_wdogs(void) +{ + test_init(); + + wdogcfg_s cfg; + uint32_t fake_count = 0x12345678; + writel(WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); + writel(WDOG_BASE + WDOGCOUNT, fake_count); + g_assert(readl(WDOG_BASE + WDOGCOUNT) == fake_count); + g_assert((uint16_t)readl(WDOG_BASE + WDOGS) == + (uint16_t)fake_count); + + for (int i = 0; i < 16; i++) { + cfg.value = readl(WDOG_BASE + WDOGCFG); + cfg.wdogscale = i; + writel(WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); + writel(WDOG_BASE + WDOGCFG, cfg.value); + g_assert((uint16_t)readl(WDOG_BASE + WDOGS) == + (uint16_t)(fake_count >> cfg.wdogscale)); + } +} + +static void test_watchdog(void) +{ + test_init(); + + wdogcfg_s cfg; + + writel(WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); + writel(WDOG_BASE + WDOGCMP0, SIFIVE_E_LFCLK_DEFAULT_FREQ); + + cfg.value = readl(WDOG_BASE + WDOGCFG); + cfg.wdogscale = 0; + cfg.wdogenalways = 1; + writel(WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); + writel(WDOG_BASE + WDOGCFG, cfg.value); + + clock_step(NANOSECONDS_PER_SECOND); + + g_assert(readl(WDOG_BASE + WDOGCOUNT) == + SIFIVE_E_LFCLK_DEFAULT_FREQ); + + g_assert(readl(WDOG_BASE + WDOGS) == + SIFIVE_E_LFCLK_DEFAULT_FREQ); + + cfg.value = readl(WDOG_BASE + WDOGCFG); + g_assert(0 == cfg.wdogscale); + g_assert(0 == cfg.wdogrsten); + g_assert(0 == cfg.wdogzerocmp); + g_assert(1 == cfg.wdogenalways); + g_assert(0 == cfg.wdogencoreawake); + g_assert(1 == cfg.wdogip0); + + writel(WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); + writel(WDOG_BASE + WDOGCOUNT, 0); + cfg.wdogip0 = 0; + writel(WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); + writel(WDOG_BASE + WDOGCFG, cfg.value); + cfg.value = readl(WDOG_BASE + WDOGCFG); + g_assert(0 == cfg.wdogip0); +} + +static void test_scaled_watchdog(void) +{ + test_init(); + + wdogcfg_s cfg; + + writel(WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); + writel(WDOG_BASE + WDOGCMP0, 10); + + cfg.value = readl(WDOG_BASE + WDOGCFG); + cfg.wdogscale = 15; + cfg.wdogenalways = 1; + writel(WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); + writel(WDOG_BASE + WDOGCFG, cfg.value); + + clock_step(NANOSECONDS_PER_SECOND * 10); + + g_assert(readl(WDOG_BASE + WDOGCOUNT) == + SIFIVE_E_LFCLK_DEFAULT_FREQ * 10); + + g_assert(10 == readl(WDOG_BASE + WDOGS)); + + cfg.value = readl(WDOG_BASE + WDOGCFG); + g_assert(15 == cfg.wdogscale); + g_assert(0 == cfg.wdogrsten); + g_assert(0 == cfg.wdogzerocmp); + g_assert(1 == cfg.wdogenalways); + g_assert(0 == cfg.wdogencoreawake); + g_assert(1 == cfg.wdogip0); + + writel(WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); + writel(WDOG_BASE + WDOGCOUNT, 0); + cfg.wdogip0 = 0; + writel(WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); + writel(WDOG_BASE + WDOGCFG, cfg.value); + cfg.value = readl(WDOG_BASE + WDOGCFG); + g_assert(0 == cfg.wdogip0); +} + +static void test_periodic_int(void) +{ + test_init(); + + wdogcfg_s cfg; + + writel(WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); + writel(WDOG_BASE + WDOGCMP0, SIFIVE_E_LFCLK_DEFAULT_FREQ); + + cfg.value = readl(WDOG_BASE + WDOGCFG); + cfg.wdogscale = 0; + cfg.wdogzerocmp = 1; + cfg.wdogenalways = 1; + writel(WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); + writel(WDOG_BASE + WDOGCFG, cfg.value); + + clock_step(NANOSECONDS_PER_SECOND); + + g_assert(0 == readl(WDOG_BASE + WDOGCOUNT)); + + g_assert(0 == readl(WDOG_BASE + WDOGS)); + + cfg.value = readl(WDOG_BASE + WDOGCFG); + g_assert(0 == cfg.wdogscale); + g_assert(0 == cfg.wdogrsten); + g_assert(1 == cfg.wdogzerocmp); + g_assert(1 == cfg.wdogenalways); + g_assert(0 == cfg.wdogencoreawake); + g_assert(1 == cfg.wdogip0); + + cfg.wdogip0 = 0; + writel(WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); + writel(WDOG_BASE + WDOGCFG, cfg.value); + cfg.value = readl(WDOG_BASE + WDOGCFG); + g_assert(0 == cfg.wdogip0); + + clock_step(NANOSECONDS_PER_SECOND); + + g_assert(0 == readl(WDOG_BASE + WDOGCOUNT)); + + g_assert(0 == readl(WDOG_BASE + WDOGS)); + + cfg.value = readl(WDOG_BASE + WDOGCFG); + g_assert(0 == cfg.wdogscale); + g_assert(0 == cfg.wdogrsten); + g_assert(1 == cfg.wdogzerocmp); + g_assert(1 == cfg.wdogenalways); + g_assert(0 == cfg.wdogencoreawake); + g_assert(1 == cfg.wdogip0); + + cfg.wdogip0 = 0; + writel(WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); + writel(WDOG_BASE + WDOGCFG, cfg.value); + cfg.value = readl(WDOG_BASE + WDOGCFG); + g_assert(0 == cfg.wdogip0); +} + +static void test_enable_disable(void) +{ + test_init(); + + wdogcfg_s cfg; + + writel(WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); + writel(WDOG_BASE + WDOGCMP0, 10); + + cfg.value = readl(WDOG_BASE + WDOGCFG); + cfg.wdogscale = 15; + cfg.wdogenalways = 1; + writel(WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); + writel(WDOG_BASE + WDOGCFG, cfg.value); + + clock_step(NANOSECONDS_PER_SECOND * 2); + + g_assert(readl(WDOG_BASE + WDOGCOUNT) == + SIFIVE_E_LFCLK_DEFAULT_FREQ * 2); + + g_assert(2 == readl(WDOG_BASE + WDOGS)); + + cfg.value = readl(WDOG_BASE + WDOGCFG); + g_assert(15 == cfg.wdogscale); + g_assert(0 == cfg.wdogrsten); + g_assert(0 == cfg.wdogzerocmp); + g_assert(1 == cfg.wdogenalways); + g_assert(0 == cfg.wdogencoreawake); + g_assert(0 == cfg.wdogip0); + + writel(WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); + cfg.wdogenalways = 0; + writel(WDOG_BASE + WDOGCFG, cfg.value); + + clock_step(NANOSECONDS_PER_SECOND * 8); + + g_assert(readl(WDOG_BASE + WDOGCOUNT) == + SIFIVE_E_LFCLK_DEFAULT_FREQ * 2); + + g_assert(2 == readl(WDOG_BASE + WDOGS)); + + cfg.value = readl(WDOG_BASE + WDOGCFG); + g_assert(15 == cfg.wdogscale); + g_assert(0 == cfg.wdogrsten); + g_assert(0 == cfg.wdogzerocmp); + g_assert(0 == cfg.wdogenalways); + g_assert(0 == cfg.wdogencoreawake); + g_assert(0 == cfg.wdogip0); + + cfg.wdogenalways = 1; + writel(WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); + writel(WDOG_BASE + WDOGCFG, cfg.value); + + clock_step(NANOSECONDS_PER_SECOND * 8); + + g_assert(readl(WDOG_BASE + WDOGCOUNT) == + SIFIVE_E_LFCLK_DEFAULT_FREQ * 10); + + g_assert(10 == readl(WDOG_BASE + WDOGS)); + + cfg.value = readl(WDOG_BASE + WDOGCFG); + g_assert(15 == cfg.wdogscale); + g_assert(0 == cfg.wdogrsten); + g_assert(0 == cfg.wdogzerocmp); + g_assert(1 == cfg.wdogenalways); + g_assert(0 == cfg.wdogencoreawake); + g_assert(1 == cfg.wdogip0); + + writel(WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); + writel(WDOG_BASE + WDOGCOUNT, 0); + cfg.wdogip0 = 0; + writel(WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); + writel(WDOG_BASE + WDOGCFG, cfg.value); + cfg.value = readl(WDOG_BASE + WDOGCFG); + g_assert(0 == cfg.wdogip0); +} + +int main(int argc, char *argv[]) +{ + int r; + + g_test_init(&argc, &argv, NULL); + + qtest_start("-machine sifive_e"); + + qtest_add_func("/sifive-e-aon-watchdog-test/wdogcount", + test_wdogcount); + qtest_add_func("/sifive-e-aon-watchdog-test/wdogcfg", + test_wdogcfg); + qtest_add_func("/sifive-e-aon-watchdog-test/wdogcmp0", + test_wdogcmp0); + qtest_add_func("/sifive-e-aon-watchdog-test/wdogkey", + test_wdogkey); + qtest_add_func("/sifive-e-aon-watchdog-test/wdogfeed", + test_wdogfeed); + qtest_add_func("/sifive-e-aon-watchdog-test/scaled_wdogs", + test_scaled_wdogs); + qtest_add_func("/sifive-e-aon-watchdog-test/watchdog", + test_watchdog); + qtest_add_func("/sifive-e-aon-watchdog-test/scaled_watchdog", + test_scaled_watchdog); + qtest_add_func("/sifive-e-aon-watchdog-test/periodic_int", + test_periodic_int); + qtest_add_func("/sifive-e-aon-watchdog-test/enable_disable", + test_enable_disable); + + r = g_test_run(); + + qtest_end(); + + return r; +}