From patchwork Sat Sep 24 09:24:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 12987534 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5CF00C6FA83 for ; Sat, 24 Sep 2022 09:24:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233420AbiIXJYW (ORCPT ); Sat, 24 Sep 2022 05:24:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46582 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233436AbiIXJYV (ORCPT ); Sat, 24 Sep 2022 05:24:21 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ACE7D13943C; Sat, 24 Sep 2022 02:24:20 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 4CDDF60B6A; Sat, 24 Sep 2022 09:24:20 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8E0A9C43470; Sat, 24 Sep 2022 09:24:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1664011459; bh=DVEFPqU3wBfERUZGu5+AFcIyKGtbL9TKbE9pFcNWQMA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Zeo10YzhHgfRlvW8OOFKZ0mQ63AdfWV2/FIvJ2XjfQCW6bL/ZIsuNU9p0hYyJsP9R 1bpIMO2F0TvgDU8Syq+gvI45BW73JKRqxWHCegiVChijWtrz4pQ0JhRI2VVn3BddAW RmKoHDs8DfR+P+yuYPoMHrbXYzycoBC6ox9jwRBamRnHUkoOUtMqZhfKu9y9sBopIo Fno1RJJCpiaG+zoE+0FIagGPDPzr5jt6hfa7wgpjpmAv9cBtpeUww/oak66/7KXdez 5Khog4/8leAWSpeiw6gmveEhlQwyhTF0X0tZM9QpduNHnuDdo/FOROi3Wxd2qDUVsT Qy/Wcq/FjoQaw== Received: by pali.im (Postfix) id D0D4A1113; Sat, 24 Sep 2022 11:24:16 +0200 (CEST) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Sergio Paracuellos , Matthias Brugger Cc: linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH 1/3] PCI: Add standard PCI Config Address macros Date: Sat, 24 Sep 2022 11:24:02 +0200 Message-Id: <20220924092404.31776-2-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220924092404.31776-1-pali@kernel.org> References: <20220924092404.31776-1-pali@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Lot of PCI and PCIe controllers are using standard Config Address for PCI Configuration Mechanism #1 (as defined in PCI Local Bus Specification) or its extended version. So introduce new macros PCI_CONF1_ADDRESS() and PCI_CONF1_EXT_ADDRESS() in include file drivers/pci/pci.h which can be suitable for PCI and PCIe controllers which uses this type of access to PCI config space. Signed-off-by: Pali Rohár Acked-by: Bjorn Helgaas --- drivers/pci/pci.h | 45 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 785f31086313..88bd77107103 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -774,4 +774,49 @@ static inline pci_power_t mid_pci_get_power_state(struct pci_dev *pdev) } #endif +/* + * Config Address for PCI Configuration Mechanism #1 + * + * See PCI Local Bus Specification, Revision 3.0, + * Section 3.2.2.3.2, Figure 3-2, p. 50. + */ + +#define PCI_CONF1_BUS_SHIFT 16 /* Bus number */ +#define PCI_CONF1_DEV_SHIFT 11 /* Device number */ +#define PCI_CONF1_FUNC_SHIFT 8 /* Function number */ + +#define PCI_CONF1_BUS_MASK 0xff +#define PCI_CONF1_DEV_MASK 0x1f +#define PCI_CONF1_FUNC_MASK 0x7 +#define PCI_CONF1_REG_MASK 0xfc /* Limit aligned offset to a maximum of 256B */ + +#define PCI_CONF1_ENABLE BIT(31) +#define PCI_CONF1_BUS(x) (((x) & PCI_CONF1_BUS_MASK) << PCI_CONF1_BUS_SHIFT) +#define PCI_CONF1_DEV(x) (((x) & PCI_CONF1_DEV_MASK) << PCI_CONF1_DEV_SHIFT) +#define PCI_CONF1_FUNC(x) (((x) & PCI_CONF1_FUNC_MASK) << PCI_CONF1_FUNC_SHIFT) +#define PCI_CONF1_REG(x) ((x) & PCI_CONF1_REG_MASK) + +#define PCI_CONF1_ADDRESS(bus, dev, func, reg) \ + (PCI_CONF1_ENABLE | \ + PCI_CONF1_BUS(bus) | \ + PCI_CONF1_DEV(dev) | \ + PCI_CONF1_FUNC(func) | \ + PCI_CONF1_REG(reg)) + +/* + * Extension of PCI Config Address for accessing extended PCIe registers + * + * No standardized specification, but used on lot of non-ECAM-compliant ARM SoCs + * or on AMD Barcelona and new CPUs. Reserved bits [27:24] of PCI Config Address + * are used for specifying additional 4 high bits of PCI Express register. + */ + +#define PCI_CONF1_EXT_REG_SHIFT 16 +#define PCI_CONF1_EXT_REG_MASK 0xf00 +#define PCI_CONF1_EXT_REG(x) (((x) & PCI_CONF1_EXT_REG_MASK) << PCI_CONF1_EXT_REG_SHIFT) + +#define PCI_CONF1_EXT_ADDRESS(bus, dev, func, reg) \ + (PCI_CONF1_ADDRESS(bus, dev, func, reg) | \ + PCI_CONF1_EXT_REG(reg)) + #endif /* DRIVERS_PCI_H */ From patchwork Sat Sep 24 09:24:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 12987536 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 59553C32771 for ; Sat, 24 Sep 2022 09:24:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233510AbiIXJY0 (ORCPT ); Sat, 24 Sep 2022 05:24:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46666 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233492AbiIXJYY (ORCPT ); Sat, 24 Sep 2022 05:24:24 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 82AB2139BE8; Sat, 24 Sep 2022 02:24:23 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id CC02CB80B3C; Sat, 24 Sep 2022 09:24:21 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 58685C433C1; Sat, 24 Sep 2022 09:24:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1664011460; bh=sHPgm7Bf+Utqg2hFFou3EDhEcuSIIzXwSlAILmNgHAU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=TIuYjPB/+Rt6i6qzAkLmJ9X2HVFB/WRMRrv+JBkqDg8om4pdGFwvK0uUG8Y4JHst+ O8wSAC8d6qFurbDaseuyKqnoX02Smx9RULumCegYwjiIaaNand/QVwdxaz3JHW/3tq EsGcq14MwISCbCIhbuYgYMArXUq8qqAu+MO0eqxd6Njtlhc3jY78NDh3PB/rRucA7H 54exG+Q29BfXcQMYf9DUBUdUs6d4kxeco2xvV9LEch6GNtMRIeKQHXCOnmR8Y2SMBz ftYhKyateVlYVtKNT7aJL9j4EAx7Gdj8aeTpa+WUjFk8LWE6qyXQErW4JupafxOCaM Wvrl72I4sJ7nA== Received: by pali.im (Postfix) id C5F871231; Sat, 24 Sep 2022 11:24:17 +0200 (CEST) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Sergio Paracuellos , Matthias Brugger Cc: linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH 2/3] PCI: ftpci100: Use PCI_CONF1_ADDRESS() macro Date: Sat, 24 Sep 2022 11:24:03 +0200 Message-Id: <20220924092404.31776-3-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220924092404.31776-1-pali@kernel.org> References: <20220924092404.31776-1-pali@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Simplify pci-ftpci100.c driver code and use new PCI_CONF1_ADDRESS() macro for accessing PCI config space. Signed-off-by: Pali Rohár --- drivers/pci/controller/pci-ftpci100.c | 21 ++++----------------- 1 file changed, 4 insertions(+), 17 deletions(-) diff --git a/drivers/pci/controller/pci-ftpci100.c b/drivers/pci/controller/pci-ftpci100.c index 88980a44461d..0cfd9d5a497c 100644 --- a/drivers/pci/controller/pci-ftpci100.c +++ b/drivers/pci/controller/pci-ftpci100.c @@ -103,13 +103,6 @@ #define FARADAY_PCI_DMA_MEM2_BASE 0x00000000 #define FARADAY_PCI_DMA_MEM3_BASE 0x00000000 -/* Defines for PCI configuration command register */ -#define PCI_CONF_ENABLE BIT(31) -#define PCI_CONF_WHERE(r) ((r) & 0xFC) -#define PCI_CONF_BUS(b) (((b) & 0xFF) << 16) -#define PCI_CONF_DEVICE(d) (((d) & 0x1F) << 11) -#define PCI_CONF_FUNCTION(f) (((f) & 0x07) << 8) - /** * struct faraday_pci_variant - encodes IP block differences * @cascaded_irq: this host has cascaded IRQs from an interrupt controller @@ -190,11 +183,8 @@ static int faraday_raw_pci_read_config(struct faraday_pci *p, int bus_number, unsigned int fn, int config, int size, u32 *value) { - writel(PCI_CONF_BUS(bus_number) | - PCI_CONF_DEVICE(PCI_SLOT(fn)) | - PCI_CONF_FUNCTION(PCI_FUNC(fn)) | - PCI_CONF_WHERE(config) | - PCI_CONF_ENABLE, + writel(PCI_CONF1_ADDRESS(bus_number, PCI_SLOT(fn), + PCI_FUNC(fn), config), p->base + FTPCI_CONFIG); *value = readl(p->base + FTPCI_DATA); @@ -225,11 +215,8 @@ static int faraday_raw_pci_write_config(struct faraday_pci *p, int bus_number, { int ret = PCIBIOS_SUCCESSFUL; - writel(PCI_CONF_BUS(bus_number) | - PCI_CONF_DEVICE(PCI_SLOT(fn)) | - PCI_CONF_FUNCTION(PCI_FUNC(fn)) | - PCI_CONF_WHERE(config) | - PCI_CONF_ENABLE, + writel(PCI_CONF1_ADDRESS(bus_number, PCI_SLOT(fn), + PCI_FUNC(fn), config), p->base + FTPCI_CONFIG); switch (size) { From patchwork Sat Sep 24 09:24:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 12987535 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 081E3C32771 for ; Sat, 24 Sep 2022 09:24:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232388AbiIXJYY (ORCPT ); Sat, 24 Sep 2022 05:24:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46612 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233484AbiIXJYX (ORCPT ); Sat, 24 Sep 2022 05:24:23 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8854D13943C; Sat, 24 Sep 2022 02:24:22 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 24BFD60DED; Sat, 24 Sep 2022 09:24:22 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 55F4EC433D7; Sat, 24 Sep 2022 09:24:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1664011461; bh=0Fp5N+iuPZzD55S6xZwszO0M3jKrv7PY7Rm1eU+7P/k=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SbM0PyTK/gMt2I+LcMA2scxDkGfXA2p1sqxnfd+fvtl4n6LErlBWm9qYvjh75kAUg jaL574qzcen/zHqZrC8pOlRltL/0mhRKSRNIgjRMGlEVx6xAT/IsKthij5P/515W+k ySlLDPVvU4Eg5ZnGLGzcJQoxiRk4GZkXT8xRpI0iYOadAY/lX3BlDrqPTja/yJqoJd m1JM9tB4vwan4EQ9PJVzNy6ob0RJQgT2E/7dNHmpVI5bWRoXE1ZcvZu046iAoObx8/ 9NbBCYmmkbzWCZxv22dqYG9r4LkNUx4nzWSyL/t030ehuH/dIFaIMisvRiHLsC6Sot MhltOqndg/U+A== Received: by pali.im (Postfix) id CDB93127C; Sat, 24 Sep 2022 11:24:18 +0200 (CEST) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Sergio Paracuellos , Matthias Brugger Cc: linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH 3/3] PCI: mt7621: Use PCI_CONF1_EXT_ADDRESS() macro Date: Sat, 24 Sep 2022 11:24:04 +0200 Message-Id: <20220924092404.31776-4-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220924092404.31776-1-pali@kernel.org> References: <20220924092404.31776-1-pali@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Simplify pcie-mt7621.c driver code and use new PCI_CONF1_EXT_ADDRESS() macro for accessing PCIe config space. Signed-off-by: Pali Rohár Acked-by: Sergio Paracuellos --- drivers/pci/controller/pcie-mt7621.c | 17 ++++++----------- 1 file changed, 6 insertions(+), 11 deletions(-) diff --git a/drivers/pci/controller/pcie-mt7621.c b/drivers/pci/controller/pcie-mt7621.c index 33eb37a2225c..4bd1abf26008 100644 --- a/drivers/pci/controller/pcie-mt7621.c +++ b/drivers/pci/controller/pcie-mt7621.c @@ -30,6 +30,8 @@ #include #include +#include "../pci.h" + /* MediaTek-specific configuration registers */ #define PCIE_FTS_NUM 0x70c #define PCIE_FTS_NUM_MASK GENMASK(15, 8) @@ -120,19 +122,12 @@ static inline void pcie_port_write(struct mt7621_pcie_port *port, writel_relaxed(val, port->base + reg); } -static inline u32 mt7621_pcie_get_cfgaddr(unsigned int bus, unsigned int slot, - unsigned int func, unsigned int where) -{ - return (((where & 0xf00) >> 8) << 24) | (bus << 16) | (slot << 11) | - (func << 8) | (where & 0xfc) | 0x80000000; -} - static void __iomem *mt7621_pcie_map_bus(struct pci_bus *bus, unsigned int devfn, int where) { struct mt7621_pcie *pcie = bus->sysdata; - u32 address = mt7621_pcie_get_cfgaddr(bus->number, PCI_SLOT(devfn), - PCI_FUNC(devfn), where); + u32 address = PCI_CONF1_EXT_ADDRESS(bus->number, PCI_SLOT(devfn), + PCI_FUNC(devfn), where); writel_relaxed(address, pcie->base + RALINK_PCI_CONFIG_ADDR); @@ -147,7 +142,7 @@ static struct pci_ops mt7621_pcie_ops = { static u32 read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg) { - u32 address = mt7621_pcie_get_cfgaddr(0, dev, 0, reg); + u32 address = PCI_CONF1_EXT_ADDRESS(0, dev, 0, reg); pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR); return pcie_read(pcie, RALINK_PCI_CONFIG_DATA); @@ -156,7 +151,7 @@ static u32 read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg) static void write_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg, u32 val) { - u32 address = mt7621_pcie_get_cfgaddr(0, dev, 0, reg); + u32 address = PCI_CONF1_EXT_ADDRESS(0, dev, 0, reg); pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR); pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA);