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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Sep 2022 11:10:42.7188 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3c2d9f9a-9b36-44b1-ac27-08da9fafc0c7 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT097.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6456 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add macro defining Responder capable bit in Precision Time Measurement capability register. Signed-off-by: Vidya Sagar Reviewed-by: Jingoo Han Acked-by: Bjorn Helgaas --- V2: * Added "Reviewed-by: Jingoo Han " include/uapi/linux/pci_regs.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 57b8e2ffb1dd..1c3591c8e09e 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -1058,6 +1058,7 @@ /* Precision Time Measurement */ #define PCI_PTM_CAP 0x04 /* PTM Capability */ #define PCI_PTM_CAP_REQ 0x00000001 /* Requester capable */ +#define PCI_PTM_CAP_RES 0x00000002 /* Responder capable */ #define PCI_PTM_CAP_ROOT 0x00000004 /* Root capable */ #define PCI_PTM_GRANULARITY_MASK 0x0000FF00 /* Clock granularity */ #define PCI_PTM_CTRL 0x08 /* PTM Control */ From patchwork Mon Sep 26 11:10:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 12988664 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 87E6BC32771 for ; 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Mon, 26 Sep 2022 04:10:31 -0700 From: Vidya Sagar To: , , , , , CC: , , , , , Subject: [PATCH V2 2/2] PCI: designware-ep: Disable PTM capabilities for EP mode Date: Mon, 26 Sep 2022 16:40:17 +0530 Message-ID: <20220926111017.12655-3-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220926111017.12655-1-vidyas@nvidia.com> References: <20220926111017.12655-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT030:EE_|IA1PR12MB6283:EE_ X-MS-Office365-Filtering-Correlation-Id: abe554fb-581a-49ee-fdaa-08da9fafc389 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Wh/+RFBfyz9HqEJEpSiGVQVWOTkw2XNka/ftf5v0r0o+2hk2SIRBIv5YAC+06h+q7E2uayy6WP9lxpPJwdd+EBBlqU5io0OEhw5ytIr3CTw2zT9p8HS+uaqHhVV5tI0b2gX21hDVg7rUpU7ftoBOOuH6CYHwxMOdo//Ej9DHOBI2IYntDclvnM6Tk5RF04ZrwH3k/h5nA6A3Zq+oH+VEyar5m6cMa/spgnsuAbOsLFXN/EAUc25KGKEb7QvnIUadMF7IFx1deAWdHpYcc/gQyp0lun3vrk86N3O8LJEvbUVl3GGDMD5YI2tDmEyMwXUq2lUh6VvhDoVTBe7aN3nI3wrPUcjl+GcsTiy6j8lHOZkc2brua4QLENLANswQhuMJ27T9RHJtb6kQtgyAGYxaDWW/PXfeQyhyOl2A3hA5DyXBNhep8WHEbjHivc2+eBQJU91RWCxRu4tLAicLfEN1nBHoxtQXtu7+lCEd+lpaWh7Y/GSDk7TWBo6NDE33Ny4Ay20ccUl2sYKKZLDysw1cca9BKo6MLIkjcG4Pu/dfiNnUaLdXb+RGCBmjR/JJ20+8txz7E2pv+X5r7vaGzya52VRQuwq+B9hM/srs2mrdN6RbUzdIVQQvaWbBkMOBPy0GY7sIVLGFppaSNBluwegrqYvGP7oxShyjmU5Bq1VWAMIXM7v6lPPkT2Doj//QFIXv1KpKtpEZp6wOQcamhK3xloObnZuhz5Hq8bv/6M+1IDEBK/fHQ3K0Lwcb5SnaUQK166YAa10LZVxDasi8utdBcQ== X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230022)(4636009)(39860400002)(136003)(346002)(376002)(396003)(451199015)(46966006)(36840700001)(40470700004)(40460700003)(8676002)(41300700001)(82740400003)(2906002)(6666004)(478600001)(7696005)(36860700001)(36756003)(26005)(5660300002)(336012)(2616005)(8936002)(186003)(1076003)(316002)(47076005)(356005)(426003)(7636003)(86362001)(82310400005)(70206006)(70586007)(110136005)(4326008)(83380400001)(54906003)(40480700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Sep 2022 11:10:47.3946 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: abe554fb-581a-49ee-fdaa-08da9fafc389 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT030.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6283 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Dual mode DesignWare PCIe IP has PTM capability enabled (if supported) even in the EP mode. The PCIe compliance for the EP mode expects PTM capabilities (ROOT_CAPABLE, RES_CAPABLE, CLK_GRAN) be disabled. Hence disable PTM for the EP mode. Signed-off-by: Vidya Sagar Reviewed-by: Jingoo Han --- V2: * Addressed review comment from Jingoo Han * Added "Reviewed-by: Jingoo Han " .../pci/controller/dwc/pcie-designware-ep.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 095fb0291ec9..b88b6597194a 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -638,6 +638,7 @@ static int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep) struct dw_pcie_ep_func *ep_func; struct device *dev = pci->dev; struct pci_epc *epc = ep->epc; + unsigned int ptm_cap_base; unsigned int offset; unsigned int nbars; u8 hdr_type; @@ -690,6 +691,7 @@ static int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep) } offset = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_REBAR); + ptm_cap_base = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_PTM); dw_pcie_dbi_ro_wr_en(pci); @@ -702,6 +704,22 @@ static int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep) dw_pcie_writel_dbi(pci, offset + PCI_REBAR_CAP, 0x0); } + /* + * PTM responder capability can be disabled only after disabling + * PTM root capability. + */ + if (ptm_cap_base) { + dw_pcie_dbi_ro_wr_en(pci); + reg = dw_pcie_readl_dbi(pci, ptm_cap_base + PCI_PTM_CAP); + reg &= ~PCI_PTM_CAP_ROOT; + dw_pcie_writel_dbi(pci, ptm_cap_base + PCI_PTM_CAP, reg); + + reg = dw_pcie_readl_dbi(pci, ptm_cap_base + PCI_PTM_CAP); + reg &= ~(PCI_PTM_CAP_RES | PCI_PTM_GRANULARITY_MASK); + dw_pcie_writel_dbi(pci, ptm_cap_base + PCI_PTM_CAP, reg); + dw_pcie_dbi_ro_wr_dis(pci); + } + dw_pcie_setup(pci); dw_pcie_dbi_ro_wr_dis(pci);