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This is a preparation for actually adding this as pll reference clock. Signed-off-by: Alexander Stein --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index c486d66056a9..adf8d85526b8 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -645,10 +645,12 @@ clk: clock-controller@30380000 { #clock-cells = <1>; clocks = <&ckil>, <&osc_25m>, <&osc_27m>, <&clk_ext1>, <&clk_ext2>, - <&clk_ext3>, <&clk_ext4>; + <&clk_ext3>, <&clk_ext4>, + <&hdmi_phy_27m>; clock-names = "ckil", "osc_25m", "osc_27m", "clk_ext1", "clk_ext2", - "clk_ext3", "clk_ext4"; + "clk_ext3", "clk_ext4", + "hdmi_phy_27m"; assigned-clocks = <&clk IMX8MQ_CLK_A53_SRC>, <&clk IMX8MQ_CLK_A53_CORE>, <&clk IMX8MQ_CLK_NOC>, From patchwork Tue Sep 27 14:06:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Stein X-Patchwork-Id: 12990663 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B2ED8C6FA82 for ; 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27 Sep 2022 16:06:43 +0200 Received: from steina-w.tq-net.de (unknown [10.123.49.11]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by vtuxmail01.tq-net.de (Postfix) with ESMTPSA id 51E61280072; Tue, 27 Sep 2022 16:06:43 +0200 (CEST) From: Alexander Stein To: Rob Herring , Krzysztof Kozlowski , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Abel Vesa , Michael Turquette , Stephen Boyd Cc: Alexander Stein , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH 2/2] clk: imx: imx8mq: Add hdmi phy 27m as proper hw clock Date: Tue, 27 Sep 2022 16:06:38 +0200 Message-Id: <20220927140638.2759111-2-alexander.stein@ew.tq-group.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220927140638.2759111-1-alexander.stein@ew.tq-group.com> References: <20220927140638.2759111-1-alexander.stein@ew.tq-group.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220927_070651_645332_1936F365 X-CRM114-Status: GOOD ( 15.52 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org So it can be referenced by IMX8MQ_CLK_HDMI_PHY_27MHZ in device tree files. Signed-off-by: Alexander Stein --- drivers/clk/imx/clk-imx8mq.c | 1 + include/dt-bindings/clock/imx8mq-clock.h | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c index 783f98b05441..7cecb964cf1f 100644 --- a/drivers/clk/imx/clk-imx8mq.c +++ b/drivers/clk/imx/clk-imx8mq.c @@ -305,6 +305,7 @@ static int imx8mq_clocks_probe(struct platform_device *pdev) hws[IMX8MQ_CLK_EXT2] = imx_obtain_fixed_clk_hw(np, "clk_ext2"); hws[IMX8MQ_CLK_EXT3] = imx_obtain_fixed_clk_hw(np, "clk_ext3"); hws[IMX8MQ_CLK_EXT4] = imx_obtain_fixed_clk_hw(np, "clk_ext4"); + hws[IMX8MQ_CLK_HDMI_PHY_27MHZ] = imx_obtain_fixed_clk_hw(np, "hdmi_phy_27m"); np = of_find_compatible_node(NULL, NULL, "fsl,imx8mq-anatop"); base = of_iomap(np, 0); diff --git a/include/dt-bindings/clock/imx8mq-clock.h b/include/dt-bindings/clock/imx8mq-clock.h index afa74d7ba100..6401cc836c31 100644 --- a/include/dt-bindings/clock/imx8mq-clock.h +++ b/include/dt-bindings/clock/imx8mq-clock.h @@ -425,7 +425,8 @@ #define IMX8MQ_CLK_MON_VIDEO_PLL2_DIV 300 #define IMX8MQ_CLK_MON_SEL 301 #define IMX8MQ_CLK_MON_CLK2_OUT 302 +#define IMX8MQ_CLK_HDMI_PHY_27MHZ 303 -#define IMX8MQ_CLK_END 303 +#define IMX8MQ_CLK_END 304 #endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */