From patchwork Tue Sep 27 14:23:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kristina Martsenko X-Patchwork-Id: 12990707 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 185CEC07E9D for ; Tue, 27 Sep 2022 14:25:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=WfO1pu4X1gGOe+rwT2gPqK2i1MmnAT9x6VRkm2FUPzc=; b=qUY9l3WZGa2nxF rCFLp93wcUlAr704fC4Kpdvckewl/hLIXZzYe9UHwz2zdXvxqzxNuhBhv9lhz/KqgxN1SjDgd9dpP QZuZouBc2QPzuum1lI/iE8h6Wfy2XT2gsjdHnWMy1YTuHTJkBmEBI96vcdCrH8rUYqMT+Cer2J104 FuMgN6YbSl1GuOg3OMAuL5mzYKUfW8Y1Tk68HKsDyxY6FbKmrGE8UiQuqh98Kehl5hWTyQrDKFr0j GtajvUvW+6xTFyqVSKXqwMlzXfOegmSMBLJTkL0EvBx2cwEmPUjj25NWyRlA4IczJxdRA/34hYlXi PM3zdfK6sxHb7t9CaIPw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1odBVL-00BD7n-Fl; Tue, 27 Sep 2022 14:24:11 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1odBVH-00BD5g-UI for linux-arm-kernel@lists.infradead.org; Tue, 27 Sep 2022 14:24:09 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 34A6D1063; Tue, 27 Sep 2022 07:24:11 -0700 (PDT) Received: from e126864.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B7A363F73B; Tue, 27 Sep 2022 07:24:03 -0700 (PDT) From: Kristina Martsenko To: linux-arm-kernel@lists.infradead.org Cc: Mark Rutland Subject: [boot-wrapper PATCH] aarch64: enable access to HCRX_EL2 Date: Tue, 27 Sep 2022 15:23:43 +0100 Message-Id: <20220927142343.1428008-1-kristina.martsenko@arm.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220927_072408_050051_4553D58E X-CRM114-Status: UNSURE ( 9.15 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Allow EL2 to access the HCRX_EL2 register which provides hypervisor controls similarly to HCR_EL2. Signed-off-by: Kristina Martsenko --- arch/aarch64/include/asm/cpu.h | 3 +++ arch/aarch64/init.c | 3 +++ 2 files changed, 6 insertions(+) base-commit: 6a0fc40035f9bb581054eb26fbac3c659cfa99b2 diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h index 69dfcd5..d063948 100644 --- a/arch/aarch64/include/asm/cpu.h +++ b/arch/aarch64/include/asm/cpu.h @@ -49,6 +49,7 @@ #define SCR_EL3_FGTEN BIT(27) #define SCR_EL3_ECVEN BIT(28) #define SCR_EL3_TME BIT(34) +#define SCR_EL3_HXEn BIT(38) #define SCR_EL3_EnTP2 BIT(41) #define HCR_EL2_RES1 BIT(1) @@ -70,6 +71,8 @@ #define ID_AA64MMFR0_EL1_FGT BITS(59, 56) #define ID_AA64MMFR0_EL1_ECV BITS(63, 60) +#define ID_AA64MMFR1_EL1_HCX BITS(43, 40) + #define ID_AA64PFR1_EL1_MTE BITS(11, 8) #define ID_AA64PFR1_EL1_SME BITS(27, 24) #define ID_AA64PFR0_EL1_SVE BITS(35, 32) diff --git a/arch/aarch64/init.c b/arch/aarch64/init.c index db73b58..471e234 100644 --- a/arch/aarch64/init.c +++ b/arch/aarch64/init.c @@ -61,6 +61,9 @@ void cpu_init_el3(void) if (mrs_field(ID_AA64MMFR0_EL1, ECV) >= 2) scr |= SCR_EL3_ECVEN; + if (mrs_field(ID_AA64MMFR1_EL1, HCX)) + scr |= SCR_EL3_HXEn; + if (mrs_field(ID_AA64PFR1_EL1, MTE) >= 2) scr |= SCR_EL3_ATA;