From patchwork Tue Sep 27 18:15:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chukun Pan X-Patchwork-Id: 12991083 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B4839C54EE9 for ; Tue, 27 Sep 2022 18:17:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=vM5GC+d7QvkZNDJ7N6Dbv/gHA/CvuHZaeHNiMiAtIMI=; b=oUzk+RDOYw+tHI DNOOFeTCejzf4pFAtTX69PRdycytB5zcPlYVrxbMNfEp5DeVBwQEGLhi/vcJw69WOABu4dXzYLcwq x10nQHHi2hgSEWQsEF8Hwh0+Lk0XDiJKLhphQPnCclGVUGP0SoT2BnLfFyG1clMnjIBQxn3EwIbca l9fZdO/HH8r//Kh0eDJw8LWcOqEhCuyymEfVzCmO2PpCS+T9IxxI7indiDlwSzIdltbokBxn8bQUF o02y51eiqzSPWO4prbRxN3HLZm1XXRH3lVASlpE3N5jYISD7l8gecw/za9CpzGQ9TZvlLiWmPhwcL AXChsVuA4ANoumRKlDOw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1odF7i-00C7sM-6t; Tue, 27 Sep 2022 18:16:02 +0000 Received: from mail-m121145.qiye.163.com ([115.236.121.145]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1odF7V-00C7pi-Is; Tue, 27 Sep 2022 18:15:52 +0000 Received: from amadeus-VLT-WX0.lan (unknown [218.85.118.195]) by mail-m121145.qiye.163.com (Hmail) with ESMTPA id 37D068000EC; Wed, 28 Sep 2022 02:15:38 +0800 (CST) From: Chukun Pan To: linux.amoon@gmail.com Cc: heiko@sntech.de, robh+dt@kernel.org, michael.riesch@wolfvision.net, krzysztof.kozlowski+dt@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Chukun Pan Subject: [PATCH 3/3] arm64: dts: rockchip: Add PCIe v3 nodes to rock-3a Date: Wed, 28 Sep 2022 02:15:31 +0800 Message-Id: <20220927181531.5546-2-amadeus@jmu.edu.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220927181531.5546-1-amadeus@jmu.edu.cn> References: <20220927181531.5546-1-amadeus@jmu.edu.cn> MIME-Version: 1.0 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWS1ZQUlXWQ8JGhUIEh9ZQVkaGkwYVh5PSkhOHktMSB0ZTlUTARMWGhIXJBQOD1 lXWRgSC1lBWUlKQ1VDTlVKSkNVSkJOWVdZFhoPEhUdFFlBWU9LSFVKSktISkNVSktLVUtZBg++ X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6Py46DDo5Pj0sDA4ePRMiPAhL TBwKCxJVSlVKTU1PSEtJTkhDQ0lKVTMWGhIXVRoWGh8eDgg7ERYOVR4fDlUYFUVZV1kSC1lBWUlK Q1VDTlVKSkNVSkJOWVdZCAFZQU9JTks3Bg++ X-HM-Tid: 0a8380295ec5b03akuuu37d068000ec X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220927_111550_043796_95C353E5 X-CRM114-Status: UNSURE ( 8.91 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add Nodes to Radxa ROCK3 Model A board to support PCIe v3. Also changed the vin-supply of vcc3v3_pcie regulator to ensure that pcie is probe properly. Signed-off-by: Chukun Pan --- .../boot/dts/rockchip/rk3568-rock-3a.dts | 52 ++++++++++++++++++- 1 file changed, 51 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts index 1b195355da2a..097cee13885d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts @@ -67,6 +67,38 @@ vcc12v_dcin: vcc12v-dcin-regulator { regulator-boot-on; }; + pcie30_avdd0v9: pcie30-avdd0v9-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc3v3_sys>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys>; + }; + + /* pi6c pcie clock generator */ + vcc3v3_pi6c_03: vcc3v3-pi6c-03-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pi6c03"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + /* actually fed by vcc5v0_sys, dependent on pi6c clock generator */ vcc3v3_pcie: vcc3v3-pcie-regulator { compatible = "regulator-fixed"; enable-active-high; @@ -76,7 +108,7 @@ vcc3v3_pcie: vcc3v3-pcie-regulator { regulator-name = "vcc3v3_pcie"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - vin-supply = <&vcc5v0_sys>; + vin-supply = <&vcc3v3_pi6c_03>; }; vcc3v3_sys: vcc3v3-sys-regulator { @@ -547,6 +579,20 @@ &pcie2x1 { status = "okay"; }; +&pcie30phy { + phy-supply = <&vcc3v3_pi6c_03>; + status = "okay"; +}; + +&pcie3x2 { + /* mPCIe slot */ + pinctrl-names = "default"; + pinctrl-0 = <&minipcie_reset_h>; + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + &pinctrl { cam { vcc_cam_en: vcc_cam_en { @@ -583,6 +629,10 @@ pcie_enable_h: pcie-enable-h { rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; }; + minipcie_reset_h: minipcie-reset-h { + rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + ngffpcie_reset_h: ngffpcie-reset-h { rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; };