From patchwork Wed Sep 28 14:59:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12992307 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3C98EC6FA90 for ; Wed, 28 Sep 2022 15:00:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234657AbiI1PA2 (ORCPT ); Wed, 28 Sep 2022 11:00:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38392 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234658AbiI1PAI (ORCPT ); Wed, 28 Sep 2022 11:00:08 -0400 Received: from mail-lj1-x231.google.com (mail-lj1-x231.google.com [IPv6:2a00:1450:4864:20::231]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 05DE12ED54 for ; Wed, 28 Sep 2022 08:00:02 -0700 (PDT) Received: by mail-lj1-x231.google.com with SMTP id j24so14643955lja.4 for ; Wed, 28 Sep 2022 08:00:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=qzCxOTmp+gxnMgVdAJunjjkZh8T2GclSG/MzKsGIiUY=; b=NIQb8EfBe92SnYRtXYZjYgO8aXOfamVx2hYlMg6azG7W5+C8LsZJNRbxSmyrhF47w9 kgpf+KO+5Jp7Ve6+VMgVYkGNCjYDfFqpSyTt/8R5a4O7f0jcFI0IMvEQvtrKLZjSUvL+ ziqRbFHB4++sG6ybw2a8pQY4EWEEyTHCaxJ4MZAQkOHfzEmytscTV//Flh8zc5RCWvb0 C2wYnuGzyFRaC5Xg4MLQa67fOfmxUzKr+9SA+/FdeVWN3pph5Khsq1fCYeqC0AinsgP2 cstQFHZfiaaeBIa9uIOeUGUQJjcyxnpihAyP1HeFuVet2cquF4dLFShI4r74MEB9HiEy ZRbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=qzCxOTmp+gxnMgVdAJunjjkZh8T2GclSG/MzKsGIiUY=; b=YASWXxSZhMBCKzils4Rs7hXtAfcH64RgpXPfxbBNK2wEwx87/8rQgN9pxwO0mIluqo SOtnxjlpewKNd6qkabt48bCfC8cgzSPSUrB7sNBwfOV9jh/PKzV7XLcLuBmNvhGTInKG HftlaxkA4aVW7/iplg5AlvHjkvMl+gX8joSQY2fojh3FoWUHzY5Oxtk6glOWnVabzVtR hZnYF2vUNX9iPX7fj+R9BM0nNBU7fXCz4C3Eq8zVpf2WT+4cJwF0oWkUpntQ0LAuFLMU iJ5eQ4msmTdz/tgaC/fuG134C0V7Z9vzy3WphEhSnnUejCj6l0Q90h52osudfaxg9TG/ kdOA== X-Gm-Message-State: ACrzQf3GXpBtIs/3OxAxQfK2fcbd3gXE+vYveLJ6YSbwPU2mGeIPdxOW Ptf96KURR+1XGFacIupO+2JBuQ== X-Google-Smtp-Source: AMsMyM5ruvrENEeGdlBxYOCN0yHTNa3cSP7FoEJE2ODTWDxMM7xcWr29/rJcssZ5L8edv984J8KOZw== X-Received: by 2002:a2e:a4db:0:b0:26c:784f:e513 with SMTP id p27-20020a2ea4db000000b0026c784fe513mr10896154ljm.310.1664377200547; Wed, 28 Sep 2022 08:00:00 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id be36-20020a056512252400b00492c017de43sm494996lfb.127.2022.09.28.07.59.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Sep 2022 08:00:00 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 01/11] dt-bindings: clock: split qcom,gcc-msm8974,-msm8226 to the separate file Date: Wed, 28 Sep 2022 17:59:48 +0300 Message-Id: <20220928145958.376288-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220928145958.376288-1-dmitry.baryshkov@linaro.org> References: <20220928145958.376288-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Move schema for the GCC on MSM8974 and MSM8226 platforms to a separate file to be able to define device-specific clock properties. Signed-off-by: Dmitry Baryshkov --- .../bindings/clock/qcom,gcc-msm8974.yaml | 65 +++++++++++++++++++ .../bindings/clock/qcom,gcc-other.yaml | 9 +-- 2 files changed, 66 insertions(+), 8 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-msm8974.yaml diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8974.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8974.yaml new file mode 100644 index 000000000000..72e8f54d0e0e --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8974.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8974.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller Binding for MSM8226 and + MSM8974, including Pro variants + +maintainers: + - Stephen Boyd + - Taniya Das + +description: | + Qualcomm global clock control module which supports the clocks, resets and + power domains on SDM630, SDM636 and SDM660 + + See also: + - dt-bindings/clock/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974) + - dt-bindings/reset/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974) + +$ref: qcom,gcc.yaml# + +properties: + compatible: + enum: + - qcom,gcc-msm8226 + - qcom,gcc-msm8974 + - qcom,gcc-msm8974pro + - qcom,gcc-msm8974pro-ac + + clocks: + items: + - description: XO source + - description: Sleep clock source + + clock-names: + items: + - const: xo + - const: sleep_clk + + power-domains: + maxItems: 1 + +required: + - compatible + +unevaluatedProperties: false + +examples: + # Example for GCC for SDM660: + - | + #include + clock-controller@fc400000 { + compatible = "qcom,gcc-msm8974"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + reg = <0x00100000 0x94000>; + + clock-names = "xo", "sleep_clk"; + clocks = <&xo_board>, + <&sleep_clk>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml index 35fc22a19000..0ec8ff215007 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml @@ -19,8 +19,6 @@ description: | - dt-bindings/clock/qcom,gcc-ipq6018.h - dt-bindings/reset/qcom,gcc-ipq6018.h - dt-bindings/clock/qcom,gcc-msm8953.h - - dt-bindings/clock/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974) - - dt-bindings/reset/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974) - dt-bindings/clock/qcom,gcc-mdm9607.h - dt-bindings/clock/qcom,gcc-mdm9615.h - dt-bindings/reset/qcom,gcc-mdm9615.h @@ -34,11 +32,7 @@ properties: - qcom,gcc-ipq4019 - qcom,gcc-ipq6018 - qcom,gcc-mdm9607 - - qcom,gcc-msm8226 - qcom,gcc-msm8953 - - qcom,gcc-msm8974 - - qcom,gcc-msm8974pro - - qcom,gcc-msm8974pro-ac - qcom,gcc-mdm9615 required: @@ -47,10 +41,9 @@ required: unevaluatedProperties: false examples: - # Example for GCC for MSM8974: - | clock-controller@900000 { - compatible = "qcom,gcc-msm8974"; + compatible = "qcom,gcc-mdm9607"; reg = <0x900000 0x4000>; #clock-cells = <1>; #reset-cells = <1>; From patchwork Wed Sep 28 14:59:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12992309 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 44021C04A95 for ; Wed, 28 Sep 2022 15:00:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234692AbiI1PAc (ORCPT ); Wed, 28 Sep 2022 11:00:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37388 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234665AbiI1PAK (ORCPT ); Wed, 28 Sep 2022 11:00:10 -0400 Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AEA752ED77 for ; Wed, 28 Sep 2022 08:00:03 -0700 (PDT) Received: by mail-lf1-x12c.google.com with SMTP id a2so20772298lfb.6 for ; Wed, 28 Sep 2022 08:00:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=qM++dOOdxNq2arb6uMckrS2brFOjaJGV3RM2kNir3B8=; b=kO4OdXiaoIFCxO3qD8o2DHgPuB6DOnejXQhxA0lKvO4OTLdTS9lpVMnhl8qU9FUbrK q3ofJjqcy+1+F8stypHzRnFvrzJn6YDjlgQ2jpD/+UuINqPqYAJUkvVbXhP63u26z81f Gi1Uh3yh7DOlVz88Mb58kbeCjCYqF6hCoeH5o8tPosPW2qg2KMHgvpIuOyeLQnOjA0gX rU4cHTOCi8+7gtT7s74cWb1A7mBah+JMW82Aeb7SCoHd0Wu1sSlg6Wf9XflMeq0oKbW5 yuV/UXFGuTVak7p6h+JJoJVmagTtFG20s8lUJE/j+t+IXxhJbGMDxYfxy01fdXtr0BwH z5cQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=qM++dOOdxNq2arb6uMckrS2brFOjaJGV3RM2kNir3B8=; b=0kXeL2t30HcEjrbhfXVbleapDabnF6IdcB8lrEPbf1v0J1Y6c5RnJTlswPoSZWEMdA ul2EwOJm+xHmSvUqjLnZEeDYb/nR8mg3CMCdEDXXGcoXWbmjm4v5kN2dnAzdpiRcdSfk bhZ7CATR59lQqfmDc+mk5GezpI8otpua7rGPwl3uEu4+28e/+he9t3Ym6fA0NpewGpzW cYROR2zMrpgHLjjrs4aVyUzCqe8UuVRtPZRbBgOTIgeRIUFbxcnHeHhrJ6Zqg4MGVW1+ xrFReFWbhLpfAcw+t0r78PX59eDRXxPI4pBvN9SyfnC4NsgeOZXf/MpeLcFZrB3GHa0K jhLg== X-Gm-Message-State: ACrzQf0tAT/m++/k7dNAp8E7rFCZAU14E5z/5UdGmfjkK7x/yMxCfxQa GJlIg1VC7brvi+QYY5wscDI1uA== X-Google-Smtp-Source: AMsMyM5dvqccT2NsgQuQ02tsXZBfzXh7YPjCAI+YQBt0m87zrJfxxKh4u4SnBtrkt2BRBlPDpDkrBg== X-Received: by 2002:a05:6512:cd:b0:49f:ba50:ec6 with SMTP id c13-20020a05651200cd00b0049fba500ec6mr12861483lfp.654.1664377201324; Wed, 28 Sep 2022 08:00:01 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id be36-20020a056512252400b00492c017de43sm494996lfb.127.2022.09.28.08.00.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Sep 2022 08:00:00 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 02/11] dt-bindings: clocks: qcom,mmcc: define clocks/clock-names for MSM8974 Date: Wed, 28 Sep 2022 17:59:49 +0300 Message-Id: <20220928145958.376288-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220928145958.376288-1-dmitry.baryshkov@linaro.org> References: <20220928145958.376288-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Define clock/clock-names properties of the MMCC device node to be used on MSM8974 platform. Signed-off-by: Dmitry Baryshkov Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/clock/qcom,mmcc.yaml | 38 +++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,mmcc.yaml b/Documentation/devicetree/bindings/clock/qcom,mmcc.yaml index 03faab5b6a41..78473475c68d 100644 --- a/Documentation/devicetree/bindings/clock/qcom,mmcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,mmcc.yaml @@ -99,6 +99,44 @@ allOf: - const: dsi2pllbyte - const: hdmipll + - if: + properties: + compatible: + contains: + enum: + - qcom,mmcc-msm8974 + then: + properties: + clocks: + items: + - description: Board XO source + - description: MMSS GPLL0 voted clock + - description: GPLL0 voted clock + - description: GPLL1 voted clock + - description: GFX3D clock source + - description: DSI phy instance 0 dsi clock + - description: DSI phy instance 0 byte clock + - description: DSI phy instance 1 dsi clock + - description: DSI phy instance 1 byte clock + - description: HDMI phy PLL clock + - description: eDP phy PLL link clock + - description: eDP phy PLL vco clock + + clock-names: + items: + - const: xo + - const: mmss_gpll0_vote + - const: gpll0_vote + - const: gpll1_vote + - const: gfx3d_clk_src + - const: dsi0pll + - const: dsi0pllbyte + - const: dsi1pll + - const: dsi1pllbyte + - const: hdmipll + - const: edp_link_clk + - const: edp_vco_div + - if: properties: compatible: From patchwork Wed Sep 28 14:59:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12992308 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1812BC6FA92 for ; Wed, 28 Sep 2022 15:00:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234592AbiI1PAa (ORCPT ); Wed, 28 Sep 2022 11:00:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37392 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234662AbiI1PAJ (ORCPT ); Wed, 28 Sep 2022 11:00:09 -0400 Received: from mail-lj1-x22c.google.com (mail-lj1-x22c.google.com [IPv6:2a00:1450:4864:20::22c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6095D11145 for ; Wed, 28 Sep 2022 08:00:04 -0700 (PDT) Received: by mail-lj1-x22c.google.com with SMTP id q17so14614050lji.11 for ; Wed, 28 Sep 2022 08:00:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=duCRDSBmxm816fhMp3Cybz4I6FiBs5NYrif88WAaOE4=; b=MDBbNWKq1TDiG6qy35DnNRzyEj5fAzf+LO4ssFFsctKY9i8CRCOqvb68kPSStjzLvv ODPhQRVsz7eP1QSKidShoA95gMKwU0jeOBfh5NlYkgQwty+7k2CCsbKOkG6Rvw85PY16 AEjttlYbIM3UCl907DHDIatCDOBNr3HeQfMjKrWFktzAz9ToboTFpBVLonaZGBqQu9ya JLghouIMCm/uPKiAs70pQTYx+P3b4/HLr2oGY0vd7WG0jzDdIgT8LtCSPyA3Wx5mo+rT SyREJ73gs7UUFhhHbOYTxPYvDADNTs2uW5YLIf5fhX4lnVgobmWXulPU3lWQmVoAEt2Y hn+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=duCRDSBmxm816fhMp3Cybz4I6FiBs5NYrif88WAaOE4=; b=YUi8sBkv6bAo+UEWA+5kvHsM0Lm+ftvOarJT4AfZVWPq1f6mShWPsz25FRU16UIgyw yXMX22zPy9UEAZdAJ+D0JMyzGss2Fa7Aj4jys+SNqjgPYl81zRb6m6U1wTElCzhB7emK 4fz2DXO1iUj+djG4sQqOWRZctHlBfBTSR+wlPqVEEENOnTlrkSKpJapczmHiMEeNqf/r 6MYyIcYn2fTGTXcwucBIruImG4vwVCtZI6Ix+6/YwQojAxkLdChnIe9YBeb8gtL5jS8Z mCuIPIhQ74d1tj2oViRt3owqf4HuhkL6OeHQBevzARaPjuBsXBf/1Zsb1/GKRQePuPJv FVTw== X-Gm-Message-State: ACrzQf2f1qSMtptiMJTlPthaaucfdJFWvOCC5V98sIZMjjpSBLNcz6F0 20JL52n9jzcWleiTL7LPaJwz3A== X-Google-Smtp-Source: AMsMyM4uoWYixifm1YnlYcAI0x1wzZLLrJD3NYc1hZrKVhIKorISF/I/g8nrZXucz3VZk1cPbcr7cQ== X-Received: by 2002:a05:651c:210e:b0:26c:7db3:17da with SMTP id a14-20020a05651c210e00b0026c7db317damr9781459ljq.220.1664377202113; Wed, 28 Sep 2022 08:00:02 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id be36-20020a056512252400b00492c017de43sm494996lfb.127.2022.09.28.08.00.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Sep 2022 08:00:01 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 03/11] clk: qcom: gcc-msm8974: use ARRAY_SIZE instead of specifying num_parents Date: Wed, 28 Sep 2022 17:59:50 +0300 Message-Id: <20220928145958.376288-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220928145958.376288-1-dmitry.baryshkov@linaro.org> References: <20220928145958.376288-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Use ARRAY_SIZE() instead of manually specifying num_parents. This makes adding/removing entries to/from parent_data easy and errorproof. Signed-off-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong --- drivers/clk/qcom/gcc-msm8974.c | 110 ++++++++++++++++----------------- 1 file changed, 55 insertions(+), 55 deletions(-) diff --git a/drivers/clk/qcom/gcc-msm8974.c b/drivers/clk/qcom/gcc-msm8974.c index bf305fa9e522..b847ce852ef8 100644 --- a/drivers/clk/qcom/gcc-msm8974.c +++ b/drivers/clk/qcom/gcc-msm8974.c @@ -88,7 +88,7 @@ static struct clk_rcg2 config_noc_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "config_noc_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -100,7 +100,7 @@ static struct clk_rcg2 periph_noc_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "periph_noc_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -112,7 +112,7 @@ static struct clk_rcg2 system_noc_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "system_noc_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -185,7 +185,7 @@ static struct clk_rcg2 usb30_master_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "usb30_master_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -205,7 +205,7 @@ static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup1_i2c_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -230,7 +230,7 @@ static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup1_spi_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -243,7 +243,7 @@ static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup2_i2c_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -257,7 +257,7 @@ static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup2_spi_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -270,7 +270,7 @@ static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup3_i2c_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -284,7 +284,7 @@ static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup3_spi_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -297,7 +297,7 @@ static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup4_i2c_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -311,7 +311,7 @@ static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup4_spi_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -324,7 +324,7 @@ static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup5_i2c_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -338,7 +338,7 @@ static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup5_spi_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -351,7 +351,7 @@ static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup6_i2c_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -365,7 +365,7 @@ static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup6_spi_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -398,7 +398,7 @@ static struct clk_rcg2 blsp1_uart1_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_uart1_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -412,7 +412,7 @@ static struct clk_rcg2 blsp1_uart2_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_uart2_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -426,7 +426,7 @@ static struct clk_rcg2 blsp1_uart3_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_uart3_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -440,7 +440,7 @@ static struct clk_rcg2 blsp1_uart4_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_uart4_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -454,7 +454,7 @@ static struct clk_rcg2 blsp1_uart5_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_uart5_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -468,7 +468,7 @@ static struct clk_rcg2 blsp1_uart6_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_uart6_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -481,7 +481,7 @@ static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup1_i2c_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -495,7 +495,7 @@ static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup1_spi_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -508,7 +508,7 @@ static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup2_i2c_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -522,7 +522,7 @@ static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup2_spi_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -535,7 +535,7 @@ static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup3_i2c_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -549,7 +549,7 @@ static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup3_spi_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -562,7 +562,7 @@ static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup4_i2c_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -576,7 +576,7 @@ static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup4_spi_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -589,7 +589,7 @@ static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup5_i2c_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -603,7 +603,7 @@ static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup5_spi_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -616,7 +616,7 @@ static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup6_i2c_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -630,7 +630,7 @@ static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup6_spi_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -644,7 +644,7 @@ static struct clk_rcg2 blsp2_uart1_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_uart1_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -658,7 +658,7 @@ static struct clk_rcg2 blsp2_uart2_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_uart2_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -672,7 +672,7 @@ static struct clk_rcg2 blsp2_uart3_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_uart3_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -686,7 +686,7 @@ static struct clk_rcg2 blsp2_uart4_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_uart4_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -700,7 +700,7 @@ static struct clk_rcg2 blsp2_uart5_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_uart5_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -714,7 +714,7 @@ static struct clk_rcg2 blsp2_uart6_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_uart6_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -741,7 +741,7 @@ static struct clk_rcg2 ce1_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "ce1_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -762,7 +762,7 @@ static struct clk_rcg2 ce2_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "ce2_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -794,7 +794,7 @@ static struct clk_rcg2 gp1_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gp1_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -808,7 +808,7 @@ static struct clk_rcg2 gp2_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gp2_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -822,7 +822,7 @@ static struct clk_rcg2 gp3_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gp3_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -840,7 +840,7 @@ static struct clk_rcg2 pdm2_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "pdm2_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -872,7 +872,7 @@ static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_pro[] = { static struct clk_init_data sdcc1_apps_clk_src_init = { .name = "sdcc1_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_floor_ops, }; @@ -894,7 +894,7 @@ static struct clk_rcg2 sdcc2_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "sdcc2_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_floor_ops, }, }; @@ -908,7 +908,7 @@ static struct clk_rcg2 sdcc3_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "sdcc3_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_floor_ops, }, }; @@ -922,7 +922,7 @@ static struct clk_rcg2 sdcc4_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "sdcc4_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_floor_ops, }, }; @@ -941,7 +941,7 @@ static struct clk_rcg2 tsif_ref_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "tsif_ref_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -959,7 +959,7 @@ static struct clk_rcg2 usb30_mock_utmi_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "usb30_mock_utmi_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -978,7 +978,7 @@ static struct clk_rcg2 usb_hs_system_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "usb_hs_system_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -1022,7 +1022,7 @@ static struct clk_rcg2 usb_hsic_io_cal_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "usb_hsic_io_cal_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 1, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -1041,7 +1041,7 @@ static struct clk_rcg2 usb_hsic_system_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "usb_hsic_system_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; From patchwork Wed Sep 28 14:59:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12992310 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A5A54C54EE9 for ; Wed, 28 Sep 2022 15:00:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234631AbiI1PAe (ORCPT ); Wed, 28 Sep 2022 11:00:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37426 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234611AbiI1PAL (ORCPT ); Wed, 28 Sep 2022 11:00:11 -0400 Received: from mail-lj1-x236.google.com (mail-lj1-x236.google.com [IPv6:2a00:1450:4864:20::236]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2E8A83207B for ; Wed, 28 Sep 2022 08:00:05 -0700 (PDT) Received: by mail-lj1-x236.google.com with SMTP id a14so14624370ljj.8 for ; Wed, 28 Sep 2022 08:00:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=rvkYwwXNz2RtbX8bEFgVafW/TqrLIdtASWYdL878aho=; b=OuC/T5e+XXTBa97Pq6H+Qtlxnn5uEKP9bv8POHCv4c8o8E41lXQEZYrMEG+br/Xt/5 jot9olxvi4OM9JaRVlRSzPiSBEi0RT2IHV9iGGlZGA8bSxqyM31ON+lPiFBch2e//U5R GunGB6g6XFDrM2pA/0wd3RBmkh4ltI/Odr1wZXwW8U6PDut7t36frzBniYTRv3HChRAA WmwRohD1jMIiuGWVpxwKMnStkw4X4sRTgd5kh0RHoGrEFAc8PBQJdiW+SymVaNFp5Wa7 c9nGUcfpZYKxOgw8fUW3UoRdInVA602NCRV+Jqv2oKwjLpxLqTWrJaOcNBNfktbeocVK 73jw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=rvkYwwXNz2RtbX8bEFgVafW/TqrLIdtASWYdL878aho=; b=JvXZWz4a3NFnw9BqXLvjMzZXJw1adLuN4dvQKcvbJGuKKvAXKafjp5GDsXXCk5xJWr qFmwfWOrpgMzqhhAkjhVYYlZqeLdbkVG09xyoLkaHAvfCnSqAYNoyCkgNQ4t+coPMsrQ UiHD1H0xf1WAvTe8teXTDdEmiM497Mst2/b7fkWzJ/DsIASHknr/Q/nik/Zp5hspEmGJ /C8mUQdW8OqVC3A7j5s7l6NTgGK1OreRsvOvKcAF2FfX7xINskip9IhhE7twPkCAe35V avxwckXHRV3tpFFlmwuwuJwdQvm3/Kg8yVyMtQAGAXXNXFR6YRV4hfMtZD2+LAvLGFCB TEWQ== X-Gm-Message-State: ACrzQf2+2sI0NLm8MIhKBtGy8rj/S1k8qNf0EazzJC7VmY50oNShM6hg tMM5IUR3tqSqtpUDDucAGtU3NQ== X-Google-Smtp-Source: AMsMyM6/4NNhkvMUVhUNP+gjiceRZ1wl8M3ZN8oDWDeHGxn/4wdDMcsGvZgukXDWZYcgaxxyhohW8Q== X-Received: by 2002:a2e:958f:0:b0:26c:fd2:80b4 with SMTP id w15-20020a2e958f000000b0026c0fd280b4mr11203358ljh.147.1664377202947; Wed, 28 Sep 2022 08:00:02 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id be36-20020a056512252400b00492c017de43sm494996lfb.127.2022.09.28.08.00.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Sep 2022 08:00:02 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 04/11] clk: qcom: gcc-msm8974: move clock parent tables down Date: Wed, 28 Sep 2022 17:59:51 +0300 Message-Id: <20220928145958.376288-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220928145958.376288-1-dmitry.baryshkov@linaro.org> References: <20220928145958.376288-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Move clock parent tables down, after the PLL declrataions, so that we can use pll hw clock fields in the next commit. Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/gcc-msm8974.c | 98 +++++++++++++++++----------------- 1 file changed, 49 insertions(+), 49 deletions(-) diff --git a/drivers/clk/qcom/gcc-msm8974.c b/drivers/clk/qcom/gcc-msm8974.c index b847ce852ef8..77f3497265a0 100644 --- a/drivers/clk/qcom/gcc-msm8974.c +++ b/drivers/clk/qcom/gcc-msm8974.c @@ -32,28 +32,6 @@ enum { P_GPLL4, }; -static const struct parent_map gcc_xo_gpll0_map[] = { - { P_XO, 0 }, - { P_GPLL0, 1 } -}; - -static const char * const gcc_xo_gpll0[] = { - "xo", - "gpll0_vote", -}; - -static const struct parent_map gcc_xo_gpll0_gpll4_map[] = { - { P_XO, 0 }, - { P_GPLL0, 1 }, - { P_GPLL4, 5 } -}; - -static const char * const gcc_xo_gpll0_gpll4[] = { - "xo", - "gpll0_vote", - "gpll4_vote", -}; - static struct clk_pll gpll0 = { .l_reg = 0x0004, .m_reg = 0x0008, @@ -81,6 +59,55 @@ static struct clk_regmap gpll0_vote = { }, }; +static struct clk_pll gpll4 = { + .l_reg = 0x1dc4, + .m_reg = 0x1dc8, + .n_reg = 0x1dcc, + .config_reg = 0x1dd4, + .mode_reg = 0x1dc0, + .status_reg = 0x1ddc, + .status_bit = 17, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpll4", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_pll_ops, + }, +}; + +static struct clk_regmap gpll4_vote = { + .enable_reg = 0x1480, + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "gpll4_vote", + .parent_names = (const char *[]){ "gpll4" }, + .num_parents = 1, + .ops = &clk_pll_vote_ops, + }, +}; + +static const struct parent_map gcc_xo_gpll0_map[] = { + { P_XO, 0 }, + { P_GPLL0, 1 } +}; + +static const char * const gcc_xo_gpll0[] = { + "xo", + "gpll0_vote", +}; + +static const struct parent_map gcc_xo_gpll0_gpll4_map[] = { + { P_XO, 0 }, + { P_GPLL0, 1 }, + { P_GPLL4, 5 } +}; + +static const char * const gcc_xo_gpll0_gpll4[] = { + "xo", + "gpll0_vote", + "gpll4_vote", +}; + static struct clk_rcg2 config_noc_clk_src = { .cmd_rcgr = 0x0150, .hid_width = 5, @@ -144,33 +171,6 @@ static struct clk_regmap gpll1_vote = { }, }; -static struct clk_pll gpll4 = { - .l_reg = 0x1dc4, - .m_reg = 0x1dc8, - .n_reg = 0x1dcc, - .config_reg = 0x1dd4, - .mode_reg = 0x1dc0, - .status_reg = 0x1ddc, - .status_bit = 17, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gpll4", - .parent_names = (const char *[]){ "xo" }, - .num_parents = 1, - .ops = &clk_pll_ops, - }, -}; - -static struct clk_regmap gpll4_vote = { - .enable_reg = 0x1480, - .enable_mask = BIT(4), - .hw.init = &(struct clk_init_data){ - .name = "gpll4_vote", - .parent_names = (const char *[]){ "gpll4" }, - .num_parents = 1, - .ops = &clk_pll_vote_ops, - }, -}; - static const struct freq_tbl ftbl_gcc_usb30_master_clk[] = { F(125000000, P_GPLL0, 1, 5, 24), { } From patchwork Wed Sep 28 14:59:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12992316 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ECB39C04A95 for ; Wed, 28 Sep 2022 15:00:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234679AbiI1PAs (ORCPT ); Wed, 28 Sep 2022 11:00:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38238 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234547AbiI1PAY (ORCPT ); Wed, 28 Sep 2022 11:00:24 -0400 Received: from mail-lj1-x234.google.com (mail-lj1-x234.google.com [IPv6:2a00:1450:4864:20::234]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 557FB367A8 for ; Wed, 28 Sep 2022 08:00:06 -0700 (PDT) Received: by mail-lj1-x234.google.com with SMTP id s10so14643516ljp.5 for ; Wed, 28 Sep 2022 08:00:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=6K48EBqA9FpQB5Fs2t5MueM5YJ3SemsoAocIXnXzoQE=; b=rsGSiePyiVxn7YSeqde3FNE8xM6vfn4U6ZU0ipUWUkg46L/Hlby+chuoJPNTXDzOdy /Wde7g5iMClDz/sfuRk2hiq1dZYPBilcNIqPJ7Rfou8naQCgUdLs0iaNm7YtvaHC9FdY ecrJQoH3+oIViqq/58pNj4oL3gKeDHZPxT/DnFs1rQ8ku0sZ2ItHtkdqbUGtN2osOBFJ iWw58J0ib2ysLg6MoJ50fgY+P/oO5ECsj/vsmQ5EXdJr4A+8Mgf0vU+HH3DP5DOV7EBa Rqh7rD8W6t4KB7wJZ7YAjsMjAygrHnz0twPQ9sjEGJJTK8f9wMC24fuLv1Z8UQM4Is/9 TyMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=6K48EBqA9FpQB5Fs2t5MueM5YJ3SemsoAocIXnXzoQE=; b=EQ7pWQBjYvQX5VMjrGnJKfb5qKeLlKjGcPMXuwZcECMHjM+Vb3bYX9LN7+jGX9sLgI rmmgOzU35NnmICZDgpDKaWiFbxsPF6y90xHZYHmcAKtpFTWE9DIYOZ4hw14mVFRTh0b2 7+9SdYoF+qinSGt54EZ60BfXXaA/G0ITGt/zAF+OQtsChim7EyTzZsLPhhbGKYXJH+Lx TXEoQT2LqlUYJolA2bbPXScwNnPZRxyf51TiNUGgCiou5eiF6gvU6UZJFOPxgEwMXgwM HaMMLCnDhiowFkFEWF5mXVNjQ5ZJYa3wuhvSQmqPA82yvfxWuBHFUXjlvrAw2DZyyCM1 Iekg== X-Gm-Message-State: ACrzQf2GWwePzlAOQA3MYmID98tLUjcU1PTH+qYALKlYzGJLBJb8utJ9 MSlnVbMrpmu74TVstSFFldBQ2Q== X-Google-Smtp-Source: AMsMyM4iWF1S99L0souJ7a0UB1eCXo2yuLBxuj2aYrGeorYzmLjYN94LuXnYMf81RVMRSRUR8qytNQ== X-Received: by 2002:a05:651c:1111:b0:26c:7178:ac4f with SMTP id e17-20020a05651c111100b0026c7178ac4fmr11141273ljo.461.1664377203767; Wed, 28 Sep 2022 08:00:03 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id be36-20020a056512252400b00492c017de43sm494996lfb.127.2022.09.28.08.00.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Sep 2022 08:00:03 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 05/11] clk: qcom: gcc-msm8974: use parent_hws/_data instead of parent_names Date: Wed, 28 Sep 2022 17:59:52 +0300 Message-Id: <20220928145958.376288-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220928145958.376288-1-dmitry.baryshkov@linaro.org> References: <20220928145958.376288-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Convert the clock driver to specify parent data rather than parent names, to actually bind using 'clock-names' specified in the DTS rather than global clock names. Use parent_hws where possible to refer parent clocks directly, skipping the lookup. Note, the system names for xo clocks were changed from "xo" to "xo_board" to follow the example of other platforms. Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/gcc-msm8974.c | 492 +++++++++++++++++---------------- 1 file changed, 253 insertions(+), 239 deletions(-) diff --git a/drivers/clk/qcom/gcc-msm8974.c b/drivers/clk/qcom/gcc-msm8974.c index 77f3497265a0..025cc9a20dbb 100644 --- a/drivers/clk/qcom/gcc-msm8974.c +++ b/drivers/clk/qcom/gcc-msm8974.c @@ -42,7 +42,9 @@ static struct clk_pll gpll0 = { .status_bit = 17, .clkr.hw.init = &(struct clk_init_data){ .name = "gpll0", - .parent_names = (const char *[]){ "xo" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "xo", .name = "xo_board", + }, .num_parents = 1, .ops = &clk_pll_ops, }, @@ -53,7 +55,9 @@ static struct clk_regmap gpll0_vote = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gpll0_vote", - .parent_names = (const char *[]){ "gpll0" }, + .parent_hws = (const struct clk_hw*[]){ + &gpll0.clkr.hw, + }, .num_parents = 1, .ops = &clk_pll_vote_ops, }, @@ -69,7 +73,9 @@ static struct clk_pll gpll4 = { .status_bit = 17, .clkr.hw.init = &(struct clk_init_data){ .name = "gpll4", - .parent_names = (const char *[]){ "xo" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "xo", .name = "xo_board", + }, .num_parents = 1, .ops = &clk_pll_ops, }, @@ -80,7 +86,9 @@ static struct clk_regmap gpll4_vote = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "gpll4_vote", - .parent_names = (const char *[]){ "gpll4" }, + .parent_hws = (const struct clk_hw*[]){ + &gpll4.clkr.hw, + }, .num_parents = 1, .ops = &clk_pll_vote_ops, }, @@ -91,9 +99,9 @@ static const struct parent_map gcc_xo_gpll0_map[] = { { P_GPLL0, 1 } }; -static const char * const gcc_xo_gpll0[] = { - "xo", - "gpll0_vote", +static const struct clk_parent_data gcc_xo_gpll0[] = { + { .fw_name = "xo", .name = "xo_board" }, + { .hw = &gpll0_vote.hw }, }; static const struct parent_map gcc_xo_gpll0_gpll4_map[] = { @@ -102,10 +110,10 @@ static const struct parent_map gcc_xo_gpll0_gpll4_map[] = { { P_GPLL4, 5 } }; -static const char * const gcc_xo_gpll0_gpll4[] = { - "xo", - "gpll0_vote", - "gpll4_vote", +static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = { + { .fw_name = "xo", .name = "xo_board" }, + { .hw = &gpll0_vote.hw }, + { .hw = &gpll4_vote.hw }, }; static struct clk_rcg2 config_noc_clk_src = { @@ -114,7 +122,7 @@ static struct clk_rcg2 config_noc_clk_src = { .parent_map = gcc_xo_gpll0_map, .clkr.hw.init = &(struct clk_init_data){ .name = "config_noc_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -126,7 +134,7 @@ static struct clk_rcg2 periph_noc_clk_src = { .parent_map = gcc_xo_gpll0_map, .clkr.hw.init = &(struct clk_init_data){ .name = "periph_noc_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -138,7 +146,7 @@ static struct clk_rcg2 system_noc_clk_src = { .parent_map = gcc_xo_gpll0_map, .clkr.hw.init = &(struct clk_init_data){ .name = "system_noc_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -154,7 +162,9 @@ static struct clk_pll gpll1 = { .status_bit = 17, .clkr.hw.init = &(struct clk_init_data){ .name = "gpll1", - .parent_names = (const char *[]){ "xo" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "xo", .name = "xo_board", + }, .num_parents = 1, .ops = &clk_pll_ops, }, @@ -165,7 +175,9 @@ static struct clk_regmap gpll1_vote = { .enable_mask = BIT(1), .hw.init = &(struct clk_init_data){ .name = "gpll1_vote", - .parent_names = (const char *[]){ "gpll1" }, + .parent_hws = (const struct clk_hw*[]){ + &gpll1.clkr.hw, + }, .num_parents = 1, .ops = &clk_pll_vote_ops, }, @@ -184,7 +196,7 @@ static struct clk_rcg2 usb30_master_clk_src = { .freq_tbl = ftbl_gcc_usb30_master_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "usb30_master_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -204,7 +216,7 @@ static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup1_i2c_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -229,7 +241,7 @@ static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup1_spi_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -242,7 +254,7 @@ static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup2_i2c_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -256,7 +268,7 @@ static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup2_spi_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -269,7 +281,7 @@ static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup3_i2c_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -283,7 +295,7 @@ static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup3_spi_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -296,7 +308,7 @@ static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = { .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup4_i2c_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -310,7 +322,7 @@ static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = { .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup4_spi_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -323,7 +335,7 @@ static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = { .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup5_i2c_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -337,7 +349,7 @@ static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = { .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup5_spi_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -350,7 +362,7 @@ static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = { .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup6_i2c_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -364,7 +376,7 @@ static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = { .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup6_spi_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -397,7 +409,7 @@ static struct clk_rcg2 blsp1_uart1_apps_clk_src = { .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_uart1_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -411,7 +423,7 @@ static struct clk_rcg2 blsp1_uart2_apps_clk_src = { .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_uart2_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -425,7 +437,7 @@ static struct clk_rcg2 blsp1_uart3_apps_clk_src = { .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_uart3_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -439,7 +451,7 @@ static struct clk_rcg2 blsp1_uart4_apps_clk_src = { .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_uart4_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -453,7 +465,7 @@ static struct clk_rcg2 blsp1_uart5_apps_clk_src = { .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_uart5_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -467,7 +479,7 @@ static struct clk_rcg2 blsp1_uart6_apps_clk_src = { .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_uart6_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -480,7 +492,7 @@ static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = { .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup1_i2c_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -494,7 +506,7 @@ static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = { .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup1_spi_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -507,7 +519,7 @@ static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = { .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup2_i2c_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -521,7 +533,7 @@ static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = { .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup2_spi_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -534,7 +546,7 @@ static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = { .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup3_i2c_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -548,7 +560,7 @@ static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = { .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup3_spi_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -561,7 +573,7 @@ static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = { .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup4_i2c_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -575,7 +587,7 @@ static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = { .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup4_spi_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -588,7 +600,7 @@ static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = { .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup5_i2c_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -602,7 +614,7 @@ static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = { .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup5_spi_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -615,7 +627,7 @@ static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = { .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup6_i2c_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -629,7 +641,7 @@ static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = { .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup6_spi_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -643,7 +655,7 @@ static struct clk_rcg2 blsp2_uart1_apps_clk_src = { .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_uart1_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -657,7 +669,7 @@ static struct clk_rcg2 blsp2_uart2_apps_clk_src = { .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_uart2_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -671,7 +683,7 @@ static struct clk_rcg2 blsp2_uart3_apps_clk_src = { .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_uart3_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -685,7 +697,7 @@ static struct clk_rcg2 blsp2_uart4_apps_clk_src = { .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_uart4_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -699,7 +711,7 @@ static struct clk_rcg2 blsp2_uart5_apps_clk_src = { .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_uart5_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -713,7 +725,7 @@ static struct clk_rcg2 blsp2_uart6_apps_clk_src = { .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_uart6_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -740,7 +752,7 @@ static struct clk_rcg2 ce1_clk_src = { .freq_tbl = ftbl_gcc_ce1_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "ce1_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -761,7 +773,7 @@ static struct clk_rcg2 ce2_clk_src = { .freq_tbl = ftbl_gcc_ce2_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "ce2_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -793,7 +805,7 @@ static struct clk_rcg2 gp1_clk_src = { .freq_tbl = ftbl_gcc_gp_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "gp1_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -807,7 +819,7 @@ static struct clk_rcg2 gp2_clk_src = { .freq_tbl = ftbl_gcc_gp_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "gp2_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -821,7 +833,7 @@ static struct clk_rcg2 gp3_clk_src = { .freq_tbl = ftbl_gcc_gp_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "gp3_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -839,7 +851,7 @@ static struct clk_rcg2 pdm2_clk_src = { .freq_tbl = ftbl_gcc_pdm2_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "pdm2_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -871,7 +883,7 @@ static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_pro[] = { static struct clk_init_data sdcc1_apps_clk_src_init = { .name = "sdcc1_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_floor_ops, }; @@ -893,7 +905,7 @@ static struct clk_rcg2 sdcc2_apps_clk_src = { .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "sdcc2_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_floor_ops, }, @@ -907,7 +919,7 @@ static struct clk_rcg2 sdcc3_apps_clk_src = { .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "sdcc3_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_floor_ops, }, @@ -921,7 +933,7 @@ static struct clk_rcg2 sdcc4_apps_clk_src = { .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "sdcc4_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_floor_ops, }, @@ -940,7 +952,7 @@ static struct clk_rcg2 tsif_ref_clk_src = { .freq_tbl = ftbl_gcc_tsif_ref_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "tsif_ref_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -958,7 +970,7 @@ static struct clk_rcg2 usb30_mock_utmi_clk_src = { .freq_tbl = ftbl_gcc_usb30_mock_utmi_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "usb30_mock_utmi_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -977,7 +989,7 @@ static struct clk_rcg2 usb_hs_system_clk_src = { .freq_tbl = ftbl_gcc_usb_hs_system_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "usb_hs_system_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -1000,9 +1012,9 @@ static struct clk_rcg2 usb_hsic_clk_src = { .freq_tbl = ftbl_gcc_usb_hsic_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "usb_hsic_clk_src", - .parent_names = (const char *[]){ - "xo", - "gpll1_vote", + .parent_data = (const struct clk_parent_data[]){ + { .fw_name = "xo", .name = "xo_board" }, + { .hw = &gpll1_vote.hw }, }, .num_parents = 2, .ops = &clk_rcg2_ops, @@ -1021,7 +1033,7 @@ static struct clk_rcg2 usb_hsic_io_cal_clk_src = { .freq_tbl = ftbl_gcc_usb_hsic_io_cal_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "usb_hsic_io_cal_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -1040,7 +1052,7 @@ static struct clk_rcg2 usb_hsic_system_clk_src = { .freq_tbl = ftbl_gcc_usb_hsic_system_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "usb_hsic_system_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -1051,8 +1063,8 @@ static struct clk_regmap gcc_mmss_gpll0_clk_src = { .enable_mask = BIT(26), .hw.init = &(struct clk_init_data){ .name = "mmss_gpll0_vote", - .parent_names = (const char *[]){ - "gpll0_vote", + .parent_hws = (const struct clk_hw*[]){ + &gpll0_vote.hw, }, .num_parents = 1, .ops = &clk_branch_simple_ops, @@ -1067,8 +1079,8 @@ static struct clk_branch gcc_bam_dma_ahb_clk = { .enable_mask = BIT(12), .hw.init = &(struct clk_init_data){ .name = "gcc_bam_dma_ahb_clk", - .parent_names = (const char *[]){ - "periph_noc_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &periph_noc_clk_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -1084,8 +1096,8 @@ static struct clk_branch gcc_blsp1_ahb_clk = { .enable_mask = BIT(17), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_ahb_clk", - .parent_names = (const char *[]){ - "periph_noc_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &periph_noc_clk_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -1100,8 +1112,8 @@ static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup1_i2c_apps_clk", - .parent_names = (const char *[]){ - "blsp1_qup1_i2c_apps_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &blsp1_qup1_i2c_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1117,8 +1129,8 @@ static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup1_spi_apps_clk", - .parent_names = (const char *[]){ - "blsp1_qup1_spi_apps_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &blsp1_qup1_spi_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1134,8 +1146,8 @@ static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup2_i2c_apps_clk", - .parent_names = (const char *[]){ - "blsp1_qup2_i2c_apps_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &blsp1_qup2_i2c_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1151,8 +1163,8 @@ static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup2_spi_apps_clk", - .parent_names = (const char *[]){ - "blsp1_qup2_spi_apps_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &blsp1_qup2_spi_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1168,8 +1180,8 @@ static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup3_i2c_apps_clk", - .parent_names = (const char *[]){ - "blsp1_qup3_i2c_apps_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &blsp1_qup3_i2c_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1185,8 +1197,8 @@ static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup3_spi_apps_clk", - .parent_names = (const char *[]){ - "blsp1_qup3_spi_apps_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &blsp1_qup3_spi_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1202,8 +1214,8 @@ static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup4_i2c_apps_clk", - .parent_names = (const char *[]){ - "blsp1_qup4_i2c_apps_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &blsp1_qup4_i2c_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1219,8 +1231,8 @@ static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup4_spi_apps_clk", - .parent_names = (const char *[]){ - "blsp1_qup4_spi_apps_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &blsp1_qup4_spi_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1236,8 +1248,8 @@ static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup5_i2c_apps_clk", - .parent_names = (const char *[]){ - "blsp1_qup5_i2c_apps_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &blsp1_qup5_i2c_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1253,8 +1265,8 @@ static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup5_spi_apps_clk", - .parent_names = (const char *[]){ - "blsp1_qup5_spi_apps_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &blsp1_qup5_spi_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1270,8 +1282,8 @@ static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup6_i2c_apps_clk", - .parent_names = (const char *[]){ - "blsp1_qup6_i2c_apps_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &blsp1_qup6_i2c_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1287,8 +1299,8 @@ static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup6_spi_apps_clk", - .parent_names = (const char *[]){ - "blsp1_qup6_spi_apps_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &blsp1_qup6_spi_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1304,8 +1316,8 @@ static struct clk_branch gcc_blsp1_uart1_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_uart1_apps_clk", - .parent_names = (const char *[]){ - "blsp1_uart1_apps_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &blsp1_uart1_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1321,8 +1333,8 @@ static struct clk_branch gcc_blsp1_uart2_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_uart2_apps_clk", - .parent_names = (const char *[]){ - "blsp1_uart2_apps_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &blsp1_uart2_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1338,8 +1350,8 @@ static struct clk_branch gcc_blsp1_uart3_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_uart3_apps_clk", - .parent_names = (const char *[]){ - "blsp1_uart3_apps_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &blsp1_uart3_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1355,8 +1367,8 @@ static struct clk_branch gcc_blsp1_uart4_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_uart4_apps_clk", - .parent_names = (const char *[]){ - "blsp1_uart4_apps_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &blsp1_uart4_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1372,8 +1384,8 @@ static struct clk_branch gcc_blsp1_uart5_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_uart5_apps_clk", - .parent_names = (const char *[]){ - "blsp1_uart5_apps_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &blsp1_uart5_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1389,8 +1401,8 @@ static struct clk_branch gcc_blsp1_uart6_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_uart6_apps_clk", - .parent_names = (const char *[]){ - "blsp1_uart6_apps_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &blsp1_uart6_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1407,8 +1419,8 @@ static struct clk_branch gcc_blsp2_ahb_clk = { .enable_mask = BIT(15), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_ahb_clk", - .parent_names = (const char *[]){ - "periph_noc_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &periph_noc_clk_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -1423,8 +1435,8 @@ static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_qup1_i2c_apps_clk", - .parent_names = (const char *[]){ - "blsp2_qup1_i2c_apps_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &blsp2_qup1_i2c_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1440,8 +1452,8 @@ static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_qup1_spi_apps_clk", - .parent_names = (const char *[]){ - "blsp2_qup1_spi_apps_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &blsp2_qup1_spi_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1457,8 +1469,8 @@ static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_qup2_i2c_apps_clk", - .parent_names = (const char *[]){ - "blsp2_qup2_i2c_apps_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &blsp2_qup2_i2c_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1474,8 +1486,8 @@ static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_qup2_spi_apps_clk", - .parent_names = (const char *[]){ - "blsp2_qup2_spi_apps_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &blsp2_qup2_spi_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1491,8 +1503,8 @@ static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_qup3_i2c_apps_clk", - .parent_names = (const char *[]){ - "blsp2_qup3_i2c_apps_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &blsp2_qup3_i2c_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1508,8 +1520,8 @@ static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_qup3_spi_apps_clk", - .parent_names = (const char *[]){ - "blsp2_qup3_spi_apps_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &blsp2_qup3_spi_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1525,8 +1537,8 @@ static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_qup4_i2c_apps_clk", - .parent_names = (const char *[]){ - "blsp2_qup4_i2c_apps_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &blsp2_qup4_i2c_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1542,8 +1554,8 @@ static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_qup4_spi_apps_clk", - .parent_names = (const char *[]){ - "blsp2_qup4_spi_apps_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &blsp2_qup4_spi_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1559,8 +1571,8 @@ static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_qup5_i2c_apps_clk", - .parent_names = (const char *[]){ - "blsp2_qup5_i2c_apps_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &blsp2_qup5_i2c_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1576,8 +1588,8 @@ static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_qup5_spi_apps_clk", - .parent_names = (const char *[]){ - "blsp2_qup5_spi_apps_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &blsp2_qup5_spi_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1593,8 +1605,8 @@ static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_qup6_i2c_apps_clk", - .parent_names = (const char *[]){ - "blsp2_qup6_i2c_apps_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &blsp2_qup6_i2c_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1610,8 +1622,8 @@ static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_qup6_spi_apps_clk", - .parent_names = (const char *[]){ - "blsp2_qup6_spi_apps_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &blsp2_qup6_spi_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1627,8 +1639,8 @@ static struct clk_branch gcc_blsp2_uart1_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_uart1_apps_clk", - .parent_names = (const char *[]){ - "blsp2_uart1_apps_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &blsp2_uart1_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1644,8 +1656,8 @@ static struct clk_branch gcc_blsp2_uart2_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_uart2_apps_clk", - .parent_names = (const char *[]){ - "blsp2_uart2_apps_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &blsp2_uart2_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1661,8 +1673,8 @@ static struct clk_branch gcc_blsp2_uart3_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_uart3_apps_clk", - .parent_names = (const char *[]){ - "blsp2_uart3_apps_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &blsp2_uart3_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1678,8 +1690,8 @@ static struct clk_branch gcc_blsp2_uart4_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_uart4_apps_clk", - .parent_names = (const char *[]){ - "blsp2_uart4_apps_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &blsp2_uart4_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1695,8 +1707,8 @@ static struct clk_branch gcc_blsp2_uart5_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_uart5_apps_clk", - .parent_names = (const char *[]){ - "blsp2_uart5_apps_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &blsp2_uart5_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1712,8 +1724,8 @@ static struct clk_branch gcc_blsp2_uart6_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_uart6_apps_clk", - .parent_names = (const char *[]){ - "blsp2_uart6_apps_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &blsp2_uart6_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1730,8 +1742,8 @@ static struct clk_branch gcc_boot_rom_ahb_clk = { .enable_mask = BIT(10), .hw.init = &(struct clk_init_data){ .name = "gcc_boot_rom_ahb_clk", - .parent_names = (const char *[]){ - "config_noc_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &config_noc_clk_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -1747,8 +1759,8 @@ static struct clk_branch gcc_ce1_ahb_clk = { .enable_mask = BIT(3), .hw.init = &(struct clk_init_data){ .name = "gcc_ce1_ahb_clk", - .parent_names = (const char *[]){ - "config_noc_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &config_noc_clk_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -1764,8 +1776,8 @@ static struct clk_branch gcc_ce1_axi_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "gcc_ce1_axi_clk", - .parent_names = (const char *[]){ - "system_noc_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &system_noc_clk_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -1781,8 +1793,8 @@ static struct clk_branch gcc_ce1_clk = { .enable_mask = BIT(5), .hw.init = &(struct clk_init_data){ .name = "gcc_ce1_clk", - .parent_names = (const char *[]){ - "ce1_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &ce1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1799,8 +1811,8 @@ static struct clk_branch gcc_ce2_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ce2_ahb_clk", - .parent_names = (const char *[]){ - "config_noc_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &config_noc_clk_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -1816,8 +1828,8 @@ static struct clk_branch gcc_ce2_axi_clk = { .enable_mask = BIT(1), .hw.init = &(struct clk_init_data){ .name = "gcc_ce2_axi_clk", - .parent_names = (const char *[]){ - "system_noc_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &system_noc_clk_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -1833,8 +1845,8 @@ static struct clk_branch gcc_ce2_clk = { .enable_mask = BIT(2), .hw.init = &(struct clk_init_data){ .name = "gcc_ce2_clk", - .parent_names = (const char *[]){ - "ce2_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &ce2_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1850,8 +1862,8 @@ static struct clk_branch gcc_gp1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_gp1_clk", - .parent_names = (const char *[]){ - "gp1_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &gp1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1867,8 +1879,8 @@ static struct clk_branch gcc_gp2_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_gp2_clk", - .parent_names = (const char *[]){ - "gp2_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &gp2_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1884,8 +1896,8 @@ static struct clk_branch gcc_gp3_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_gp3_clk", - .parent_names = (const char *[]){ - "gp3_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &gp3_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1901,8 +1913,8 @@ static struct clk_branch gcc_lpass_q6_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_lpass_q6_axi_clk", - .parent_names = (const char *[]){ - "system_noc_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &system_noc_clk_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -1917,8 +1929,8 @@ static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_mmss_noc_cfg_ahb_clk", - .parent_names = (const char *[]){ - "config_noc_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &config_noc_clk_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -1934,8 +1946,8 @@ static struct clk_branch gcc_ocmem_noc_cfg_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ocmem_noc_cfg_ahb_clk", - .parent_names = (const char *[]){ - "config_noc_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &config_noc_clk_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -1950,8 +1962,8 @@ static struct clk_branch gcc_mss_cfg_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_mss_cfg_ahb_clk", - .parent_names = (const char *[]){ - "config_noc_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &config_noc_clk_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -1966,8 +1978,8 @@ static struct clk_branch gcc_mss_q6_bimc_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_mss_q6_bimc_axi_clk", - .parent_names = (const char *[]){ - "system_noc_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &system_noc_clk_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -1982,8 +1994,8 @@ static struct clk_branch gcc_pdm2_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pdm2_clk", - .parent_names = (const char *[]){ - "pdm2_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &pdm2_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1999,8 +2011,8 @@ static struct clk_branch gcc_pdm_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pdm_ahb_clk", - .parent_names = (const char *[]){ - "periph_noc_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &periph_noc_clk_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -2015,7 +2027,9 @@ static struct clk_branch gcc_pdm_xo4_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pdm_xo4_clk", - .parent_names = (const char *[]){ "xo" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "xo", .name = "xo_board", + }, .num_parents = 1, .ops = &clk_branch2_ops, }, @@ -2030,8 +2044,8 @@ static struct clk_branch gcc_prng_ahb_clk = { .enable_mask = BIT(13), .hw.init = &(struct clk_init_data){ .name = "gcc_prng_ahb_clk", - .parent_names = (const char *[]){ - "periph_noc_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &periph_noc_clk_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -2046,8 +2060,8 @@ static struct clk_branch gcc_sdcc1_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sdcc1_ahb_clk", - .parent_names = (const char *[]){ - "periph_noc_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &periph_noc_clk_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -2062,8 +2076,8 @@ static struct clk_branch gcc_sdcc1_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sdcc1_apps_clk", - .parent_names = (const char *[]){ - "sdcc1_apps_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &sdcc1_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2079,8 +2093,8 @@ static struct clk_branch gcc_sdcc1_cdccal_ff_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sdcc1_cdccal_ff_clk", - .parent_names = (const char *[]){ - "xo" + .parent_data = (const struct clk_parent_data[]){ + { .fw_name = "xo", .name = "xo_board" } }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -2095,8 +2109,8 @@ static struct clk_branch gcc_sdcc1_cdccal_sleep_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sdcc1_cdccal_sleep_clk", - .parent_names = (const char *[]){ - "sleep_clk_src" + .parent_data = (const struct clk_parent_data[]){ + { .fw_name = "sleep_clk", .name = "sleep_clk_src" } }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -2111,8 +2125,8 @@ static struct clk_branch gcc_sdcc2_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sdcc2_ahb_clk", - .parent_names = (const char *[]){ - "periph_noc_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &periph_noc_clk_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -2127,8 +2141,8 @@ static struct clk_branch gcc_sdcc2_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sdcc2_apps_clk", - .parent_names = (const char *[]){ - "sdcc2_apps_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &sdcc2_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2144,8 +2158,8 @@ static struct clk_branch gcc_sdcc3_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sdcc3_ahb_clk", - .parent_names = (const char *[]){ - "periph_noc_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &periph_noc_clk_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -2160,8 +2174,8 @@ static struct clk_branch gcc_sdcc3_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sdcc3_apps_clk", - .parent_names = (const char *[]){ - "sdcc3_apps_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &sdcc3_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2177,8 +2191,8 @@ static struct clk_branch gcc_sdcc4_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sdcc4_ahb_clk", - .parent_names = (const char *[]){ - "periph_noc_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &periph_noc_clk_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -2193,8 +2207,8 @@ static struct clk_branch gcc_sdcc4_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sdcc4_apps_clk", - .parent_names = (const char *[]){ - "sdcc4_apps_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &sdcc4_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2210,8 +2224,8 @@ static struct clk_branch gcc_sys_noc_usb3_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sys_noc_usb3_axi_clk", - .parent_names = (const char *[]){ - "usb30_master_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &usb30_master_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2227,8 +2241,8 @@ static struct clk_branch gcc_tsif_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_tsif_ahb_clk", - .parent_names = (const char *[]){ - "periph_noc_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &periph_noc_clk_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -2243,8 +2257,8 @@ static struct clk_branch gcc_tsif_ref_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_tsif_ref_clk", - .parent_names = (const char *[]){ - "tsif_ref_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &tsif_ref_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2260,8 +2274,8 @@ static struct clk_branch gcc_usb2a_phy_sleep_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb2a_phy_sleep_clk", - .parent_names = (const char *[]){ - "sleep_clk_src", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "sleep_clk", .name = "sleep_clk_src", }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -2276,8 +2290,8 @@ static struct clk_branch gcc_usb2b_phy_sleep_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb2b_phy_sleep_clk", - .parent_names = (const char *[]){ - "sleep_clk_src", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "sleep_clk", .name = "sleep_clk_src", }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -2292,8 +2306,8 @@ static struct clk_branch gcc_usb30_master_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb30_master_clk", - .parent_names = (const char *[]){ - "usb30_master_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &usb30_master_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2309,8 +2323,8 @@ static struct clk_branch gcc_usb30_mock_utmi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb30_mock_utmi_clk", - .parent_names = (const char *[]){ - "usb30_mock_utmi_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &usb30_mock_utmi_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2326,8 +2340,8 @@ static struct clk_branch gcc_usb30_sleep_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb30_sleep_clk", - .parent_names = (const char *[]){ - "sleep_clk_src", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "sleep_clk", .name = "sleep_clk_src", }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -2342,8 +2356,8 @@ static struct clk_branch gcc_usb_hs_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb_hs_ahb_clk", - .parent_names = (const char *[]){ - "periph_noc_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &periph_noc_clk_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -2358,8 +2372,8 @@ static struct clk_branch gcc_usb_hs_system_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb_hs_system_clk", - .parent_names = (const char *[]){ - "usb_hs_system_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &usb_hs_system_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2375,8 +2389,8 @@ static struct clk_branch gcc_usb_hsic_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb_hsic_ahb_clk", - .parent_names = (const char *[]){ - "periph_noc_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &periph_noc_clk_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -2391,8 +2405,8 @@ static struct clk_branch gcc_usb_hsic_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb_hsic_clk", - .parent_names = (const char *[]){ - "usb_hsic_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &usb_hsic_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2408,8 +2422,8 @@ static struct clk_branch gcc_usb_hsic_io_cal_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb_hsic_io_cal_clk", - .parent_names = (const char *[]){ - "usb_hsic_io_cal_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &usb_hsic_io_cal_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2425,8 +2439,8 @@ static struct clk_branch gcc_usb_hsic_io_cal_sleep_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb_hsic_io_cal_sleep_clk", - .parent_names = (const char *[]){ - "sleep_clk_src", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "sleep_clk", .name = "sleep_clk_src", }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -2441,8 +2455,8 @@ static struct clk_branch gcc_usb_hsic_system_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb_hsic_system_clk", - .parent_names = (const char *[]){ - "usb_hsic_system_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &usb_hsic_system_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2844,7 +2858,7 @@ static void msm8226_clock_override(void) static void msm8974_pro_clock_override(void) { - sdcc1_apps_clk_src_init.parent_names = gcc_xo_gpll0_gpll4; + sdcc1_apps_clk_src_init.parent_data = gcc_xo_gpll0_gpll4; sdcc1_apps_clk_src_init.num_parents = 3; sdcc1_apps_clk_src.freq_tbl = ftbl_gcc_sdcc1_apps_clk_pro; sdcc1_apps_clk_src.parent_map = gcc_xo_gpll0_gpll4_map; From patchwork Wed Sep 28 14:59:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12992313 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4AE62C6FA92 for ; Wed, 28 Sep 2022 15:00:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234674AbiI1PAo (ORCPT ); Wed, 28 Sep 2022 11:00:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36792 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234623AbiI1PAR (ORCPT ); Wed, 28 Sep 2022 11:00:17 -0400 Received: from mail-lf1-x135.google.com (mail-lf1-x135.google.com [IPv6:2a00:1450:4864:20::135]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 562F0367B7 for ; Wed, 28 Sep 2022 08:00:06 -0700 (PDT) Received: by mail-lf1-x135.google.com with SMTP id 10so20797476lfy.5 for ; Wed, 28 Sep 2022 08:00:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=2kS0hYpfUuaV5KsEXWP/lDx5+l6PN7wJvPgJ9tbwDA0=; b=VAdhQctFQWioF74NOD+w0YCv2zXqaN7FG2NsGtHhYaMv8RQ84zudprxk1PyLom9qII 0v0L9+olIGVOLnhXRSwyAwQfKtlkon475K5rpgY29+FLRfFi494K6gD7EDq9U+drGES2 DaEONXlWtNJD5mkC696AqT5R3JaVHIEME8puAjxvWxnTqCYWLXKb5sq380pm68M3ogcL ewG8WOl5qjuDNep7TUUd2WOl4joxXZfpIvDzGzt9cW4vd3M427yUfnRZGwv5n1mMTl0V KpS6MW3dDHsiJefQvyBgGQfzcXGCGypwJ/GiPLLJ0HqZTzgDOgJMf4ZjLEEZR+R81rT3 yV0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=2kS0hYpfUuaV5KsEXWP/lDx5+l6PN7wJvPgJ9tbwDA0=; b=a6+nNEzK7olgGdAd57Be7HwdYXtrc1153W/m0ziu4HRSQzh+9Vx1ZkfLZEmQ5YvRtf CV8w64wPoKYIDPCevTgcwd3WYIhvUU+kX8q3Ti9z0168NnOdy0M4+bPzY80KvFPvSXmR 8M3lWvDBGD4G1u1GUNUYXE9k8xhDdcXiV/gvrMWOyqkVA84lp4Fr0xDK2MUMaOSn4hXe ICtWi9NEB8uLWu9SeuhF70Drg/WqNbN3hFH9uzRFd+/GMxy3+uA5C6QnvIs/A2PjiR7X BZ/H7T1y0uovUQlnoegtqu709i+695BMEmxgcbdZbmn4Sh6qRXi8LogCKLcsZoTJ9dmX XR6g== X-Gm-Message-State: ACrzQf353okh8fjzgDgjR31g3W2LH34i876M405w/wVldg1gBiSjotGU JNNuPvHIKt4NTIunATzXwZAuhw== X-Google-Smtp-Source: AMsMyM6eL21ikLeJe9RQLblnMtEquUYoNpyQFgXtRpsYmgL4Nks6/l3Iz3SE9fNIIGR44cxOmbluzA== X-Received: by 2002:a05:6512:c13:b0:49f:9a2f:8b86 with SMTP id z19-20020a0565120c1300b0049f9a2f8b86mr13198508lfu.413.1664377204439; Wed, 28 Sep 2022 08:00:04 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id be36-20020a056512252400b00492c017de43sm494996lfb.127.2022.09.28.08.00.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Sep 2022 08:00:04 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 06/11] clk: qcom: mmcc-msm8974: use ARRAY_SIZE instead of specifying num_parents Date: Wed, 28 Sep 2022 17:59:53 +0300 Message-Id: <20220928145958.376288-7-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220928145958.376288-1-dmitry.baryshkov@linaro.org> References: <20220928145958.376288-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Use ARRAY_SIZE() instead of manually specifying num_parents. This makes adding/removing entries to/from parent_data easy and errorproof. Signed-off-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong --- drivers/clk/qcom/mmcc-msm8974.c | 74 ++++++++++++++++----------------- 1 file changed, 37 insertions(+), 37 deletions(-) diff --git a/drivers/clk/qcom/mmcc-msm8974.c b/drivers/clk/qcom/mmcc-msm8974.c index f74662925a58..9008df2305df 100644 --- a/drivers/clk/qcom/mmcc-msm8974.c +++ b/drivers/clk/qcom/mmcc-msm8974.c @@ -252,7 +252,7 @@ static struct clk_rcg2 mmss_ahb_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "mmss_ahb_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -289,7 +289,7 @@ static struct clk_rcg2 mmss_axi_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "mmss_axi_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -313,7 +313,7 @@ static struct clk_rcg2 ocmemnoc_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "ocmemnoc_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -332,7 +332,7 @@ static struct clk_rcg2 csi0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "csi0_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -345,7 +345,7 @@ static struct clk_rcg2 csi1_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "csi1_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -358,7 +358,7 @@ static struct clk_rcg2 csi2_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "csi2_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -371,7 +371,7 @@ static struct clk_rcg2 csi3_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "csi3_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -418,7 +418,7 @@ static struct clk_rcg2 vfe0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "vfe0_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -431,7 +431,7 @@ static struct clk_rcg2 vfe1_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "vfe1_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -472,7 +472,7 @@ static struct clk_rcg2 mdp_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "mdp_clk_src", .parent_names = mmcc_xo_mmpll0_dsi_hdmi_gpll0, - .num_parents = 6, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_dsi_hdmi_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -495,7 +495,7 @@ static struct clk_rcg2 jpeg0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "jpeg0_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -508,7 +508,7 @@ static struct clk_rcg2 jpeg1_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "jpeg1_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -521,7 +521,7 @@ static struct clk_rcg2 jpeg2_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "jpeg2_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -534,7 +534,7 @@ static struct clk_rcg2 pclk0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "pclk0_clk_src", .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0, - .num_parents = 6, + .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0), .ops = &clk_pixel_ops, .flags = CLK_SET_RATE_PARENT, }, @@ -548,7 +548,7 @@ static struct clk_rcg2 pclk1_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "pclk1_clk_src", .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0, - .num_parents = 6, + .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0), .ops = &clk_pixel_ops, .flags = CLK_SET_RATE_PARENT, }, @@ -581,7 +581,7 @@ static struct clk_rcg2 vcodec0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "vcodec0_clk_src", .parent_names = mmcc_xo_mmpll0_1_3_gpll0, - .num_parents = 5, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_3_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -599,7 +599,7 @@ static struct clk_rcg2 cci_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cci_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -623,7 +623,7 @@ static struct clk_rcg2 camss_gp0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "camss_gp0_clk_src", .parent_names = mmcc_xo_mmpll0_1_gpll1_0, - .num_parents = 5, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_gpll1_0), .ops = &clk_rcg2_ops, }, }; @@ -637,7 +637,7 @@ static struct clk_rcg2 camss_gp1_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "camss_gp1_clk_src", .parent_names = mmcc_xo_mmpll0_1_gpll1_0, - .num_parents = 5, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_gpll1_0), .ops = &clk_rcg2_ops, }, }; @@ -672,7 +672,7 @@ static struct clk_rcg2 mclk0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "mclk0_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -685,7 +685,7 @@ static struct clk_rcg2 mclk1_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "mclk1_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -698,7 +698,7 @@ static struct clk_rcg2 mclk2_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "mclk2_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -711,7 +711,7 @@ static struct clk_rcg2 mclk3_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "mclk3_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -730,7 +730,7 @@ static struct clk_rcg2 csi0phytimer_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "csi0phytimer_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -743,7 +743,7 @@ static struct clk_rcg2 csi1phytimer_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "csi1phytimer_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -756,7 +756,7 @@ static struct clk_rcg2 csi2phytimer_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "csi2phytimer_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -787,7 +787,7 @@ static struct clk_rcg2 cpp_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cpp_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -805,7 +805,7 @@ static struct clk_rcg2 byte0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "byte0_clk_src", .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0, - .num_parents = 6, + .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0), .ops = &clk_byte2_ops, .flags = CLK_SET_RATE_PARENT, }, @@ -819,7 +819,7 @@ static struct clk_rcg2 byte1_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "byte1_clk_src", .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0, - .num_parents = 6, + .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0), .ops = &clk_byte2_ops, .flags = CLK_SET_RATE_PARENT, }, @@ -838,7 +838,7 @@ static struct clk_rcg2 edpaux_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "edpaux_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -857,7 +857,7 @@ static struct clk_rcg2 edplink_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "edplink_clk_src", .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0, - .num_parents = 6, + .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0), .ops = &clk_rcg2_ops, .flags = CLK_SET_RATE_PARENT, }, @@ -877,7 +877,7 @@ static struct clk_rcg2 edppixel_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "edppixel_clk_src", .parent_names = mmcc_xo_dsi_hdmi_edp, - .num_parents = 6, + .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp), .ops = &clk_edp_pixel_ops, }, }; @@ -895,7 +895,7 @@ static struct clk_rcg2 esc0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "esc0_clk_src", .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0, - .num_parents = 6, + .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -908,7 +908,7 @@ static struct clk_rcg2 esc1_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "esc1_clk_src", .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0, - .num_parents = 6, + .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -926,7 +926,7 @@ static struct clk_rcg2 extpclk_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "extpclk_clk_src", .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0, - .num_parents = 6, + .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0), .ops = &clk_byte_ops, .flags = CLK_SET_RATE_PARENT, }, @@ -945,7 +945,7 @@ static struct clk_rcg2 hdmi_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "hdmi_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -963,7 +963,7 @@ static struct clk_rcg2 vsync_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "vsync_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; From patchwork Wed Sep 28 14:59:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12992312 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6F845C54EE9 for ; Wed, 28 Sep 2022 15:00:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234642AbiI1PAm (ORCPT ); Wed, 28 Sep 2022 11:00:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39124 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234671AbiI1PAQ (ORCPT ); Wed, 28 Sep 2022 11:00:16 -0400 Received: from mail-lf1-x12a.google.com (mail-lf1-x12a.google.com [IPv6:2a00:1450:4864:20::12a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5559A36410 for ; Wed, 28 Sep 2022 08:00:07 -0700 (PDT) Received: by mail-lf1-x12a.google.com with SMTP id bu25so18900828lfb.3 for ; Wed, 28 Sep 2022 08:00:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=1ck4npv+t8dwCS4jYR1P3eWkVMaet1CFj1hH27mCExM=; b=TWIqNZt8DUjo3tDxZJEn6rvYObdzV7TY+tbUqubVO0GuzrfI961jB6iEJ2ckfOKCUg EGXrsSVvPnI1Nop7xeewAocZ8jLkBrqfgxceMoO3ItU/XHuNww7IrZqCUmlg4pMJIWuS qMBZuPFPx2LnmJNzWA1kqzudXwgFyWNF/nzCw2c67jmpdnc7oOj9bR7qBHT9XDNLVaVM QtT+HoLNgVrkg4nk4hwjNP1yFdf7gLeSqoKItrWJ+x9L0jeZeM7DWu4Fxe8xoSH0qJgj 9Y1+b3N3AGLyE2iOoG8Et68wmU6NV5IAeDpdPp5FPm+LbEXUVXbcp59YthI/H4auFYFl OECA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=1ck4npv+t8dwCS4jYR1P3eWkVMaet1CFj1hH27mCExM=; b=tB81/PCKVTWZZuQ+/FFeqy7enDd9X2N1MTkLjODQ/K5N0UKLP4c37nu5VwTmRzRsUL lFyUvO4l6yvZC/8FoerdJiex+jjqP3XUQTJ+aJsffcv/bplh6aPxQ/m+aUSE7tfb/PtE GSBDm7LiOMB6qCkzrpWP2urAs1AYgt/pWESz8xn0lRR3xVOEZtMIvjDnL2hxurUKUVMN dRqMO/kX9O0SdSP6XhNXqqBuC3uPETLPlDpHBDN0IPoxA0a1HdbEIuzxPfKP93Sze6Bu aaN71rOepYklJDTvRx8Vq7WX+uXsUNDK7H4gg4hWFtvfmZpcDmdP73zIxKPoLbtn1/oN +V/g== X-Gm-Message-State: ACrzQf1KOgaGo7+KkOfdfafxmFxkZTeOn4lXUZlfNJ9bQYLuQud7FuO/ fIjCX5eE3TmqmNl+mG85gN1YIA== X-Google-Smtp-Source: AMsMyM7OaszzkpmLh+D9VgfCRPwWppUC2bVIQ7keFMlRQG0cS6oHkl1yjlWVzoYKFdd7E1aypldd8w== X-Received: by 2002:a05:6512:3f29:b0:4a1:c920:ebad with SMTP id y41-20020a0565123f2900b004a1c920ebadmr7341273lfa.574.1664377205113; Wed, 28 Sep 2022 08:00:05 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id be36-20020a056512252400b00492c017de43sm494996lfb.127.2022.09.28.08.00.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Sep 2022 08:00:04 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 07/11] clk: qcom: mmcc-msm8974: move clock parent tables down Date: Wed, 28 Sep 2022 17:59:54 +0300 Message-Id: <20220928145958.376288-8-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220928145958.376288-1-dmitry.baryshkov@linaro.org> References: <20220928145958.376288-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Move clock parent tables down, after the PLL declrataions, so that we can use pll hw clock fields in the next commit. Signed-off-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong --- drivers/clk/qcom/mmcc-msm8974.c | 170 ++++++++++++++++---------------- 1 file changed, 85 insertions(+), 85 deletions(-) diff --git a/drivers/clk/qcom/mmcc-msm8974.c b/drivers/clk/qcom/mmcc-msm8974.c index 9008df2305df..57f1a351c8f6 100644 --- a/drivers/clk/qcom/mmcc-msm8974.c +++ b/drivers/clk/qcom/mmcc-msm8974.c @@ -42,6 +42,91 @@ enum { P_DSI1PLL_BYTE, }; +static struct clk_pll mmpll0 = { + .l_reg = 0x0004, + .m_reg = 0x0008, + .n_reg = 0x000c, + .config_reg = 0x0014, + .mode_reg = 0x0000, + .status_reg = 0x001c, + .status_bit = 17, + .clkr.hw.init = &(struct clk_init_data){ + .name = "mmpll0", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_pll_ops, + }, +}; + +static struct clk_regmap mmpll0_vote = { + .enable_reg = 0x0100, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmpll0_vote", + .parent_names = (const char *[]){ "mmpll0" }, + .num_parents = 1, + .ops = &clk_pll_vote_ops, + }, +}; + +static struct clk_pll mmpll1 = { + .l_reg = 0x0044, + .m_reg = 0x0048, + .n_reg = 0x004c, + .config_reg = 0x0050, + .mode_reg = 0x0040, + .status_reg = 0x005c, + .status_bit = 17, + .clkr.hw.init = &(struct clk_init_data){ + .name = "mmpll1", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_pll_ops, + }, +}; + +static struct clk_regmap mmpll1_vote = { + .enable_reg = 0x0100, + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "mmpll1_vote", + .parent_names = (const char *[]){ "mmpll1" }, + .num_parents = 1, + .ops = &clk_pll_vote_ops, + }, +}; + +static struct clk_pll mmpll2 = { + .l_reg = 0x4104, + .m_reg = 0x4108, + .n_reg = 0x410c, + .config_reg = 0x4110, + .mode_reg = 0x4100, + .status_reg = 0x411c, + .clkr.hw.init = &(struct clk_init_data){ + .name = "mmpll2", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_pll_ops, + }, +}; + +static struct clk_pll mmpll3 = { + .l_reg = 0x0084, + .m_reg = 0x0088, + .n_reg = 0x008c, + .config_reg = 0x0090, + .mode_reg = 0x0080, + .status_reg = 0x009c, + .status_bit = 17, + .clkr.hw.init = &(struct clk_init_data){ + .name = "mmpll3", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_pll_ops, + }, +}; + static const struct parent_map mmcc_xo_mmpll0_mmpll1_gpll0_map[] = { { P_XO, 0 }, { P_MMPLL0, 1 }, @@ -160,91 +245,6 @@ static const char * const mmcc_xo_dsibyte_hdmi_edp_gpll0[] = { "dsi1pllbyte", }; -static struct clk_pll mmpll0 = { - .l_reg = 0x0004, - .m_reg = 0x0008, - .n_reg = 0x000c, - .config_reg = 0x0014, - .mode_reg = 0x0000, - .status_reg = 0x001c, - .status_bit = 17, - .clkr.hw.init = &(struct clk_init_data){ - .name = "mmpll0", - .parent_names = (const char *[]){ "xo" }, - .num_parents = 1, - .ops = &clk_pll_ops, - }, -}; - -static struct clk_regmap mmpll0_vote = { - .enable_reg = 0x0100, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmpll0_vote", - .parent_names = (const char *[]){ "mmpll0" }, - .num_parents = 1, - .ops = &clk_pll_vote_ops, - }, -}; - -static struct clk_pll mmpll1 = { - .l_reg = 0x0044, - .m_reg = 0x0048, - .n_reg = 0x004c, - .config_reg = 0x0050, - .mode_reg = 0x0040, - .status_reg = 0x005c, - .status_bit = 17, - .clkr.hw.init = &(struct clk_init_data){ - .name = "mmpll1", - .parent_names = (const char *[]){ "xo" }, - .num_parents = 1, - .ops = &clk_pll_ops, - }, -}; - -static struct clk_regmap mmpll1_vote = { - .enable_reg = 0x0100, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "mmpll1_vote", - .parent_names = (const char *[]){ "mmpll1" }, - .num_parents = 1, - .ops = &clk_pll_vote_ops, - }, -}; - -static struct clk_pll mmpll2 = { - .l_reg = 0x4104, - .m_reg = 0x4108, - .n_reg = 0x410c, - .config_reg = 0x4110, - .mode_reg = 0x4100, - .status_reg = 0x411c, - .clkr.hw.init = &(struct clk_init_data){ - .name = "mmpll2", - .parent_names = (const char *[]){ "xo" }, - .num_parents = 1, - .ops = &clk_pll_ops, - }, -}; - -static struct clk_pll mmpll3 = { - .l_reg = 0x0084, - .m_reg = 0x0088, - .n_reg = 0x008c, - .config_reg = 0x0090, - .mode_reg = 0x0080, - .status_reg = 0x009c, - .status_bit = 17, - .clkr.hw.init = &(struct clk_init_data){ - .name = "mmpll3", - .parent_names = (const char *[]){ "xo" }, - .num_parents = 1, - .ops = &clk_pll_ops, - }, -}; - static struct clk_rcg2 mmss_ahb_clk_src = { .cmd_rcgr = 0x5000, .hid_width = 5, From patchwork Wed Sep 28 14:59:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12992317 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A8566C6FA96 for ; Wed, 28 Sep 2022 15:00:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234542AbiI1PAt (ORCPT ); Wed, 28 Sep 2022 11:00:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35922 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234687AbiI1PA1 (ORCPT ); Wed, 28 Sep 2022 11:00:27 -0400 Received: from mail-lf1-x12f.google.com (mail-lf1-x12f.google.com [IPv6:2a00:1450:4864:20::12f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C2DA838A06 for ; Wed, 28 Sep 2022 08:00:08 -0700 (PDT) Received: by mail-lf1-x12f.google.com with SMTP id i26so20766886lfp.11 for ; Wed, 28 Sep 2022 08:00:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=7skB2+qMExbn7LvzN0ZV5MWPE9hyK/hR7QNlldLTIWE=; b=xQuoa7RhVrOnVKMAil4bmusTMxMGeV7BSqE/9lcPvbStixwe6W5xOmyieI+8dzTwn2 YR33ByPLdSUUj9U7S8IAMs8qP+BjKAnVk1ECimT6qTQAPCpmYId/0nWihcYxkQMyEtNb /7CySMcWgw8wwOvrTXvagoCxexJYM4J0Xj5aa8rjVRQFBsqHFaSF8je1/vG3VrjJB5BM 7+OZxNIVkyb5k1a8mQn6TBhUKeIUejAlsV64On4S+C9IofiJfg5DGBNvIQ/lQmPKkWRp S4ebp+cHjb3C1T1H7jYs3OByfF7H5JzFfsg98CjS/d1gG8ULlPAj4La1XPvPBe/4saFs CSrA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=7skB2+qMExbn7LvzN0ZV5MWPE9hyK/hR7QNlldLTIWE=; b=05Wqjxz/UQa2gyD7ReOM+jmeatXA612Vyk+78aDUUFadW6QyE04MjKFrPdxFXGgeng oNqEY2Q30VrfXQ2U11eeo1xvXvTyPIz4yNNHlugqv1ksMn8hpFrpWYdZXaRLm9exFqto odZ8WXIHU7lf0S2/k549oIadkFxRNXEtZszaUO3Jjz1XPtNFwjEDB0LG5jYgcn1Ou+hn 9cPyte8aSguUy/Z12IC7CC90k5F9lK1mFlKWXqkR3BgONRs5NXwKSbVi6ZLDhLjFcqdU JwhaWuZImI6MudtElu7NyMvcqTaoeHG/BBIJontgbDgAvcA6H04tURycUGY+75G0HAXW ekLg== X-Gm-Message-State: ACrzQf16JjgT8YKgAZV0yToz1v8ZjgymLl8nIv+w9zVrsyTGs7KJ8hmT 30J7e3G686+O5LYhXXqdIhNm4Q== X-Google-Smtp-Source: AMsMyM4liERtaqBEN/d67Az23cWxiU1WYIhZTv9fn8ie0fEuCHbxZj0dZOptGadbGij2GOCQiHFTlw== X-Received: by 2002:a05:6512:3c8d:b0:49a:d44b:41d with SMTP id h13-20020a0565123c8d00b0049ad44b041dmr13928319lfv.690.1664377205944; Wed, 28 Sep 2022 08:00:05 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id be36-20020a056512252400b00492c017de43sm494996lfb.127.2022.09.28.08.00.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Sep 2022 08:00:05 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 08/11] clk: qcom: mmcc-msm8974: use parent_hws/_data instead of parent_names Date: Wed, 28 Sep 2022 17:59:55 +0300 Message-Id: <20220928145958.376288-9-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220928145958.376288-1-dmitry.baryshkov@linaro.org> References: <20220928145958.376288-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Convert the clock driver to specify parent data rather than parent names, to actually bind using 'clock-names' specified in the DTS rather than global clock names. Use parent_hws where possible to refer parent clocks directly, skipping the lookup. Note, the system names for xo clocks were changed from "xo" to "xo_board" to follow the example of other platforms. Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/mmcc-msm8974.c | 516 ++++++++++++++++---------------- 1 file changed, 264 insertions(+), 252 deletions(-) diff --git a/drivers/clk/qcom/mmcc-msm8974.c b/drivers/clk/qcom/mmcc-msm8974.c index 57f1a351c8f6..4273fce9a4a4 100644 --- a/drivers/clk/qcom/mmcc-msm8974.c +++ b/drivers/clk/qcom/mmcc-msm8974.c @@ -52,7 +52,9 @@ static struct clk_pll mmpll0 = { .status_bit = 17, .clkr.hw.init = &(struct clk_init_data){ .name = "mmpll0", - .parent_names = (const char *[]){ "xo" }, + .parent_data = (const struct clk_parent_data[]){ + { .fw_name = "xo", .name = "xo_board" }, + }, .num_parents = 1, .ops = &clk_pll_ops, }, @@ -63,7 +65,9 @@ static struct clk_regmap mmpll0_vote = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "mmpll0_vote", - .parent_names = (const char *[]){ "mmpll0" }, + .parent_hws = (const struct clk_hw*[]){ + &mmpll0.clkr.hw + }, .num_parents = 1, .ops = &clk_pll_vote_ops, }, @@ -79,7 +83,9 @@ static struct clk_pll mmpll1 = { .status_bit = 17, .clkr.hw.init = &(struct clk_init_data){ .name = "mmpll1", - .parent_names = (const char *[]){ "xo" }, + .parent_data = (const struct clk_parent_data[]){ + { .fw_name = "xo", .name = "xo_board" }, + }, .num_parents = 1, .ops = &clk_pll_ops, }, @@ -90,7 +96,9 @@ static struct clk_regmap mmpll1_vote = { .enable_mask = BIT(1), .hw.init = &(struct clk_init_data){ .name = "mmpll1_vote", - .parent_names = (const char *[]){ "mmpll1" }, + .parent_hws = (const struct clk_hw*[]){ + &mmpll1.clkr.hw + }, .num_parents = 1, .ops = &clk_pll_vote_ops, }, @@ -105,7 +113,9 @@ static struct clk_pll mmpll2 = { .status_reg = 0x411c, .clkr.hw.init = &(struct clk_init_data){ .name = "mmpll2", - .parent_names = (const char *[]){ "xo" }, + .parent_data = (const struct clk_parent_data[]){ + { .fw_name = "xo", .name = "xo_board" }, + }, .num_parents = 1, .ops = &clk_pll_ops, }, @@ -121,7 +131,9 @@ static struct clk_pll mmpll3 = { .status_bit = 17, .clkr.hw.init = &(struct clk_init_data){ .name = "mmpll3", - .parent_names = (const char *[]){ "xo" }, + .parent_data = (const struct clk_parent_data[]){ + { .fw_name = "xo", .name = "xo_board" }, + }, .num_parents = 1, .ops = &clk_pll_ops, }, @@ -134,11 +146,11 @@ static const struct parent_map mmcc_xo_mmpll0_mmpll1_gpll0_map[] = { { P_GPLL0, 5 } }; -static const char * const mmcc_xo_mmpll0_mmpll1_gpll0[] = { - "xo", - "mmpll0_vote", - "mmpll1_vote", - "mmss_gpll0_vote", +static const struct clk_parent_data mmcc_xo_mmpll0_mmpll1_gpll0[] = { + { .fw_name = "xo", .name = "xo_board" }, + { .hw = &mmpll0_vote.hw }, + { .hw = &mmpll1_vote.hw }, + { .fw_name = "mmss_gpll0_vote", .name = "mmss_gpll0_vote" }, }; static const struct parent_map mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = { @@ -150,13 +162,13 @@ static const struct parent_map mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = { { P_DSI1PLL, 3 } }; -static const char * const mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = { - "xo", - "mmpll0_vote", - "hdmipll", - "mmss_gpll0_vote", - "dsi0pll", - "dsi1pll", +static const struct clk_parent_data mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = { + { .fw_name = "xo", .name = "xo_board" }, + { .hw = &mmpll0_vote.hw }, + { .fw_name = "hdmipll", .name = "hdmipll" }, + { .fw_name = "mmss_gpll0_vote", .name = "mmss_gpll0_vote" }, + { .fw_name = "dsi0pll", .name = "dsi0pll" }, + { .fw_name = "dsi1pll", .name = "dsi1pll" }, }; static const struct parent_map mmcc_xo_mmpll0_1_3_gpll0_map[] = { @@ -167,12 +179,12 @@ static const struct parent_map mmcc_xo_mmpll0_1_3_gpll0_map[] = { { P_MMPLL3, 3 } }; -static const char * const mmcc_xo_mmpll0_1_3_gpll0[] = { - "xo", - "mmpll0_vote", - "mmpll1_vote", - "mmss_gpll0_vote", - "mmpll3", +static const struct clk_parent_data mmcc_xo_mmpll0_1_3_gpll0[] = { + { .fw_name = "xo", .name = "xo_board" }, + { .hw = &mmpll0_vote.hw }, + { .hw = &mmpll1_vote.hw }, + { .fw_name = "mmss_gpll0_vote", .name = "mmss_gpll0_vote" }, + { .hw = &mmpll3.clkr.hw }, }; static const struct parent_map mmcc_xo_mmpll0_1_gpll1_0_map[] = { @@ -183,12 +195,12 @@ static const struct parent_map mmcc_xo_mmpll0_1_gpll1_0_map[] = { { P_GPLL1, 4 } }; -static const char * const mmcc_xo_mmpll0_1_gpll1_0[] = { - "xo", - "mmpll0_vote", - "mmpll1_vote", - "mmss_gpll0_vote", - "gpll1_vote", +static const struct clk_parent_data mmcc_xo_mmpll0_1_gpll1_0[] = { + { .fw_name = "xo", .name = "xo_board" }, + { .hw = &mmpll0_vote.hw }, + { .hw = &mmpll1_vote.hw }, + { .fw_name = "mmss_gpll0_vote", .name = "mmss_gpll0_vote" }, + { .fw_name = "gpll1_vote", .name = "gpll1_vote" }, }; static const struct parent_map mmcc_xo_dsi_hdmi_edp_map[] = { @@ -200,13 +212,13 @@ static const struct parent_map mmcc_xo_dsi_hdmi_edp_map[] = { { P_DSI1PLL, 2 } }; -static const char * const mmcc_xo_dsi_hdmi_edp[] = { - "xo", - "edp_link_clk", - "hdmipll", - "edp_vco_div", - "dsi0pll", - "dsi1pll", +static const struct clk_parent_data mmcc_xo_dsi_hdmi_edp[] = { + { .fw_name = "xo", .name = "xo_board" }, + { .fw_name = "edp_link_clk", .name = "edp_link_clk" }, + { .fw_name = "hdmipll", .name = "hdmipll" }, + { .fw_name = "edp_vco_div", .name = "edp_vco_div" }, + { .fw_name = "dsi0pll", .name = "dsi0pll" }, + { .fw_name = "dsi1pll", .name = "dsi1pll" }, }; static const struct parent_map mmcc_xo_dsi_hdmi_edp_gpll0_map[] = { @@ -218,13 +230,13 @@ static const struct parent_map mmcc_xo_dsi_hdmi_edp_gpll0_map[] = { { P_DSI1PLL, 2 } }; -static const char * const mmcc_xo_dsi_hdmi_edp_gpll0[] = { - "xo", - "edp_link_clk", - "hdmipll", - "gpll0_vote", - "dsi0pll", - "dsi1pll", +static const struct clk_parent_data mmcc_xo_dsi_hdmi_edp_gpll0[] = { + { .fw_name = "xo", .name = "xo_board" }, + { .fw_name = "edp_link_clk", .name = "edp_link_clk" }, + { .fw_name = "hdmipll", .name = "hdmipll" }, + { .fw_name = "gpll0_vote", .name = "gpll0_vote" }, + { .fw_name = "dsi0pll", .name = "dsi0pll" }, + { .fw_name = "dsi1pll", .name = "dsi1pll" }, }; static const struct parent_map mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = { @@ -236,13 +248,13 @@ static const struct parent_map mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = { { P_DSI1PLL_BYTE, 2 } }; -static const char * const mmcc_xo_dsibyte_hdmi_edp_gpll0[] = { - "xo", - "edp_link_clk", - "hdmipll", - "gpll0_vote", - "dsi0pllbyte", - "dsi1pllbyte", +static const struct clk_parent_data mmcc_xo_dsibyte_hdmi_edp_gpll0[] = { + { .fw_name = "xo", .name = "xo_board" }, + { .fw_name = "edp_link_clk", .name = "edp_link_clk" }, + { .fw_name = "hdmipll", .name = "hdmipll" }, + { .fw_name = "gpll0_vote", .name = "gpll0_vote" }, + { .fw_name = "dsi0pllbyte", .name = "dsi0pllbyte" }, + { .fw_name = "dsi1pllbyte", .name = "dsi1pllbyte" }, }; static struct clk_rcg2 mmss_ahb_clk_src = { @@ -251,7 +263,7 @@ static struct clk_rcg2 mmss_ahb_clk_src = { .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, .clkr.hw.init = &(struct clk_init_data){ .name = "mmss_ahb_clk_src", - .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, + .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0, .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, @@ -288,7 +300,7 @@ static struct clk_rcg2 mmss_axi_clk_src = { .freq_tbl = ftbl_mmss_axi_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "mmss_axi_clk_src", - .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, + .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0, .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, @@ -312,7 +324,7 @@ static struct clk_rcg2 ocmemnoc_clk_src = { .freq_tbl = ftbl_ocmemnoc_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "ocmemnoc_clk_src", - .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, + .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0, .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, @@ -331,7 +343,7 @@ static struct clk_rcg2 csi0_clk_src = { .freq_tbl = ftbl_camss_csi0_3_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "csi0_clk_src", - .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, + .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0, .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, @@ -344,7 +356,7 @@ static struct clk_rcg2 csi1_clk_src = { .freq_tbl = ftbl_camss_csi0_3_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "csi1_clk_src", - .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, + .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0, .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, @@ -357,7 +369,7 @@ static struct clk_rcg2 csi2_clk_src = { .freq_tbl = ftbl_camss_csi0_3_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "csi2_clk_src", - .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, + .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0, .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, @@ -370,7 +382,7 @@ static struct clk_rcg2 csi3_clk_src = { .freq_tbl = ftbl_camss_csi0_3_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "csi3_clk_src", - .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, + .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0, .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, @@ -417,7 +429,7 @@ static struct clk_rcg2 vfe0_clk_src = { .freq_tbl = ftbl_camss_vfe_vfe0_1_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "vfe0_clk_src", - .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, + .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0, .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, @@ -430,7 +442,7 @@ static struct clk_rcg2 vfe1_clk_src = { .freq_tbl = ftbl_camss_vfe_vfe0_1_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "vfe1_clk_src", - .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, + .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0, .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, @@ -471,7 +483,7 @@ static struct clk_rcg2 mdp_clk_src = { .freq_tbl = ftbl_mdss_mdp_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "mdp_clk_src", - .parent_names = mmcc_xo_mmpll0_dsi_hdmi_gpll0, + .parent_data = mmcc_xo_mmpll0_dsi_hdmi_gpll0, .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_dsi_hdmi_gpll0), .ops = &clk_rcg2_ops, }, @@ -494,7 +506,7 @@ static struct clk_rcg2 jpeg0_clk_src = { .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "jpeg0_clk_src", - .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, + .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0, .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, @@ -507,7 +519,7 @@ static struct clk_rcg2 jpeg1_clk_src = { .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "jpeg1_clk_src", - .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, + .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0, .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, @@ -520,7 +532,7 @@ static struct clk_rcg2 jpeg2_clk_src = { .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "jpeg2_clk_src", - .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, + .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0, .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, @@ -533,7 +545,7 @@ static struct clk_rcg2 pclk0_clk_src = { .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map, .clkr.hw.init = &(struct clk_init_data){ .name = "pclk0_clk_src", - .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0, + .parent_data = mmcc_xo_dsi_hdmi_edp_gpll0, .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0), .ops = &clk_pixel_ops, .flags = CLK_SET_RATE_PARENT, @@ -547,7 +559,7 @@ static struct clk_rcg2 pclk1_clk_src = { .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map, .clkr.hw.init = &(struct clk_init_data){ .name = "pclk1_clk_src", - .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0, + .parent_data = mmcc_xo_dsi_hdmi_edp_gpll0, .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0), .ops = &clk_pixel_ops, .flags = CLK_SET_RATE_PARENT, @@ -580,7 +592,7 @@ static struct clk_rcg2 vcodec0_clk_src = { .freq_tbl = ftbl_venus0_vcodec0_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "vcodec0_clk_src", - .parent_names = mmcc_xo_mmpll0_1_3_gpll0, + .parent_data = mmcc_xo_mmpll0_1_3_gpll0, .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_3_gpll0), .ops = &clk_rcg2_ops, }, @@ -598,7 +610,7 @@ static struct clk_rcg2 cci_clk_src = { .freq_tbl = ftbl_camss_cci_cci_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "cci_clk_src", - .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, + .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0, .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, @@ -622,7 +634,7 @@ static struct clk_rcg2 camss_gp0_clk_src = { .freq_tbl = ftbl_camss_gp0_1_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "camss_gp0_clk_src", - .parent_names = mmcc_xo_mmpll0_1_gpll1_0, + .parent_data = mmcc_xo_mmpll0_1_gpll1_0, .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_gpll1_0), .ops = &clk_rcg2_ops, }, @@ -636,7 +648,7 @@ static struct clk_rcg2 camss_gp1_clk_src = { .freq_tbl = ftbl_camss_gp0_1_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "camss_gp1_clk_src", - .parent_names = mmcc_xo_mmpll0_1_gpll1_0, + .parent_data = mmcc_xo_mmpll0_1_gpll1_0, .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_gpll1_0), .ops = &clk_rcg2_ops, }, @@ -671,7 +683,7 @@ static struct clk_rcg2 mclk0_clk_src = { .freq_tbl = ftbl_camss_mclk0_3_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "mclk0_clk_src", - .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, + .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0, .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, @@ -684,7 +696,7 @@ static struct clk_rcg2 mclk1_clk_src = { .freq_tbl = ftbl_camss_mclk0_3_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "mclk1_clk_src", - .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, + .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0, .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, @@ -697,7 +709,7 @@ static struct clk_rcg2 mclk2_clk_src = { .freq_tbl = ftbl_camss_mclk0_3_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "mclk2_clk_src", - .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, + .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0, .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, @@ -710,7 +722,7 @@ static struct clk_rcg2 mclk3_clk_src = { .freq_tbl = ftbl_camss_mclk0_3_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "mclk3_clk_src", - .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, + .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0, .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, @@ -729,7 +741,7 @@ static struct clk_rcg2 csi0phytimer_clk_src = { .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "csi0phytimer_clk_src", - .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, + .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0, .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, @@ -742,7 +754,7 @@ static struct clk_rcg2 csi1phytimer_clk_src = { .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "csi1phytimer_clk_src", - .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, + .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0, .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, @@ -755,7 +767,7 @@ static struct clk_rcg2 csi2phytimer_clk_src = { .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "csi2phytimer_clk_src", - .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, + .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0, .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, @@ -786,7 +798,7 @@ static struct clk_rcg2 cpp_clk_src = { .freq_tbl = ftbl_camss_vfe_cpp_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "cpp_clk_src", - .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, + .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0, .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, @@ -804,7 +816,7 @@ static struct clk_rcg2 byte0_clk_src = { .freq_tbl = byte_freq_tbl, .clkr.hw.init = &(struct clk_init_data){ .name = "byte0_clk_src", - .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0, + .parent_data = mmcc_xo_dsibyte_hdmi_edp_gpll0, .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0), .ops = &clk_byte2_ops, .flags = CLK_SET_RATE_PARENT, @@ -818,7 +830,7 @@ static struct clk_rcg2 byte1_clk_src = { .freq_tbl = byte_freq_tbl, .clkr.hw.init = &(struct clk_init_data){ .name = "byte1_clk_src", - .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0, + .parent_data = mmcc_xo_dsibyte_hdmi_edp_gpll0, .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0), .ops = &clk_byte2_ops, .flags = CLK_SET_RATE_PARENT, @@ -837,7 +849,7 @@ static struct clk_rcg2 edpaux_clk_src = { .freq_tbl = ftbl_mdss_edpaux_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "edpaux_clk_src", - .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, + .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0, .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, @@ -856,7 +868,7 @@ static struct clk_rcg2 edplink_clk_src = { .freq_tbl = ftbl_mdss_edplink_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "edplink_clk_src", - .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0, + .parent_data = mmcc_xo_dsi_hdmi_edp_gpll0, .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0), .ops = &clk_rcg2_ops, .flags = CLK_SET_RATE_PARENT, @@ -876,7 +888,7 @@ static struct clk_rcg2 edppixel_clk_src = { .freq_tbl = edp_pixel_freq_tbl, .clkr.hw.init = &(struct clk_init_data){ .name = "edppixel_clk_src", - .parent_names = mmcc_xo_dsi_hdmi_edp, + .parent_data = mmcc_xo_dsi_hdmi_edp, .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp), .ops = &clk_edp_pixel_ops, }, @@ -894,7 +906,7 @@ static struct clk_rcg2 esc0_clk_src = { .freq_tbl = ftbl_mdss_esc0_1_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "esc0_clk_src", - .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0, + .parent_data = mmcc_xo_dsibyte_hdmi_edp_gpll0, .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0), .ops = &clk_rcg2_ops, }, @@ -907,7 +919,7 @@ static struct clk_rcg2 esc1_clk_src = { .freq_tbl = ftbl_mdss_esc0_1_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "esc1_clk_src", - .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0, + .parent_data = mmcc_xo_dsibyte_hdmi_edp_gpll0, .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0), .ops = &clk_rcg2_ops, }, @@ -925,7 +937,7 @@ static struct clk_rcg2 extpclk_clk_src = { .freq_tbl = extpclk_freq_tbl, .clkr.hw.init = &(struct clk_init_data){ .name = "extpclk_clk_src", - .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0, + .parent_data = mmcc_xo_dsi_hdmi_edp_gpll0, .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0), .ops = &clk_byte_ops, .flags = CLK_SET_RATE_PARENT, @@ -944,7 +956,7 @@ static struct clk_rcg2 hdmi_clk_src = { .freq_tbl = ftbl_mdss_hdmi_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "hdmi_clk_src", - .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, + .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0, .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, @@ -962,7 +974,7 @@ static struct clk_rcg2 vsync_clk_src = { .freq_tbl = ftbl_mdss_vsync_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "vsync_clk_src", - .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, + .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0, .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, @@ -975,8 +987,8 @@ static struct clk_branch camss_cci_cci_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_cci_cci_ahb_clk", - .parent_names = (const char *[]){ - "mmss_ahb_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &mmss_ahb_clk_src.clkr.hw }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -991,8 +1003,8 @@ static struct clk_branch camss_cci_cci_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_cci_cci_clk", - .parent_names = (const char *[]){ - "cci_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cci_clk_src.clkr.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1008,8 +1020,8 @@ static struct clk_branch camss_csi0_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_csi0_ahb_clk", - .parent_names = (const char *[]){ - "mmss_ahb_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &mmss_ahb_clk_src.clkr.hw }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -1024,8 +1036,8 @@ static struct clk_branch camss_csi0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_csi0_clk", - .parent_names = (const char *[]){ - "csi0_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &csi0_clk_src.clkr.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1041,8 +1053,8 @@ static struct clk_branch camss_csi0phy_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_csi0phy_clk", - .parent_names = (const char *[]){ - "csi0_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &csi0_clk_src.clkr.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1058,8 +1070,8 @@ static struct clk_branch camss_csi0pix_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_csi0pix_clk", - .parent_names = (const char *[]){ - "csi0_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &csi0_clk_src.clkr.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1075,8 +1087,8 @@ static struct clk_branch camss_csi0rdi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_csi0rdi_clk", - .parent_names = (const char *[]){ - "csi0_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &csi0_clk_src.clkr.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1092,8 +1104,8 @@ static struct clk_branch camss_csi1_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_csi1_ahb_clk", - .parent_names = (const char *[]){ - "mmss_ahb_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &mmss_ahb_clk_src.clkr.hw }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -1108,8 +1120,8 @@ static struct clk_branch camss_csi1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_csi1_clk", - .parent_names = (const char *[]){ - "csi1_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &csi1_clk_src.clkr.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1125,8 +1137,8 @@ static struct clk_branch camss_csi1phy_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_csi1phy_clk", - .parent_names = (const char *[]){ - "csi1_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &csi1_clk_src.clkr.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1142,8 +1154,8 @@ static struct clk_branch camss_csi1pix_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_csi1pix_clk", - .parent_names = (const char *[]){ - "csi1_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &csi1_clk_src.clkr.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1159,8 +1171,8 @@ static struct clk_branch camss_csi1rdi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_csi1rdi_clk", - .parent_names = (const char *[]){ - "csi1_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &csi1_clk_src.clkr.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1176,8 +1188,8 @@ static struct clk_branch camss_csi2_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_csi2_ahb_clk", - .parent_names = (const char *[]){ - "mmss_ahb_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &mmss_ahb_clk_src.clkr.hw }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -1192,8 +1204,8 @@ static struct clk_branch camss_csi2_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_csi2_clk", - .parent_names = (const char *[]){ - "csi2_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &csi2_clk_src.clkr.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1209,8 +1221,8 @@ static struct clk_branch camss_csi2phy_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_csi2phy_clk", - .parent_names = (const char *[]){ - "csi2_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &csi2_clk_src.clkr.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1226,8 +1238,8 @@ static struct clk_branch camss_csi2pix_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_csi2pix_clk", - .parent_names = (const char *[]){ - "csi2_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &csi2_clk_src.clkr.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1243,8 +1255,8 @@ static struct clk_branch camss_csi2rdi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_csi2rdi_clk", - .parent_names = (const char *[]){ - "csi2_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &csi2_clk_src.clkr.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1260,8 +1272,8 @@ static struct clk_branch camss_csi3_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_csi3_ahb_clk", - .parent_names = (const char *[]){ - "mmss_ahb_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &mmss_ahb_clk_src.clkr.hw }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -1276,8 +1288,8 @@ static struct clk_branch camss_csi3_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_csi3_clk", - .parent_names = (const char *[]){ - "csi3_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &csi3_clk_src.clkr.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1293,8 +1305,8 @@ static struct clk_branch camss_csi3phy_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_csi3phy_clk", - .parent_names = (const char *[]){ - "csi3_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &csi3_clk_src.clkr.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1310,8 +1322,8 @@ static struct clk_branch camss_csi3pix_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_csi3pix_clk", - .parent_names = (const char *[]){ - "csi3_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &csi3_clk_src.clkr.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1327,8 +1339,8 @@ static struct clk_branch camss_csi3rdi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_csi3rdi_clk", - .parent_names = (const char *[]){ - "csi3_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &csi3_clk_src.clkr.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1344,8 +1356,8 @@ static struct clk_branch camss_csi_vfe0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_csi_vfe0_clk", - .parent_names = (const char *[]){ - "vfe0_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &vfe0_clk_src.clkr.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1361,8 +1373,8 @@ static struct clk_branch camss_csi_vfe1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_csi_vfe1_clk", - .parent_names = (const char *[]){ - "vfe1_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &vfe1_clk_src.clkr.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1378,8 +1390,8 @@ static struct clk_branch camss_gp0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_gp0_clk", - .parent_names = (const char *[]){ - "camss_gp0_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &camss_gp0_clk_src.clkr.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1395,8 +1407,8 @@ static struct clk_branch camss_gp1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_gp1_clk", - .parent_names = (const char *[]){ - "camss_gp1_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &camss_gp1_clk_src.clkr.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1412,8 +1424,8 @@ static struct clk_branch camss_ispif_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_ispif_ahb_clk", - .parent_names = (const char *[]){ - "mmss_ahb_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &mmss_ahb_clk_src.clkr.hw }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -1428,8 +1440,8 @@ static struct clk_branch camss_jpeg_jpeg0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_jpeg_jpeg0_clk", - .parent_names = (const char *[]){ - "jpeg0_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &jpeg0_clk_src.clkr.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1445,8 +1457,8 @@ static struct clk_branch camss_jpeg_jpeg1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_jpeg_jpeg1_clk", - .parent_names = (const char *[]){ - "jpeg1_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &jpeg1_clk_src.clkr.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1462,8 +1474,8 @@ static struct clk_branch camss_jpeg_jpeg2_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_jpeg_jpeg2_clk", - .parent_names = (const char *[]){ - "jpeg2_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &jpeg2_clk_src.clkr.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1479,8 +1491,8 @@ static struct clk_branch camss_jpeg_jpeg_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_jpeg_jpeg_ahb_clk", - .parent_names = (const char *[]){ - "mmss_ahb_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &mmss_ahb_clk_src.clkr.hw }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -1495,8 +1507,8 @@ static struct clk_branch camss_jpeg_jpeg_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_jpeg_jpeg_axi_clk", - .parent_names = (const char *[]){ - "mmss_axi_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &mmss_axi_clk_src.clkr.hw }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -1511,8 +1523,8 @@ static struct clk_branch camss_jpeg_jpeg_ocmemnoc_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_jpeg_jpeg_ocmemnoc_clk", - .parent_names = (const char *[]){ - "ocmemnoc_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &ocmemnoc_clk_src.clkr.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1528,8 +1540,8 @@ static struct clk_branch camss_mclk0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_mclk0_clk", - .parent_names = (const char *[]){ - "mclk0_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &mclk0_clk_src.clkr.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1545,8 +1557,8 @@ static struct clk_branch camss_mclk1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_mclk1_clk", - .parent_names = (const char *[]){ - "mclk1_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &mclk1_clk_src.clkr.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1562,8 +1574,8 @@ static struct clk_branch camss_mclk2_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_mclk2_clk", - .parent_names = (const char *[]){ - "mclk2_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &mclk2_clk_src.clkr.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1579,8 +1591,8 @@ static struct clk_branch camss_mclk3_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_mclk3_clk", - .parent_names = (const char *[]){ - "mclk3_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &mclk3_clk_src.clkr.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1596,8 +1608,8 @@ static struct clk_branch camss_micro_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_micro_ahb_clk", - .parent_names = (const char *[]){ - "mmss_ahb_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &mmss_ahb_clk_src.clkr.hw }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -1612,8 +1624,8 @@ static struct clk_branch camss_phy0_csi0phytimer_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_phy0_csi0phytimer_clk", - .parent_names = (const char *[]){ - "csi0phytimer_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &csi0phytimer_clk_src.clkr.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1629,8 +1641,8 @@ static struct clk_branch camss_phy1_csi1phytimer_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_phy1_csi1phytimer_clk", - .parent_names = (const char *[]){ - "csi1phytimer_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &csi1phytimer_clk_src.clkr.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1646,8 +1658,8 @@ static struct clk_branch camss_phy2_csi2phytimer_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_phy2_csi2phytimer_clk", - .parent_names = (const char *[]){ - "csi2phytimer_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &csi2phytimer_clk_src.clkr.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1663,8 +1675,8 @@ static struct clk_branch camss_top_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_top_ahb_clk", - .parent_names = (const char *[]){ - "mmss_ahb_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &mmss_ahb_clk_src.clkr.hw }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -1679,8 +1691,8 @@ static struct clk_branch camss_vfe_cpp_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_vfe_cpp_ahb_clk", - .parent_names = (const char *[]){ - "mmss_ahb_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &mmss_ahb_clk_src.clkr.hw }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -1695,8 +1707,8 @@ static struct clk_branch camss_vfe_cpp_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_vfe_cpp_clk", - .parent_names = (const char *[]){ - "cpp_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cpp_clk_src.clkr.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1712,8 +1724,8 @@ static struct clk_branch camss_vfe_vfe0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_vfe_vfe0_clk", - .parent_names = (const char *[]){ - "vfe0_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &vfe0_clk_src.clkr.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1729,8 +1741,8 @@ static struct clk_branch camss_vfe_vfe1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_vfe_vfe1_clk", - .parent_names = (const char *[]){ - "vfe1_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &vfe1_clk_src.clkr.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1746,8 +1758,8 @@ static struct clk_branch camss_vfe_vfe_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_vfe_vfe_ahb_clk", - .parent_names = (const char *[]){ - "mmss_ahb_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &mmss_ahb_clk_src.clkr.hw }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -1762,8 +1774,8 @@ static struct clk_branch camss_vfe_vfe_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_vfe_vfe_axi_clk", - .parent_names = (const char *[]){ - "mmss_axi_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &mmss_axi_clk_src.clkr.hw }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -1778,8 +1790,8 @@ static struct clk_branch camss_vfe_vfe_ocmemnoc_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_vfe_vfe_ocmemnoc_clk", - .parent_names = (const char *[]){ - "ocmemnoc_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &ocmemnoc_clk_src.clkr.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1795,8 +1807,8 @@ static struct clk_branch mdss_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "mdss_ahb_clk", - .parent_names = (const char *[]){ - "mmss_ahb_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &mmss_ahb_clk_src.clkr.hw }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -1811,8 +1823,8 @@ static struct clk_branch mdss_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "mdss_axi_clk", - .parent_names = (const char *[]){ - "mmss_axi_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &mmss_axi_clk_src.clkr.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1828,8 +1840,8 @@ static struct clk_branch mdss_byte0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "mdss_byte0_clk", - .parent_names = (const char *[]){ - "byte0_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &byte0_clk_src.clkr.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1845,8 +1857,8 @@ static struct clk_branch mdss_byte1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "mdss_byte1_clk", - .parent_names = (const char *[]){ - "byte1_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &byte1_clk_src.clkr.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1862,8 +1874,8 @@ static struct clk_branch mdss_edpaux_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "mdss_edpaux_clk", - .parent_names = (const char *[]){ - "edpaux_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &edpaux_clk_src.clkr.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1879,8 +1891,8 @@ static struct clk_branch mdss_edplink_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "mdss_edplink_clk", - .parent_names = (const char *[]){ - "edplink_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &edplink_clk_src.clkr.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1896,8 +1908,8 @@ static struct clk_branch mdss_edppixel_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "mdss_edppixel_clk", - .parent_names = (const char *[]){ - "edppixel_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &edppixel_clk_src.clkr.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1913,8 +1925,8 @@ static struct clk_branch mdss_esc0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "mdss_esc0_clk", - .parent_names = (const char *[]){ - "esc0_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &esc0_clk_src.clkr.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1930,8 +1942,8 @@ static struct clk_branch mdss_esc1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "mdss_esc1_clk", - .parent_names = (const char *[]){ - "esc1_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &esc1_clk_src.clkr.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1947,8 +1959,8 @@ static struct clk_branch mdss_extpclk_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "mdss_extpclk_clk", - .parent_names = (const char *[]){ - "extpclk_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &extpclk_clk_src.clkr.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1964,8 +1976,8 @@ static struct clk_branch mdss_hdmi_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "mdss_hdmi_ahb_clk", - .parent_names = (const char *[]){ - "mmss_ahb_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &mmss_ahb_clk_src.clkr.hw }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -1980,8 +1992,8 @@ static struct clk_branch mdss_hdmi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "mdss_hdmi_clk", - .parent_names = (const char *[]){ - "hdmi_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &hdmi_clk_src.clkr.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1997,8 +2009,8 @@ static struct clk_branch mdss_mdp_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "mdss_mdp_clk", - .parent_names = (const char *[]){ - "mdp_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &mdp_clk_src.clkr.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2014,8 +2026,8 @@ static struct clk_branch mdss_mdp_lut_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "mdss_mdp_lut_clk", - .parent_names = (const char *[]){ - "mdp_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &mdp_clk_src.clkr.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2031,8 +2043,8 @@ static struct clk_branch mdss_pclk0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "mdss_pclk0_clk", - .parent_names = (const char *[]){ - "pclk0_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &pclk0_clk_src.clkr.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2048,8 +2060,8 @@ static struct clk_branch mdss_pclk1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "mdss_pclk1_clk", - .parent_names = (const char *[]){ - "pclk1_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &pclk1_clk_src.clkr.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2065,8 +2077,8 @@ static struct clk_branch mdss_vsync_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "mdss_vsync_clk", - .parent_names = (const char *[]){ - "vsync_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &vsync_clk_src.clkr.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2082,8 +2094,8 @@ static struct clk_branch mmss_misc_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "mmss_misc_ahb_clk", - .parent_names = (const char *[]){ - "mmss_ahb_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &mmss_ahb_clk_src.clkr.hw }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -2098,8 +2110,8 @@ static struct clk_branch mmss_mmssnoc_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "mmss_mmssnoc_ahb_clk", - .parent_names = (const char *[]){ - "mmss_ahb_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &mmss_ahb_clk_src.clkr.hw }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -2115,8 +2127,8 @@ static struct clk_branch mmss_mmssnoc_bto_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "mmss_mmssnoc_bto_ahb_clk", - .parent_names = (const char *[]){ - "mmss_ahb_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &mmss_ahb_clk_src.clkr.hw }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -2132,8 +2144,8 @@ static struct clk_branch mmss_mmssnoc_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "mmss_mmssnoc_axi_clk", - .parent_names = (const char *[]){ - "mmss_axi_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &mmss_axi_clk_src.clkr.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, @@ -2149,8 +2161,8 @@ static struct clk_branch mmss_s0_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "mmss_s0_axi_clk", - .parent_names = (const char *[]){ - "mmss_axi_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &mmss_axi_clk_src.clkr.hw }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -2166,8 +2178,8 @@ static struct clk_branch ocmemcx_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "ocmemcx_ahb_clk", - .parent_names = (const char *[]){ - "mmss_ahb_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &mmss_ahb_clk_src.clkr.hw }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -2182,8 +2194,8 @@ static struct clk_branch ocmemcx_ocmemnoc_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "ocmemcx_ocmemnoc_clk", - .parent_names = (const char *[]){ - "ocmemnoc_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &ocmemnoc_clk_src.clkr.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2199,8 +2211,8 @@ static struct clk_branch oxili_ocmemgx_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "oxili_ocmemgx_clk", - .parent_names = (const char *[]){ - "gfx3d_clk_src", + .parent_data = (const struct clk_parent_data[]){ + { .fw_name = "gfx3d_clk_src", .name = "gfx3d_clk_src" }, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2216,8 +2228,8 @@ static struct clk_branch ocmemnoc_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "ocmemnoc_clk", - .parent_names = (const char *[]){ - "ocmemnoc_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &ocmemnoc_clk_src.clkr.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2233,8 +2245,8 @@ static struct clk_branch oxili_gfx3d_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "oxili_gfx3d_clk", - .parent_names = (const char *[]){ - "gfx3d_clk_src", + .parent_data = (const struct clk_parent_data[]){ + { .fw_name = "gfx3d_clk_src", .name = "gfx3d_clk_src" }, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2250,8 +2262,8 @@ static struct clk_branch oxilicx_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "oxilicx_ahb_clk", - .parent_names = (const char *[]){ - "mmss_ahb_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &mmss_ahb_clk_src.clkr.hw }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -2266,8 +2278,8 @@ static struct clk_branch oxilicx_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "oxilicx_axi_clk", - .parent_names = (const char *[]){ - "mmss_axi_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &mmss_axi_clk_src.clkr.hw }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -2282,8 +2294,8 @@ static struct clk_branch venus0_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "venus0_ahb_clk", - .parent_names = (const char *[]){ - "mmss_ahb_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &mmss_ahb_clk_src.clkr.hw }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -2298,8 +2310,8 @@ static struct clk_branch venus0_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "venus0_axi_clk", - .parent_names = (const char *[]){ - "mmss_axi_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &mmss_axi_clk_src.clkr.hw }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -2314,8 +2326,8 @@ static struct clk_branch venus0_ocmemnoc_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "venus0_ocmemnoc_clk", - .parent_names = (const char *[]){ - "ocmemnoc_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &ocmemnoc_clk_src.clkr.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2331,8 +2343,8 @@ static struct clk_branch venus0_vcodec0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "venus0_vcodec0_clk", - .parent_names = (const char *[]){ - "vcodec0_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &vcodec0_clk_src.clkr.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, From patchwork Wed Sep 28 14:59:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12992314 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EAB19C6FA94 for ; Wed, 28 Sep 2022 15:00:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234622AbiI1PAr (ORCPT ); Wed, 28 Sep 2022 11:00:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35684 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234620AbiI1PAW (ORCPT ); Wed, 28 Sep 2022 11:00:22 -0400 Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [IPv6:2a00:1450:4864:20::130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2B8C538A2F for ; Wed, 28 Sep 2022 08:00:09 -0700 (PDT) Received: by mail-lf1-x130.google.com with SMTP id a8so20752167lff.13 for ; Wed, 28 Sep 2022 08:00:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=UcpWFZqwzt2iPUQPqE8ypJYgI9SteXXhQqUr61/Zf2k=; b=EPkX704LXYnO0oJVGzo2xpWyJXpQv40SbmJzXrqu7NMm/12Ah3IOPA0ulzrEpVGVwX oAPej9VOH2FrD6vAJ6PSrY2L0Osfzh2W+WMd05QzzQVhg+UCPsWDpE2HrBGtDGc2gqSL MnV88GSpFKRd0DvmUa+A0rC9YI0u+dNw/jzzG8iRGNFN39O2FX031ZjL1u/mh6p5fjc+ /2733TO5jIcVAwhONGk9CrsFKi5eYzkUxh/vUDIemrQAh8dl/I6sxI/7lB83vqNqAVZ3 Ni5t9sJyamhi11v3r1MQrnw2spEe15Rqwf8kCAHuuwfkiMzWtvFamcQjawaE1Ru/3Sgu pIvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=UcpWFZqwzt2iPUQPqE8ypJYgI9SteXXhQqUr61/Zf2k=; b=G8sNsxWiHRTLm6dgAjLJIJ6JNpTNDn359i6PtAaqPDHeg51ZBO6ej0mvd1Eg00g9Pc 13q3aI+JTrrYSZvd6Hh0/ksozIt0fSujZORjVqT1KWv1I8OkJjBp34VHzM7LU8rKpn1M oGXVq8KMm4QBQG0r0zekVDjfW25krNMzW7HHP/z8f9aCOUOKGP53OELKkNusiFeJvQd2 dh2e9JobepjHPoPmsIfKlzwMckBhsNvDXaF7pYSTwoIPV8U8bWsZ7/LXU7+XpvrEbNx3 CX4O8lw6YfRoro4R/EfUDgqnbkAWNWktxtuYzh3gjKiTy0e6QAkVz3migqIW/wiUfkFz PXGA== X-Gm-Message-State: ACrzQf2FDsImZYwmoCHR5QcTBYdYirtf917x2eFWD9mP+nxNkY1I+kzv +6gx9KsDWH1tF68YUHbrHtqBDA== X-Google-Smtp-Source: AMsMyM7fP3m0ynNAHGGn5XPBEmJRAZ/tM1Qz4XFFKB2zBUc+VqbSxoNYUHlg1ky96pszg6F33zIzAA== X-Received: by 2002:a05:6512:2250:b0:49b:817a:c318 with SMTP id i16-20020a056512225000b0049b817ac318mr14495322lfu.535.1664377206802; Wed, 28 Sep 2022 08:00:06 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id be36-20020a056512252400b00492c017de43sm494996lfb.127.2022.09.28.08.00.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Sep 2022 08:00:06 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 09/11] ARM: dts: qcom: msm8974: add second DSI host and PHY Date: Wed, 28 Sep 2022 17:59:56 +0300 Message-Id: <20220928145958.376288-10-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220928145958.376288-1-dmitry.baryshkov@linaro.org> References: <20220928145958.376288-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add second DSI host and PHY available on the msm8974 platform. Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom-msm8974.dtsi | 78 +++++++++++++++++++++++++++++ 1 file changed, 78 insertions(+) diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 7a9be0acf3f5..810a163ca14f 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -1541,6 +1541,13 @@ mdp5_intf1_out: endpoint { remote-endpoint = <&dsi0_in>; }; }; + + port@1 { + reg = <1>; + mdp5_intf2_out: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; }; }; @@ -1614,6 +1621,77 @@ dsi0_phy: dsi-phy@fd922a00 { status = "disabled"; }; + + dsi1: dsi@fd922e00 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0xfd922e00 0x1f8>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>; + assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; + + clocks = <&mmcc MDSS_MDP_CLK>, + <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MDSS_BYTE1_CLK>, + <&mmcc MDSS_PCLK1_CLK>, + <&mmcc MDSS_ESC1_CLK>, + <&mmcc MMSS_MISC_AHB_CLK>; + clock-names = "mdp_core", + "iface", + "bus", + "byte", + "pixel", + "core", + "core_mmss"; + + phys = <&dsi1_phy>; + phy-names = "dsi-phy"; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi1_in: endpoint { + remote-endpoint = <&mdp5_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + dsi1_out: endpoint { + }; + }; + }; + }; + + dsi1_phy: dsi-phy@fd923000 { + compatible = "qcom,dsi-phy-28nm-hpm"; + reg = <0xfd923000 0xd4>, + <0xfd923100 0x280>, + <0xfd923380 0x30>; + reg-names = "dsi_pll", + "dsi_phy", + "dsi_phy_regulator"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; }; gpu: adreno@fdb00000 { From patchwork Wed Sep 28 14:59:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12992311 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BB052C04A95 for ; Wed, 28 Sep 2022 15:00:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234693AbiI1PAg (ORCPT ); Wed, 28 Sep 2022 11:00:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37442 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234635AbiI1PAN (ORCPT ); Wed, 28 Sep 2022 11:00:13 -0400 Received: from mail-lf1-x132.google.com (mail-lf1-x132.google.com [IPv6:2a00:1450:4864:20::132]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AEF65BF55 for ; Wed, 28 Sep 2022 08:00:09 -0700 (PDT) Received: by mail-lf1-x132.google.com with SMTP id a8so20752235lff.13 for ; Wed, 28 Sep 2022 08:00:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=LtgKFbu4xqrBfa/UrtX2sBDc1GeFUYPgf38w51iW7Nk=; b=Iv35MiLznn/D0K8UTRyRcqgGBwwGImiPAYgqYnb+ZzlkVb3BcS9NVIUNjDYi5nB3Pb WK9EjEtjpWBDVSFuE/lQibiPhn74MWHfsx62bmFd+wjS7yMLouMVm1+sZ0gZ5SGOhM0a WoOagqQkrTPRLTvdtTvcAUb9/tEKt1DP2taUN3ghOLOJhHTlV+2ZBvezH8TNRIwzBsEf B5JrOa4tRWAdAhi7FRmSnraHrrGcfBPqEuhCFwtU9z1gZaUUxvSBSQTP+8AyVuxms1lS hgMN6fhk3oQQAbMwQaLaCYk7HeyOevF4zQ4pwXgahvyGnDV/AwqKONdSNnXXsfU41kDJ icmg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=LtgKFbu4xqrBfa/UrtX2sBDc1GeFUYPgf38w51iW7Nk=; b=SKseVA4w74m0E2PSf9CN6353aCMsqfVaiI1Jmphe/t6OQ1xzydsoGlsa3FX59Mfzke /j6FUKecHgq5RZfzqoQ2wTTVGgbv3KVHrPcBq/gcNEQIdlyIalcIEe5GN3Qlom7P+Jy4 BhSp7/O4dhyoe0BjQl4BTfa7+HGmqFtib3p+7HdR1yZZucGWPHxlxYRyfbwKYtZf9+lZ y/WgG4UnxmljfCFPFNDsFEBZX6FvIjbl4ksd0EpXRAurrnoxwM7/wMlIx+K0WW7MTgiB f7LFvoecqSVX0pp+hdJzDkQZcDiOhzzBHc1GQ8Qa3aAHfRg/L4TJyOA/kPIHdoH+e+7D I/QA== X-Gm-Message-State: ACrzQf38d7hwG1DiZBuhWwkYsWIXrZIHftCbC0Z9xy3mt4UIGqIPGakz 5BZ+d5TNbNKjxSOHCclwDlsWmw== X-Google-Smtp-Source: AMsMyM4FREszGlL2+XHKulFWgB1264kaoph75qVa8jSSu2nL5puYWiGKb2yxb9iuFhfkdBFVhDkWoA== X-Received: by 2002:ac2:57c9:0:b0:49c:3e64:de95 with SMTP id k9-20020ac257c9000000b0049c3e64de95mr13703590lfo.452.1664377207499; Wed, 28 Sep 2022 08:00:07 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id be36-20020a056512252400b00492c017de43sm494996lfb.127.2022.09.28.08.00.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Sep 2022 08:00:07 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 10/11] ARM: dts: qcom: msm8974: add clocks and clock-names to gcc device Date: Wed, 28 Sep 2022 17:59:57 +0300 Message-Id: <20220928145958.376288-11-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220928145958.376288-1-dmitry.baryshkov@linaro.org> References: <20220928145958.376288-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add clocks and clock-names nodes to the gcc device to bind clocks using the DT links. Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom-msm8974.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 810a163ca14f..68ef494ca87a 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -1054,6 +1054,10 @@ gcc: clock-controller@fc400000 { #reset-cells = <1>; #power-domain-cells = <1>; reg = <0xfc400000 0x4000>; + + clock-names = "xo", "sleep_clk"; + clocks = <&xo_board>, + <&sleep_clk>; }; rpm_msg_ram: memory@fc428000 { From patchwork Wed Sep 28 14:59:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12992315 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 234BAC32771 for ; Wed, 28 Sep 2022 15:00:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234619AbiI1PAq (ORCPT ); Wed, 28 Sep 2022 11:00:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36036 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234645AbiI1PAT (ORCPT ); Wed, 28 Sep 2022 11:00:19 -0400 Received: from mail-lf1-x133.google.com (mail-lf1-x133.google.com [IPv6:2a00:1450:4864:20::133]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3FC3D1A040 for ; Wed, 28 Sep 2022 08:00:10 -0700 (PDT) Received: by mail-lf1-x133.google.com with SMTP id g1so3168792lfu.12 for ; Wed, 28 Sep 2022 08:00:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=Gv+TB5vz0jii361bUqWIooViGxmGQPct0fTOn1q1P3o=; b=g3r+hb6XIf8X+C3ses6PuIx0RVsHov7HhClz0ZX/jDhI2KJcEQ4MS862BV0Cw+ExXe 1kh196l24uxLctMgqvX/RVlaTrulILQnGEN36KFG6BIhdgD30EFQZv2MniHoXFokpw3b TNTvMXUfMYwbSyqjOZqMqGfQNZUvjQBacJOx/LjG2oM3zzWZUouMGXXlaQ+q5IqY2/Xd VvjclNlEeiJ5SJmya8OnisNOABYlbXpqHjxw/wc/wsAfIQIGucOgh7eBRrZ1rP+0L4Pt AB891HjYfz9F/qvs5D5Pk1fR+FbbebfdSJL2R9DyxJzWxdpAYB7C/ETuQb19m7hybwMn ZOyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=Gv+TB5vz0jii361bUqWIooViGxmGQPct0fTOn1q1P3o=; b=8GpFByd2JlVFUHCBOHB3WgpI0s57xWEzjS0LbjZrkp3z09K13vvCWg3IuwJJ6EWUYj ozfFBMjwF/JPYMypujZO+blWW/zXLjFdPsLUGdH37kOwT7bAtu/2lErUVNzF/kAhCDnk ocimYGvpO/r+e2a457RYbsScDGIwIBw1Vla0BsOidRDlenAgcarjxtTB95uu/BXqX/Ly +vjGvXRWyddwcckuqy2Dh5IAsPN5Rvc4cc41qi+xYFzBB4dWJVykfmnHV4qnSxk6Fshx Z4u6OTIbGT/nWsySW9bFRqMwVVrE3ivQEO077fsOghvJxHVMPB4doLuBnlnQt1TIHzZD ccYw== X-Gm-Message-State: ACrzQf09ppW0J0nuylZFJQzTWV0CQ80CF2+Vib/ewpk3DRMuHlBMdPAw /Ws7nqDz5pcADT6eI+ryLEsFBw== X-Google-Smtp-Source: AMsMyM6+32vjuH06+MaZVY7m2dFezl2OxIKB66cvsrnIjyMoz0Vk+W7GBmOh4h6UI0C5MESuIaknMA== X-Received: by 2002:a05:6512:2384:b0:497:ad1c:799 with SMTP id c4-20020a056512238400b00497ad1c0799mr13258871lfv.294.1664377208230; Wed, 28 Sep 2022 08:00:08 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id be36-20020a056512252400b00492c017de43sm494996lfb.127.2022.09.28.08.00.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Sep 2022 08:00:07 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 11/11] ARM: dts: qcom: msm8974: add clocks and clock-names to mmcc device Date: Wed, 28 Sep 2022 17:59:58 +0300 Message-Id: <20220928145958.376288-12-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220928145958.376288-1-dmitry.baryshkov@linaro.org> References: <20220928145958.376288-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add clocks and clock-names nodes to the mmcc device to bind clocks using the DT links. Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom-msm8974.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 68ef494ca87a..3b7940022cdd 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -1493,6 +1493,30 @@ mmcc: clock-controller@fd8c0000 { #reset-cells = <1>; #power-domain-cells = <1>; reg = <0xfd8c0000 0x6000>; + clocks = <&xo_board>, + <&gcc GCC_MMSS_GPLL0_CLK_SRC>, + <&gcc GPLL0_VOTE>, + <&gcc GPLL1_VOTE>, + <&rpmcc RPM_SMD_GFX3D_CLK_SRC>, + <&dsi0_phy 1>, + <&dsi0_phy 0>, + <&dsi1_phy 1>, + <&dsi1_phy 0>, + <0>, + <0>, + <0>; + clock-names = "xo", + "mmss_gpll0_vote", + "gpll0_vote", + "gpll1_vote", + "gfx3d_clk_src", + "dsi0pll", + "dsi0pllbyte", + "dsi1pll", + "dsi1pllbyte", + "hdmipll", + "edp_link_clk", + "edp_vco_div"; }; mdss: mdss@fd900000 {