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Fri, 30 Sep 2022 12:28:04 -0700 Received: from rnnvmail205.nvidia.com (10.129.68.10) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Fri, 30 Sep 2022 12:28:04 -0700 Received: from vidyas-desktop.nvidia.com (10.127.8.9) by mail.nvidia.com (10.129.68.10) with Microsoft SMTP Server id 15.2.986.29 via Frontend Transport; Fri, 30 Sep 2022 12:28:00 -0700 From: Vidya Sagar To: , , , , , , , , , CC: , , , , , , , Subject: [PATCH V1 1/4] dt-bindings: Add "hotplug-gpios" PCIe property Date: Sat, 1 Oct 2022 00:57:44 +0530 Message-ID: <20220930192747.21471-2-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220930192747.21471-1-vidyas@nvidia.com> References: <20220930192747.21471-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT008:EE_|DM4PR12MB5213:EE_ X-MS-Office365-Filtering-Correlation-Id: 03c06304-ed3f-4ffa-bf91-08daa319ed3a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Sep 2022 19:28:17.3875 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 03c06304-ed3f-4ffa-bf91-08daa319ed3a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT008.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5213 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Provide a way for the firmware to tell the OS about the GPIO that can be used to get the Hot-Plug and Unplug events. Signed-off-by: Vidya Sagar --- Documentation/devicetree/bindings/pci/pci.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/pci.txt b/Documentation/devicetree/bindings/pci/pci.txt index 6a8f2874a24d..7b89bddc8dde 100644 --- a/Documentation/devicetree/bindings/pci/pci.txt +++ b/Documentation/devicetree/bindings/pci/pci.txt @@ -32,6 +32,10 @@ driver implementation may support the following properties: root port to downstream device and host bridge drivers can do programming which depends on CLKREQ signal existence. For example, programming root port not to advertise ASPM L1 Sub-States support if there is no CLKREQ signal. +- hotplug-gpios: + If present this property specifies the GPIO to be used for Hot-Plug/Unplug + functionality. It is used by the PCIe GPIO Hot-Plug core driver for + PCIe device Hot-Plug/Unplug events. PCI-PCI Bridge properties ------------------------- From patchwork Fri Sep 30 19:27:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 12995919 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ABADAC43217 for ; Fri, 30 Sep 2022 19:28:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231549AbiI3T21 (ORCPT ); Fri, 30 Sep 2022 15:28:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37566 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232050AbiI3T2Z (ORCPT ); Fri, 30 Sep 2022 15:28:25 -0400 Received: from NAM02-BN1-obe.outbound.protection.outlook.com (mail-bn1nam07on2089.outbound.protection.outlook.com [40.107.212.89]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9521AC7459; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Sep 2022 19:28:21.4549 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5ffccc90-00a0-4120-39a2-08daa319efa0 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT066.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5390 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org This adds a standalone driver to support PCIe hotplug functionality merely based on a GPIO indicating the status of a downstream device connectivity. It looks for "hotplug-gpios" property in the corresponding device node to get the GPIO information. It also provides a mechanism for platform drivers of the controllers to register ops to perform any platform specific operations while enabling/disabling the slots. Signed-off-by: Vidya Sagar --- drivers/pci/hotplug/Kconfig | 11 ++ drivers/pci/hotplug/Makefile | 1 + drivers/pci/hotplug/gpio_php.c | 200 +++++++++++++++++++++++++++++++++ drivers/pci/hotplug/gpiophp.h | 40 +++++++ 4 files changed, 252 insertions(+) create mode 100644 drivers/pci/hotplug/gpio_php.c create mode 100644 drivers/pci/hotplug/gpiophp.h diff --git a/drivers/pci/hotplug/Kconfig b/drivers/pci/hotplug/Kconfig index 840a84bb5ee2..dbac64ff6915 100644 --- a/drivers/pci/hotplug/Kconfig +++ b/drivers/pci/hotplug/Kconfig @@ -158,4 +158,15 @@ config HOTPLUG_PCI_S390 When in doubt, say Y. +config HOTPLUG_PCI_GPIO + bool "GPIO based PCI Hotplug Support" + depends on OF_GPIO + help + Say Y here if you want to have GPIO based PCIe hot-plug framework. + This framework helps to register a GPIO based Hot-Plug controller + with the system where a GPIO can be used to represent device + connect and disconnect states. + + When in doubt, say N. + endif # HOTPLUG_PCI diff --git a/drivers/pci/hotplug/Makefile b/drivers/pci/hotplug/Makefile index 5196983220df..70e11d698807 100644 --- a/drivers/pci/hotplug/Makefile +++ b/drivers/pci/hotplug/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_HOTPLUG_PCI_RPA) += rpaphp.o obj-$(CONFIG_HOTPLUG_PCI_RPA_DLPAR) += rpadlpar_io.o obj-$(CONFIG_HOTPLUG_PCI_ACPI) += acpiphp.o obj-$(CONFIG_HOTPLUG_PCI_S390) += s390_pci_hpc.o +obj-$(CONFIG_HOTPLUG_PCI_GPIO) += gpio_php.o # acpiphp_ibm extends acpiphp, so should be linked afterwards. diff --git a/drivers/pci/hotplug/gpio_php.c b/drivers/pci/hotplug/gpio_php.c new file mode 100644 index 000000000000..33c8105aade5 --- /dev/null +++ b/drivers/pci/hotplug/gpio_php.c @@ -0,0 +1,200 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * GPIO based PCI Hotplug Driver. + * + */ + +#include +#include +#include +#include +#include +#include "../pci.h" +#include "../pcie/portdrv.h" + +#include "gpiophp.h" + +static DEFINE_MUTEX(slot_mutex); + +static inline struct gpio_hotplug_slot *to_gpio_hotplug_slot(struct hotplug_slot *slot) +{ + return container_of(slot, struct gpio_hotplug_slot, hotplug_slot); +} + +static int gpio_hp_get_power_status(struct hotplug_slot *hotplug_slot, u8 *value) +{ + struct gpio_hotplug_slot *slot = to_gpio_hotplug_slot(hotplug_slot); + struct pci_dev *dev; + + pci_config_pm_runtime_get(slot->pdev); + dev = pci_get_slot(slot->pdev->subordinate, PCI_DEVFN(0, 0)); + if (dev) { + pci_dev_put(dev); + *value = 1; + } else { + *value = 0; + } + pci_dbg(slot->pdev, "Power Status = %u\n", *value); + pci_config_pm_runtime_put(slot->pdev); + + return 0; +} + +static int gpio_hp_enable_slot(struct hotplug_slot *hotplug_slot) +{ + struct gpio_hotplug_slot *slot = to_gpio_hotplug_slot(hotplug_slot); + int ret = 0; + u8 value; + + mutex_lock(&slot_mutex); + + gpio_hp_get_power_status(hotplug_slot, &value); + if (value) { + pci_info(slot->pdev, "Device is already plugged-in\n"); + goto exit; + } + + if (slot->plat_ops && slot->plat_ops->enable) + slot->plat_ops->enable(slot); + + pm_runtime_get_sync(&slot->pdev->dev); + + pci_lock_rescan_remove(); + pci_rescan_bus(slot->pdev->bus); + pci_unlock_rescan_remove(); + + pm_runtime_put(&slot->pdev->dev); + +exit: + mutex_unlock(&slot_mutex); + return ret; +} + +static int gpio_hp_disable_slot(struct hotplug_slot *hotplug_slot) +{ + struct gpio_hotplug_slot *slot = to_gpio_hotplug_slot(hotplug_slot); + struct pci_dev *dev, *temp; + u8 value; + + mutex_lock(&slot_mutex); + + gpio_hp_get_power_status(hotplug_slot, &value); + if (!value) { + pci_info(slot->pdev, "Device is already removed\n"); + goto exit; + } + + pci_lock_rescan_remove(); + + list_for_each_entry_safe_reverse(dev, temp, &slot->pdev->subordinate->devices, bus_list) { + pci_dev_get(dev); + pci_stop_and_remove_bus_device(dev); + pci_dev_put(dev); + } + + pci_unlock_rescan_remove(); + +exit: + if (slot->plat_ops && slot->plat_ops->disable) + slot->plat_ops->disable(slot); + mutex_unlock(&slot_mutex); + return 0; +} + +static const struct hotplug_slot_ops gpio_hotplug_slot_ops = { + .enable_slot = gpio_hp_enable_slot, + .disable_slot = gpio_hp_disable_slot, + .get_power_status = gpio_hp_get_power_status, +}; + +static irqreturn_t pcie_gpio_hp_irq(int irq, void *arg) +{ + struct gpio_hotplug_slot *slot = arg; + + if (gpiod_get_value(slot->gpiod)) { + pci_dbg(slot->pdev, "Hot-Plug Event\n"); + gpio_hp_enable_slot(&slot->hotplug_slot); + } else { + pci_dbg(slot->pdev, "Hot-UnPlug Event\n"); + gpio_hp_disable_slot(&slot->hotplug_slot); + } + + return IRQ_HANDLED; +} + +int register_gpio_hotplug_slot(struct gpio_hotplug_slot *slot) +{ + struct device *dev = &slot->pdev->dev; + struct pci_dev *pdev = slot->pdev; + struct gpio_desc *gpiod; + unsigned int irq; + char *name; + int ret; + + gpiod = devm_gpiod_get(&pdev->bus->dev, "hotplug", GPIOD_IN); + if (IS_ERR(gpiod)) { + ret = PTR_ERR(gpiod); + pci_err(pdev, "Failed to find GPIO for Hot-Plug functionality: %d\n", ret); + return ret; + } + + ret = gpiod_to_irq(gpiod); + if (ret < 0) { + pci_err(pdev, "Failed to get IRQ for Hot_Plug GPIO: %d\n", ret); + return ret; + } + irq = (unsigned int)ret; + + slot->gpiod = gpiod; + slot->hotplug_slot.ops = &gpio_hotplug_slot_ops; + slot->irq = irq; + + name = devm_kasprintf(dev, GFP_KERNEL, "slot_%u", slot->slot_nr); + if (!name) { + ret = -ENOMEM; + goto exit; + } + + ret = pci_hp_register(&slot->hotplug_slot, pdev->subordinate, 0, name); + if (ret) { + pci_err(pdev, "Failed to register hotplug slot: %d\n", ret); + goto exit; + } + + name = devm_kasprintf(dev, GFP_KERNEL, "pcie_gpio_hp_irq_%u", slot->slot_nr); + if (!name) { + ret = -ENOMEM; + goto exit; + } + + ret = devm_request_threaded_irq(dev, slot->irq, + NULL, pcie_gpio_hp_irq, + IRQF_TRIGGER_RISING | + IRQF_TRIGGER_FALLING | IRQF_ONESHOT, + name, slot); + if (ret < 0) { + pci_err(pdev, "Failed to request IRQ for Hot-Plug: %d\n", ret); + goto exit; + } + + pci_dbg(pdev, "Hot-Plug Slot registered for %s\n", pci_name(pdev)); + + gpio_hp_enable_slot(&slot->hotplug_slot); + + return 0; + +exit: + return ret; +} + +void unregister_gpio_hotplug_slot(struct gpio_hotplug_slot *slot) +{ + struct device *dev = &slot->pdev->dev; + struct pci_dev *pdev = slot->pdev; + + gpio_hp_disable_slot(&slot->hotplug_slot); + devm_free_irq(dev, slot->irq, slot); + pci_hp_deregister(&slot->hotplug_slot); + devm_gpiod_put(&pdev->bus->dev, slot->gpiod); +} + diff --git a/drivers/pci/hotplug/gpiophp.h b/drivers/pci/hotplug/gpiophp.h new file mode 100644 index 000000000000..77cc76976e0d --- /dev/null +++ b/drivers/pci/hotplug/gpiophp.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * GPIO based PCI Hotplug Driver. + * + */ + +#ifndef _GPIOPHP_H +#define _GPIOPHP_H + +#include + +struct gpio_hotplug_slot; + +struct gpio_hotplug_slot_plat_ops { + int (*enable)(struct gpio_hotplug_slot *hp_slot); + int (*disable)(struct gpio_hotplug_slot *hp_slot); +}; + +struct gpio_hotplug_slot { + struct device_node *np; + int slot_nr; + const struct gpio_hotplug_slot_plat_ops *plat_ops; + struct pci_dev *pdev; + + struct gpio_desc *gpiod; + unsigned int irq; + + struct hotplug_slot hotplug_slot; +}; + +#ifdef CONFIG_HOTPLUG_PCI_GPIO +int register_gpio_hotplug_slot(struct gpio_hotplug_slot *hp_slot); +void unregister_gpio_hotplug_slot(struct gpio_hotplug_slot *hp_slot); +#else +static inline int register_gpio_hotplug_slot(struct gpio_hotplug_slot *hp_slot) +{ return 0; } +static inline void unregister_gpio_hotplug_slot(struct gpio_hotplug_slot *hp_slot) {} +#endif + +#endif //_GPIOPHP_H From patchwork Fri Sep 30 19:27:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 12995920 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9E76CC43219 for ; Fri, 30 Sep 2022 19:28:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232057AbiI3T2c (ORCPT ); Fri, 30 Sep 2022 15:28:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37778 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232079AbiI3T2a (ORCPT ); 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Sep 2022 19:28:26.4711 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ee1c7464-b0e0-4e90-cb8a-08daa319f2a4 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT020.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB6535 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add support to configure a slot as a pluggable slot by not power-gating the respective controller based on the DT property "hotplug-gpios". Signed-off-by: Vidya Sagar --- drivers/pci/controller/dwc/pcie-tegra194.c | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 2600304522eb..0370e881422d 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -280,6 +280,8 @@ struct tegra_pcie_dw { unsigned int phy_count; struct phy **phys; + bool slot_pluggable; + struct dentry *debugfs; /* Endpoint mode specific */ @@ -1089,6 +1091,7 @@ static int tegra_pcie_dw_parse_dt(struct tegra_pcie_dw *pcie) { struct platform_device *pdev = to_platform_device(pcie->dev); struct device_node *np = pcie->dev->of_node; + struct property *prop; int ret; pcie->dbi_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); @@ -1158,6 +1161,10 @@ static int tegra_pcie_dw_parse_dt(struct tegra_pcie_dw *pcie) pcie->enable_srns = of_property_read_bool(np, "nvidia,enable-srns"); + prop = of_find_property(np, "hotplug-gpios", NULL); + if (prop) + pcie->slot_pluggable = true; + if (pcie->of_data->mode == DW_PCIE_RC_TYPE) return 0; @@ -1655,7 +1662,7 @@ static int tegra_pcie_config_rp(struct tegra_pcie_dw *pcie) } pcie->link_state = tegra_pcie_dw_link_up(&pcie->pci); - if (!pcie->link_state) { + if (!pcie->link_state && !pcie->slot_pluggable) { ret = -ENOMEDIUM; goto fail_host_init; } @@ -2267,7 +2274,7 @@ static int tegra_pcie_dw_remove(struct platform_device *pdev) struct tegra_pcie_dw *pcie = platform_get_drvdata(pdev); if (pcie->of_data->mode == DW_PCIE_RC_TYPE) { - if (!pcie->link_state) + if (!pcie->link_state && !pcie->slot_pluggable) return 0; debugfs_remove_recursive(pcie->debugfs); @@ -2296,7 +2303,7 @@ static int tegra_pcie_dw_suspend_late(struct device *dev) return -EPERM; } - if (!pcie->link_state) + if (!pcie->link_state && !pcie->slot_pluggable) return 0; /* Enable HW_HOT_RST mode */ @@ -2315,7 +2322,7 @@ static int tegra_pcie_dw_suspend_noirq(struct device *dev) { struct tegra_pcie_dw *pcie = dev_get_drvdata(dev); - if (!pcie->link_state) + if (!pcie->link_state && !pcie->slot_pluggable) return 0; tegra_pcie_downstream_dev_to_D0(pcie); @@ -2330,7 +2337,7 @@ static int tegra_pcie_dw_resume_noirq(struct device *dev) struct tegra_pcie_dw *pcie = dev_get_drvdata(dev); int ret; - if (!pcie->link_state) + if (!pcie->link_state && !pcie->slot_pluggable) return 0; ret = tegra_pcie_config_controller(pcie, true); @@ -2366,7 +2373,7 @@ static int tegra_pcie_dw_resume_early(struct device *dev) return -ENOTSUPP; } - if (!pcie->link_state) + if (!pcie->link_state && !pcie->slot_pluggable) return 0; /* Disable HW_HOT_RST mode */ @@ -2388,7 +2395,7 @@ static void tegra_pcie_dw_shutdown(struct platform_device *pdev) struct tegra_pcie_dw *pcie = platform_get_drvdata(pdev); if (pcie->of_data->mode == DW_PCIE_RC_TYPE) { - if (!pcie->link_state) + if (!pcie->link_state && !pcie->slot_pluggable) return; debugfs_remove_recursive(pcie->debugfs); From patchwork Fri Sep 30 19:27:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 12995921 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A5EFEC4332F for ; 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Fri, 30 Sep 2022 12:28:19 -0700 From: Vidya Sagar To: , , , , , , , , , CC: , , , , , , , Subject: [PATCH V1 4/4] PCI: tegra194: Enable GPIO based Hot-Plug support Date: Sat, 1 Oct 2022 00:57:47 +0530 Message-ID: <20220930192747.21471-5-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220930192747.21471-1-vidyas@nvidia.com> References: <20220930192747.21471-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT017:EE_|MN2PR12MB4520:EE_ X-MS-Office365-Filtering-Correlation-Id: 01eea430-e602-4b2b-c644-08daa319f5f4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: PDqXc/jPTJVhA6z6NB3nb1zE582WPn0h6ZMPL78XdwxYGedySZM7QyHbOAEqbdrYS6UiPeOPKjlWJCvx6ESDV0URFFdRqzmmPBCdx3WyGKL+L9tKdlqDW1v92cJ7VWKCMBPwqYvLtdDGniQEyRKE1xr1FHpzDfVpjqX1djk7kt2zFZ8CwiOspwtE/DYJTPisF/E0Mse0Yp0PfauKJUAWTwI6Dm6rFWkiXKalMn3y6BYpjqaE0xOhEjWqbedrWrRsNT4lAMLlWY/ToBztV1X8zwcJA/SgGdzaQ5EjInWCZdrxiWqJeYD3C9O0ALbILe5BlB2qHJgDlI55hYZcTjW+/WjTU6EPsnuSIV1ocH8WOwEriiWRl694bRlNsjTcbvlp2KBFES80lqnrN9hfR9Y/H33QZQ0XD5wF1MEX84Pp2cBD1c58gZ18zRZZokcuerVLbqQn/XoPltkVCc9/8LCy5tHxPtWn6kO8Iqwr7DuvHuSC9nqZiGlN1Hw2eYhMVmOyMpZo4+82EQI5s1T3vg0ifpnxD8AjSji703d9CTBmLBAOAIx196PP68coLGCHjR7Q/0bo5RGl8qJKtIrfPNlgicTs7RojBsr/c6ZzDjvWmq+0IBgwYwdqRpcxHOJBQo2fgEvjubvLcc3aQZ95RYJtwUW/ciOE0Pd4910w6+0o0Q/7HL57fQvfxgjWdYzKmr7xtp5n7105xis/bGBBC+vycHIvnlG/dENaCVRIOiUHHRwRNvkf6lx5oK4j1lIfBZsK12ejqVFS+oXab1b2GGQCSkweTt6XUhANVwL77pLGmqY= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230022)(4636009)(136003)(376002)(39860400002)(346002)(396003)(451199015)(36840700001)(40470700004)(46966006)(47076005)(26005)(36756003)(2906002)(2616005)(8936002)(41300700001)(70586007)(7696005)(70206006)(36860700001)(8676002)(426003)(110136005)(86362001)(336012)(4326008)(54906003)(40460700003)(7416002)(6666004)(5660300002)(316002)(186003)(1076003)(7636003)(478600001)(40480700001)(921005)(83380400001)(356005)(82310400005)(82740400003);DIR:OUT;SFP:1101; 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Signed-off-by: Vidya Sagar --- drivers/pci/controller/dwc/pcie-tegra194.c | 64 ++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 0370e881422d..1b70aba08473 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -36,6 +36,7 @@ #include #include #include "../../pci.h" +#include "../../hotplug/gpiophp.h" #define TEGRA194_DWC_IP_VER 0x490A #define TEGRA234_DWC_IP_VER 0x562A @@ -281,6 +282,7 @@ struct tegra_pcie_dw { struct phy **phys; bool slot_pluggable; + struct gpio_hotplug_slot hp_slot; struct dentry *debugfs; @@ -296,6 +298,11 @@ static inline struct tegra_pcie_dw *to_tegra_pcie(struct dw_pcie *pci) return container_of(pci, struct tegra_pcie_dw, pci); } +static inline struct tegra_pcie_dw *to_tegra_pcie_from_slot(struct gpio_hotplug_slot *slot) +{ + return container_of(slot, struct tegra_pcie_dw, hp_slot); +} + static inline void appl_writel(struct tegra_pcie_dw *pcie, const u32 value, const u32 reg) { @@ -1046,6 +1053,45 @@ static const struct dw_pcie_ops tegra_dw_pcie_ops = { .stop_link = tegra_pcie_dw_stop_link, }; +static int tegra_pcie_slot_enable(struct gpio_hotplug_slot *slot) +{ + struct tegra_pcie_dw *pcie = to_tegra_pcie_from_slot(slot); + int ret; + + ret = tegra_pcie_dw_start_link(&pcie->pci); + if (!ret) + pcie->link_state = tegra_pcie_dw_link_up(&pcie->pci); + + return ret; +} + +static int tegra_pcie_slot_disable(struct gpio_hotplug_slot *slot) +{ + struct tegra_pcie_dw *pcie = to_tegra_pcie_from_slot(slot); + u32 val; + + val = appl_readl(pcie, APPL_PINMUX); + val &= ~APPL_PINMUX_PEX_RST; + appl_writel(pcie, val, APPL_PINMUX); + + /* + * Deassert LTSSM state to stop the state toggling between + * polling and detect. + */ + val = readl(pcie->appl_base + APPL_CTRL); + val &= ~APPL_CTRL_LTSSM_EN; + writel(val, pcie->appl_base + APPL_CTRL); + + pcie->link_state = tegra_pcie_dw_link_up(&pcie->pci); + + return 0; +} + +static const struct gpio_hotplug_slot_plat_ops tegra_pcie_gpio_hp_plat_ops = { + .enable = tegra_pcie_slot_enable, + .disable = tegra_pcie_slot_disable, +}; + static const struct dw_pcie_host_ops tegra_pcie_dw_host_ops = { .host_init = tegra_pcie_dw_host_init, }; @@ -1676,6 +1722,20 @@ static int tegra_pcie_config_rp(struct tegra_pcie_dw *pcie) pcie->debugfs = debugfs_create_dir(name, NULL); init_debugfs(pcie); + if (pcie->slot_pluggable) { + pcie->hp_slot.plat_ops = &tegra_pcie_gpio_hp_plat_ops; + pcie->hp_slot.np = pcie->dev->of_node; + pcie->hp_slot.slot_nr = pcie->cid; + pcie->hp_slot.pdev = pci_get_slot(pcie->pci.pp.bridge->bus, PCI_DEVFN(0, 0)); + + ret = register_gpio_hotplug_slot(&pcie->hp_slot); + if (ret < 0) + dev_warn(dev, + "Failed to register platform ops for GPIO Hot-Plug controller: %d\n", + ret); + ret = 0; + } + return ret; fail_host_init: @@ -2277,6 +2337,8 @@ static int tegra_pcie_dw_remove(struct platform_device *pdev) if (!pcie->link_state && !pcie->slot_pluggable) return 0; + if (pcie->slot_pluggable) + unregister_gpio_hotplug_slot(&pcie->hp_slot); debugfs_remove_recursive(pcie->debugfs); tegra_pcie_deinit_controller(pcie); pm_runtime_put_sync(pcie->dev); @@ -2398,6 +2460,8 @@ static void tegra_pcie_dw_shutdown(struct platform_device *pdev) if (!pcie->link_state && !pcie->slot_pluggable) return; + if (pcie->slot_pluggable) + unregister_gpio_hotplug_slot(&pcie->hp_slot); debugfs_remove_recursive(pcie->debugfs); tegra_pcie_downstream_dev_to_D0(pcie);