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[93.5.22.158]) by smtp.googlemail.com with ESMTPSA id d3-20020a5d6dc3000000b0022e3cba367fsm5473645wrz.100.2022.10.04.03.01.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Oct 2022 03:01:50 -0700 (PDT) From: Alexandre Mergnat Date: Tue, 04 Oct 2022 12:01:39 +0200 Subject: [PATCH v2 1/3] dt-bindings: iommu: mediatek: add binding documentation for MT8365 SoC MIME-Version: 1.0 Message-Id: <20221001-iommu-support-v2-1-dbfef2eeebc9@baylibre.com> References: <20221001-iommu-support-v2-0-dbfef2eeebc9@baylibre.com> In-Reply-To: <20221001-iommu-support-v2-0-dbfef2eeebc9@baylibre.com> To: Rob Herring , Yong Wu , Matthias Brugger , Will Deacon , Joerg Roedel , Robin Murphy , Krzysztof Kozlowski Cc: Alexandre Mergnat , linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Fabien Parent , Markus Schneider-Pargmann , Amjad Ouled-Ameur , devicetree@vger.kernel.org, iommu@lists.linux.dev X-Mailer: b4 0.10.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=6140; i=amergnat@baylibre.com; h=from:subject:message-id; bh=XDDgL/nAc/yVfhySRg5fQSvB2yy2X96A0sg/pLmBfiI=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBjPASLyCQhh1p5oK89+7HM/pTAZNpLHJaNLzqnTLyh dWFyDBKJAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCYzwEiwAKCRArRkmdfjHURbbQD/ sEYgF/OcVD0T6MVcho0PMKaPJP+jRHhjAf5V58c0Xj8x11F19pfUsLBNF+Eelo6nrSTKLMfC9lwycO ptrDCa1dndDR5yjBMma/JrrWUMosbE+imYC4q5VRicdJhbZYJ9OXlO+osTcO31OmSHhIc/5RTcnHav t3GjQDPr4Q/FAeXj7KottyXrRF9aMGUrWZyujgR3LyzTNa9sxSOpxXs48yVStPR/EKiCwq2zZc5ZfF eEZoIr2YMUUgXk97zFanU/s4Cr9hyxi5FLkG2AS38PWRCjAXWnzb6BTDNKA3xytFYN8Je15T+OavfQ fQvnoFy1ibQEOQewJo8jARMxvr25Yjw5Ebmdm2mrQkmlawk+PTciMpQpKXur7SWzfLeM2ps8zNpUWX 6CBrLqTXuWNS3HoYFVXzPs6dZl9x9g4Pd6WP9/Z5zv2kNNAnIqbaId++CDtzLNyJWSiglFoEPsmKLY RqfjNKm/EVlmivzNKSQDbXofkri276dKTKIFwO8F1WJ7j44PXy2alzMnSf0GxRPAhNw7Crd7KlN2S7 wL0NIQE/7qe1gyxNhP7xgqE38g7vxVJPJ4QhKTeWYi+FsG4+z5DT9F8nxbrSTFQ6gy0m2jB9Xn2Miq JCDrt+4yb+GHA/Z3hwA1OlbZqyZg1bJXzjvr7JK/iKR1wZ0qEcxo5puLFDfA== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221004_030154_776034_764AE807 X-CRM114-Status: GOOD ( 11.86 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org From: Fabien Parent Add IOMMU binding documentation for the MT8365 SoC. Signed-off-by: Fabien Parent Signed-off-by: Markus Schneider-Pargmann Signed-off-by: Alexandre Mergnat --- .../devicetree/bindings/iommu/mediatek,iommu.yaml | 2 + include/dt-bindings/memory/mt8365-larb-port.h | 90 ++++++++++++++++++++++ 2 files changed, 92 insertions(+) diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml index fee0241b5098..4b8cf3ce6963 100644 --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml @@ -81,6 +81,7 @@ properties: - mediatek,mt8195-iommu-vdo # generation two - mediatek,mt8195-iommu-vpp # generation two - mediatek,mt8195-iommu-infra # generation two + - mediatek,mt8365-m4u # generation two - description: mt7623 generation one items: @@ -130,6 +131,7 @@ properties: dt-binding/memory/mt8186-memory-port.h for mt8186, dt-binding/memory/mt8192-larb-port.h for mt8192. dt-binding/memory/mt8195-memory-port.h for mt8195. + dt-binding/memory/mt8365-larb-port.h for mt8365. power-domains: maxItems: 1 diff --git a/include/dt-bindings/memory/mt8365-larb-port.h b/include/dt-bindings/memory/mt8365-larb-port.h new file mode 100644 index 000000000000..56d5a5dd519e --- /dev/null +++ b/include/dt-bindings/memory/mt8365-larb-port.h @@ -0,0 +1,90 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Yong Wu + */ +#ifndef _DT_BINDINGS_MEMORY_MT8365_LARB_PORT_H_ +#define _DT_BINDINGS_MEMORY_MT8365_LARB_PORT_H_ + +#include + +#define M4U_LARB0_ID 0 +#define M4U_LARB1_ID 1 +#define M4U_LARB2_ID 2 +#define M4U_LARB3_ID 3 + +/* larb0 */ +#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0) +#define M4U_PORT_DISP_OVL0_2L MTK_M4U_ID(M4U_LARB0_ID, 1) +#define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 2) +#define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 3) +#define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB0_ID, 4) +#define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 5) +#define M4U_PORT_MDP_WROT1 MTK_M4U_ID(M4U_LARB0_ID, 6) +#define M4U_PORT_MDP_WROT0 MTK_M4U_ID(M4U_LARB0_ID, 7) +#define M4U_PORT_MDP_RDMA1 MTK_M4U_ID(M4U_LARB0_ID, 8) +#define M4U_PORT_DISP_FAKE0 MTK_M4U_ID(M4U_LARB0_ID, 9) +#define M4U_PORT_APU_READ MTK_M4U_ID(M4U_LARB0_ID, 10) +#define M4U_PORT_APU_WRITE MTK_M4U_ID(M4U_LARB0_ID, 11) + +/* larb1 */ +#define M4U_PORT_VENC_RCPU MTK_M4U_ID(M4U_LARB1_ID, 0) +#define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB1_ID, 1) +#define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB1_ID, 2) +#define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(M4U_LARB1_ID, 3) +#define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB1_ID, 4) +#define M4U_PORT_VENC_NBM_RDMA MTK_M4U_ID(M4U_LARB1_ID, 5) +#define M4U_PORT_VENC_NBM_RDMA_LITE MTK_M4U_ID(M4U_LARB1_ID, 6) +#define M4U_PORT_JPGENC_Y_RDMA MTK_M4U_ID(M4U_LARB1_ID, 7) +#define M4U_PORT_JPGENC_C_RDMA MTK_M4U_ID(M4U_LARB1_ID, 8) +#define M4U_PORT_JPGENC_Q_TABLE MTK_M4U_ID(M4U_LARB1_ID, 9) +#define M4U_PORT_JPGENC_BSDMA MTK_M4U_ID(M4U_LARB1_ID, 10) +#define M4U_PORT_JPGDEC_WDMA MTK_M4U_ID(M4U_LARB1_ID, 11) +#define M4U_PORT_JPGDEC_BSDMA MTK_M4U_ID(M4U_LARB1_ID, 12) +#define M4U_PORT_VENC_NBM_WDMA MTK_M4U_ID(M4U_LARB1_ID, 13) +#define M4U_PORT_VENC_NBM_WDMA_LITE MTK_M4U_ID(M4U_LARB1_ID, 14) +#define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB1_ID, 15) +#define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB1_ID, 16) +#define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB1_ID, 17) +#define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB1_ID, 18) + +/* larb2 */ +#define M4U_PORT_CAM_IMGO MTK_M4U_ID(M4U_LARB2_ID, 0) +#define M4U_PORT_CAM_RRZO MTK_M4U_ID(M4U_LARB2_ID, 1) +#define M4U_PORT_CAM_AAO MTK_M4U_ID(M4U_LARB2_ID, 2) +#define M4U_PORT_CAM_LCS MTK_M4U_ID(M4U_LARB2_ID, 3) +#define M4U_PORT_CAM_ESFKO MTK_M4U_ID(M4U_LARB2_ID, 4) +#define M4U_PORT_CAM_CAM_SV0 MTK_M4U_ID(M4U_LARB2_ID, 5) +#define M4U_PORT_CAM_CAM_SV1 MTK_M4U_ID(M4U_LARB2_ID, 6) +#define M4U_PORT_CAM_LSCI MTK_M4U_ID(M4U_LARB2_ID, 7) +#define M4U_PORT_CAM_LSCI_D MTK_M4U_ID(M4U_LARB2_ID, 8) +#define M4U_PORT_CAM_AFO MTK_M4U_ID(M4U_LARB2_ID, 9) +#define M4U_PORT_CAM_SPARE MTK_M4U_ID(M4U_LARB2_ID, 10) +#define M4U_PORT_CAM_BPCI MTK_M4U_ID(M4U_LARB2_ID, 11) +#define M4U_PORT_CAM_BPCI_D MTK_M4U_ID(M4U_LARB2_ID, 12) +#define M4U_PORT_CAM_UFDI MTK_M4U_ID(M4U_LARB2_ID, 13) +#define M4U_PORT_CAM_IMGI MTK_M4U_ID(M4U_LARB2_ID, 14) +#define M4U_PORT_CAM_IMG2O MTK_M4U_ID(M4U_LARB2_ID, 15) +#define M4U_PORT_CAM_IMG3O MTK_M4U_ID(M4U_LARB2_ID, 16) +#define M4U_PORT_CAM_WPE0_I MTK_M4U_ID(M4U_LARB2_ID, 17) +#define M4U_PORT_CAM_WPE1_I MTK_M4U_ID(M4U_LARB2_ID, 18) +#define M4U_PORT_CAM_WPE_O MTK_M4U_ID(M4U_LARB2_ID, 19) +#define M4U_PORT_CAM_FD0_I MTK_M4U_ID(M4U_LARB2_ID, 20) +#define M4U_PORT_CAM_FD1_I MTK_M4U_ID(M4U_LARB2_ID, 21) +#define M4U_PORT_CAM_FD0_O MTK_M4U_ID(M4U_LARB2_ID, 22) +#define M4U_PORT_CAM_FD1_O MTK_M4U_ID(M4U_LARB2_ID, 23) + +/* larb3 */ +#define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB3_ID, 0) +#define M4U_PORT_HW_VDEC_UFO_EXT MTK_M4U_ID(M4U_LARB3_ID, 1) +#define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB3_ID, 2) +#define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB3_ID, 3) +#define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB3_ID, 4) +#define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB3_ID, 5) +#define M4U_PORT_HW_VDEC_TILE_EXT MTK_M4U_ID(M4U_LARB3_ID, 6) +#define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB3_ID, 7) +#define M4U_PORT_HW_VDEC_VLD2_EXT MTK_M4U_ID(M4U_LARB3_ID, 8) +#define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB3_ID, 9) +#define M4U_PORT_HW_VDEC_RG_CTRL_DMA_EXT MTK_M4U_ID(M4U_LARB3_ID, 10) + +#endif From patchwork Tue Oct 4 10:01:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Mergnat X-Patchwork-Id: 12998098 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org 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[93.5.22.158]) by smtp.googlemail.com with ESMTPSA id d3-20020a5d6dc3000000b0022e3cba367fsm5473645wrz.100.2022.10.04.03.01.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Oct 2022 03:01:51 -0700 (PDT) From: Alexandre Mergnat Date: Tue, 04 Oct 2022 12:01:40 +0200 Subject: [PATCH v2 2/3] iommu/mediatek: add support for 6-bit encoded port IDs MIME-Version: 1.0 Message-Id: <20221001-iommu-support-v2-2-dbfef2eeebc9@baylibre.com> References: <20221001-iommu-support-v2-0-dbfef2eeebc9@baylibre.com> In-Reply-To: <20221001-iommu-support-v2-0-dbfef2eeebc9@baylibre.com> To: Rob Herring , Yong Wu , Matthias Brugger , Will Deacon , Joerg Roedel , Robin Murphy , Krzysztof Kozlowski Cc: Alexandre Mergnat , linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Fabien Parent , Markus Schneider-Pargmann , Amjad Ouled-Ameur , devicetree@vger.kernel.org, iommu@lists.linux.dev X-Mailer: b4 0.10.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=5941; i=amergnat@baylibre.com; h=from:subject:message-id; bh=poDJT7kVKFCzuP8AS6+Z3lQvstHhtNzhwUfS9ADL8m4=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBjPASLI0qNjwoycoxtw2YRuYwQznnVA/L5C8e/1O4T 02ghUbSJAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCYzwEiwAKCRArRkmdfjHURb58EA ChJ/5F8pJnAY3CQAUrbkpRveMzBQsCluotHM8KtXwhDs4gtosZR3gf6RPP5+5x5qcUBNMtHwGgLgKc 3joMrEMg0ngf/4WdW2YYFCCuqICFSE8Xd6SzMnL5vEzyFrEjNoal7JMJuA9VGr+GQArokXZg+jJMGg g8Yuh5c97+8A85+nW37YPp29LDFxxwzP7v0qLLl4bU3ek1ETq53ElHUs3dVRLEb+emUDMMdbJGuR5S UbZsueoscrsUdrIexC3oO86wb9Y/z3/isevvk7yoGdH+q2stTFD0HY1CKFV8v9dLSHvbNOvfasQAbx /RCmoNSu9D6ranJFiNklbNnESct4j2G0yLNOvc3JjJn8+MaBpljYnAOgZxzZF1O+cSKTdRZXM8jXsG uUof2xTYE2DCUR0mR6QrbulBzjFVUKWXSS09kMMou3t8t/VXyv6wVC83mM8obD0hQvzoMtZqISWsYc N6oqtC354yZWm916frLQJ/kZ9TlxnqBTiVr5VBk6/Oh13BqQ7SxWS3u24EMit5+6OXSWHI4oaLnt4+ vGWAhHgqRiH2nYE78srZbXBFE2QLugPudyjjj5QQyjbGTwdEIZeL1QPRRjrDvjguKDtW/K/myNm3Re dlnCHWpX+N4nR5xIn2B6/sZGgRrZz0wfRoHwojsIA6rjTccpGJOSTr2hrXIQ== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221004_030155_253014_72C15E78 X-CRM114-Status: GOOD ( 14.97 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org From: Fabien Parent Until now the port ID was always encoded as a 5-bit data. On MT8365, the port ID is encoded as a 6-bit data. This requires to rework the macros F_MMU_INT_ID_LARB_ID, and F_MMU_INT_ID_PORT_ID in order to support 5-bit and 6-bit encoded port IDs. Signed-off-by: Fabien Parent Signed-off-by: Markus Schneider-Pargmann Signed-off-by: Alexandre Mergnat --- drivers/iommu/mtk_iommu.c | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index 5a4e00e4bbbc..a57ce509c8b5 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -108,8 +108,10 @@ #define F_MMU_INT_ID_SUB_COMM_ID(a) (((a) >> 7) & 0x3) #define F_MMU_INT_ID_COMM_ID_EXT(a) (((a) >> 10) & 0x7) #define F_MMU_INT_ID_SUB_COMM_ID_EXT(a) (((a) >> 7) & 0x7) -#define F_MMU_INT_ID_LARB_ID(a) (((a) >> 7) & 0x7) -#define F_MMU_INT_ID_PORT_ID(a) (((a) >> 2) & 0x1f) +#define F_MMU_INT_ID_LARB_ID(a, int_id_port_width) \ + ((a) >> (((int_id_port_width) + 2) & 0x7)) +#define F_MMU_INT_ID_PORT_ID(a, int_id_port_width) \ + (((a) >> 2) & GENMASK((int_id_port_width) - 1, 0)) #define MTK_PROTECT_PA_ALIGN 256 #define MTK_IOMMU_BANK_SZ 0x1000 @@ -188,6 +190,7 @@ struct mtk_iommu_plat_data { enum mtk_iommu_plat m4u_plat; u32 flags; u32 inv_sel_reg; + u8 int_id_port_width; char *pericfg_comp_str; struct list_head *hw_list; @@ -441,7 +444,8 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id) fault_pa |= (u64)pa34_32 << 32; if (MTK_IOMMU_IS_TYPE(plat_data, MTK_IOMMU_TYPE_MM)) { - fault_port = F_MMU_INT_ID_PORT_ID(regval); + fault_port = F_MMU_INT_ID_PORT_ID(regval, + data->plat_data->int_id_port_width); if (MTK_IOMMU_HAS_FLAG(plat_data, HAS_SUB_COMM_2BITS)) { fault_larb = F_MMU_INT_ID_COMM_ID(regval); sub_comm = F_MMU_INT_ID_SUB_COMM_ID(regval); @@ -449,7 +453,8 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id) fault_larb = F_MMU_INT_ID_COMM_ID_EXT(regval); sub_comm = F_MMU_INT_ID_SUB_COMM_ID_EXT(regval); } else { - fault_larb = F_MMU_INT_ID_LARB_ID(regval); + fault_larb = F_MMU_INT_ID_LARB_ID( + regval, data->plat_data->int_id_port_width); } fault_larb = data->plat_data->larbid_remap[fault_larb][sub_comm]; } @@ -1379,6 +1384,7 @@ static const struct mtk_iommu_plat_data mt2712_data = { .banks_enable = {true}, .iova_region_nr = ARRAY_SIZE(single_domain), .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}, {6}, {7}}, + .int_id_port_width = 5, }; static const struct mtk_iommu_plat_data mt6779_data = { @@ -1391,6 +1397,7 @@ static const struct mtk_iommu_plat_data mt6779_data = { .iova_region = single_domain, .iova_region_nr = ARRAY_SIZE(single_domain), .larbid_remap = {{0}, {1}, {2}, {3}, {5}, {7, 8}, {10}, {9}}, + .int_id_port_width = 5, }; static const struct mtk_iommu_plat_data mt6795_data = { @@ -1404,6 +1411,7 @@ static const struct mtk_iommu_plat_data mt6795_data = { .iova_region = single_domain, .iova_region_nr = ARRAY_SIZE(single_domain), .larbid_remap = {{0}, {1}, {2}, {3}, {4}}, /* Linear mapping. */ + .int_id_port_width = 5, }; static const struct mtk_iommu_plat_data mt8167_data = { @@ -1415,6 +1423,7 @@ static const struct mtk_iommu_plat_data mt8167_data = { .iova_region = single_domain, .iova_region_nr = ARRAY_SIZE(single_domain), .larbid_remap = {{0}, {1}, {2}}, /* Linear mapping. */ + .int_id_port_width = 5, }; static const struct mtk_iommu_plat_data mt8173_data = { @@ -1428,6 +1437,7 @@ static const struct mtk_iommu_plat_data mt8173_data = { .iova_region = single_domain, .iova_region_nr = ARRAY_SIZE(single_domain), .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}}, /* Linear mapping. */ + .int_id_port_width = 5, }; static const struct mtk_iommu_plat_data mt8183_data = { @@ -1439,6 +1449,7 @@ static const struct mtk_iommu_plat_data mt8183_data = { .iova_region = single_domain, .iova_region_nr = ARRAY_SIZE(single_domain), .larbid_remap = {{0}, {4}, {5}, {6}, {7}, {2}, {3}, {1}}, + .int_id_port_width = 5, }; static const struct mtk_iommu_plat_data mt8186_data_mm = { @@ -1453,6 +1464,7 @@ static const struct mtk_iommu_plat_data mt8186_data_mm = { .banks_enable = {true}, .iova_region = mt8192_multi_dom, .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom), + .int_id_port_width = 5, }; static const struct mtk_iommu_plat_data mt8192_data = { @@ -1466,6 +1478,7 @@ static const struct mtk_iommu_plat_data mt8192_data = { .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom), .larbid_remap = {{0}, {1}, {4, 5}, {7}, {2}, {9, 11, 19, 20}, {0, 14, 16}, {0, 13, 18, 17}}, + .int_id_port_width = 5, }; static const struct mtk_iommu_plat_data mt8195_data_infra = { @@ -1481,6 +1494,7 @@ static const struct mtk_iommu_plat_data mt8195_data_infra = { }, .iova_region = single_domain, .iova_region_nr = ARRAY_SIZE(single_domain), + .int_id_port_width = 5, }; static const struct mtk_iommu_plat_data mt8195_data_vdo = { @@ -1495,6 +1509,7 @@ static const struct mtk_iommu_plat_data mt8195_data_vdo = { .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom), .larbid_remap = {{2, 0}, {21}, {24}, {7}, {19}, {9, 10, 11}, {13, 17, 15/* 17b */, 25}, {5}}, + .int_id_port_width = 5, }; static const struct mtk_iommu_plat_data mt8195_data_vpp = { @@ -1513,6 +1528,7 @@ static const struct mtk_iommu_plat_data mt8195_data_vpp = { /* 16: 16a; 29: 16b; 30: CCUtop0; 31: CCUtop1 */ {14, 16, 29, 26, 30, 31, 18}, {4, MTK_INVALID_LARBID, MTK_INVALID_LARBID, MTK_INVALID_LARBID, 6}}, + .int_id_port_width = 5, }; static const struct of_device_id mtk_iommu_of_ids[] = { From patchwork Tue Oct 4 10:01:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Mergnat X-Patchwork-Id: 12998097 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D4CBEC433FE for ; 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[93.5.22.158]) by smtp.googlemail.com with ESMTPSA id d3-20020a5d6dc3000000b0022e3cba367fsm5473645wrz.100.2022.10.04.03.01.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Oct 2022 03:01:52 -0700 (PDT) From: Alexandre Mergnat Date: Tue, 04 Oct 2022 12:01:41 +0200 Subject: [PATCH v2 3/3] iommu/mediatek: add support for MT8365 SoC MIME-Version: 1.0 Message-Id: <20221001-iommu-support-v2-3-dbfef2eeebc9@baylibre.com> References: <20221001-iommu-support-v2-0-dbfef2eeebc9@baylibre.com> In-Reply-To: <20221001-iommu-support-v2-0-dbfef2eeebc9@baylibre.com> To: Rob Herring , Yong Wu , Matthias Brugger , Will Deacon , Joerg Roedel , Robin Murphy , Krzysztof Kozlowski Cc: Alexandre Mergnat , linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Fabien Parent , Markus Schneider-Pargmann , Amjad Ouled-Ameur , devicetree@vger.kernel.org, iommu@lists.linux.dev X-Mailer: b4 0.10.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=1834; i=amergnat@baylibre.com; h=from:subject:message-id; bh=gxfKtOcvwaqvfxbBFQC1V9d4zYH8j2MMwYTDkwSvA64=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBjPASL1Deu6Z2zUrYCapL6mHfzitqM2lCpSojrm1ZA FReZPU+JAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCYzwEiwAKCRArRkmdfjHURZUGD/ 9O7uNTCvNAEKKImI7SsasH1T+l0x/ce701ne1kIqklNfeP/U44HmutCEmxEUnam83dDuM8705t9l1T nFpn8NIAvLZ+pxn1+UuBHimCFs8R+CzPaMBQbeX9moANniY0a8UjHDwr1BrTfxyJeooP9nnwatyqwh YK1X2Kdzv0sv4QLz3vdC8DUBjDD4/82gDc4qfN3mQmsbneZR4NU8BMXd+NNoP0p6voRIvVoj9KEibU 4l+6w+WPpLziPQPUhLYNs/WsDOWrg67S/pU/AhSgXYKoAm6/SnasDMc4M0AndwCVnnVAkYR9nqBB38 iDeeZKXzPp27BFvkUi07tkywwGknAG7Io7byvmyP28wDWoDvJGWsV4vY6kMdBMumxa4RbyjyIm63vR 6lo2acvS6CRUkx9QtWWsCQDhItHwqKUec5Hia2xidfFEmWy1j42jdBm29FHJXLOewfXNz1lga+bjsK 7aX2h7ZevTDEq+1k1nD9YuFYTRcXFiTGVgkPO0qDPH+6HIfMv7+u593LPpef/AQRk+86zUDnFPDvOj MG+en9irRvaumGU+vnwdhEGhaz2iRfxpTN7oZoeSbyZE1DGfSmsEjkkNP3tZZbGXplI8yq1bMMdF5/ U+TAiTFa4DRPmXssdkT/K3LORzI2RN1rctlJabAVBHirP3hQp1lamp91EWBA== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221004_030154_809369_ED88F40B X-CRM114-Status: GOOD ( 10.52 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org From: Fabien Parent Add IOMMU support for MT8365 SoC. Signed-off-by: Fabien Parent Reviewed-by: Amjad Ouled-Ameur Tested-by: Amjad Ouled-Ameur Signed-off-by: Markus Schneider-Pargmann Signed-off-by: Alexandre Mergnat Reviewed-by: AngeloGioacchino Del Regno --- drivers/iommu/mtk_iommu.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index a57ce509c8b5..ce8c9660208e 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -167,6 +167,7 @@ enum mtk_iommu_plat { M4U_MT8186, M4U_MT8192, M4U_MT8195, + M4U_MT8365, }; struct mtk_iommu_iova_region { @@ -1531,6 +1532,18 @@ static const struct mtk_iommu_plat_data mt8195_data_vpp = { .int_id_port_width = 5, }; +static const struct mtk_iommu_plat_data mt8365_data = { + .m4u_plat = M4U_MT8365, + .flags = RESET_AXI, + .inv_sel_reg = REG_MMU_INV_SEL_GEN1, + .banks_num = 1, + .banks_enable = {true}, + .iova_region = single_domain, + .iova_region_nr = ARRAY_SIZE(single_domain), + .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}}, /* Linear mapping. */ + .int_id_port_width = 6, +}; + static const struct of_device_id mtk_iommu_of_ids[] = { { .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data}, { .compatible = "mediatek,mt6779-m4u", .data = &mt6779_data}, @@ -1543,6 +1556,7 @@ static const struct of_device_id mtk_iommu_of_ids[] = { { .compatible = "mediatek,mt8195-iommu-infra", .data = &mt8195_data_infra}, { .compatible = "mediatek,mt8195-iommu-vdo", .data = &mt8195_data_vdo}, { .compatible = "mediatek,mt8195-iommu-vpp", .data = &mt8195_data_vpp}, + { .compatible = "mediatek,mt8365-m4u", .data = &mt8365_data}, {} };