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Tue, 4 Oct 2022 21:15:16 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT063.mail.protection.outlook.com (10.13.177.110) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5709.10 via Frontend Transport; Tue, 4 Oct 2022 21:15:16 +0000 Received: from dev.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Tue, 4 Oct 2022 16:15:14 -0500 From: Alex Hung To: , Subject: [RFC PATCH 1/5] drm: Add 3D LUT mode and its attributes Date: Tue, 4 Oct 2022 15:14:47 -0600 Message-ID: <20221004211451.1475215-2-alex.hung@amd.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221004211451.1475215-1-alex.hung@amd.com> References: <20221004211451.1475215-1-alex.hung@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT063:EE_|BL3PR12MB6380:EE_ X-MS-Office365-Filtering-Correlation-Id: 0aabb7ed-9510-4868-e060-08daa64d88a6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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CAT:NONE; SFS:(13230022)(4636009)(376002)(39860400002)(136003)(346002)(396003)(451199015)(40470700004)(46966006)(36840700001)(54906003)(110136005)(82310400005)(478600001)(86362001)(44832011)(70586007)(41300700001)(8676002)(5660300002)(36756003)(316002)(40480700001)(8936002)(4326008)(70206006)(356005)(36860700001)(16526019)(1076003)(82740400003)(40460700003)(81166007)(186003)(6666004)(2616005)(7696005)(336012)(26005)(47076005)(426003)(2906002)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Oct 2022 21:15:16.0895 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0aabb7ed-9510-4868-e060-08daa64d88a6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT063.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR12MB6380 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mwen@igalia.com, bhawanpreet.lakha@amd.com, Alex Hung Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" A struct is defined for 3D LUT modes to be supported by hardware. The elements includes lut_isze, lut_stride, bit_depth, color_format and flags. Note: A patchset "IGT tests for pre-blending 3D LUT interfaces" for this proposal is sent to IGT mailing list. Signed-off-by: Alex Hung --- include/uapi/drm/drm_mode.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h index d0ce48d2e732..334e8a9b49cc 100644 --- a/include/uapi/drm/drm_mode.h +++ b/include/uapi/drm/drm_mode.h @@ -877,6 +877,23 @@ struct drm_color_lut_ext { __u64 reserved; }; +/* + * struct drm_mode_3dlut_mode - 3D LUT mode information. + * @lut_size: number of valid points on every dimension of 3D LUT. + * @lut_stride: number of points on every dimension of 3D LUT. + * @bit_depth: number of bits of RGB. If color_mode defines entries with higher + * bit_depth the least significant bits will be truncated. + * @color_format: fourcc values, ex. DRM_FORMAT_XRGB16161616 or DRM_FORMAT_XBGR16161616. + * @flags: flags for hardware-sepcific features + */ +struct drm_mode_3dlut_mode { + __u16 lut_size; + __u16 lut_stride[3]; + __u16 bit_depth; + __u32 color_format; + __u32 flags; +}; + #define DRM_MODE_PAGE_FLIP_EVENT 0x01 #define DRM_MODE_PAGE_FLIP_ASYNC 0x02 #define DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE 0x4 From patchwork Tue Oct 4 21:14:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Hung X-Patchwork-Id: 12998688 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B7957C433FE for ; Tue, 4 Oct 2022 21:15:46 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 98D9310E175; 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Tue, 4 Oct 2022 16:15:26 -0500 From: Alex Hung To: , Subject: [RFC PATCH 2/5] drm: Add Plane 3DLUT and 3DLUT mode properties Date: Tue, 4 Oct 2022 15:14:48 -0600 Message-ID: <20221004211451.1475215-3-alex.hung@amd.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221004211451.1475215-1-alex.hung@amd.com> References: <20221004211451.1475215-1-alex.hung@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT099:EE_|LV2PR12MB5728:EE_ X-MS-Office365-Filtering-Correlation-Id: aa37bec4-da73-4537-2123-08daa64d93f7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: K7e0NXhsh/ZCP4t4/zE8vE2zQgePMlHo77gBnmnsVAO5q4qib+677woHVBBYqirAxDoBMA1uOAkT5/1IWBV9ZwVhttrZqPdtM5tstbd9MRgWgD9yyKMY4SJ8XLVt9BH7ISbreve2VepcQwUpUCR3ZFsRXBvV79aKXv7qt/1TbDADyvXgFXa+Rn8wV1r091mKmQarALNdIBsgd3Sw6V6QBu4BmddI37JAYz41EqgYeq8AHdL+GoEEfcx9cEjwT/k/wymkxHqOGkA3WNqf7TsIHgV/avnmtSSCXm+aVodZ1WgUdA+i9rbIW6bYxRdCUBJeD9fHbX+RREOOlCLJ0+YSGgauvUzmfaAgHpwgqdN8z0B3d1IdNqXGa/KsnDaFp9OewAPsjC/0Rxzg06AfdTaAm1HSzoNK/KGC8ixdpItk4pU9JX1M6045O2h4WFPEalaKzvOehVtqpM1j8pSHsC97/TQwmdQNAc5DR5jaR3aIrjWOhwt1XCRb+H7u1IlvgPU+DzDPjXRCRWLrlAgZIEGNInAdbGwN4V2XHdx7sWnxJJJk1RT+tO+JxDkNB5s7LVJh65WkWuJjnf5cvrpLqe+p4Qk7UhvpBJHo/qPqB8cV234UvHcRrBZTr7+QOFwff/tKoUHd7xGojEI02mQnBq+iEiv8m8AVpFdSCf1xSg1M8dNHJiJm98QjGS/r7FexHCRwSoEtA7daHNQQrXylKTn/KcehTlHCgzEGN5XoVS7D6atyIlob5M5vgp8hiPwH58zv3cCEWXxKDne/1idCuSyGexU5326RXWOD3bJt9VZy51Gfn5eGsvydCopckW4kCm1A X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230022)(4636009)(376002)(39860400002)(136003)(396003)(346002)(451199015)(40470700004)(36840700001)(46966006)(82740400003)(16526019)(70586007)(40460700003)(81166007)(8676002)(2616005)(356005)(70206006)(186003)(426003)(40480700001)(478600001)(6666004)(336012)(1076003)(47076005)(36756003)(7696005)(36860700001)(316002)(4326008)(54906003)(26005)(86362001)(110136005)(82310400005)(83380400001)(2906002)(44832011)(41300700001)(5660300002)(8936002)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Oct 2022 21:15:35.0392 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: aa37bec4-da73-4537-2123-08daa64d93f7 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT099.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5728 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mwen@igalia.com, bhawanpreet.lakha@amd.com, Alex Hung Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add plane lut_3d mode and lut_3d as blob properties. lut_3d mode is an enum property with values as blob_ids. Userspace can get supported modes and also set one of the modes. Note: A patchset "IGT tests for pre-blending 3D LUT interfaces" for this proposal is sent to IGT mailing list. Signed-off-by: Alex Hung --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++ drivers/gpu/drm/drm_atomic_state_helper.c | 3 ++ drivers/gpu/drm/drm_atomic_uapi.c | 11 ++++++ drivers/gpu/drm/drm_color_mgmt.c | 37 +++++++++++++++++++ include/drm/drm_mode_object.h | 2 +- include/drm/drm_plane.h | 31 ++++++++++++++++ 6 files changed, 87 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index f546c1326db3..ee277f357140 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -8006,6 +8006,10 @@ static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, drm_plane_attach_gamma_properties(plane); drm_plane_attach_ctm_property(plane); + /* TODO need to check ASICs */ + drm_plane_create_3d_lut_properties(plane->dev, plane, 1); + drm_plane_attach_3dlut_properties(plane); + /* Create (reset) the plane state */ if (plane->funcs->reset) plane->funcs->reset(plane); diff --git a/drivers/gpu/drm/drm_atomic_state_helper.c b/drivers/gpu/drm/drm_atomic_state_helper.c index 7ddf6e4b956b..85900cd1bffe 100644 --- a/drivers/gpu/drm/drm_atomic_state_helper.c +++ b/drivers/gpu/drm/drm_atomic_state_helper.c @@ -318,6 +318,8 @@ void __drm_atomic_helper_plane_duplicate_state(struct drm_plane *plane, drm_property_blob_get(state->ctm); if (state->gamma_lut) drm_property_blob_get(state->gamma_lut); + if (state->lut_3d) + drm_property_blob_get(state->lut_3d); state->color_mgmt_changed = false; } @@ -369,6 +371,7 @@ void __drm_atomic_helper_plane_destroy_state(struct drm_plane_state *state) drm_property_blob_put(state->degamma_lut); drm_property_blob_put(state->ctm); drm_property_blob_put(state->gamma_lut); + drm_property_blob_put(state->lut_3d); } EXPORT_SYMBOL(__drm_atomic_helper_plane_destroy_state); diff --git a/drivers/gpu/drm/drm_atomic_uapi.c b/drivers/gpu/drm/drm_atomic_uapi.c index ba3e64cb184a..66e59e7c194d 100644 --- a/drivers/gpu/drm/drm_atomic_uapi.c +++ b/drivers/gpu/drm/drm_atomic_uapi.c @@ -622,6 +622,13 @@ static int drm_atomic_plane_set_property(struct drm_plane *plane, &replaced); state->color_mgmt_changed |= replaced; return ret; + } else if (property == plane->lut_3d_property) { + ret = drm_atomic_replace_property_blob_from_id(dev, + &state->lut_3d, val, -1, 8, &replaced); + state->color_mgmt_changed |= replaced; + return 0; + } else if (property == plane->lut_3d_mode_property) { + state->lut_3d_mode = val; } else if (property == config->prop_fb_damage_clips) { ret = drm_atomic_replace_property_blob_from_id(dev, &state->fb_damage_clips, @@ -700,6 +707,10 @@ drm_atomic_plane_get_property(struct drm_plane *plane, } else if (property == plane->gamma_lut_property) { *val = (state->gamma_lut) ? state->gamma_lut->base.id : 0; + } else if (property == plane->lut_3d_property) { + *val = (state->lut_3d) ? state->lut_3d->base.id : 0; + } else if (property == plane->lut_3d_mode_property) { + *val = state->lut_3d_mode; } else if (property == config->prop_fb_damage_clips) { *val = (state->fb_damage_clips) ? state->fb_damage_clips->base.id : 0; diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c index b5b3ff7f654d..4bfe5b5c9670 100644 --- a/drivers/gpu/drm/drm_color_mgmt.c +++ b/drivers/gpu/drm/drm_color_mgmt.c @@ -706,6 +706,43 @@ void drm_plane_attach_gamma_properties(struct drm_plane *plane) } EXPORT_SYMBOL(drm_plane_attach_gamma_properties); +int drm_plane_create_3d_lut_properties(struct drm_device *dev, + struct drm_plane *plane, + int num_values) +{ + struct drm_property *mode; + struct drm_property *blob; + + mode = drm_property_create(dev, DRM_MODE_PROP_ENUM, "PLANE_3D_LUT_MODE", num_values); + if (!mode) + return -ENOMEM; + + plane->lut_3d_mode_property = mode; + + blob = drm_property_create(dev, DRM_MODE_PROP_BLOB, "PLANE_3D_LUT", 0); + if (!blob) + return -ENOMEM; + + plane->lut_3d_property = blob; + + return 0; +} +EXPORT_SYMBOL(drm_plane_create_3d_lut_properties); + +void drm_plane_attach_3dlut_properties(struct drm_plane *plane) +{ + if (!plane->lut_3d_property) + return; + + drm_object_attach_property(&plane->base, plane->lut_3d_property, 0); + + if (!plane->lut_3d_mode_property) + return; + + drm_object_attach_property(&plane->base, plane->lut_3d_mode_property, 0); +} +EXPORT_SYMBOL(drm_plane_attach_3dlut_properties); + int drm_plane_color_add_gamma_degamma_mode_range(struct drm_plane *plane, const char *name, const struct drm_color_lut_range *ranges, diff --git a/include/drm/drm_mode_object.h b/include/drm/drm_mode_object.h index d4128c7daa08..c2b31dbf7325 100644 --- a/include/drm/drm_mode_object.h +++ b/include/drm/drm_mode_object.h @@ -60,7 +60,7 @@ struct drm_mode_object { void (*free_cb)(struct kref *kref); }; -#define DRM_OBJECT_MAX_PROPERTY 26 +#define DRM_OBJECT_MAX_PROPERTY 28 /** * struct drm_object_properties - property tracking for &drm_mode_object */ diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h index 8989bb1aa46c..4e272144170f 100644 --- a/include/drm/drm_plane.h +++ b/include/drm/drm_plane.h @@ -275,6 +275,21 @@ struct drm_plane_state { */ struct drm_property_blob *gamma_lut; + /** + * @lut_3d_mode: + * This is a blob_id and exposes the platform capabilities wrt + * various 3dlut. This also helps user select a 3dlut mode amongst + * the supported ones. + */ + u32 lut_3d_mode; + + /** + * @lut_3d: + * 3D lookup table blob. The blob data is laid out as defined by the + * FOURCC value in color_format in the drm_mode_3dlut_mode struct. + */ + struct drm_property_blob *lut_3d; + u8 color_mgmt_changed : 1; }; @@ -818,6 +833,18 @@ struct drm_plane { * used to convert the framebuffer's colors to non-linear gamma. */ struct drm_property *gamma_lut_property; + + /** + * @lut_3d_mode_property: Optional Plane property to set the 3DLUT mode + * used to convert the framebuffer's colors to non-linear gamma. + */ + struct drm_property *lut_3d_mode_property; + + /** + * @lut_3d_property: Optional Plane property to set the 3DLUT + * used to convert the framebuffer's colors to non-linear gamma. + */ + struct drm_property *lut_3d_property; }; #define obj_to_plane(x) container_of(x, struct drm_plane, base) @@ -915,6 +942,10 @@ int drm_plane_create_color_mgmt_properties(struct drm_device *dev, void drm_plane_attach_degamma_properties(struct drm_plane *plane); void drm_plane_attach_ctm_property(struct drm_plane *plane); void drm_plane_attach_gamma_properties(struct drm_plane *plane); +int drm_plane_create_3d_lut_properties(struct drm_device *dev, + struct drm_plane *plane, + int num_values); +void drm_plane_attach_3dlut_properties(struct drm_plane *plane); int drm_plane_color_add_gamma_degamma_mode_range(struct drm_plane *plane, const char *name, const struct drm_color_lut_range *ranges, From patchwork Tue Oct 4 21:14:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Hung X-Patchwork-Id: 12998689 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1CC7FC4332F for ; Tue, 4 Oct 2022 21:15:53 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7964B10E173; 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Tue, 4 Oct 2022 16:15:38 -0500 From: Alex Hung To: , Subject: [RFC PATCH 3/5] drm/amd/display: Define 3D LUT struct for HDR planes Date: Tue, 4 Oct 2022 15:14:49 -0600 Message-ID: <20221004211451.1475215-4-alex.hung@amd.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221004211451.1475215-1-alex.hung@amd.com> References: <20221004211451.1475215-1-alex.hung@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT091:EE_|SA1PR12MB7247:EE_ X-MS-Office365-Filtering-Correlation-Id: a15425ae-c8e6-4fe0-e466-08daa64d96c1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: hgUWk5ugej0AIY47OlZJDKICursRyYjQImnsZitSLy4+smLdCUV1YPJnhRmSmr7vJeGZomC025DIKNzhmCukVs+we0jX9OfYh9AXMJRmFdpSKwDPKEUlC6nBCLIeSk1I6t/tJU22IwMP//9DeskrP/XYqGenJXHasSJRg2lFUPxES6MUN4ZMShuEXSdsKjz0Aa3wjf4ycZ/9dtZ6I9MNnZ/IfqLkzyFXVdlAfmKRcXBeeswOujICHU9zX2fdwEDoEA5WfF27fSVfcVoSLMw4d235iRLDpwQQkLG8cxMlU2I3e3ubzT841Xhr0F1v3Jic8XI+oJ6ev91rupY2WIruxLizpCcyCWWlfWayhvfllmvCFZueWYiAy6oaIKYU4bvrDCefWqshjKou49j75x7HWXtD0EvXQOXe+E6aqyGu5hVwrwYPRkb6PEiqrn9epF98aNf5srljYoyki4RyExF86vYFfVCL8wwczejkR+cBkViyaypjHCrTGfeXsJcCrV2jfsHAlzt7j1Bv7U+z1k8IRLuqUapAOepPn4paYuIl3ny9kCPRzbDWa9Z8Luv+4rg1CMTocN9y5snzP7TYU4oEVZ17W7rLFaBuiGE0hdwTb6vprPxFqoK2BnTOs/mpm4dm3VFrvVJnL8hO2ocMa2Y+yrCmo4kMUr+omOT2sKlCCcnjrac2fSqQ6ZINOYdxlCzr2zMgM9f2NGXUUMIrC31GtH7Mei8oj7khHYOucv58qYEVRkAZ482zk5e1ZeuGNB8YCyqsL/xPRF9GvWVdBjXmmaxGP7eh0yWHe/u/kcPGknDnRldu8DD5e8E/NwfZoBSc X-Forefront-Antispam-Report: CIP:165.204.84.17; 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Note: A patchset "IGT tests for pre-blending 3D LUT interfaces" for this proposal is sent to IGT mailing list. Signed-off-by: Alex Hung --- .../gpu/drm/amd/display/modules/color/color_gamma.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.h b/drivers/gpu/drm/amd/display/modules/color/color_gamma.h index e06e0a8effc8..aceb23b03a4b 100644 --- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.h +++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.h @@ -27,6 +27,7 @@ #define COLOR_MOD_COLOR_GAMMA_H_ #include "color_table.h" +#include struct dc_transfer_func; struct dc_gamma; @@ -35,6 +36,17 @@ struct dc_rgb_fixed; struct dc_color_caps; enum dc_transfer_func_predefined; +/* + * 3D LUT mode for 17x17x17 LUT and 12 bits of color depth + */ +static const struct drm_mode_3dlut_mode lut_3d_mode_17_12bit = { + .lut_size = 17, + .lut_stride = {17, 17, 18}, + .bit_depth = 12, + .color_format = DRM_FORMAT_XRGB16161616, + .flags = 0, +}; + static const struct drm_color_lut_range nonlinear_pwl[] = { { .flags = (DRM_MODE_LUT_GAMMA | DRM_MODE_LUT_REFLECT_NEGATIVE | DRM_MODE_LUT_INTERPOLATE | DRM_MODE_LUT_REUSE_LAST | DRM_MODE_LUT_NON_DECREASING), From patchwork Tue Oct 4 21:14:50 2022 Content-Type: text/plain; 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Note: A patchset "IGT tests for pre-blending 3D LUT interfaces" for this proposal is sent to IGT mailing list. Signed-off-by: Alex Hung --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++ drivers/gpu/drm/drm_color_mgmt.c | 31 +++++++++++++++++++ include/drm/drm_plane.h | 2 ++ 3 files changed, 36 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index ee277f357140..7094578a683f 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -8008,6 +8008,9 @@ static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, /* TODO need to check ASICs */ drm_plane_create_3d_lut_properties(plane->dev, plane, 1); + res = drm_plane_color_add_3dlut_mode(plane, "3dlut_17_12bit", &lut_3d_mode_17_12bit, sizeof(lut_3d_mode_17_12bit)); + if (res) + return res; drm_plane_attach_3dlut_properties(plane); /* Create (reset) the plane state */ diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c index 4bfe5b5c9670..5418ca24db73 100644 --- a/drivers/gpu/drm/drm_color_mgmt.c +++ b/drivers/gpu/drm/drm_color_mgmt.c @@ -743,6 +743,37 @@ void drm_plane_attach_3dlut_properties(struct drm_plane *plane) } EXPORT_SYMBOL(drm_plane_attach_3dlut_properties); +int drm_plane_color_add_3dlut_mode(struct drm_plane *plane, + const char *name, + const struct drm_mode_3dlut_mode *mode_3dlut, + size_t length) +{ + struct drm_property_blob *blob; + struct drm_property *prop = NULL; + int ret; + + prop = plane->lut_3d_mode_property; + + if (!prop) + return -EINVAL; + + if (length == 0 && name) + return drm_property_add_enum(prop, 0, name); + + blob = drm_property_create_blob(plane->dev, length, mode_3dlut); + if (IS_ERR(blob)) + return PTR_ERR(blob); + + ret = drm_property_add_enum(prop, blob->base.id, name); + if (ret) { + drm_property_blob_put(blob); + return ret; + } + + return 0; +} +EXPORT_SYMBOL(drm_plane_color_add_3dlut_mode); + int drm_plane_color_add_gamma_degamma_mode_range(struct drm_plane *plane, const char *name, const struct drm_color_lut_range *ranges, diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h index 4e272144170f..f94f91466675 100644 --- a/include/drm/drm_plane.h +++ b/include/drm/drm_plane.h @@ -946,6 +946,8 @@ int drm_plane_create_3d_lut_properties(struct drm_device *dev, struct drm_plane *plane, int num_values); void drm_plane_attach_3dlut_properties(struct drm_plane *plane); +int drm_plane_color_add_3dlut_mode(struct drm_plane *plane, const char *name, + const struct drm_mode_3dlut_mode *mode_3dlut, size_t length); int drm_plane_color_add_gamma_degamma_mode_range(struct drm_plane *plane, const char *name, const struct drm_color_lut_range *ranges, From patchwork Tue Oct 4 21:14:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Hung X-Patchwork-Id: 12998691 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4A14AC433F5 for ; Tue, 4 Oct 2022 21:16:11 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9099610E182; 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Tue, 4 Oct 2022 16:16:02 -0500 From: Alex Hung To: , Subject: [RFC PATCH 5/5] drm/amd/display: Fill 3D LUT from userspace Date: Tue, 4 Oct 2022 15:14:51 -0600 Message-ID: <20221004211451.1475215-6-alex.hung@amd.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221004211451.1475215-1-alex.hung@amd.com> References: <20221004211451.1475215-1-alex.hung@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT091:EE_|PH7PR12MB7282:EE_ X-MS-Office365-Filtering-Correlation-Id: 228564bc-9456-42e1-590c-08daa64da4fa X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 0aTQ4g3m9Mctvk7YOUAQapp5MNsokv1sEeDIXp9xc3yr4KaM7L6JPWKWeUTy+ac62hosr3O64AJRKJ8BWSDrrz1aPFQSNETNg3wlSz/JXL4FPhpS7pMYax/8QVvzalz2VYLk/CEljyPkmcnkOvgVOItAhwG8792B9F3dVncY49TYNOCZXxD8ZhzfFWnlEfGwex7daJxSQh/PhNcPaGZI0gqKzO4BQ0u9vG7SwX1pAKO9vltWWTif2kZiKo34SLDusIrwLZl2ux1raUqZcISv0RvgGEnUBB6eGwi4NREQI6LWdZADEQ/un8K6/YU6BUdn1APRodLJ8V2L+ULqRkc9OULJfjh/xPLtASmKDX8TQFpT0NiOavv1W3p+K1yM1g0BfA3IMxLDNjV21w+StJuXrGUZG0dHFe7sRZQzX99jN62JO3zs6L7AsT+/+261BwWRtZ99BYWIh/79VHdYs9X3Tx/ky/SWVmYZZE5kJ4DftdgR51n0pts8B2jGg7mb4OAAWCQ0ExtX0b2vTXoTQ76JehNoa/27ShLfVntmhhBjeGFiuZd2StV1bvOfQaxgBUSXszEQRo5wyFoMJdkF3gH7dlHhsyane1Lt5UKrdqMXBC1NlBcvo4ey/FfnxJ5zupFQ85hwpX/w2VsFrpu3WVF+FTamiy2t+Yz27mL8Nnm+uE20CdtKGBpydsymiDSvF8vGWjv+DXmconUmWn/9dIWyzrxOnk4Yfn4smGVjf/lm8Y1svCo+E1S7cHqiTL7f6Sgw7yPoSadzAac1ENLDvw/WAGPkuXUVDeQyHKQcNWWFhha3jesIl21CRGJMvWCDFH+a X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230022)(4636009)(376002)(346002)(39860400002)(136003)(396003)(451199015)(46966006)(40470700004)(36840700001)(40460700003)(82740400003)(356005)(83380400001)(40480700001)(478600001)(86362001)(36860700001)(26005)(6666004)(7696005)(2906002)(186003)(8936002)(44832011)(36756003)(82310400005)(70206006)(316002)(70586007)(110136005)(8676002)(81166007)(1076003)(2616005)(41300700001)(336012)(5660300002)(426003)(16526019)(47076005)(4326008)(54906003)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Oct 2022 21:16:03.6284 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 228564bc-9456-42e1-590c-08daa64da4fa X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT091.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7282 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mwen@igalia.com, bhawanpreet.lakha@amd.com, Alex Hung Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Implement the 3D LUT interface, convert and pass the data for amdgpu driver. Note: A patchset "IGT tests for pre-blending 3D LUT interfaces" for this proposal is sent to IGT mailing list. Signed-off-by: Alex Hung --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 13 ++ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 1 + .../amd/display/amdgpu_dm/amdgpu_dm_color.c | 181 ++++++++++++++++++ 3 files changed, 195 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 7094578a683f..10e6dc5c8552 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -5656,6 +5656,19 @@ static int fill_dc_plane_attributes(struct amdgpu_device *adev, dc_plane_state->in_transfer_func->type = TF_TYPE_HWPWL; } + /* 3D LUT from userspace */ + if (plane_state->color_mgmt_changed) { + if (plane_state->lut_3d && dc_plane_state->lut3d_func) { + ret = amdgpu_dm_fill_3dlut_data(plane_state, &dc_plane_state->lut3d_func->lut_3d); + if (!ret) + dc_plane_state->lut3d_func->state.bits.initialized = 1; + else + return ret; + } else { + /* TODO disable 3D LUT */ + } + } + return 0; } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index 667957087ccf..644c5ff6ee9a 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -726,6 +726,7 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, struct dc_plane_state *dc_plane_state); void amdgpu_dm_fill_pwl_data(struct drm_property_blob *lut_blob, struct pwl_params *lut_params, struct drm_color_lut_range *pwl_definition, int pwl_size); +int amdgpu_dm_fill_3dlut_data(const struct drm_plane_state *plane_state, struct tetrahedral_params *param); void amdgpu_dm_update_connector_after_detect( struct amdgpu_dm_connector *aconnector); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c index ae633fe52525..705852bf63e7 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c @@ -22,6 +22,7 @@ * Authors: AMD * */ + #include #include "amdgpu.h" #include "amdgpu_mode.h" #include "amdgpu_dm.h" @@ -469,6 +470,186 @@ int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state) return 0; } +#define R_3DLUT 0 +#define G_3DLUT 1 +#define B_3DLUT 2 + +static __u16 extract_rgb_value(void *lut_3d, __u32 color_format, __u8 color) +{ + __u64 val = *(__u64 *) lut_3d; + + switch (color_format) { + case DRM_FORMAT_XRGB16161616: + if (color == R_3DLUT) + return val & 0xFFFF; + else if (color == G_3DLUT) + return (val >> 16) & 0xFFFF; + else if (color == B_3DLUT) + return (val >> 32) & 0xFFFF; + break; + case DRM_FORMAT_XBGR16161616: + if (color == B_3DLUT) + return val & 0xFFFF; + else if (color == G_3DLUT) + return (val >> 16) & 0xFFFF; + else if (color == R_3DLUT) + return (val >> 32) & 0xFFFF; + break; + case DRM_FORMAT_XRGB8888: + if (color == R_3DLUT) + return val & 0xFF; + else if (color == G_3DLUT) + return (val >> 8) & 0xFF; + else if (color == B_3DLUT) + return (val >> 16) & 0xFF; + break; + case DRM_FORMAT_XBGR8888: + if (color == B_3DLUT) + return val & 0xFF; + else if (color == G_3DLUT) + return (val >> 8) & 0xFF; + else if (color == R_3DLUT) + return (val >> 16) & 0xFF; + break; + default: + return 0; + } + + return 0; +} + +static bool extract_rgb_data(const struct drm_plane_state *plane_state, struct drm_mode_3dlut_mode *mode, __u16 *lut_data) +{ + __u16 i, lut_volume; + void *lut_3d = plane_state->lut_3d->data; + __u32 cfmt = mode->color_format; + + /* copy RGB accordingly */ + lut_volume = mode->lut_size * mode->lut_size * mode->lut_size; + for (i = 0; i < lut_volume; i += 3) { + lut_data[i] = extract_rgb_value(lut_3d, cfmt, R_3DLUT); + lut_data[i+1] = extract_rgb_value(lut_3d, cfmt, G_3DLUT); + lut_data[i+2] = extract_rgb_value(lut_3d, cfmt, B_3DLUT); + + if (cfmt == DRM_FORMAT_XRGB16161616 || cfmt == DRM_FORMAT_XBGR16161616) + lut_3d += sizeof(__u64); + else if (cfmt == DRM_FORMAT_XRGB8888 || cfmt == DRM_FORMAT_XBGR8888) + lut_3d += sizeof(__u32); + else + return false; + } + return true; +} + +static void convert_3dlut_to_tetrahedral_params(struct dc_rgb *rgb, + bool is_17x17x17, bool is_12_bits, struct tetrahedral_params *params) +{ + struct dc_rgb *lut0; + struct dc_rgb *lut1; + struct dc_rgb *lut2; + struct dc_rgb *lut3; + int i, lut_i; + + int num_values; + + if (is_17x17x17 == false) { + lut0 = params->tetrahedral_9.lut0; + lut1 = params->tetrahedral_9.lut1; + lut2 = params->tetrahedral_9.lut2; + lut3 = params->tetrahedral_9.lut3; + num_values = 729; + } else { + lut0 = params->tetrahedral_17.lut0; + lut1 = params->tetrahedral_17.lut1; + lut2 = params->tetrahedral_17.lut2; + lut3 = params->tetrahedral_17.lut3; + num_values = 4913; + } + + params->use_12bits = is_12_bits; + params->use_tetrahedral_9 = !is_17x17x17; + + for (lut_i = 0, i = 0; i < num_values - 4; lut_i++, i += 4) { + lut0[lut_i].red = rgb[i].red; + lut0[lut_i].green = rgb[i].green; + lut0[lut_i].blue = rgb[i].blue; + + lut1[lut_i].red = rgb[i + 1].red; + lut1[lut_i].green = rgb[i + 1].green; + lut1[lut_i].blue = rgb[i + 1].blue; + + lut2[lut_i].red = rgb[i + 2].red; + lut2[lut_i].green = rgb[i + 2].green; + lut2[lut_i].blue = rgb[i + 2].blue; + + lut3[lut_i].red = rgb[i + 3].red; + lut3[lut_i].green = rgb[i + 3].green; + lut3[lut_i].blue = rgb[i + 3].blue; + } + + lut0[lut_i].red = rgb[i].red; + lut0[lut_i].green = rgb[i].green; + lut0[lut_i].blue = rgb[i].blue; +} + +/* only use for 17x17x17 */ +bool convert_to_tetrahedral(unsigned short rgb_lib[17*17*17*3], struct tetrahedral_params *params) +{ + bool ret = false; + struct dc_rgb *rgb_area = NULL; + int ind = 0; + int ind_lut = 0; + int nir, nig, nib; + + rgb_area = kvcalloc(17 * 17 * 17, sizeof(struct dc_rgb), GFP_KERNEL); + if (rgb_area == NULL) + goto release; + + memset(rgb_area, 0, sizeof(17 * 17 * 17 * sizeof(struct dc_rgb))); + + for (nib = 0; nib < 17; nib++) { + for (nig = 0; nig < 17; nig++) { + for (nir = 0; nir < 17; nir++) { + ind_lut = 3 * (nib + 17*nig + 289*nir); + + rgb_area[ind].red = rgb_lib[ind_lut + 0]; + rgb_area[ind].green = rgb_lib[ind_lut + 1]; + rgb_area[ind].blue = rgb_lib[ind_lut + 2]; + ind++; + } + } + } + convert_3dlut_to_tetrahedral_params(rgb_area, true, true, params); + kvfree(rgb_area); + ret = true; + +release: + return ret; +} + +int amdgpu_dm_fill_3dlut_data(const struct drm_plane_state *plane_state, struct tetrahedral_params *param) +{ + const struct drm_mode_3dlut_mode *mode = &lut_3d_mode_17_12bit; + unsigned short *lut_data; + + lut_data = kmalloc(mode->lut_size * mode->lut_size * mode->lut_size * sizeof(__u16) * 3, GFP_KERNEL); + if (!extract_rgb_data(plane_state, mode, lut_data)) + return -EINVAL; + + if (!convert_to_tetrahedral(lut_data, param)) + return -EINVAL; + + kfree(lut_data); + + if (mode->lut_size == 17) + param->use_tetrahedral_9 = false; + + if (mode->bit_depth == 12) + param->use_12bits = true; + + return 0; +} + /** * amdgpu_dm_update_crtc_color_mgmt: Maps DRM color management to DC stream. * @crtc: amdgpu_dm crtc state