From patchwork Wed Oct 5 11:18:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 12999141 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E5401C4332F for ; Wed, 5 Oct 2022 11:19:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229498AbiJELTE (ORCPT ); Wed, 5 Oct 2022 07:19:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44692 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229769AbiJELTD (ORCPT ); Wed, 5 Oct 2022 07:19:03 -0400 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 318E558B7D; Wed, 5 Oct 2022 04:19:01 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.95,159,1661785200"; d="scan'208";a="135441480" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 05 Oct 2022 20:19:00 +0900 Received: from localhost.localdomain (unknown [10.226.92.36]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 9734F40062A3; Wed, 5 Oct 2022 20:18:57 +0900 (JST) From: Biju Das To: Michael Turquette , Stephen Boyd Cc: Biju Das , Geert Uytterhoeven , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Chris Paterson , Biju Das , Prabhakar Mahadev Lad Subject: [PATCH] clk: renesas: r9a07g044: Add MTU3a clock and reset entry Date: Wed, 5 Oct 2022 12:18:55 +0100 Message-Id: <20221005111855.553436-1-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Add MTU3a clock and reset entry to CPG driver. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven --- RFC->v1: No change. --- drivers/clk/renesas/r9a07g044-cpg.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c index 02a4fc41bb6e..12b1a83625cb 100644 --- a/drivers/clk/renesas/r9a07g044-cpg.c +++ b/drivers/clk/renesas/r9a07g044-cpg.c @@ -182,7 +182,7 @@ static const struct { }; static const struct { - struct rzg2l_mod_clk common[76]; + struct rzg2l_mod_clk common[77]; #ifdef CONFIG_CLK_R9A07G054 struct rzg2l_mod_clk drp[0]; #endif @@ -204,6 +204,8 @@ static const struct { 0x534, 1), DEF_MOD("ostm2_pclk", R9A07G044_OSTM2_PCLK, R9A07G044_CLK_P0, 0x534, 2), + DEF_MOD("mtu_x_mck", R9A07G044_MTU_X_MCK_MTU3, R9A07G044_CLK_P0, + 0x538, 0), DEF_MOD("gpt_pclk", R9A07G044_GPT_PCLK, R9A07G044_CLK_P0, 0x540, 0), DEF_MOD("poeg_a_clkp", R9A07G044_POEG_A_CLKP, R9A07G044_CLK_P0, @@ -356,6 +358,7 @@ static struct rzg2l_reset r9a07g044_resets[] = { DEF_RST(R9A07G044_OSTM0_PRESETZ, 0x834, 0), DEF_RST(R9A07G044_OSTM1_PRESETZ, 0x834, 1), DEF_RST(R9A07G044_OSTM2_PRESETZ, 0x834, 2), + DEF_RST(R9A07G044_MTU_X_PRESET_MTU3, 0x838, 0), DEF_RST(R9A07G044_GPT_RST_C, 0x840, 0), DEF_RST(R9A07G044_POEG_A_RST, 0x844, 0), DEF_RST(R9A07G044_POEG_B_RST, 0x844, 1),