From patchwork Thu Oct 6 04:38:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alan Previn X-Patchwork-Id: 12999960 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 892CDC433FE for ; Thu, 6 Oct 2022 04:36:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 72E9810E7DF; Thu, 6 Oct 2022 04:36:51 +0000 (UTC) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 93CF010E4DB for ; Thu, 6 Oct 2022 04:36:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1665030992; x=1696566992; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=XkvRKFPX9SyyZdlcfGZTDftMd4uyFE8djihBnY7dkc0=; b=DANj+4kC/xdcA8WJ2PmGpNIw/PtdaJ7c6DwetmxgPy8OZT+THXwyQLXo U8/U8MJVL9IOZ9aYz13NKN8q8d0PsN8nkVSNFzC727v4gNirc4jKdT0t3 6nkUO6t6lOx3HixRkleCYl9yW/NPxNs2+wXL6XaMuQJKKCogYdhNQtQ7Z JuLtN1sCYnMV6K8M7cxct6cHxd15LP/sAJDsfG/QMv9FxFpK4/VD06eDd 6KOzZG44aYDDeXTYfZSn41w5fpRhCdMVaka+HcKloLpTpmBo92cLtzn7L 1obGEi+ZXqRSDPzRZW0p/hBh+Ykgq1zBw8Ji7RxUdET0+D9M+My9wa6s6 A==; X-IronPort-AV: E=McAfee;i="6500,9779,10491"; a="290599847" X-IronPort-AV: E=Sophos;i="5.95,162,1661842800"; d="scan'208";a="290599847" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Oct 2022 21:36:31 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10491"; a="953462910" X-IronPort-AV: E=Sophos;i="5.95,162,1661842800"; d="scan'208";a="953462910" Received: from aalteres-desk.fm.intel.com ([10.80.57.53]) by fmsmga005.fm.intel.com with ESMTP; 05 Oct 2022 21:36:31 -0700 From: Alan Previn To: intel-gfx@lists.freedesktop.org Date: Wed, 5 Oct 2022 21:38:27 -0700 Message-Id: <20221006043834.606220-2-alan.previn.teres.alexis@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221006043834.606220-1-alan.previn.teres.alexis@intel.com> References: <20221006043834.606220-1-alan.previn.teres.alexis@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 1/7] drm/i915/pxp: Make gt and pxp init/fini aware of PXP-owning-GT X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" In preparation for future MTL-PXP feature support, PXP control context should only valid on the correct gt tile. Depending on the device-info this mat not necessarily be the root GT tile and depends on which tile owns the VEBOX and KCR. PXP is still a global feature (despite the control-context being accessed via the owning GT structure) so let's also update HAS_PXP macro be called with the i915 handle instead of the gt handle. the correct gt-ptr access to grab the pxp handle. Update intel_pxp_init/fini aware of PXP-owning-GT to only initialize the PXP control-context of the correct GT structure. Signed-off-by: Alan Previn --- drivers/gpu/drm/i915/gt/intel_gt.c | 4 ++++ drivers/gpu/drm/i915/gt/intel_gt_types.h | 5 +++++ drivers/gpu/drm/i915/gt/intel_sa_media.c | 4 ++++ drivers/gpu/drm/i915/i915_drv.h | 6 +++--- drivers/gpu/drm/i915/i915_pci.c | 1 + drivers/gpu/drm/i915/intel_device_info.h | 1 + drivers/gpu/drm/i915/pxp/intel_pxp.c | 22 +++++++++++++++++--- drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c | 2 +- 8 files changed, 38 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index b367cfff48d5..e61f6c5ed440 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -850,6 +850,10 @@ int intel_gt_probe_all(struct drm_i915_private *i915) gt->name = "Primary GT"; gt->info.engine_mask = RUNTIME_INFO(i915)->platform_engine_mask; + /* device config determines which GT owns the global pxp-tee context */ + if (VDBOX_MASK(gt) && !INTEL_INFO(i915)->has_nonroot_pxpgt) + gt->pxptee_iface_owner = true; + drm_dbg(&i915->drm, "Setting up %s\n", gt->name); ret = intel_gt_tile_setup(gt, phys_addr); if (ret) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h index 30003d68fd51..fd554ec415cd 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h @@ -279,6 +279,11 @@ struct intel_gt { u8 wb_index; /* Only used on HAS_L3_CCS_READ() platforms */ } mocs; + /* + * In a multi-tile GPU, only one GT-tile can contain + * the single valid global pxp + tee context. + */ + bool pxptee_iface_owner; struct intel_pxp pxp; /* gt/gtN sysfs */ diff --git a/drivers/gpu/drm/i915/gt/intel_sa_media.c b/drivers/gpu/drm/i915/gt/intel_sa_media.c index e8f3d18c12b8..038344b48760 100644 --- a/drivers/gpu/drm/i915/gt/intel_sa_media.c +++ b/drivers/gpu/drm/i915/gt/intel_sa_media.c @@ -36,6 +36,10 @@ int intel_sa_mediagt_setup(struct intel_gt *gt, phys_addr_t phys_addr, gt->uncore = uncore; gt->phys_addr = phys_addr; + /* On MTL, the standalone media owns the global PXP/TEE context. */ + if (HAS_PXP(gt) && gt->info.id == 1) + gt->pxptee_iface_owner = true; + /* * For current platforms we can assume there's only a single * media GT and cache it for quick lookup. diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 90ed8e6db2fe..9fd0c065aa23 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -928,9 +928,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define HAS_GLOBAL_MOCS_REGISTERS(dev_priv) (INTEL_INFO(dev_priv)->has_global_mocs) -#define HAS_PXP(dev_priv) ((IS_ENABLED(CONFIG_DRM_I915_PXP) && \ - INTEL_INFO(dev_priv)->has_pxp) && \ - VDBOX_MASK(to_gt(dev_priv))) +#define HAS_PXP(gt) (IS_ENABLED(CONFIG_DRM_I915_PXP) && \ + (INTEL_INFO((gt)->i915)->has_pxp) && \ + VDBOX_MASK(gt)) #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch) diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 38460a0bd7cb..6ee1cd6f1194 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -1149,6 +1149,7 @@ static const struct intel_device_info mtl_info = { .__runtime.memory_regions = REGION_SMEM | REGION_STOLEN_LMEM, .__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(CCS0), .require_force_probe = 1, + .has_nonroot_pxpgt = 1, }; #undef PLATFORM diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index bc87d3156b14..8508d3795593 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -167,6 +167,7 @@ enum intel_ppgtt_type { func(has_mslice_steering); \ func(has_one_eu_per_fuse_bit); \ func(has_pxp); \ + func(has_nonroot_pxpgt); \ func(has_rc6); \ func(has_rc6p); \ func(has_rps); \ diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c index 5efe61f67546..a18dfeca919b 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c @@ -138,11 +138,22 @@ static void pxp_init_full(struct intel_pxp *pxp) destroy_vcs_context(pxp); } +static bool _gt_needs_teelink(struct intel_gt *gt) +{ + return intel_huc_is_loaded_by_gsc(>->uc.huc) && intel_uc_uses_huc(>->uc); +} + void intel_pxp_init(struct intel_pxp *pxp) { struct intel_gt *gt = pxp_to_gt(pxp); - /* we rely on the mei PXP module */ + /* + * In current platforms we only need a single pxp component but must reside + * within the owner gt. + */ + if (!gt->pxptee_iface_owner) + return; + if (!IS_ENABLED(CONFIG_INTEL_MEI_PXP)) return; @@ -150,14 +161,19 @@ void intel_pxp_init(struct intel_pxp *pxp) * If HuC is loaded by GSC but PXP is disabled, we can skip the init of * the full PXP session/object management and just init the tee channel. */ - if (HAS_PXP(gt->i915)) + if (HAS_PXP(gt)) pxp_init_full(pxp); - else if (intel_huc_is_loaded_by_gsc(>->uc.huc) && intel_uc_uses_huc(>->uc)) + else if (_gt_needs_teelink(gt)) intel_pxp_tee_component_init(pxp); } void intel_pxp_fini(struct intel_pxp *pxp) { + struct intel_gt *gt = pxp_to_gt(pxp); + + if (!gt->pxptee_iface_owner) + return; + pxp->arb_is_valid = false; intel_pxp_tee_component_fini(pxp); diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c b/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c index 4359e8be4101..7b37f061044d 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c @@ -70,7 +70,7 @@ void intel_pxp_debugfs_register(struct intel_pxp *pxp, struct dentry *gt_root) if (!gt_root) return; - if (!HAS_PXP((pxp_to_gt(pxp)->i915))) + if (!HAS_PXP((pxp_to_gt(pxp)))) return; root = debugfs_create_dir("pxp", gt_root); From patchwork Thu Oct 6 04:38:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alan Previn X-Patchwork-Id: 12999953 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C6EBDC433FE for ; Thu, 6 Oct 2022 04:36:36 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AB56110E4A0; Thu, 6 Oct 2022 04:36:35 +0000 (UTC) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id BAE0710E7D9 for ; Thu, 6 Oct 2022 04:36:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1665030992; x=1696566992; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=He4/mu5qYRabEK29MJqMgL/KHoJ2q809WL8lh6AqaF8=; b=EMuiAovNgTL/7UbO8AjoJxmAo7OxwjpinH/52+dtstlHX8nO7eaMiqCQ jCqRPmBsD0WHik/GxhTpxSIQ4mZpbSXUhgYSKB7zIgi2DXkGQZMsxxnba 19GXLeSlnvbeeZx6ghbleOE3IsEg3jTBgenmKWogjhB34qHfOWiM6ZAmw +tgl7TI6i41ivsAhltqj/xiLOOO1PVXVl6UF6zOr3X7+DVOZqBg/SiRzT UrG3P9GO539hVKki/dbKrw0s7r35TSAkc7U0fAjdwJQVCi3XQc0IF25vd +861+VFunTlMQl3amfHDRnXENNgD9bJowmCxWNEUmMfHO/ZRZMWCkkSaO Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10491"; a="290599849" X-IronPort-AV: E=Sophos;i="5.95,162,1661842800"; d="scan'208";a="290599849" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Oct 2022 21:36:31 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10491"; a="953462911" X-IronPort-AV: E=Sophos;i="5.95,162,1661842800"; d="scan'208";a="953462911" Received: from aalteres-desk.fm.intel.com ([10.80.57.53]) by fmsmga005.fm.intel.com with ESMTP; 05 Oct 2022 21:36:31 -0700 From: Alan Previn To: intel-gfx@lists.freedesktop.org Date: Wed, 5 Oct 2022 21:38:28 -0700 Message-Id: <20221006043834.606220-3-alan.previn.teres.alexis@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221006043834.606220-1-alan.previn.teres.alexis@intel.com> References: <20221006043834.606220-1-alan.previn.teres.alexis@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 2/7] drm/i915/pxp: Make intel_pxp_is_enabled implicitly sort PXP-owning-GT X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Make intel_pxp_is_enabled implicitly find the PXP-owning-GT. PXP feature support is a device-config flag. In preparation for MTL PXP control-context shall reside on of the two GT's. That said, update intel_pxp_is_enabled to take in i915 as its input and internally find the right gt to check if PXP is enabled so its transparent to callers of this functions. Signed-off-by: Alan Previn --- drivers/gpu/drm/i915/gem/i915_gem_context.c | 2 +- drivers/gpu/drm/i915/gem/i915_gem_create.c | 2 +- drivers/gpu/drm/i915/pxp/intel_pxp.c | 27 ++++++++++++++++++-- drivers/gpu/drm/i915/pxp/intel_pxp.h | 4 ++- drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 2 +- drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c | 2 +- drivers/gpu/drm/i915/pxp/intel_pxp_irq.c | 5 +++- drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 8 +++--- drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 4 +-- 9 files changed, 42 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c index 0bcde53c50c6..df03c1c7feb9 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c @@ -257,7 +257,7 @@ static int proto_context_set_protected(struct drm_i915_private *i915, if (!protected) { pc->uses_protected_content = false; - } else if (!intel_pxp_is_enabled(&to_gt(i915)->pxp)) { + } else if (!intel_pxp_is_enabled(i915)) { ret = -ENODEV; } else if ((pc->user_flags & BIT(UCONTEXT_RECOVERABLE)) || !(pc->user_flags & BIT(UCONTEXT_BANNABLE))) { diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c b/drivers/gpu/drm/i915/gem/i915_gem_create.c index 33673fe7ee0a..e44803f9bec4 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_create.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c @@ -384,7 +384,7 @@ static int ext_set_protected(struct i915_user_extension __user *base, void *data if (ext.flags) return -EINVAL; - if (!intel_pxp_is_enabled(&to_gt(ext_data->i915)->pxp)) + if (!intel_pxp_is_enabled(ext_data->i915)) return -ENODEV; ext_data->flags |= I915_BO_PROTECTED; diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c index a18dfeca919b..93e9bc383461 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c @@ -9,6 +9,7 @@ #include "intel_pxp_tee.h" #include "gem/i915_gem_context.h" #include "gt/intel_context.h" +#include "gt/intel_gt.h" #include "i915_drv.h" /** @@ -39,16 +40,38 @@ * performed via the mei_pxp component module. */ +struct intel_gt *intel_pxp_get_owning_gt(struct drm_i915_private *i915) +{ + struct intel_gt *gt = NULL; + int i = 0; + + for_each_gt(gt, i915, i) { + if (gt && gt->pxptee_iface_owner) + return gt; + } + return NULL; +} + struct intel_gt *pxp_to_gt(const struct intel_pxp *pxp) { return container_of(pxp, struct intel_gt, pxp); } -bool intel_pxp_is_enabled(const struct intel_pxp *pxp) +static bool _pxp_is_enabled(struct intel_pxp *pxp) { return pxp->ce; } +bool intel_pxp_is_enabled(struct drm_i915_private *i915) +{ + struct intel_gt *gt = intel_pxp_get_owning_gt(i915); + + if (!gt) + return false; + + return _pxp_is_enabled(>->pxp); +} + bool intel_pxp_is_active(const struct intel_pxp *pxp) { return pxp->arb_is_valid; @@ -222,7 +245,7 @@ int intel_pxp_start(struct intel_pxp *pxp) { int ret = 0; - if (!intel_pxp_is_enabled(pxp)) + if (!_pxp_is_enabled(pxp)) return -ENODEV; if (wait_for(pxp_component_bound(pxp), 250)) diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h index 2da309088c6d..e82154a147b9 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.h +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h @@ -11,9 +11,11 @@ struct intel_pxp; struct drm_i915_gem_object; +struct drm_i915_private; struct intel_gt *pxp_to_gt(const struct intel_pxp *pxp); -bool intel_pxp_is_enabled(const struct intel_pxp *pxp); +struct intel_gt *intel_pxp_get_owning_gt(struct drm_i915_private *i915); +bool intel_pxp_is_enabled(struct drm_i915_private *i915); bool intel_pxp_is_active(const struct intel_pxp *pxp); void intel_pxp_init(struct intel_pxp *pxp); diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c index f41e45763d0d..1d409149c0e8 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c @@ -99,7 +99,7 @@ int intel_pxp_terminate_session(struct intel_pxp *pxp, u32 id) u32 *cs; int err = 0; - if (!intel_pxp_is_enabled(pxp)) + if (!intel_pxp_is_enabled(pxp_to_gt(pxp)->i915)) return 0; rq = i915_request_create(ce); diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c b/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c index 7b37f061044d..907d3aba7a9c 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c @@ -18,7 +18,7 @@ static int pxp_info_show(struct seq_file *m, void *data) { struct intel_pxp *pxp = m->private; struct drm_printer p = drm_seq_file_printer(m); - bool enabled = intel_pxp_is_enabled(pxp); + bool enabled = intel_pxp_is_enabled(pxp_to_gt(pxp)->i915); if (!enabled) { drm_printf(&p, "pxp disabled\n"); diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c index c28be430718a..6f515c163d2f 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c @@ -22,7 +22,10 @@ void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir) { struct intel_gt *gt = pxp_to_gt(pxp); - if (GEM_WARN_ON(!intel_pxp_is_enabled(pxp))) + if (!gt->pxptee_iface_owner) + return; + + if (GEM_WARN_ON(!intel_pxp_is_enabled(gt->i915))) return; lockdep_assert_held(gt->irq_lock); diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c index 6a7d4e2ee138..5f713ac5c3ce 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c @@ -11,7 +11,7 @@ void intel_pxp_suspend_prepare(struct intel_pxp *pxp) { - if (!intel_pxp_is_enabled(pxp)) + if (!intel_pxp_is_enabled(pxp_to_gt(pxp)->i915)) return; pxp->arb_is_valid = false; @@ -23,7 +23,7 @@ void intel_pxp_suspend(struct intel_pxp *pxp) { intel_wakeref_t wakeref; - if (!intel_pxp_is_enabled(pxp)) + if (!intel_pxp_is_enabled(pxp_to_gt(pxp)->i915)) return; with_intel_runtime_pm(&pxp_to_gt(pxp)->i915->runtime_pm, wakeref) { @@ -34,7 +34,7 @@ void intel_pxp_suspend(struct intel_pxp *pxp) void intel_pxp_resume(struct intel_pxp *pxp) { - if (!intel_pxp_is_enabled(pxp)) + if (!intel_pxp_is_enabled(pxp_to_gt(pxp)->i915)) return; /* @@ -50,7 +50,7 @@ void intel_pxp_resume(struct intel_pxp *pxp) void intel_pxp_runtime_suspend(struct intel_pxp *pxp) { - if (!intel_pxp_is_enabled(pxp)) + if (!intel_pxp_is_enabled(pxp_to_gt(pxp)->i915)) return; pxp->arb_is_valid = false; diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c index 052fd2f9a583..792a56edfde7 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c @@ -152,7 +152,7 @@ static int i915_pxp_tee_component_bind(struct device *i915_kdev, return 0; /* the component is required to fully start the PXP HW */ - if (intel_pxp_is_enabled(pxp)) + if (intel_pxp_is_enabled(i915)) intel_pxp_init_hw(pxp); intel_runtime_pm_put(&i915->runtime_pm, wakeref); @@ -167,7 +167,7 @@ static void i915_pxp_tee_component_unbind(struct device *i915_kdev, struct intel_pxp *pxp = i915_dev_to_pxp(i915_kdev); intel_wakeref_t wakeref; - if (intel_pxp_is_enabled(pxp)) + if (intel_pxp_is_enabled(i915)) with_intel_runtime_pm_if_in_use(&i915->runtime_pm, wakeref) intel_pxp_fini_hw(pxp); From patchwork Thu Oct 6 04:38:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alan Previn X-Patchwork-Id: 12999954 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D8876C4332F for ; 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a="290599850" X-IronPort-AV: E=Sophos;i="5.95,162,1661842800"; d="scan'208";a="290599850" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Oct 2022 21:36:32 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10491"; a="953462912" X-IronPort-AV: E=Sophos;i="5.95,162,1661842800"; d="scan'208";a="953462912" Received: from aalteres-desk.fm.intel.com ([10.80.57.53]) by fmsmga005.fm.intel.com with ESMTP; 05 Oct 2022 21:36:31 -0700 From: Alan Previn To: intel-gfx@lists.freedesktop.org Date: Wed, 5 Oct 2022 21:38:29 -0700 Message-Id: <20221006043834.606220-4-alan.previn.teres.alexis@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221006043834.606220-1-alan.previn.teres.alexis@intel.com> References: <20221006043834.606220-1-alan.previn.teres.alexis@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 3/7] drm/i915/pxp: Make intel_pxp_is_active implicitly sort PXP-owning-GT X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Make intel_pxp_is_active implicitly find the PXP-owning-GT. As per prior two patches, callers of this function shall now pass in i915 since PXP is a global GPU feature. Make intel_pxp_is_active implicitly find the right gt to check if PXP is active so it's transparent to the callers. Signed-off-by: Alan Previn --- drivers/gpu/drm/i915/gem/i915_gem_context.c | 2 +- drivers/gpu/drm/i915/pxp/intel_pxp.c | 11 ++++++++--- drivers/gpu/drm/i915/pxp/intel_pxp.h | 2 +- drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c | 4 ++-- drivers/gpu/drm/i915/pxp/intel_pxp_irq.c | 2 +- 5 files changed, 13 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c index df03c1c7feb9..8443b485c62f 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c @@ -271,7 +271,7 @@ static int proto_context_set_protected(struct drm_i915_private *i915, */ pc->pxp_wakeref = intel_runtime_pm_get(&i915->runtime_pm); - if (!intel_pxp_is_active(&to_gt(i915)->pxp)) + if (!intel_pxp_is_active(i915)) ret = intel_pxp_start(&to_gt(i915)->pxp); } diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c index 93e9bc383461..57b4e9f9e4d1 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c @@ -72,9 +72,14 @@ bool intel_pxp_is_enabled(struct drm_i915_private *i915) return _pxp_is_enabled(>->pxp); } -bool intel_pxp_is_active(const struct intel_pxp *pxp) +bool intel_pxp_is_active(struct drm_i915_private *i915) { - return pxp->arb_is_valid; + struct intel_gt *gt = intel_pxp_get_owning_gt(i915); + + if (!gt) + return false; + + return gt->pxp.arb_is_valid; } /* KCR register definitions */ @@ -292,7 +297,7 @@ int intel_pxp_key_check(struct intel_pxp *pxp, struct drm_i915_gem_object *obj, bool assign) { - if (!intel_pxp_is_active(pxp)) + if (!intel_pxp_is_active(pxp_to_gt(pxp)->i915)) return -ENODEV; if (!i915_gem_object_is_protected(obj)) diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h index e82154a147b9..0219ff285788 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.h +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h @@ -16,7 +16,7 @@ struct drm_i915_private; struct intel_gt *pxp_to_gt(const struct intel_pxp *pxp); struct intel_gt *intel_pxp_get_owning_gt(struct drm_i915_private *i915); bool intel_pxp_is_enabled(struct drm_i915_private *i915); -bool intel_pxp_is_active(const struct intel_pxp *pxp); +bool intel_pxp_is_active(struct drm_i915_private *i915); void intel_pxp_init(struct intel_pxp *pxp); void intel_pxp_fini(struct intel_pxp *pxp); diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c b/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c index 907d3aba7a9c..210dd2f28c42 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c @@ -25,7 +25,7 @@ static int pxp_info_show(struct seq_file *m, void *data) return 0; } - drm_printf(&p, "active: %s\n", str_yes_no(intel_pxp_is_active(pxp))); + drm_printf(&p, "active: %s\n", str_yes_no(intel_pxp_is_active(pxp_to_gt(pxp)->i915))); drm_printf(&p, "instance counter: %u\n", pxp->key_instance); return 0; @@ -43,7 +43,7 @@ static int pxp_terminate_set(void *data, u64 val) struct intel_pxp *pxp = data; struct intel_gt *gt = pxp_to_gt(pxp); - if (!intel_pxp_is_active(pxp)) + if (!intel_pxp_is_active(gt->i915)) return -ENODEV; /* simulate a termination interrupt */ diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c index 6f515c163d2f..a8baffb51389 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c @@ -89,7 +89,7 @@ void intel_pxp_irq_disable(struct intel_pxp *pxp) * called in a path were the driver consider the session as valid and * doesn't call a termination on restart. */ - GEM_WARN_ON(intel_pxp_is_active(pxp)); + GEM_WARN_ON(intel_pxp_is_active(gt->i915)); spin_lock_irq(gt->irq_lock); From patchwork Thu Oct 6 04:38:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alan Previn X-Patchwork-Id: 12999957 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A7097C433F5 for ; Thu, 6 Oct 2022 04:36:51 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0692E10E7DA; Thu, 6 Oct 2022 04:36:39 +0000 (UTC) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 168EB10E4DB for ; Thu, 6 Oct 2022 04:36:33 +0000 (UTC) DKIM-Signature: v=1; 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d="scan'208";a="953462913" Received: from aalteres-desk.fm.intel.com ([10.80.57.53]) by fmsmga005.fm.intel.com with ESMTP; 05 Oct 2022 21:36:31 -0700 From: Alan Previn To: intel-gfx@lists.freedesktop.org Date: Wed, 5 Oct 2022 21:38:30 -0700 Message-Id: <20221006043834.606220-5-alan.previn.teres.alexis@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221006043834.606220-1-alan.previn.teres.alexis@intel.com> References: <20221006043834.606220-1-alan.previn.teres.alexis@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 4/7] drm/i915/pxp: Make PXP tee component bind/unbind aware of PXP-owning-GT X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Ensure i915_pxp_tee_component_bind / unbind implicitly sorts out getting the correct PXP control-context from the PXP-owning-GT when establishing or ending connection. Signed-off-by: Alan Previn --- drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c index 792a56edfde7..05d5ad1092b8 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c @@ -20,8 +20,12 @@ static inline struct intel_pxp *i915_dev_to_pxp(struct device *i915_kdev) { struct drm_i915_private *i915 = kdev_to_i915(i915_kdev); + struct intel_gt *gt = intel_pxp_get_owning_gt(i915); - return &to_gt(i915)->pxp; + if (!gt) + return NULL; + + return >->pxp; } static int intel_pxp_tee_io_message(struct intel_pxp *pxp, @@ -128,10 +132,16 @@ static int i915_pxp_tee_component_bind(struct device *i915_kdev, { struct drm_i915_private *i915 = kdev_to_i915(i915_kdev); struct intel_pxp *pxp = i915_dev_to_pxp(i915_kdev); - struct intel_uc *uc = &pxp_to_gt(pxp)->uc; + struct intel_uc *uc; intel_wakeref_t wakeref; int ret = 0; + if (!pxp) { + drm_warn(&i915->drm, "tee comp binding without a PXP-owner GT\n"); + return -ENODEV; + } + uc = &pxp_to_gt(pxp)->uc; + mutex_lock(&pxp->tee_mutex); pxp->pxp_component = data; pxp->pxp_component->tee_dev = tee_kdev; @@ -167,6 +177,9 @@ static void i915_pxp_tee_component_unbind(struct device *i915_kdev, struct intel_pxp *pxp = i915_dev_to_pxp(i915_kdev); intel_wakeref_t wakeref; + if (!pxp) + return; + if (intel_pxp_is_enabled(i915)) with_intel_runtime_pm_if_in_use(&i915->runtime_pm, wakeref) intel_pxp_fini_hw(pxp); From patchwork Thu Oct 6 04:38:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alan Previn X-Patchwork-Id: 12999955 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E7B37C433F5 for ; Thu, 6 Oct 2022 04:36:45 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4AE6110E7DB; Thu, 6 Oct 2022 04:36:39 +0000 (UTC) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3E12E10E7D9 for ; Thu, 6 Oct 2022 04:36:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1665030993; x=1696566993; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=W+C+Fb32cO/dXuLnbqlgL/j3gI0pF1wY+UuhBJLYQFk=; b=Y1wWKmo0mjURDv356EwujWdINkbpZ+Avwt5FCsVpJWe0dhALRRa9b1ER EdNTI/GvJfotQWiW9JEyxB2wOeYLVSAUlm+LQBzUj8sSvgvRHmTzGPKza s3yyW0WZsJ0p4ryx3bYYORas7YHZ+DXPOyvPZNB4qKcvRZdKu6WnlCoxQ g9jsaXQ/IArROPVoHbNfqP9ZIUj6QM3tGJus06tYa0Q4IKgr/28DCOmlN mevzgxzkMLywo6yHMSVYDz2kBLIvfFO1P22Kmdem2asY4vxNfXqpqksO7 ypmZyuR5rKjplBKC/YHyIEhFAYOne33kHofP0hruFKil+mqzvcplbGxLN w==; X-IronPort-AV: E=McAfee;i="6500,9779,10491"; a="290599852" X-IronPort-AV: E=Sophos;i="5.95,162,1661842800"; d="scan'208";a="290599852" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Oct 2022 21:36:32 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10491"; a="953462914" X-IronPort-AV: E=Sophos;i="5.95,162,1661842800"; d="scan'208";a="953462914" Received: from aalteres-desk.fm.intel.com ([10.80.57.53]) by fmsmga005.fm.intel.com with ESMTP; 05 Oct 2022 21:36:31 -0700 From: Alan Previn To: intel-gfx@lists.freedesktop.org Date: Wed, 5 Oct 2022 21:38:31 -0700 Message-Id: <20221006043834.606220-6-alan.previn.teres.alexis@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221006043834.606220-1-alan.previn.teres.alexis@intel.com> References: <20221006043834.606220-1-alan.previn.teres.alexis@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 5/7] drm/i915/pxp: Make intel_pxp_start implicitly sort PXP-owning-GT X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Make intel_pxp_is_start implicitly find the PXP-owning-GT. Callers of this function shall now pass in i915 since PXP is a global GPU feature. Make intel_pxp_start implicitly find the right gt to start PXP arb session so it's transparent to the callers. Signed-off-by: Alan Previn --- drivers/gpu/drm/i915/gem/i915_gem_context.c | 2 +- drivers/gpu/drm/i915/pxp/intel_pxp.c | 9 ++++++++- drivers/gpu/drm/i915/pxp/intel_pxp.h | 2 +- 3 files changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c index 8443b485c62f..11bf0d48ef50 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c @@ -272,7 +272,7 @@ static int proto_context_set_protected(struct drm_i915_private *i915, pc->pxp_wakeref = intel_runtime_pm_get(&i915->runtime_pm); if (!intel_pxp_is_active(i915)) - ret = intel_pxp_start(&to_gt(i915)->pxp); + ret = intel_pxp_start(i915); } return ret; diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c index 57b4e9f9e4d1..944c8466f786 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c @@ -246,10 +246,17 @@ static bool pxp_component_bound(struct intel_pxp *pxp) * the arb session is restarted from the irq work when we receive the * termination completion interrupt */ -int intel_pxp_start(struct intel_pxp *pxp) +int intel_pxp_start(struct drm_i915_private *i915) { + struct intel_gt *gt = intel_pxp_get_owning_gt(i915); + struct intel_pxp *pxp; int ret = 0; + if (!gt) + return -ENODEV; + + pxp = >->pxp; + if (!_pxp_is_enabled(pxp)) return -ENODEV; diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h index 0219ff285788..61ef3bedc3a0 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.h +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h @@ -26,7 +26,7 @@ void intel_pxp_fini_hw(struct intel_pxp *pxp); void intel_pxp_mark_termination_in_progress(struct intel_pxp *pxp); -int intel_pxp_start(struct intel_pxp *pxp); +int intel_pxp_start(struct drm_i915_private *i915); int intel_pxp_key_check(struct intel_pxp *pxp, struct drm_i915_gem_object *obj, From patchwork Thu Oct 6 04:38:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alan Previn X-Patchwork-Id: 12999959 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4EA94C433FE for ; Thu, 6 Oct 2022 04:36:56 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3AA1110E7E0; Thu, 6 Oct 2022 04:36:49 +0000 (UTC) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6084910E4A0 for ; Thu, 6 Oct 2022 04:36:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1665030993; x=1696566993; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=micz+el/BL0npX12Xu3Aztr99uNhkLQEE3Xvro6Daw8=; b=eY7jfkNML7aoCpJlUTaKTn7onlG0G5fn7+uGwbqjQm+sVV/ooQkcfAVw 9F0VZ7OJLi9apBvUk15y3qwaWiFKltpdYf/s/UUwGxrcRkCZAagn+gHZ0 ZCZwh9m3d6p50NppEFGaORijWqw7x8USVo+PnIVwSO5YNPxZUZ/ixyzLW PuX8ZwyNX0O+6CRjiXVKMuPZz5uFZnNte/6MJ3weGxvjVJOfs/yjiDOWm eHslCY1soMWg2+wFhNpvy2A7oBO9Qm9OwGIJufeZ1Le5g3uuPygPMDxk/ OvYK3U4+mLiDDqpYc5W9Q+YoQaJh24yiElxF7jpUoWsbD6dLJW15q3TiM Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10491"; a="290599853" X-IronPort-AV: E=Sophos;i="5.95,162,1661842800"; d="scan'208";a="290599853" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Oct 2022 21:36:32 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10491"; a="953462915" X-IronPort-AV: E=Sophos;i="5.95,162,1661842800"; d="scan'208";a="953462915" Received: from aalteres-desk.fm.intel.com ([10.80.57.53]) by fmsmga005.fm.intel.com with ESMTP; 05 Oct 2022 21:36:31 -0700 From: Alan Previn To: intel-gfx@lists.freedesktop.org Date: Wed, 5 Oct 2022 21:38:32 -0700 Message-Id: <20221006043834.606220-7-alan.previn.teres.alexis@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221006043834.606220-1-alan.previn.teres.alexis@intel.com> References: <20221006043834.606220-1-alan.previn.teres.alexis@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 6/7] drm/i915/pxp: Make intel_pxp_key_check implicitly sort PXP-owning-GT X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Make intel_pxp_key_check implicitly find the PXP-owning-GT. Callers of this function shall now pass in i915 since PXP is a global GPU feature. Make intel_pxp_key_check implicitly find the right gt to verify pxp session key establishment count so it's transparent to the callers. Signed-off-by: Alan Previn --- drivers/gpu/drm/i915/display/skl_universal_plane.c | 2 +- drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 2 +- drivers/gpu/drm/i915/pxp/intel_pxp.c | 12 ++++++++++-- drivers/gpu/drm/i915/pxp/intel_pxp.h | 2 +- 4 files changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index 7cb713043408..04e78acbaf5f 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -1841,7 +1841,7 @@ static bool bo_has_valid_encryption(struct drm_i915_gem_object *obj) { struct drm_i915_private *i915 = to_i915(obj->base.dev); - return intel_pxp_key_check(&to_gt(i915)->pxp, obj, false) == 0; + return intel_pxp_key_check(i915, obj, false) == 0; } static bool pxp_is_borked(struct drm_i915_gem_object *obj) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index 8f5796cf9c9c..79fb8da1c646 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -868,7 +868,7 @@ static struct i915_vma *eb_lookup_vma(struct i915_execbuffer *eb, u32 handle) */ if (i915_gem_context_uses_protected_content(eb->gem_context) && i915_gem_object_is_protected(obj)) { - err = intel_pxp_key_check(&vm->gt->pxp, obj, true); + err = intel_pxp_key_check(vm->gt->i915, obj, true); if (err) { i915_gem_object_put(obj); return ERR_PTR(err); diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c index 944c8466f786..148f9fbd907a 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c @@ -300,11 +300,19 @@ void intel_pxp_fini_hw(struct intel_pxp *pxp) intel_pxp_irq_disable(pxp); } -int intel_pxp_key_check(struct intel_pxp *pxp, +int intel_pxp_key_check(struct drm_i915_private *i915, struct drm_i915_gem_object *obj, bool assign) { - if (!intel_pxp_is_active(pxp_to_gt(pxp)->i915)) + struct intel_gt *gt = intel_pxp_get_owning_gt(i915); + struct intel_pxp *pxp; + + if (!gt) + return -ENODEV; + + pxp = >->pxp; + + if (!intel_pxp_is_active(i915)) return -ENODEV; if (!i915_gem_object_is_protected(obj)) diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h index 61ef3bedc3a0..94fec55389df 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.h +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h @@ -28,7 +28,7 @@ void intel_pxp_mark_termination_in_progress(struct intel_pxp *pxp); int intel_pxp_start(struct drm_i915_private *i915); -int intel_pxp_key_check(struct intel_pxp *pxp, +int intel_pxp_key_check(struct drm_i915_private *i915, struct drm_i915_gem_object *obj, bool assign); From patchwork Thu Oct 6 04:38:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alan Previn X-Patchwork-Id: 12999956 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C54B4C433FE for ; Thu, 6 Oct 2022 04:36:48 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D437B10E7D9; Thu, 6 Oct 2022 04:36:38 +0000 (UTC) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6C25110E7DA for ; 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a="953462916" X-IronPort-AV: E=Sophos;i="5.95,162,1661842800"; d="scan'208";a="953462916" Received: from aalteres-desk.fm.intel.com ([10.80.57.53]) by fmsmga005.fm.intel.com with ESMTP; 05 Oct 2022 21:36:31 -0700 From: Alan Previn To: intel-gfx@lists.freedesktop.org Date: Wed, 5 Oct 2022 21:38:33 -0700 Message-Id: <20221006043834.606220-8-alan.previn.teres.alexis@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221006043834.606220-1-alan.previn.teres.alexis@intel.com> References: <20221006043834.606220-1-alan.previn.teres.alexis@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 7/7] drm/i915/pxp: Make intel_pxp power management implicitly sort PXP-owning-GT X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Make PXP suspend/ resume functions implicitly verify if the caller is the PXP-owning-GT. PXP control structure still hangs off the intel_gt structure that manages has gt-level power management events. Thus change the input param to intel_gt structure and let PXP implicitly take the expected action only if triggered from the PXP-owning-GT. Signed-off-by: Alan Previn --- drivers/gpu/drm/i915/gt/intel_gt_pm.c | 10 +++--- drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 44 ++++++++++++++++++++----- drivers/gpu/drm/i915/pxp/intel_pxp_pm.h | 22 ++++++------- 3 files changed, 51 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_pm.c index f553e2173bda..0f477dfb392d 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c @@ -276,7 +276,7 @@ int intel_gt_resume(struct intel_gt *gt) intel_uc_resume(>->uc); - intel_pxp_resume(>->pxp); + intel_pxp_resume(gt); user_forcewake(gt, false); @@ -312,7 +312,7 @@ void intel_gt_suspend_prepare(struct intel_gt *gt) user_forcewake(gt, true); wait_for_suspend(gt); - intel_pxp_suspend_prepare(>->pxp); + intel_pxp_suspend_prepare(gt); } static suspend_state_t pm_suspend_target(void) @@ -337,7 +337,7 @@ void intel_gt_suspend_late(struct intel_gt *gt) GEM_BUG_ON(gt->awake); intel_uc_suspend(>->uc); - intel_pxp_suspend(>->pxp); + intel_pxp_suspend(gt); /* * On disabling the device, we want to turn off HW access to memory @@ -365,7 +365,7 @@ void intel_gt_suspend_late(struct intel_gt *gt) void intel_gt_runtime_suspend(struct intel_gt *gt) { - intel_pxp_runtime_suspend(>->pxp); + intel_pxp_runtime_suspend(gt); intel_uc_runtime_suspend(>->uc); GT_TRACE(gt, "\n"); @@ -383,7 +383,7 @@ int intel_gt_runtime_resume(struct intel_gt *gt) if (ret) return ret; - intel_pxp_runtime_resume(>->pxp); + intel_pxp_runtime_resume(gt); return 0; } diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c index 5f713ac5c3ce..81e03c4eea71 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c @@ -9,34 +9,54 @@ #include "intel_pxp_session.h" #include "i915_drv.h" -void intel_pxp_suspend_prepare(struct intel_pxp *pxp) +void intel_pxp_suspend_prepare(struct intel_gt *gt) { - if (!intel_pxp_is_enabled(pxp_to_gt(pxp)->i915)) + struct intel_pxp *pxp; + + if (!intel_pxp_is_enabled(gt->i915)) + return; + + if (!gt->pxptee_iface_owner) return; + pxp = >->pxp; + pxp->arb_is_valid = false; intel_pxp_invalidate(pxp); } -void intel_pxp_suspend(struct intel_pxp *pxp) +void intel_pxp_suspend(struct intel_gt *gt) { + struct intel_pxp *pxp; intel_wakeref_t wakeref; - if (!intel_pxp_is_enabled(pxp_to_gt(pxp)->i915)) + if (!intel_pxp_is_enabled(gt->i915)) return; - with_intel_runtime_pm(&pxp_to_gt(pxp)->i915->runtime_pm, wakeref) { + if (!gt->pxptee_iface_owner) + return; + + pxp = >->pxp; + + with_intel_runtime_pm(>->i915->runtime_pm, wakeref) { intel_pxp_fini_hw(pxp); pxp->hw_state_invalidated = false; } } -void intel_pxp_resume(struct intel_pxp *pxp) +void intel_pxp_resume(struct intel_gt *gt) { - if (!intel_pxp_is_enabled(pxp_to_gt(pxp)->i915)) + struct intel_pxp *pxp; + + if (!intel_pxp_is_enabled(gt->i915)) + return; + + if (!gt->pxptee_iface_owner) return; + pxp = >->pxp; + /* * The PXP component gets automatically unbound when we go into S3 and * re-bound after we come out, so in that scenario we can defer the @@ -48,11 +68,17 @@ void intel_pxp_resume(struct intel_pxp *pxp) intel_pxp_init_hw(pxp); } -void intel_pxp_runtime_suspend(struct intel_pxp *pxp) +void intel_pxp_runtime_suspend(struct intel_gt *gt) { - if (!intel_pxp_is_enabled(pxp_to_gt(pxp)->i915)) + struct intel_pxp *pxp; + + if (!intel_pxp_is_enabled(gt->i915)) + return; + + if (!gt->pxptee_iface_owner) return; + pxp = >->pxp; pxp->arb_is_valid = false; intel_pxp_fini_hw(pxp); diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.h b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.h index 586be769104f..c87d54699793 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.h +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.h @@ -6,32 +6,32 @@ #ifndef __INTEL_PXP_PM_H__ #define __INTEL_PXP_PM_H__ -struct intel_pxp; +struct intel_gt; #ifdef CONFIG_DRM_I915_PXP -void intel_pxp_suspend_prepare(struct intel_pxp *pxp); -void intel_pxp_suspend(struct intel_pxp *pxp); -void intel_pxp_resume(struct intel_pxp *pxp); -void intel_pxp_runtime_suspend(struct intel_pxp *pxp); +void intel_pxp_suspend_prepare(struct intel_gt *gt); +void intel_pxp_suspend(struct intel_gt *gt); +void intel_pxp_resume(struct intel_gt *gt); +void intel_pxp_runtime_suspend(struct intel_gt *gt); #else -static inline void intel_pxp_suspend_prepare(struct intel_pxp *pxp) +static inline void intel_pxp_suspend_prepare(struct intel_gt *gt) { } -static inline void intel_pxp_suspend(struct intel_pxp *pxp) +static inline void intel_pxp_suspend(struct intel_gt *gt) { } -static inline void intel_pxp_resume(struct intel_pxp *pxp) +static inline void intel_pxp_resume(struct intel_gt *gt) { } -static inline void intel_pxp_runtime_suspend(struct intel_pxp *pxp) +static inline void intel_pxp_runtime_suspend(struct intel_gt *gt) { } #endif -static inline void intel_pxp_runtime_resume(struct intel_pxp *pxp) +static inline void intel_pxp_runtime_resume(struct intel_gt *gt) { - intel_pxp_resume(pxp); + intel_pxp_resume(gt); } #endif /* __INTEL_PXP_PM_H__ */