From patchwork Wed Oct 12 04:51:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas De Marchi X-Patchwork-Id: 13004677 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AEAE5C4332F for ; Wed, 12 Oct 2022 04:52:09 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CD74C10E32A; Wed, 12 Oct 2022 04:51:49 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7F32D10E31C; Wed, 12 Oct 2022 04:51:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1665550303; x=1697086303; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=H4v1M05nUOxjGbYQ6sC47/OrUzmGPqCBlVIqhM2NPZU=; b=GRL7NQAAmUa1WSYNnC+SpRwdPlM105GU+F1tuH2NXvW60whn7Ss/4K45 xohmUe/tF5hvYt//zbSyeu1awMy6VZrOQ/JMlFdxpe0ejmRjqQ3S5s5GJ nlFDrkS0eDDvfzuohH1+5fgBaD942+4M0P3vF2aqx5XYtpoTTzySfenpk zU/CUvUzVdSgF75Jppvl4UAtQtiuXleDYTg2O6fl6Vd8JhRyKvUxVksls PNxBBwZOBHsnLy4t4KOnU2quXMIdga1Xs/Kgirw9XvuMDKaQi49/OyzZz pngpzUBV0v82igHk10BdnObA5MBiPAOPYYvZcEAJxWodImv9NPK0iUHDD Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10497"; a="284423458" X-IronPort-AV: E=Sophos;i="5.95,178,1661842800"; d="scan'208";a="284423458" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Oct 2022 21:51:42 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10497"; a="577698655" X-IronPort-AV: E=Sophos;i="5.95,178,1661842800"; d="scan'208";a="577698655" Received: from lucas-s2600cw.jf.intel.com ([10.165.21.143]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Oct 2022 21:51:41 -0700 From: Lucas De Marchi To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, Lucas De Marchi Subject: [PATCH 1/3] drm/i915: Add _PICK_EVEN_RANGES() Date: Tue, 11 Oct 2022 21:51:08 -0700 Message-Id: <20221011-pick-even-ranges-v1-1-1aaea52752ed@intel.com> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20221011-pick-even-ranges-v1-0-1aaea52752ed@intel.com> References: <20221011-pick-even-ranges-v1-0-1aaea52752ed@intel.com> MIME-Version: 1.0 X-Mailer: b4 0.10.1 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Anusha Srivatsa Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" It's a constant pattern in the driver to need to use 2 ranges of MMIOs based on port, phy, pll, etc. When that happens, instead of using _PICK_EVEN(), _PICK() needs to be used. Using _PICK() is discouraged due to some reasons like: 1) It increases the code size since the array is declared in each call site 2) Developers need to be careful not to incur an out-of-bounds array access 3) Developers need to be careful that the indexes match the table. For that it may be that the table needs to contain holes, making (1) even worse. Signed-off-by: Lucas De Marchi (cherry picked from commit 55a65ca6e5d8f7f46fe4cf29c76a9f1b4ddef5ce) --- drivers/gpu/drm/i915/i915_reg.h | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 3edfbe92c6dd..d157dd693e41 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -126,10 +126,24 @@ #define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a))) /* - * Given the arbitrary numbers in varargs, pick the 0-based __index'th number. + * Like _PICK_EVEN(), but supports 2 ranges of evenly spaced addres offsets. The + * @__use_first_range argument selects if the first or second range should be + * used. It's usually in the form like ``(pll) < n``, in which ``n`` is the + * number of registers in the first range. Example:: * - * Always prefer _PICK_EVEN() over this if the numbers are evenly spaced. + * #define _FOO_A 0xf000 + * #define _FOO_B 0xf004 + * #define _FOO_C 0xf008 + * #define _SUPER_FOO_A 0xa000 + * #define _SUPER_FOO_B 0xaf00 + * #define FOO(x) _MMIO(_PICK_EVEN_RANGES(x, (x) < 3, \ + * _FOO_A, _FOO_B, \ + * _SUPER_FOO_A, _SUPER_FOO_B)) */ +#define _PICK_EVEN_RANGES(__index, __use_first_range, __a, __b, __c, __d) \ + ((__use_first_range) ? _PICK_EVEN(__index, __a, __b) : \ + _PICK_EVEN(__index, __c, __d)) + #define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index]) /* From patchwork Wed Oct 12 04:51:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas De Marchi X-Patchwork-Id: 13004676 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A3A24C4332F for ; Wed, 12 Oct 2022 04:52:03 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E9AB310E326; Wed, 12 Oct 2022 04:51:48 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id ACF4010E320; Wed, 12 Oct 2022 04:51:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1665550303; x=1697086303; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=trOZeSN/sAQ6QPyIH22yKHJNbvNXL/LVcvSAB4nj+zU=; b=JCqBySz5PYcWSK85MUojjOCGp2vFLWaMiIwKNObRzAipBJKGzC+NaiBZ NW7VowRT22onuRjq1RM+wZa7meaPKr+X/7Ia3IazCmjQxqFwsaCK7SwDM vGAfaV6KRy/H8Z5kCIRThupU8TTbUiw3kOuWfrTX2B+s4798CS6ENBxOB muJyaxJbrDFwc/9b+FC5j8ALOtdBvI31aVUTl0B8mj6zdjBxYiBQ35wkt XSxkmmeiQvZFppE1cOMO+l/sQxpaIxu5l8Smz4JGHcUunlKJIAojuobLb 7wIc00IXLGYNXL2Mcp2j3qbPZhgxCCL5RiuMmCfijSKbv59pxo9Ff43eY w==; X-IronPort-AV: E=McAfee;i="6500,9779,10497"; a="284423460" X-IronPort-AV: E=Sophos;i="5.95,178,1661842800"; d="scan'208";a="284423460" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Oct 2022 21:51:42 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10497"; a="577698658" X-IronPort-AV: E=Sophos;i="5.95,178,1661842800"; d="scan'208";a="577698658" Received: from lucas-s2600cw.jf.intel.com ([10.165.21.143]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Oct 2022 21:51:41 -0700 From: Lucas De Marchi To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, Lucas De Marchi Subject: [PATCH 2/3] drm/i915: Fix coding style on DPLL*_ENABLE defines Date: Tue, 11 Oct 2022 21:51:09 -0700 Message-Id: <20221011-pick-even-ranges-v1-2-1aaea52752ed@intel.com> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20221011-pick-even-ranges-v1-0-1aaea52752ed@intel.com> References: <20221011-pick-even-ranges-v1-0-1aaea52752ed@intel.com> MIME-Version: 1.0 X-Mailer: b4 0.10.1 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Anusha Srivatsa Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Abide by the rules in the top of the header: 2 spaces for bitfield, prefix offsets with underscore and prefer the use of REG_BIT(). Signed-off-by: Lucas De Marchi (cherry picked from commit c5545ec37a7f5b928f3f6e3993f1f24b9e70ba32) --- drivers/gpu/drm/i915/i915_reg.h | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index d157dd693e41..ad8f839046f5 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7305,20 +7305,20 @@ enum skl_power_gate { ADLS_DPCLKA_DDIK_SEL_MASK) /* ICL PLL */ -#define DPLL0_ENABLE 0x46010 -#define DPLL1_ENABLE 0x46014 +#define _DPLL0_ENABLE 0x46010 +#define _DPLL1_ENABLE 0x46014 #define _ADLS_DPLL2_ENABLE 0x46018 #define _ADLS_DPLL3_ENABLE 0x46030 -#define PLL_ENABLE (1 << 31) -#define PLL_LOCK (1 << 30) -#define PLL_POWER_ENABLE (1 << 27) -#define PLL_POWER_STATE (1 << 26) -#define ICL_DPLL_ENABLE(pll) _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \ +#define PLL_ENABLE REG_BIT(31) +#define PLL_LOCK REG_BIT(30) +#define PLL_POWER_ENABLE REG_BIT(27) +#define PLL_POWER_STATE REG_BIT(26) +#define ICL_DPLL_ENABLE(pll) _MMIO_PLL3(pll, _DPLL0_ENABLE, _DPLL1_ENABLE, \ _ADLS_DPLL2_ENABLE, _ADLS_DPLL3_ENABLE) #define _DG2_PLL3_ENABLE 0x4601C -#define DG2_PLL_ENABLE(pll) _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \ +#define DG2_PLL_ENABLE(pll) _MMIO_PLL3(pll, _DPLL0_ENABLE, _DPLL1_ENABLE, \ _ADLS_DPLL2_ENABLE, _DG2_PLL3_ENABLE) #define TBT_PLL_ENABLE _MMIO(0x46020) @@ -7327,12 +7327,12 @@ enum skl_power_gate { #define _MG_PLL2_ENABLE 0x46034 #define _MG_PLL3_ENABLE 0x46038 #define _MG_PLL4_ENABLE 0x4603C -/* Bits are the same as DPLL0_ENABLE */ +/* Bits are the same as _DPLL0_ENABLE */ #define MG_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \ _MG_PLL2_ENABLE) /* DG1 PLL */ -#define DG1_DPLL_ENABLE(pll) _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \ +#define DG1_DPLL_ENABLE(pll) _MMIO_PLL3(pll, _DPLL0_ENABLE, _DPLL1_ENABLE, \ _MG_PLL1_ENABLE, _MG_PLL2_ENABLE) /* ADL-P Type C PLL */ From patchwork Wed Oct 12 04:51:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas De Marchi X-Patchwork-Id: 13004679 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 971E1C433FE for ; Wed, 12 Oct 2022 04:52:19 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E011710E33C; Wed, 12 Oct 2022 04:51:56 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id E573410E321; Wed, 12 Oct 2022 04:51:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1665550303; x=1697086303; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=hzo02FYd5kgYgvebJ4cPMaJTtQSmqXNmg4sPCFpzJxM=; b=nvbRW788KUVD3A6SqkihoSDrJhgtY7KILfvKI7YuB3sylE1eLn473VDJ p1ybctg2Uk5Lv+thNt2tFXFtdUCA1ATgpE9SxL8exyp94NGMMVg1hVsng AcF6LAUakm4Lc78y8Bi3JRLd2goxn9Jq64WeiPNCOik516p6G6w5Ui56P 8h1CByDYymjipiwPlxI3JddrgLSgfVqhX90FwWmHLVi/OMFV9xf6vzRwd yP2upQFj8LXCbsPP3BFR4RGsO35cMtzXPwXy3lIRzLenyt38gf1bNVKJY ++v/XB+rPkGhvecs2ndGjGwpjStr2NXk9qun4m8MsiFk4Nsqtwb2vH3Sw Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10497"; a="284423462" X-IronPort-AV: E=Sophos;i="5.95,178,1661842800"; d="scan'208";a="284423462" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Oct 2022 21:51:42 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10497"; a="577698661" X-IronPort-AV: E=Sophos;i="5.95,178,1661842800"; d="scan'208";a="577698661" Received: from lucas-s2600cw.jf.intel.com ([10.165.21.143]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Oct 2022 21:51:41 -0700 From: Lucas De Marchi To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, Lucas De Marchi Subject: [PATCH 3/3] drm/i915: Convert pll macros to _PICK_EVEN_RANGES Date: Tue, 11 Oct 2022 21:51:10 -0700 Message-Id: <20221011-pick-even-ranges-v1-3-1aaea52752ed@intel.com> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20221011-pick-even-ranges-v1-0-1aaea52752ed@intel.com> References: <20221011-pick-even-ranges-v1-0-1aaea52752ed@intel.com> MIME-Version: 1.0 X-Mailer: b4 0.10.1 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Anusha Srivatsa Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Avoid the array lookup, converting the PLL macros after ICL to _PICK_EVEN_RANGES. This provides the following reduction in code size: $ size build64/drivers/gpu/drm/i915/i915.o{.old,.new} text data bss dec hex filename 3570297 131232 6824 3708353 3895c1 build64/drivers/gpu/drm/i915/i915.o.old 3569686 131232 6824 3707742 38935e build64/drivers/gpu/drm/i915/i915.o.new At the same time it's safer, avoiding out-of-bounds array access. Signed-off-by: Lucas De Marchi (cherry picked from commit 592d15e3d72009bfb9f7a933c292510f8564a4cf) --- drivers/gpu/drm/i915/i915_reg.h | 59 ++++++++++++++++++++--------------------- 1 file changed, 29 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index ad8f839046f5..df30bcc53489 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7313,13 +7313,15 @@ enum skl_power_gate { #define PLL_LOCK REG_BIT(30) #define PLL_POWER_ENABLE REG_BIT(27) #define PLL_POWER_STATE REG_BIT(26) -#define ICL_DPLL_ENABLE(pll) _MMIO_PLL3(pll, _DPLL0_ENABLE, _DPLL1_ENABLE, \ - _ADLS_DPLL2_ENABLE, _ADLS_DPLL3_ENABLE) +#define ICL_DPLL_ENABLE(pll) _MMIO(_PICK_EVEN_RANGES(pll, (pll) < 3, \ + _DPLL0_ENABLE, _DPLL1_ENABLE, \ + _ADLS_DPLL3_ENABLE, _ADLS_DPLL3_ENABLE)) #define _DG2_PLL3_ENABLE 0x4601C -#define DG2_PLL_ENABLE(pll) _MMIO_PLL3(pll, _DPLL0_ENABLE, _DPLL1_ENABLE, \ - _ADLS_DPLL2_ENABLE, _DG2_PLL3_ENABLE) +#define DG2_PLL_ENABLE(pll) _MMIO(_PICK_EVEN_RANGES(pll, (pll) < 3, \ + _DPLL0_ENABLE, _DPLL1_ENABLE, \ + _DG2_PLL3_ENABLE, _DG2_PLL3_ENABLE)) #define TBT_PLL_ENABLE _MMIO(0x46020) @@ -7332,8 +7334,9 @@ enum skl_power_gate { _MG_PLL2_ENABLE) /* DG1 PLL */ -#define DG1_DPLL_ENABLE(pll) _MMIO_PLL3(pll, _DPLL0_ENABLE, _DPLL1_ENABLE, \ - _MG_PLL1_ENABLE, _MG_PLL2_ENABLE) +#define DG1_DPLL_ENABLE(pll) _MMIO(_PICK_EVEN_RANGES(pll, (pll) < 2, \ + _DPLL0_ENABLE, _DPLL1_ENABLE, \ + _MG_PLL1_ENABLE, _MG_PLL2_ENABLE)) /* ADL-P Type C PLL */ #define PORTTC1_PLL_ENABLE 0x46038 @@ -7393,9 +7396,9 @@ enum skl_power_gate { #define _TGL_DPLL0_CFGCR0 0x164284 #define _TGL_DPLL1_CFGCR0 0x16428C #define _TGL_TBTPLL_CFGCR0 0x16429C -#define TGL_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \ - _TGL_DPLL1_CFGCR0, \ - _TGL_TBTPLL_CFGCR0) +#define TGL_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_RANGES(pll, (pll) < 2, \ + _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0, \ + _TGL_TBTPLL_CFGCR0, _TGL_TBTPLL_CFGCR0)) #define RKL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR0, \ _TGL_DPLL1_CFGCR0) @@ -7408,40 +7411,36 @@ enum skl_power_gate { #define _TGL_DPLL0_CFGCR1 0x164288 #define _TGL_DPLL1_CFGCR1 0x164290 #define _TGL_TBTPLL_CFGCR1 0x1642A0 -#define TGL_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \ - _TGL_DPLL1_CFGCR1, \ - _TGL_TBTPLL_CFGCR1) +#define TGL_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_RANGES(pll, (pll) < 2, \ + _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1, \ + _TGL_TBTPLL_CFGCR1, _TGL_TBTPLL_CFGCR1)) #define RKL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR1, \ _TGL_DPLL1_CFGCR1) #define _DG1_DPLL2_CFGCR0 0x16C284 #define _DG1_DPLL3_CFGCR0 0x16C28C -#define DG1_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \ - _TGL_DPLL1_CFGCR0, \ - _DG1_DPLL2_CFGCR0, \ - _DG1_DPLL3_CFGCR0) +#define DG1_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_RANGES(pll, (pll) < 2, \ + _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0, \ + _DG1_DPLL2_CFGCR0, _DG1_DPLL3_CFGCR0)) #define _DG1_DPLL2_CFGCR1 0x16C288 #define _DG1_DPLL3_CFGCR1 0x16C290 -#define DG1_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \ - _TGL_DPLL1_CFGCR1, \ - _DG1_DPLL2_CFGCR1, \ - _DG1_DPLL3_CFGCR1) +#define DG1_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_RANGES(pll, (pll) < 2, \ + _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1, \ + _DG1_DPLL2_CFGCR1, _DG1_DPLL3_CFGCR1)) /* For ADL-S DPLL4_CFGCR0/1 are used to control DPLL2 */ -#define _ADLS_DPLL3_CFGCR0 0x1642C0 #define _ADLS_DPLL4_CFGCR0 0x164294 -#define ADLS_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \ - _TGL_DPLL1_CFGCR0, \ - _ADLS_DPLL4_CFGCR0, \ - _ADLS_DPLL3_CFGCR0) +#define _ADLS_DPLL3_CFGCR0 0x1642C0 +#define ADLS_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_RANGES(pll, (pll) < 2, \ + _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0, \ + _ADLS_DPLL4_CFGCR0, _ADLS_DPLL3_CFGCR0)) -#define _ADLS_DPLL3_CFGCR1 0x1642C4 #define _ADLS_DPLL4_CFGCR1 0x164298 -#define ADLS_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \ - _TGL_DPLL1_CFGCR1, \ - _ADLS_DPLL4_CFGCR1, \ - _ADLS_DPLL3_CFGCR1) +#define _ADLS_DPLL3_CFGCR1 0x1642C4 +#define ADLS_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_RANGES(pll, (pll) < 2, \ + _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1, \ + _ADLS_DPLL4_CFGCR1, _ADLS_DPLL3_CFGCR1)) #define _DKL_PHY1_BASE 0x168000 #define _DKL_PHY2_BASE 0x169000