From patchwork Thu Oct 13 13:18:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Stein X-Patchwork-Id: 13005987 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2548FC4332F for ; Thu, 13 Oct 2022 13:19:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229964AbiJMNTO (ORCPT ); Thu, 13 Oct 2022 09:19:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35198 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229966AbiJMNTN (ORCPT ); Thu, 13 Oct 2022 09:19:13 -0400 Received: from mx1.tq-group.com (mx1.tq-group.com [93.104.207.81]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 14B074E190; Thu, 13 Oct 2022 06:19:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tq-group.com; i=@tq-group.com; q=dns/txt; s=key1; t=1665667145; x=1697203145; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=G3oHLugWLky0csD+inQW1HPD0hUDCdDKmAGzQ9GFoOY=; b=T+9S+Xv9PeciUadYC11eMcnN97eWkuAKIYSIRhYaEmzczAt5eKNQNp2d gwz534HtFD3C5PVom9cin7HxwopiIgxQ9m2FWBp5WOUwVJTmRvdB2rMb4 WL8jc0F8m3PAGeu3szDLsFiahUvldnXaCtwyjl7W1R2Tzgpxh4dfdXj1o 4BiGVpdOvtb487GtsQsBfaF10Lrp3KnWxb1cEPbEvTUyjaHwaifiXhL8K vNKQQQcBAp9Pr39Viu9qB2hTqBBSF5attK7YhimaAVBZMHzUAGUSO1u+I Fk61FAfoi6ZCOlW56LqWbEWiGJ91WAmf1ezuRO7WC2/eRnrrzMaJNe22v Q==; X-IronPort-AV: E=Sophos;i="5.95,180,1661810400"; d="scan'208";a="26736847" Received: from unknown (HELO tq-pgp-pr1.tq-net.de) ([192.168.6.15]) by mx1-pgp.tq-group.com with ESMTP; 13 Oct 2022 15:19:02 +0200 Received: from mx1.tq-group.com ([192.168.6.7]) by tq-pgp-pr1.tq-net.de (PGP Universal service); Thu, 13 Oct 2022 15:19:02 +0200 X-PGP-Universal: processed; by tq-pgp-pr1.tq-net.de on Thu, 13 Oct 2022 15:19:02 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tq-group.com; i=@tq-group.com; q=dns/txt; s=key1; t=1665667142; x=1697203142; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=G3oHLugWLky0csD+inQW1HPD0hUDCdDKmAGzQ9GFoOY=; b=mxPKZjGxVzFAMHIkc0anQdf4mWkEWBe44TF7lIqvSL7jvp+fRSuhb8TV 7S1EBl4/wd1J3I7oWShD1nYH7zbCeQNuug0SufOD8k/dqCV5Fl6Zd5fbz dcmsTg+YBQEu+RmgQMLTLbX14MjHARKxfqyBoaIFwMK73M7gUp5jrqR0l Zgzfm/3qdiPDRwisAIa1DCTC3iOGuS7YXQGt9jkAUNyll3P1rGL20o0x3 3lP/RUMWfIlvdOhYB2ZLrjv7PVHEIcUa7/atQDo1JTOzG68LQOuwc6zbf L9CiUKKWFRSmUkgTynKxtmElBgSroyPdVeR7lAFCgB+G4jFErMSDpbsci Q==; X-IronPort-AV: E=Sophos;i="5.95,180,1661810400"; d="scan'208";a="26736846" Received: from vtuxmail01.tq-net.de ([10.115.0.20]) by mx1.tq-group.com with ESMTP; 13 Oct 2022 15:19:02 +0200 Received: from steina-w.tq-net.de (unknown [10.123.53.21]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by vtuxmail01.tq-net.de (Postfix) with ESMTPSA id 7544A280056; Thu, 13 Oct 2022 15:19:02 +0200 (CEST) From: Alexander Stein To: Abel Vesa , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Shawn Guo , Sascha Hauer , Fabio Estevam Cc: Alexander Stein , Pengutronix Kernel Team , NXP Linux Team , Anson Huang , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 1/5] ARM: dts: imx6qdl: add clocks to clock controller node Date: Thu, 13 Oct 2022 15:18:35 +0200 Message-Id: <20221013131839.1365394-2-alexander.stein@ew.tq-group.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221013131839.1365394-1-alexander.stein@ew.tq-group.com> References: <20221013131839.1365394-1-alexander.stein@ew.tq-group.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add missing anaclk clocks and needed labels for the existing clocks. Signed-off-by: Alexander Stein --- arch/arm/boot/dts/imx6qdl.dtsi | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 1a4b299815ca..e357ee2df779 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -54,23 +54,35 @@ aliases { }; clocks { - ckil { + ckil: ckil { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; }; - ckih1 { + ckih1: ckih1 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; - osc { + osc: osc { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24000000>; }; + + anaclk1: anaclk1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + anaclk2: anaclk2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; }; ldb: ldb { @@ -686,6 +698,10 @@ clks: clock-controller@20c4000 { interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>, <0 88 IRQ_TYPE_LEVEL_HIGH>; #clock-cells = <1>; + clocks = <&osc>, <&ckil>, <&ckih1>, + <&anaclk1>, <&anaclk2>; + clock-names = "osc", "ckil", "ckih1", + "anaclk1", "anaclk2"; }; anatop: anatop@20c8000 { From patchwork Thu Oct 13 13:18:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Stein X-Patchwork-Id: 13005986 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2CC2CC4332F for ; Thu, 13 Oct 2022 13:19:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229874AbiJMNTK (ORCPT ); Thu, 13 Oct 2022 09:19:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35044 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229943AbiJMNTJ (ORCPT ); Thu, 13 Oct 2022 09:19:09 -0400 Received: from mx1.tq-group.com (mx1.tq-group.com [93.104.207.81]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8523212FF8C; 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Thu, 13 Oct 2022 15:19:02 +0200 (CEST) From: Alexander Stein To: Abel Vesa , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Shawn Guo , Sascha Hauer , Fabio Estevam Cc: Alexander Stein , Pengutronix Kernel Team , NXP Linux Team , Anson Huang , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 2/5] dt-bindings: clock: Add ipp_di0 and ipp_di1 clocks to i.MX6Q bindings Date: Thu, 13 Oct 2022 15:18:36 +0200 Message-Id: <20221013131839.1365394-3-alexander.stein@ew.tq-group.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221013131839.1365394-1-alexander.stein@ew.tq-group.com> References: <20221013131839.1365394-1-alexander.stein@ew.tq-group.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org These are alternative input clocks for IPU available as external inputs. Signed-off-by: Alexander Stein --- Documentation/devicetree/bindings/clock/imx6q-clock.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/imx6q-clock.yaml b/Documentation/devicetree/bindings/clock/imx6q-clock.yaml index 4f4637eddb8b..329e4cb95dc0 100644 --- a/Documentation/devicetree/bindings/clock/imx6q-clock.yaml +++ b/Documentation/devicetree/bindings/clock/imx6q-clock.yaml @@ -34,6 +34,8 @@ properties: - description: ckih1 clock input - description: anaclk1 clock input - description: anaclk2 clock input + - description: ipp_di0 clock input + - description: ipp_di1 clock input clock-names: items: @@ -42,6 +44,8 @@ properties: - const: ckih1 - const: anaclk1 - const: anaclk2 + - const: ipp_di0 + - const: ipp_di1 fsl,pmic-stby-poweroff: $ref: /schemas/types.yaml#/definitions/flag From patchwork Thu Oct 13 13:18:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Stein X-Patchwork-Id: 13005989 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1205CC4321E for ; Thu, 13 Oct 2022 13:19:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229979AbiJMNTT (ORCPT ); Thu, 13 Oct 2022 09:19:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35364 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229484AbiJMNTS (ORCPT ); Thu, 13 Oct 2022 09:19:18 -0400 Received: from mx1.tq-group.com (mx1.tq-group.com [93.104.207.81]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 150C04E1A5; Thu, 13 Oct 2022 06:19:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tq-group.com; i=@tq-group.com; q=dns/txt; s=key1; t=1665667150; x=1697203150; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=DjCc8SJrGVWpiGwVXlXdMk13NbJ0gVyRaa4NngcEEjM=; b=UzcscVa5F4le8+PjU1aEI+AkGqGvfz0NCtPCfL3++zWN8SWDCqboCOsj vL1qxdLG4KZuFN1K5afd3IGelCAHhvfjgh/f1jSrPeu7jVB9z2r1eYSf0 EVSRJpqz2z1lpviDY6XRTR7vc/tg8Ll7MxvRc0/Vlp9NlvETwWJ81EPe6 W9Hu9D7dfkiyAGiJm9eytF33LTSYkeYx99f38Pdn+SIAqxjvN1e6/fnUd Y2VpkRCG5RUSl8RJoDVXUiek1N9jaSkkjMKf/+8fF0lxwEbWFjr9wi+B1 wDGGj6fiW6sLT9dvXxeAkMjPICPgo21VhOBP0bOQgL8iSrU32+Ks8uQNz w==; X-IronPort-AV: E=Sophos;i="5.95,180,1661810400"; d="scan'208";a="26736851" Received: from unknown (HELO tq-pgp-pr1.tq-net.de) ([192.168.6.15]) by mx1-pgp.tq-group.com with ESMTP; 13 Oct 2022 15:19:03 +0200 Received: from mx1.tq-group.com ([192.168.6.7]) by tq-pgp-pr1.tq-net.de (PGP Universal service); Thu, 13 Oct 2022 15:19:03 +0200 X-PGP-Universal: processed; by tq-pgp-pr1.tq-net.de on Thu, 13 Oct 2022 15:19:03 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tq-group.com; i=@tq-group.com; q=dns/txt; s=key1; t=1665667143; x=1697203143; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=DjCc8SJrGVWpiGwVXlXdMk13NbJ0gVyRaa4NngcEEjM=; b=dinCcrBkmhzm3wY3dxtU9DRQiC2JhJ49vEuoDcEtvvaGJZIc6I9rcqKQ 7yEiBjn4xdQKjHf8tLZC1sL0cBwufhrWJHzLnx9LtOnjxrghM+YsPV7bI xRSHv5KE0aV+LVgI2hIrVwYNDqDoA3aJFpEmAjhIZcBYlJbV0rPbTgiNY w9rIDeuyQh/ZAgfszTP/9uBT21xgYfctitmM9j5ch5UeQ4OLU3B3cNhrN rhu3WnAQsuogVFrXMAAs332WL0zrr/FWSWY6Z0r8Biiio/CNjOPWSRIYu 83CXOU6yKx3BwPhtbT/sArgpX5TuRfjfLEZ47y7fK2DjZOlmyFxakyl2E g==; X-IronPort-AV: E=Sophos;i="5.95,180,1661810400"; d="scan'208";a="26736850" Received: from vtuxmail01.tq-net.de ([10.115.0.20]) by mx1.tq-group.com with ESMTP; 13 Oct 2022 15:19:03 +0200 Received: from steina-w.tq-net.de (unknown [10.123.53.21]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by vtuxmail01.tq-net.de (Postfix) with ESMTPSA id 1B3BE280056; Thu, 13 Oct 2022 15:19:03 +0200 (CEST) From: Alexander Stein To: Abel Vesa , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Shawn Guo , Sascha Hauer , Fabio Estevam Cc: Alexander Stein , Pengutronix Kernel Team , NXP Linux Team , Anson Huang , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 3/5] ARM: dts: imx6qdl: add missing ipp_di clocks to clock controller node Date: Thu, 13 Oct 2022 15:18:37 +0200 Message-Id: <20221013131839.1365394-4-alexander.stein@ew.tq-group.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221013131839.1365394-1-alexander.stein@ew.tq-group.com> References: <20221013131839.1365394-1-alexander.stein@ew.tq-group.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org These are external input clocks and a rate must be provided explicitly. Signed-off-by: Alexander Stein --- arch/arm/boot/dts/imx6qdl.dtsi | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index e357ee2df779..def4e4e4b29e 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -83,6 +83,20 @@ anaclk2: anaclk2 { #clock-cells = <0>; clock-frequency = <0>; }; + + ipp_di0: ipp-di0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "ipp_di0"; + }; + + ipp_di1: ipp-di1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "ipp_di1"; + }; }; ldb: ldb { @@ -699,9 +713,11 @@ clks: clock-controller@20c4000 { <0 88 IRQ_TYPE_LEVEL_HIGH>; #clock-cells = <1>; clocks = <&osc>, <&ckil>, <&ckih1>, - <&anaclk1>, <&anaclk2>; + <&anaclk1>, <&anaclk2>, + <&ipp_di0>, <&ipp_di1>; clock-names = "osc", "ckil", "ckih1", - "anaclk1", "anaclk2"; + "anaclk1", "anaclk2", + "ipp_di0", "ipp_di1"; }; anatop: anatop@20c8000 { From patchwork Thu Oct 13 13:18:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Stein X-Patchwork-Id: 13005990 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2C762C4332F for ; Thu, 13 Oct 2022 13:19:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229801AbiJMNTV (ORCPT ); Thu, 13 Oct 2022 09:19:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35298 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229943AbiJMNTT (ORCPT ); Thu, 13 Oct 2022 09:19:19 -0400 Received: from mx1.tq-group.com (mx1.tq-group.com [93.104.207.81]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9FC8E4E183; Thu, 13 Oct 2022 06:19:11 -0700 (PDT) DKIM-Signature: v=1; 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Thu, 13 Oct 2022 15:19:03 +0200 (CEST) From: Alexander Stein To: Abel Vesa , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Shawn Guo , Sascha Hauer , Fabio Estevam Cc: Alexander Stein , Pengutronix Kernel Team , NXP Linux Team , Anson Huang , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 4/5] clk: imx6q: Add ipp-di0 and ipp-di1 clocks Date: Thu, 13 Oct 2022 15:18:38 +0200 Message-Id: <20221013131839.1365394-5-alexander.stein@ew.tq-group.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221013131839.1365394-1-alexander.stein@ew.tq-group.com> References: <20221013131839.1365394-1-alexander.stein@ew.tq-group.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Described in CCM_CHSCCDR and CCM_CSCDR2 in the fields ipuX_diX_pre_clk_sel. Signed-off-by: Alexander Stein --- drivers/clk/imx/clk-imx6q.c | 20 ++++++++++++-------- include/dt-bindings/clock/imx6qdl-clock.h | 4 +++- 2 files changed, 15 insertions(+), 9 deletions(-) diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c index de36f58d551c..6f25361302a6 100644 --- a/drivers/clk/imx/clk-imx6q.c +++ b/drivers/clk/imx/clk-imx6q.c @@ -38,14 +38,14 @@ static const char *gpu3d_shader_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2 static const char *ipu_sels[] = { "mmdc_ch0_axi", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", }; static const char *ldb_di_sels[] = { "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "mmdc_ch1_axi", "pll3_usb_otg", }; static const char *ipu_di_pre_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd1_540m", }; -static const char *ipu1_di0_sels[] = { "ipu1_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; -static const char *ipu1_di1_sels[] = { "ipu1_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; -static const char *ipu2_di0_sels[] = { "ipu2_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; -static const char *ipu2_di1_sels[] = { "ipu2_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; -static const char *ipu1_di0_sels_2[] = { "ipu1_di0_pre", "dummy", "dummy", "ldb_di0_podf", "ldb_di1_podf", }; -static const char *ipu1_di1_sels_2[] = { "ipu1_di1_pre", "dummy", "dummy", "ldb_di0_podf", "ldb_di1_podf", }; -static const char *ipu2_di0_sels_2[] = { "ipu2_di0_pre", "dummy", "dummy", "ldb_di0_podf", "ldb_di1_podf", }; -static const char *ipu2_di1_sels_2[] = { "ipu2_di1_pre", "dummy", "dummy", "ldb_di0_podf", "ldb_di1_podf", }; +static const char *ipu1_di0_sels[] = { "ipu1_di0_pre", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", }; +static const char *ipu1_di1_sels[] = { "ipu1_di1_pre", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", }; +static const char *ipu2_di0_sels[] = { "ipu2_di0_pre", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", }; +static const char *ipu2_di1_sels[] = { "ipu2_di1_pre", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", }; +static const char *ipu1_di0_sels_2[] = { "ipu1_di0_pre", "ipp_di0", "ipp_di1", "ldb_di0_podf", "ldb_di1_podf", }; +static const char *ipu1_di1_sels_2[] = { "ipu1_di1_pre", "ipp_di0", "ipp_di1", "ldb_di0_podf", "ldb_di1_podf", }; +static const char *ipu2_di0_sels_2[] = { "ipu2_di0_pre", "ipp_di0", "ipp_di1", "ldb_di0_podf", "ldb_di1_podf", }; +static const char *ipu2_di1_sels_2[] = { "ipu2_di1_pre", "ipp_di0", "ipp_di1", "ldb_di0_podf", "ldb_di1_podf", }; static const char *hsi_tx_sels[] = { "pll3_120m", "pll2_pfd2_396m", }; static const char *pcie_axi_sels[] = { "axi", "ahb", }; static const char *ssi_sels[] = { "pll3_pfd2_508m", "pll3_pfd3_454m", "pll4_audio_div", }; @@ -452,6 +452,10 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) hws[IMX6QDL_CLK_ANACLK1] = imx6q_obtain_fixed_clk_hw(ccm_node, "anaclk1", 0); hws[IMX6QDL_CLK_ANACLK2] = imx6q_obtain_fixed_clk_hw(ccm_node, "anaclk2", 0); + /* ipp_di clocks are external input */ + hws[IMX6QDL_CLK_IPP_DI0] = imx6q_obtain_fixed_clk_hw(ccm_node, "ipp_di0", 0); + hws[IMX6QDL_CLK_IPP_DI1] = imx6q_obtain_fixed_clk_hw(ccm_node, "ipp_di1", 0); + np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop"); anatop_base = base = of_iomap(np, 0); WARN_ON(!base); diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h index e20c43cc36f6..2beb8738ae3d 100644 --- a/include/dt-bindings/clock/imx6qdl-clock.h +++ b/include/dt-bindings/clock/imx6qdl-clock.h @@ -273,6 +273,8 @@ #define IMX6QDL_CLK_MMDC_P0_IPG 263 #define IMX6QDL_CLK_DCIC1 264 #define IMX6QDL_CLK_DCIC2 265 -#define IMX6QDL_CLK_END 266 +#define IMX6QDL_CLK_IPP_DI0 266 +#define IMX6QDL_CLK_IPP_DI1 267 +#define IMX6QDL_CLK_END 268 #endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */ From patchwork Thu Oct 13 13:18:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Stein X-Patchwork-Id: 13005988 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 486EFC433FE for ; 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X-IronPort-AV: E=Sophos;i="5.95,180,1661810400"; d="scan'208";a="26736855" Received: from vtuxmail01.tq-net.de ([10.115.0.20]) by mx1.tq-group.com with ESMTP; 13 Oct 2022 15:19:03 +0200 Received: from steina-w.tq-net.de (unknown [10.123.53.21]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by vtuxmail01.tq-net.de (Postfix) with ESMTPSA id 9855C280056; Thu, 13 Oct 2022 15:19:03 +0200 (CEST) From: Alexander Stein To: Abel Vesa , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Shawn Guo , Sascha Hauer , Fabio Estevam Cc: Alexander Stein , Pengutronix Kernel Team , NXP Linux Team , Anson Huang , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 5/5] ARM: dts: imx6q: add ipp_di0 and ipp_di1 pad configuration Date: Thu, 13 Oct 2022 15:18:39 +0200 Message-Id: <20221013131839.1365394-6-alexander.stein@ew.tq-group.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221013131839.1365394-1-alexander.stein@ew.tq-group.com> References: <20221013131839.1365394-1-alexander.stein@ew.tq-group.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The reference manual does not mention this setting, but it works. Signed-off-by: Alexander Stein --- arch/arm/boot/dts/imx6dl-pinfunc.h | 3 +++ arch/arm/boot/dts/imx6q-pinfunc.h | 3 +++ 2 files changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/imx6dl-pinfunc.h b/arch/arm/boot/dts/imx6dl-pinfunc.h index 9d88d09f9bf6..876ff4545c30 100644 --- a/arch/arm/boot/dts/imx6dl-pinfunc.h +++ b/arch/arm/boot/dts/imx6dl-pinfunc.h @@ -525,11 +525,13 @@ #define MX6QDL_PAD_EIM_DA12__EPDC_DATA02 0x194 0x564 0x000 0x8 0x0 #define MX6QDL_PAD_EIM_DA13__EIM_AD13 0x198 0x568 0x000 0x0 0x0 #define MX6QDL_PAD_EIM_DA13__IPU1_DI1_D0_CS 0x198 0x568 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_DA13__IPP_DI1_CLK 0x198 0x568 0x000 0x2 0x0 #define MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x198 0x568 0x000 0x5 0x0 #define MX6QDL_PAD_EIM_DA13__SRC_BOOT_CFG13 0x198 0x568 0x000 0x7 0x0 #define MX6QDL_PAD_EIM_DA13__EPDC_DATA13 0x198 0x568 0x000 0x8 0x0 #define MX6QDL_PAD_EIM_DA14__EIM_AD14 0x19c 0x56c 0x000 0x0 0x0 #define MX6QDL_PAD_EIM_DA14__IPU1_DI1_D1_CS 0x19c 0x56c 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_DA14__IPP_DI0_CLK 0x19c 0x56c 0x000 0x2 0x0 #define MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x19c 0x56c 0x000 0x5 0x0 #define MX6QDL_PAD_EIM_DA14__SRC_BOOT_CFG14 0x19c 0x56c 0x000 0x7 0x0 #define MX6QDL_PAD_EIM_DA14__EPDC_DATA14 0x19c 0x56c 0x000 0x8 0x0 @@ -602,6 +604,7 @@ #define MX6QDL_PAD_EIM_EB1__EPDC_SDSHR 0x1c8 0x598 0x000 0x8 0x0 #define MX6QDL_PAD_EIM_EB2__EIM_EB2_B 0x1cc 0x59c 0x000 0x0 0x0 #define MX6QDL_PAD_EIM_EB2__ECSPI1_SS0 0x1cc 0x59c 0x7e4 0x1 0x2 +#define MX6QDL_PAD_EIM_EB2__IPP_DI1_CLK 0x1cc 0x59c 0x000 0x2 0x0 #define MX6QDL_PAD_EIM_EB2__IPU1_CSI1_DATA19 0x1cc 0x59c 0x8ac 0x3 0x1 #define MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x1cc 0x59c 0x860 0x4 0x0 #define MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1cc 0x59c 0x000 0x5 0x0 diff --git a/arch/arm/boot/dts/imx6q-pinfunc.h b/arch/arm/boot/dts/imx6q-pinfunc.h index e40409d04b97..40e53273c2e2 100644 --- a/arch/arm/boot/dts/imx6q-pinfunc.h +++ b/arch/arm/boot/dts/imx6q-pinfunc.h @@ -76,6 +76,7 @@ #define MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x088 0x39c 0x88c 0x6 0x0 #define MX6QDL_PAD_EIM_EB2__EIM_EB2_B 0x08c 0x3a0 0x000 0x0 0x0 #define MX6QDL_PAD_EIM_EB2__ECSPI1_SS0 0x08c 0x3a0 0x800 0x1 0x0 +#define MX6QDL_PAD_EIM_EB2__IPP_DI1_CLK 0x08c 0x3a0 0x000 0x2 0x0 #define MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x08c 0x3a0 0x8d4 0x3 0x0 #define MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x08c 0x3a0 0x890 0x4 0x0 #define MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x08c 0x3a0 0x000 0x5 0x0 @@ -373,10 +374,12 @@ #define MX6QDL_PAD_EIM_DA12__SRC_BOOT_CFG12 0x144 0x458 0x000 0x7 0x0 #define MX6QDL_PAD_EIM_DA13__EIM_AD13 0x148 0x45c 0x000 0x0 0x0 #define MX6QDL_PAD_EIM_DA13__IPU1_DI1_D0_CS 0x148 0x45c 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_DA13__IPP_DI1_CLK 0x148 0x45c 0x000 0x2 0x0 #define MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x148 0x45c 0x000 0x5 0x0 #define MX6QDL_PAD_EIM_DA13__SRC_BOOT_CFG13 0x148 0x45c 0x000 0x7 0x0 #define MX6QDL_PAD_EIM_DA14__EIM_AD14 0x14c 0x460 0x000 0x0 0x0 #define MX6QDL_PAD_EIM_DA14__IPU1_DI1_D1_CS 0x14c 0x460 0x000 0x1 0x0 +#define MX6QDL_PAD_EIM_DA14__IPP_DI0_CLK 0x14c 0x460 0x000 0x2 0x0 #define MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x14c 0x460 0x000 0x5 0x0 #define MX6QDL_PAD_EIM_DA14__SRC_BOOT_CFG14 0x14c 0x460 0x000 0x7 0x0 #define MX6QDL_PAD_EIM_DA15__EIM_AD15 0x150 0x464 0x000 0x0 0x0