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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2022 17:57:44.1766 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5f5f20a5-ddf2-4208-ea25-08daad446e24 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT072.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4266 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Platforms that cannot support their core initialization without the reference clock from the host, implement the feature 'core_init_notifier' to indicate the DesignWare sub-system about when their core is getting initialized. Any accesses to the core (Ex:- DBI) would the core being ready result in system hang in such systems (Ex:- tegra194). This patch moves any access to the core to dw_pcie_ep_init_complete() API which is effectively called only after the core initialization. It also introduces .ep_init_late() ops hook to be used for any post init work that platform drivers may have to do. Signed-off-by: Vidya Sagar Acked-by: Jingoo Han --- V5: * Changed dw_pcie_ep_init_complete() to dw_pcie_ep_init_late() * Skipped memory allocation if done already. This is to avoid freeing and then allocating again during PERST# toggles from the host. V4: * Addressed review comments from Bjorn and Manivannan * Moved dw_pcie_ep_init_complete() inside dw_pcie_ep_init_notify() * Added .ep_init_late() ops to perform late init tasks .../pci/controller/dwc/pcie-designware-ep.c | 125 +++++++++++------- drivers/pci/controller/dwc/pcie-designware.h | 10 +- 2 files changed, 80 insertions(+), 55 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 83ddb190292e..f300ea2f7bf7 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -23,14 +23,6 @@ void dw_pcie_ep_linkup(struct dw_pcie_ep *ep) } EXPORT_SYMBOL_GPL(dw_pcie_ep_linkup); -void dw_pcie_ep_init_notify(struct dw_pcie_ep *ep) -{ - struct pci_epc *epc = ep->epc; - - pci_epc_init_notify(epc); -} -EXPORT_SYMBOL_GPL(dw_pcie_ep_init_notify); - struct dw_pcie_ep_func * dw_pcie_ep_get_func_from_ep(struct dw_pcie_ep *ep, u8 func_no) { @@ -640,12 +632,17 @@ static unsigned int dw_pcie_ep_find_ext_capability(struct dw_pcie *pci, int cap) return 0; } -int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep) +static int dw_pcie_ep_init_late(struct dw_pcie_ep *ep) { struct dw_pcie *pci = to_dw_pcie_from_ep(ep); + struct dw_pcie_ep_func *ep_func; + struct device *dev = pci->dev; + struct pci_epc *epc = ep->epc; unsigned int offset; unsigned int nbars; u8 hdr_type; + u8 func_no; + void *addr; u32 reg; int i; @@ -658,6 +655,51 @@ int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep) return -EIO; } + dw_pcie_version_detect(pci); + + dw_pcie_iatu_detect(pci); + + if (!ep->ib_window_map) { + ep->ib_window_map = devm_bitmap_zalloc(dev, pci->num_ib_windows, + GFP_KERNEL); + if (!ep->ib_window_map) + return -ENOMEM; + } + + if (!ep->ob_window_map) { + ep->ob_window_map = devm_bitmap_zalloc(dev, pci->num_ob_windows, + GFP_KERNEL); + if (!ep->ob_window_map) + return -ENOMEM; + } + + if (!ep->outbound_addr) { + addr = devm_kcalloc(dev, pci->num_ob_windows, sizeof(phys_addr_t), + GFP_KERNEL); + if (!addr) + return -ENOMEM; + ep->outbound_addr = addr; + } + + for (func_no = 0; func_no < epc->max_functions; func_no++) { + + ep_func = dw_pcie_ep_get_func_from_ep(ep, func_no); + if (ep_func) + continue; + + ep_func = devm_kzalloc(dev, sizeof(*ep_func), GFP_KERNEL); + if (!ep_func) + return -ENOMEM; + + ep_func->func_no = func_no; + ep_func->msi_cap = dw_pcie_ep_find_capability(ep, func_no, + PCI_CAP_ID_MSI); + ep_func->msix_cap = dw_pcie_ep_find_capability(ep, func_no, + PCI_CAP_ID_MSIX); + + list_add_tail(&ep_func->list, &ep->func_list); + } + offset = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_REBAR); dw_pcie_dbi_ro_wr_en(pci); @@ -676,13 +718,28 @@ int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep) return 0; } -EXPORT_SYMBOL_GPL(dw_pcie_ep_init_complete); + +int dw_pcie_ep_init_notify(struct dw_pcie_ep *ep) +{ + struct pci_epc *epc = ep->epc; + int ret; + + ret = dw_pcie_ep_init_late(ep); + if (ret) + return ret; + + if (ep->ops->ep_init_late) + ep->ops->ep_init_late(ep); + + pci_epc_init_notify(epc); + + return 0; +} +EXPORT_SYMBOL_GPL(dw_pcie_ep_init_notify); int dw_pcie_ep_init(struct dw_pcie_ep *ep) { int ret; - void *addr; - u8 func_no; struct resource *res; struct pci_epc *epc; struct dw_pcie *pci = to_dw_pcie_from_ep(ep); @@ -690,7 +747,6 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) struct platform_device *pdev = to_platform_device(dev); struct device_node *np = dev->of_node; const struct pci_epc_features *epc_features; - struct dw_pcie_ep_func *ep_func; INIT_LIST_HEAD(&ep->func_list); @@ -719,26 +775,6 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) ep->phys_base = res->start; ep->addr_size = resource_size(res); - dw_pcie_version_detect(pci); - - dw_pcie_iatu_detect(pci); - - ep->ib_window_map = devm_bitmap_zalloc(dev, pci->num_ib_windows, - GFP_KERNEL); - if (!ep->ib_window_map) - return -ENOMEM; - - ep->ob_window_map = devm_bitmap_zalloc(dev, pci->num_ob_windows, - GFP_KERNEL); - if (!ep->ob_window_map) - return -ENOMEM; - - addr = devm_kcalloc(dev, pci->num_ob_windows, sizeof(phys_addr_t), - GFP_KERNEL); - if (!addr) - return -ENOMEM; - ep->outbound_addr = addr; - if (pci->link_gen < 1) pci->link_gen = of_pci_get_max_link_speed(np); @@ -755,20 +791,6 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) if (ret < 0) epc->max_functions = 1; - for (func_no = 0; func_no < epc->max_functions; func_no++) { - ep_func = devm_kzalloc(dev, sizeof(*ep_func), GFP_KERNEL); - if (!ep_func) - return -ENOMEM; - - ep_func->func_no = func_no; - ep_func->msi_cap = dw_pcie_ep_find_capability(ep, func_no, - PCI_CAP_ID_MSI); - ep_func->msix_cap = dw_pcie_ep_find_capability(ep, func_no, - PCI_CAP_ID_MSIX); - - list_add_tail(&ep_func->list, &ep->func_list); - } - if (ep->ops->ep_init) ep->ops->ep_init(ep); @@ -793,7 +815,14 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) return 0; } - ret = dw_pcie_ep_init_complete(ep); + /* + * NOTE:- Avoid accessing the hardware (Ex:- DBI space) before this + * step as platforms that implement 'core_init_notifier' feature may + * not have the hardware ready (i.e. core initialized) for access + * (Ex: tegra194). Any hardware access on such platforms result + * in system hard hang. + */ + ret = dw_pcie_ep_init_late(ep); if (ret) goto err_free_epc_mem; diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 45fcdfc8c035..7252513956b7 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -253,6 +253,7 @@ struct dw_pcie_rp { struct dw_pcie_ep_ops { void (*ep_init)(struct dw_pcie_ep *ep); + void (*ep_init_late)(struct dw_pcie_ep *ep); int (*raise_irq)(struct dw_pcie_ep *ep, u8 func_no, enum pci_epc_irq_type type, u16 interrupt_num); const struct pci_epc_features* (*get_features)(struct dw_pcie_ep *ep); @@ -467,8 +468,7 @@ static inline void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, #ifdef CONFIG_PCIE_DW_EP void dw_pcie_ep_linkup(struct dw_pcie_ep *ep); int dw_pcie_ep_init(struct dw_pcie_ep *ep); -int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep); -void dw_pcie_ep_init_notify(struct dw_pcie_ep *ep); +int dw_pcie_ep_init_notify(struct dw_pcie_ep *ep); void dw_pcie_ep_exit(struct dw_pcie_ep *ep); int dw_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep, u8 func_no); int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no, @@ -490,15 +490,11 @@ static inline int dw_pcie_ep_init(struct dw_pcie_ep *ep) return 0; } -static inline int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep) +static inline int dw_pcie_ep_init_notify(struct dw_pcie_ep *ep) { return 0; } -static inline void dw_pcie_ep_init_notify(struct dw_pcie_ep *ep) -{ -} - static inline void dw_pcie_ep_exit(struct dw_pcie_ep *ep) { } From patchwork Thu Oct 13 17:57:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 13006277 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1BA7EC43217 for ; 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Thu, 13 Oct 2022 10:57:29 -0700 From: Vidya Sagar To: , , , , , , , , , , CC: , , , , , , , , Subject: [PATCH V5 2/3] PCI: qcom-ep: Refactor EP initialization completion Date: Thu, 13 Oct 2022 23:27:11 +0530 Message-ID: <20221013175712.7539-3-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221013175712.7539-1-vidyas@nvidia.com> References: <20221013175712.7539-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT013:EE_|SN7PR12MB7227:EE_ X-MS-Office365-Filtering-Correlation-Id: 374c9b82-3c9d-4830-57eb-08daad44729e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 5vjPstjsUYR7yt0M0ZMmo6gEWM7hVQBrhVJHxObEdQkq3vDp1L9CZgRRfs8S9jFnHfhbUdurYfVg5c/IGaElJwbhisPowBgEEjodiRs8T6lWvNvwnKu8galkKMFQqXyYVfx+PhqJBjcFTBWPHR7qzj5wUQAh6JHrIic/Pks3E3Vi4AarwDR3iFA0LvxRDhhT9FPPobwqh13t9KZ/UOQA3NR8h6HlNnhjn/TQp1WuuW6F+Y4a4aYrpgZFVfE2FMwMgYKpS00QhnAX/hHGeUAqOdROUxJeEAdT1PIDrVY2by+LV/PVI6JxILC/Cn4FJ96Oyiwt+Ii29WB2tysTdc6lZ97wqRlQD3Q1XUuHPpuoWAZmx6J0h0KMJQEkiOE8hBf1y9BItSX7bQvxN09s9ooB+x7yfND98WNh64SoJXyH6ANSco1O1oxj9QtAhW+qNJ5dn58GL7w+Cbf5d8HIoIEFlUg51IPB/wQujmXPYT1ZHjysCT9Wh8TSanFEwPRtN7zRMF4FgfLPJmOTGX6vFZhiKFXtLaZq+tLTmSMfzL1lUO6Yvwb+nnXa41xQORx5RhygZ/pU4zHiw2UXPelRygmUea5+bGLvbn441fATYl30IfJ52OSgC5wnlXhZOB3IMP9LOG9NbyLeawZLAhIsQPPRNvxHdsW1FShTC6/jTG3oBoka/JGXAfLQhFAPkLT+RrnHCRT8Vn7pIgAeHTCnZ71Q6CntIAm0ooUBqmL0VgJDOH2n111e0JNwueTmLRkN/45fDcsk7UYL/Wc9NCCzHVu1Q4LfAt+IIQ7oMpsSdkO/KJA= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230022)(4636009)(39860400002)(376002)(346002)(396003)(136003)(451199015)(46966006)(40470700004)(36840700001)(26005)(7696005)(316002)(82740400003)(8676002)(70586007)(36860700001)(86362001)(40460700003)(921005)(70206006)(356005)(7636003)(40480700001)(336012)(186003)(2616005)(1076003)(478600001)(6666004)(110136005)(83380400001)(36756003)(82310400005)(4326008)(2906002)(426003)(41300700001)(54906003)(47076005)(5660300002)(7416002)(8936002);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2022 17:57:51.6832 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 374c9b82-3c9d-4830-57eb-08daad44729e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT013.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7227 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Move the post initialization code to .ep_init_late() call back and call only dw_pcie_ep_init_notify() which internally takes care of calling dw_pcie_ep_init_complete(). Signed-off-by: Vidya Sagar --- V5: * None V4: * New patch in this series drivers/pci/controller/dwc/pcie-qcom-ep.c | 27 ++++++++++++++--------- 1 file changed, 16 insertions(+), 11 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index e33eb3871309..c418b20042aa 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -361,22 +361,12 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *pci) PARF_INT_ALL_LINK_UP; writel_relaxed(val, pcie_ep->parf + PARF_INT_ALL_MASK); - ret = dw_pcie_ep_init_complete(&pcie_ep->pci.ep); + ret = dw_pcie_ep_init_notify(&pcie_ep->pci.ep); if (ret) { dev_err(dev, "Failed to complete initialization: %d\n", ret); goto err_disable_resources; } - /* - * The physical address of the MMIO region which is exposed as the BAR - * should be written to MHI BASE registers. - */ - writel_relaxed(pcie_ep->mmio_res->start, - pcie_ep->parf + PARF_MHI_BASE_ADDR_LOWER); - writel_relaxed(0, pcie_ep->parf + PARF_MHI_BASE_ADDR_UPPER); - - dw_pcie_ep_init_notify(&pcie_ep->pci.ep); - /* Enable LTSSM */ val = readl_relaxed(pcie_ep->parf + PARF_LTSSM); val |= BIT(8); @@ -643,8 +633,23 @@ static void qcom_pcie_ep_init(struct dw_pcie_ep *ep) dw_pcie_ep_reset_bar(pci, bar); } +static void qcom_pcie_ep_init_late(struct dw_pcie_ep *ep) +{ + struct dw_pcie *pci = to_dw_pcie_from_ep(ep); + struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci); + + /* + * The physical address of the MMIO region which is exposed as the BAR + * should be written to MHI BASE registers. + */ + writel_relaxed(pcie_ep->mmio_res->start, + pcie_ep->parf + PARF_MHI_BASE_ADDR_LOWER); + writel_relaxed(0, pcie_ep->parf + PARF_MHI_BASE_ADDR_UPPER); +} + static const struct dw_pcie_ep_ops pci_ep_ops = { .ep_init = qcom_pcie_ep_init, + .ep_init_late = qcom_pcie_ep_init_late, .raise_irq = qcom_pcie_ep_raise_irq, .get_features = qcom_pcie_epc_get_features, }; From patchwork Thu Oct 13 17:57:12 2022 Content-Type: text/plain; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2022 17:57:57.7537 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 57a65003-5fc0-43c9-9e87-08daad44763c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT072.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6293 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Call only dw_pcie_ep_init_notify() which internally takes care of calling dw_pcie_ep_init_complete() to notify about the EP initialization completion to the DWC EP framework. Signed-off-by: Vidya Sagar --- V5: * None V4: * New patch in this series drivers/pci/controller/dwc/pcie-tegra194.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 1b6b437823d2..2600304522eb 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -1885,14 +1885,12 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie) val = (upper_32_bits(ep->msi_mem_phys) & MSIX_ADDR_MATCH_HIGH_OFF_MASK); dw_pcie_writel_dbi(pci, MSIX_ADDR_MATCH_HIGH_OFF, val); - ret = dw_pcie_ep_init_complete(ep); + ret = dw_pcie_ep_init_notify(ep); if (ret) { dev_err(dev, "Failed to complete initialization: %d\n", ret); goto fail_init_complete; } - dw_pcie_ep_init_notify(ep); - /* Program the private control to allow sending LTR upstream */ if (pcie->of_data->has_ltr_req_fix) { val = appl_readl(pcie, APPL_LTR_MSG_2);