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Fri, 14 Oct 2022 00:25:02 -0700 Received: from rnnvmail204.nvidia.com (10.129.68.6) by rnnvmail203.nvidia.com (10.129.68.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Fri, 14 Oct 2022 00:25:01 -0700 Received: from pshete-ubuntu.nvidia.com (10.127.8.14) by mail.nvidia.com (10.129.68.6) with Microsoft SMTP Server id 15.2.986.29 via Frontend Transport; Fri, 14 Oct 2022 00:24:58 -0700 From: Prathamesh Shete To: , , , , , , , CC: , , , Subject: [PATCH v8 1/3] mmc: sdhci-tegra: Separate Tegra194 and Tegra234 SoC data Date: Fri, 14 Oct 2022 12:54:54 +0530 Message-ID: <20221014072456.28953-1-pshete@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT033:EE_|SJ0PR12MB6831:EE_ X-MS-Office365-Filtering-Correlation-Id: 4b1c7714-d7f1-40d3-5773-08daadb53dee X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Oct 2022 07:25:16.5124 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4b1c7714-d7f1-40d3-5773-08daadb53dee X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT033.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB6831 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Create new SoC data structure for Tegra234 platforms. Additional features, tap value configurations are added/ updated for Tegra234 platform hence separate Tegra194 and Tegra234 SoC data. Signed-off-by: Aniruddha Tvs Rao Signed-off-by: Prathamesh Shete Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci-tegra.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index 2d2d8260c681..a6c5bbae77b4 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -1556,7 +1556,21 @@ static const struct sdhci_tegra_soc_data soc_data_tegra194 = { .max_tap_delay = 139, }; +static const struct sdhci_tegra_soc_data soc_data_tegra234 = { + .pdata = &sdhci_tegra186_pdata, + .dma_mask = DMA_BIT_MASK(39), + .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL | + NVQUIRK_HAS_PADCALIB | + NVQUIRK_DIS_CARD_CLK_CONFIG_TAP | + NVQUIRK_ENABLE_SDR50 | + NVQUIRK_ENABLE_SDR104 | + NVQUIRK_HAS_TMCLK, + .min_tap_delay = 95, + .max_tap_delay = 111, +}; + static const struct of_device_id sdhci_tegra_dt_match[] = { + { .compatible = "nvidia,tegra234-sdhci", .data = &soc_data_tegra234 }, { .compatible = "nvidia,tegra194-sdhci", .data = &soc_data_tegra194 }, { .compatible = "nvidia,tegra186-sdhci", .data = &soc_data_tegra186 }, { .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 }, From patchwork Fri Oct 14 07:24:55 2022 Content-Type: text/plain; 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Fri, 14 Oct 2022 00:25:07 -0700 Received: from rnnvmail204.nvidia.com (10.129.68.6) by rnnvmail203.nvidia.com (10.129.68.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Fri, 14 Oct 2022 00:25:06 -0700 Received: from pshete-ubuntu.nvidia.com (10.127.8.14) by mail.nvidia.com (10.129.68.6) with Microsoft SMTP Server id 15.2.986.29 via Frontend Transport; Fri, 14 Oct 2022 00:25:03 -0700 From: Prathamesh Shete To: , , , , , , , CC: , , , Subject: [PATCH v8 2/3] mmc: sdhci-tegra: Add support to program MC stream ID Date: Fri, 14 Oct 2022 12:54:55 +0530 Message-ID: <20221014072456.28953-2-pshete@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221014072456.28953-1-pshete@nvidia.com> References: <20221014072456.28953-1-pshete@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT092:EE_|BN9PR12MB5164:EE_ X-MS-Office365-Filtering-Correlation-Id: 0e4ad806-cb3d-49c2-33ca-08daadb545f5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Oct 2022 07:25:29.8542 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0e4ad806-cb3d-49c2-33ca-08daadb545f5 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT092.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN9PR12MB5164 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org SMMU clients are supposed to program stream ID from their respective address spaces instead of MC override. Define NVQUIRK_PROGRAM_STREAMID and use it to program SMMU stream ID from the SDMMC client address space. Signed-off-by: Aniruddha TVS Rao Signed-off-by: Prathamesh Shete Acked-by: Adrian Hunter Acked-by: Thierry Reding --- drivers/mmc/host/sdhci-tegra.c | 42 ++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index a6c5bbae77b4..0cd7c3f7e6f4 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -25,6 +25,10 @@ #include #include #include +#ifdef CONFIG_IOMMU_API +#include +#include +#endif #include @@ -94,6 +98,8 @@ #define SDHCI_TEGRA_AUTO_CAL_STATUS 0x1ec #define SDHCI_TEGRA_AUTO_CAL_ACTIVE BIT(31) +#define SDHCI_TEGRA_CIF2AXI_CTRL_0 0x1fc + #define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0) #define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1) #define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2) @@ -121,6 +127,7 @@ #define NVQUIRK_HAS_TMCLK BIT(10) #define NVQUIRK_HAS_ANDROID_GPT_SECTOR BIT(11) +#define NVQUIRK_PROGRAM_STREAMID BIT(12) /* SDMMC CQE Base Address for Tegra Host Ver 4.1 and Higher */ #define SDHCI_TEGRA_CQE_BASE_ADDR 0xF000 @@ -177,6 +184,9 @@ struct sdhci_tegra { bool enable_hwcq; unsigned long curr_clk_rate; u8 tuned_tap_delay; +#ifdef CONFIG_IOMMU_API + u32 streamid; +#endif }; static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg) @@ -1564,6 +1574,7 @@ static const struct sdhci_tegra_soc_data soc_data_tegra234 = { NVQUIRK_DIS_CARD_CLK_CONFIG_TAP | NVQUIRK_ENABLE_SDR50 | NVQUIRK_ENABLE_SDR104 | + NVQUIRK_PROGRAM_STREAMID | NVQUIRK_HAS_TMCLK, .min_tap_delay = 95, .max_tap_delay = 111, @@ -1630,6 +1641,33 @@ static int sdhci_tegra_add_host(struct sdhci_host *host) return ret; } +/* Program MC streamID for DMA transfers */ +#ifdef CONFIG_IOMMU_API +static void program_stream_id(struct device *dev) +{ + struct sdhci_host *host = dev_get_drvdata(dev); + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); + struct iommu_fwspec *fwspec; + + if (tegra_host->soc_data->nvquirks & NVQUIRK_PROGRAM_STREAMID) { + fwspec = dev_iommu_fwspec_get(dev); + if (!fwspec) { + dev_warn(mmc_dev(host->mmc), + "iommu fwspec is NULL, continue without stream ID\n"); + } else { + tegra_host->streamid = fwspec->ids[0] & 0xff; + tegra_sdhci_writel(host, tegra_host->streamid | + FIELD_PREP(GENMASK(15, 8), + tegra_host->streamid), + SDHCI_TEGRA_CIF2AXI_CTRL_0); + } + } +} +#else +static void program_stream_id(struct device *dev) { } +#endif + static int sdhci_tegra_probe(struct platform_device *pdev) { const struct sdhci_tegra_soc_data *soc_data; @@ -1775,6 +1813,8 @@ static int sdhci_tegra_probe(struct platform_device *pdev) if (rc) goto err_add_host; + program_stream_id(&pdev->dev); + return 0; err_add_host: @@ -1871,6 +1911,8 @@ static int sdhci_tegra_resume(struct device *dev) if (ret) return ret; + program_stream_id(dev); + ret = sdhci_resume_host(host); if (ret) goto disable_clk; From patchwork Fri Oct 14 07:24:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prathamesh Shete X-Patchwork-Id: 13006721 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 67409C4332F for ; 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Fri, 14 Oct 2022 00:25:08 -0700 From: Prathamesh Shete To: , , , , , , , CC: , , , Subject: [PATCH v8 3/3] mmc: sdhci-tegra: Issue CMD and DAT resets together Date: Fri, 14 Oct 2022 12:54:56 +0530 Message-ID: <20221014072456.28953-3-pshete@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221014072456.28953-1-pshete@nvidia.com> References: <20221014072456.28953-1-pshete@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT092:EE_|PH8PR12MB6961:EE_ X-MS-Office365-Filtering-Correlation-Id: 5b0c530e-b42d-4d3a-1928-08daadb549e8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Qsom0MQ2G2XETLoEqrGTCM0zamrDNUYJgKzpnAJlmo/ojs02b8ULdQixyyR7Ta7eBU/Rcb5VhW7PTO/18/qZSjqSS2I8y9cv1/xT8L+eweJ/tN7xvas/mrIo5BWowXwgsqHUa9ltSjVw35HdS+Ijh2Lj+Ff0LIted3JwBRN9EYYrPKUq7YChbhv1Zs8pOlpCXOWwwJWswKOemEePZYp870raS5tJOYlN+k933vORtXfQPxkmeF6YX4OUiEPO6Z70h/QhghG5K1MUuxC79R/tprKdr9fFNO1eSm3CAeNhl6coDCKsG84nqt23m6ZhZJkW10i3eM2/ETQnodef6UTj39zRTtsCo3irprAaYXX1O5DsNh+LQkVjui2ePyak5dobMtX8a4NBhj7sx4CVC8xKkUV/VPBwezt8h4ZQMmGrtCPZ3ORGqyP1393HdTPJyrwsPedwi2poNVthwFrVkm1LLUUwIsDam41XzuMyPIYcnCJD83tP1RLbxGvDUakaKBEFBZgTDmDL3T/HQPNqMNDE+cmrLyeTB6R7K3OLi8yFNRv8d4YBSA8L396840hreTziKQ6Yc32ZZF6G6FpUiSh8/sLTjsVNzr3W/KUKsGaL/zjRoXNJwajAvoT9JxsVJ497OoWX9Eef1MBukMvQL6pxT3o+RW90id91b5IRkED1V07yiXTSJDMRIQ/NX6hvtFD5i1JbewPEawr5BWQNv91BwMNq6lVqWzWxHFxe35SE8QdfVk/+2Ooj+BuCEDta+pvQhcwiAwZxfZWQDMIXhCfxDw== X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230022)(4636009)(346002)(39860400002)(136003)(376002)(396003)(451199015)(40470700004)(46966006)(36840700001)(40460700003)(7636003)(356005)(70586007)(478600001)(1076003)(47076005)(8936002)(6666004)(70206006)(426003)(5660300002)(86362001)(186003)(107886003)(82310400005)(4326008)(2616005)(54906003)(316002)(36756003)(8676002)(82740400003)(336012)(26005)(41300700001)(83380400001)(110136005)(36860700001)(2906002)(7696005)(40480700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Oct 2022 07:25:36.4792 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5b0c530e-b42d-4d3a-1928-08daadb549e8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT092.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB6961 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org In case of error condition to avoid system crash Tegra SDMMC controller requires CMD and DAT resets issued together. SDHCI controller FSM goes into bad state due to rapid SD card hot-plug event. Issuing reset on the CMD FSM before DATA FSM results in kernel panic, hence add support to issue CMD and DAT resets together. This is applicable to Tegra186 and later chips. Signed-off-by: Aniruddha TVS Rao Signed-off-by: Prathamesh Shete Acked-by: Adrian Hunter Acked-by: Thierry Reding --- drivers/mmc/host/sdhci-tegra.c | 3 ++- drivers/mmc/host/sdhci.c | 5 +++++ drivers/mmc/host/sdhci.h | 2 ++ 3 files changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index 0cd7c3f7e6f4..9fbea5bbfa4a 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -1535,7 +1535,8 @@ static const struct sdhci_pltfm_data sdhci_tegra186_pdata = { SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, - .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, + .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | + SDHCI_QUIRK2_ISSUE_CMD_DAT_RESET_TOGETHER, .ops = &tegra186_sdhci_ops, }; diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 2b5dda521b0e..8512a69f1aae 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -270,6 +270,11 @@ enum sdhci_reset_reason { static void sdhci_reset_for_reason(struct sdhci_host *host, enum sdhci_reset_reason reason) { + if (host->quirks2 & + SDHCI_QUIRK2_ISSUE_CMD_DAT_RESET_TOGETHER) { + sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); + return; + } switch (reason) { case SDHCI_RESET_FOR_INIT: sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index d750c464bd1e..6a5766774b05 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -478,6 +478,8 @@ struct sdhci_host { * block count. */ #define SDHCI_QUIRK2_USE_32BIT_BLK_CNT (1<<18) +/* Issue CMD and DATA reset together */ +#define SDHCI_QUIRK2_ISSUE_CMD_DAT_RESET_TOGETHER (1<<19) int irq; /* Device IRQ */ void __iomem *ioaddr; /* Mapped address */