From patchwork Fri Oct 14 08:15:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Christian_K=C3=B6nig?= X-Patchwork-Id: 13006765 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8B7C3C433FE for ; Fri, 14 Oct 2022 08:16:03 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A36E910EA96; Fri, 14 Oct 2022 08:16:01 +0000 (UTC) Received: from mail-ed1-x530.google.com (mail-ed1-x530.google.com [IPv6:2a00:1450:4864:20::530]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7C13E10EA96; Fri, 14 Oct 2022 08:15:57 +0000 (UTC) Received: by mail-ed1-x530.google.com with SMTP id a13so5889968edj.0; Fri, 14 Oct 2022 01:15:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=Tiq+iZ8WHyngN/AauVz6Bi2y5WOuCWMci27ME2OuFVA=; b=OtYtw4lO/czie0rpjgh2BgsFgqTFYYwqfo0FTaehi609mTI3Rnt0+LOFYG2VtTqw1+ TDzmq4HfG79ceq1+iNYGzsoP/GLcLUzICZHPsJq7wJA7TFEE8u2NhvSBqz7DtkXDk8vn MHOYU1rZgTUcibC5qC6dHXmEVIJrXWlaiCBMs2ikv9IC0SSd+t85MvElW6rwVtCybnuc sOQIqd9SxZA6ibWmtNjUYeYtEdtj/I0UNnkD2Amqbr2Max1jSnkFMhb2hI/tKpTKUTkU uhFB2Dnwv4nkb4iQWR5/TZTwkE44yHs4TXqCQNdEqQj1q6z3eh5ugwdSReBbSl/xoLQO AWKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=Tiq+iZ8WHyngN/AauVz6Bi2y5WOuCWMci27ME2OuFVA=; b=vSENLGuU5T8AqotPBQJu2k9AixOkLv6jT5T3WeqWXGC4S1f+H7lxyfKgzc0y1A5KZx UdbJZC+nA8fLBqYGIHDiZzh/Yz+NwGcskMMCdmljVJGCzZycuGMmjRP8xHs+w6EFEy1m sj6NY3Aj0PwwBr1SMsWSNWYObypNie8yl/0JMpLuatPpgTun6E52L9mAI9VAFuoc9EL5 MOetS3Mn6IEarHeyHG/j+AfplR5lTg6KWC9WQ3PWz4goD/Mz/BRLoYUU08XfWncgU7z9 qlycQAIzkMzZb8JrwE33o+crQ18a6b+5q0yXXL62akZ+3WxYZ+HV3yuLJscm2Lb2O27K QUOQ== X-Gm-Message-State: ACrzQf1PkgCF/FE9tBsX67eu5368UR33EmiYLnKkleYxdtJFmoFdk78F urUBSioha8/d+unJuNwPG8c= X-Google-Smtp-Source: AMsMyM5kEC1M52w1Fj9TW33rmzmDwveDjjNBlmEPlubyz6eZ4p25Fi5F4stmsUPB7IcSdgvEBYeH8w== X-Received: by 2002:a05:6402:847:b0:453:943b:bf4 with SMTP id b7-20020a056402084700b00453943b0bf4mr3245709edz.301.1665735355961; Fri, 14 Oct 2022 01:15:55 -0700 (PDT) Received: from able.fritz.box (p5b0eacfe.dip0.t-ipconnect.de. [91.14.172.254]) by smtp.gmail.com with ESMTPSA id lb17-20020a170907785100b0078d886c871bsm1146188ejc.70.2022.10.14.01.15.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Oct 2022 01:15:55 -0700 (PDT) From: " =?utf-8?q?Christian_K=C3=B6nig?= " X-Google-Original-From: =?utf-8?q?Christian_K=C3=B6nig?= To: luben.tuikov@amd.com, dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org Subject: [PATCH 1/2] drm/sched: add DRM_SCHED_FENCE_DONT_PIPELINE flag Date: Fri, 14 Oct 2022 10:15:52 +0200 Message-Id: <20221014081553.114899-1-christian.koenig@amd.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Christian_K=C3=B6nig?= , stable@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Setting this flag on a scheduler fence prevents pipelining of jobs depending on this fence. In other words we always insert a full CPU round trip before dependen jobs are pushed to the pipeline. Signed-off-by: Christian König CC: stable@vger.kernel.org # 5.19+ Reviewed-by: Alex Deucher Acked-by: Luben Tuikov Acked-by: Luben Tuikov --- drivers/gpu/drm/scheduler/sched_entity.c | 3 ++- include/drm/gpu_scheduler.h | 9 +++++++++ 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/scheduler/sched_entity.c b/drivers/gpu/drm/scheduler/sched_entity.c index 191c56064f19..43d337d8b153 100644 --- a/drivers/gpu/drm/scheduler/sched_entity.c +++ b/drivers/gpu/drm/scheduler/sched_entity.c @@ -385,7 +385,8 @@ static bool drm_sched_entity_add_dependency_cb(struct drm_sched_entity *entity) } s_fence = to_drm_sched_fence(fence); - if (s_fence && s_fence->sched == sched) { + if (s_fence && s_fence->sched == sched && + !test_bit(DRM_SCHED_FENCE_DONT_PIPELINE, &fence->flags)) { /* * Fence is from the same scheduler, only need to wait for diff --git a/include/drm/gpu_scheduler.h b/include/drm/gpu_scheduler.h index 0fca8f38bee4..f01d14b231ed 100644 --- a/include/drm/gpu_scheduler.h +++ b/include/drm/gpu_scheduler.h @@ -32,6 +32,15 @@ #define MAX_WAIT_SCHED_ENTITY_Q_EMPTY msecs_to_jiffies(1000) +/** + * DRM_SCHED_FENCE_DONT_PIPELINE - Prefent dependency pipelining + * + * Setting this flag on a scheduler fence prevents pipelining of jobs depending + * on this fence. In other words we always insert a full CPU round trip before + * dependen jobs are pushed to the hw queue. + */ +#define DRM_SCHED_FENCE_DONT_PIPELINE DMA_FENCE_FLAG_USER_BITS + struct drm_gem_object; struct drm_gpu_scheduler; From patchwork Fri Oct 14 08:15:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Christian_K=C3=B6nig?= X-Patchwork-Id: 13006766 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4D0C6C433FE for ; Fri, 14 Oct 2022 08:16:13 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8736F10EA9B; Fri, 14 Oct 2022 08:16:11 +0000 (UTC) Received: from mail-ed1-x52d.google.com (mail-ed1-x52d.google.com [IPv6:2a00:1450:4864:20::52d]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9BC0510EA96; Fri, 14 Oct 2022 08:15:58 +0000 (UTC) Received: by mail-ed1-x52d.google.com with SMTP id s30so5848436eds.1; Fri, 14 Oct 2022 01:15:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Zi3g0gUsoeReyu3M9Dd3IEc+zU79SSSBwTJbXIApLpg=; b=R6gVvB8anInV7lNdqB+ENmzugVdF686pFgLU5ufl0FN5l3OTFcnE/CWYXB84tZWN62 s6QW8dEAhbSikwOJY0rGxepIzcU4RfQhQ3sdOtyLYwgbzPSXBjSUhKoGlPQ71P5895p1 rJAjUNy4tk2fVD4LbYDT7qtLD57naKlhvMVoLV1EGACb6X4EcvivZTGcj6EBOhvqK0bq KbdFuCpRtU0LgfvGEv+zjrQsHYR+PmKRG38pZhcy0IV81KaJl9+FBbZhedHVdPJ9QRbA BOJKXfdptuyNjQ2FWqKjvaAPLj7/Pt3SkDR0ZGULOam1FdC+InCwIHCKa/5WH2TkPhne lYFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Zi3g0gUsoeReyu3M9Dd3IEc+zU79SSSBwTJbXIApLpg=; b=TRxUheUpILuvmliOpprEIOLA9/nouA6vs0tvO7J6C3dZiX0+kyiEjn/XpzpTiLUFQc jkNij+NhUPGszmhKi2y+fxi0fOOfaxsLD0huuhKn2K8GmcViLSsXsA/9R69eBbq2Z0iX 7jk1unSFcZNpA3riowhFRDw8DUs8XZbYzDaCijlYGJ20z+AAQR6gmgB2pfwcp3eCR1J1 ghUBQjKIG2VVnIizdXtioQ55gTUOnz6O7SdelVGXWfWF3ZbWns/dCsr42Qr16WlOi+7a yk5wiuNeN3U3rIjN4LF9DA2lfeSvv+Cp5mrMdyr3cBAJY215g9Gj7oKF6kY3h4DqmF0n U1ZA== X-Gm-Message-State: ACrzQf0BtmBGw4sZ2CJhLZvvTxI47B670VM+wzcAxDLcx3mcz9JHRRIB +gZ1Dcd6Kvhjund8aDP9NSc= X-Google-Smtp-Source: AMsMyM46Gt3+KeRKQ//eFjkr9Auam70HriXsymEnFt0GVzMbcHlD7zThEefdDu9I06HPHf9hJXFZ6A== X-Received: by 2002:a05:6402:450c:b0:443:6279:774f with SMTP id ez12-20020a056402450c00b004436279774fmr3352022edb.11.1665735357051; Fri, 14 Oct 2022 01:15:57 -0700 (PDT) Received: from able.fritz.box (p5b0eacfe.dip0.t-ipconnect.de. [91.14.172.254]) by smtp.gmail.com with ESMTPSA id lb17-20020a170907785100b0078d886c871bsm1146188ejc.70.2022.10.14.01.15.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Oct 2022 01:15:56 -0700 (PDT) From: " =?utf-8?q?Christian_K=C3=B6nig?= " X-Google-Original-From: =?utf-8?q?Christian_K=C3=B6nig?= To: luben.tuikov@amd.com, dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org Subject: [PATCH 2/2] drm/amdgpu: use DRM_SCHED_FENCE_DONT_PIPELINE for VM updates Date: Fri, 14 Oct 2022 10:15:53 +0200 Message-Id: <20221014081553.114899-2-christian.koenig@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221014081553.114899-1-christian.koenig@amd.com> References: <20221014081553.114899-1-christian.koenig@amd.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Christian_K=C3=B6nig?= , stable@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Make sure that we always have a CPU round trip to let the submission code correctly decide if a TLB flush is necessary or not. Signed-off-by: Christian König CC: stable@vger.kernel.org # 5.19+ Acked-by: Luben Tuikov --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c index 2b0669c464f6..69e105fa41f6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c @@ -116,8 +116,15 @@ static int amdgpu_vm_sdma_commit(struct amdgpu_vm_update_params *p, DMA_RESV_USAGE_BOOKKEEP); } - if (fence && !p->immediate) + if (fence && !p->immediate) { + /* + * Most hw generations now have a separate queue for page table + * updates, but when the queue is shared with userspace we need + * the extra CPU round trip to correctly flush the TLB. + */ + set_bit(DRM_SCHED_FENCE_DONT_PIPELINE, &f->flags); swap(*fence, f); + } dma_fence_put(f); return 0;