From patchwork Sun Oct 16 16:15:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luca Weiss X-Patchwork-Id: 13007871 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 04678C4332F for ; Sun, 16 Oct 2022 16:16:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229829AbiJPQQl (ORCPT ); Sun, 16 Oct 2022 12:16:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45906 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229904AbiJPQQg (ORCPT ); Sun, 16 Oct 2022 12:16:36 -0400 Received: from mail.z3ntu.xyz (mail.z3ntu.xyz [128.199.32.197]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AD56E38463; Sun, 16 Oct 2022 09:16:35 -0700 (PDT) Received: from g550jk.arnhem.chello.nl (31-151-115-246.dynamic.upc.nl [31.151.115.246]) by mail.z3ntu.xyz (Postfix) with ESMTPSA id 005BFC9CFA; Sun, 16 Oct 2022 16:16:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=z3ntu.xyz; s=z3ntu; t=1665936964; bh=WWnMVLsQ16tzIdinutsamMLE27RcGg5gLBVDOG/S19g=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=GMkvuz6d/pvx0C/xQMH9xqlrXmHVDh2i7p7ZkCphjpcVLF83qTxORGPhGDzr/iR21 +NzBHn+cKAmoON3GfztzKxhSOmFNSakCOQNL3opMdRmKAwOC8Mc6l3ExsLAZJezyrC JdZE/eJE9ZTrIJj832cQ8/sBKE1jb58vZwo4eesg= From: Luca Weiss To: linux-arm-msm@vger.kernel.org Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, Luca Weiss , Rob Herring , Andy Gross , Bjorn Andersson , Konrad Dybcio , Joerg Roedel , Will Deacon , Robin Murphy , Rob Herring , Krzysztof Kozlowski , iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 1/3] dt-bindings: qcom-iommu: Add Qualcomm MSM8953 compatible Date: Sun, 16 Oct 2022 18:15:51 +0200 Message-Id: <20221016161554.673006-2-luca@z3ntu.xyz> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20221016161554.673006-1-luca@z3ntu.xyz> References: <20221016161554.673006-1-luca@z3ntu.xyz> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Document the compatible used for IOMMU on the msm8953 SoC. Signed-off-by: Luca Weiss Acked-by: Rob Herring --- Changes since v3: - no changes Documentation/devicetree/bindings/iommu/qcom,iommu.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/iommu/qcom,iommu.txt b/Documentation/devicetree/bindings/iommu/qcom,iommu.txt index 059139abce35..e6cecfd360eb 100644 --- a/Documentation/devicetree/bindings/iommu/qcom,iommu.txt +++ b/Documentation/devicetree/bindings/iommu/qcom,iommu.txt @@ -10,6 +10,7 @@ to non-secure vs secure interrupt line. - compatible : Should be one of: "qcom,msm8916-iommu" + "qcom,msm8953-iommu" Followed by "qcom,msm-iommu-v1". From patchwork Sun Oct 16 16:15:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luca Weiss X-Patchwork-Id: 13007868 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 83684C43217 for ; Sun, 16 Oct 2022 16:16:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229768AbiJPQQJ (ORCPT ); Sun, 16 Oct 2022 12:16:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45438 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229751AbiJPQQI (ORCPT ); Sun, 16 Oct 2022 12:16:08 -0400 Received: from mail.z3ntu.xyz (mail.z3ntu.xyz [128.199.32.197]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 185302A27A; Sun, 16 Oct 2022 09:16:06 -0700 (PDT) Received: from g550jk.arnhem.chello.nl (31-151-115-246.dynamic.upc.nl [31.151.115.246]) by mail.z3ntu.xyz (Postfix) with ESMTPSA id 8E3EBCAC3C; Sun, 16 Oct 2022 16:16:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=z3ntu.xyz; s=z3ntu; t=1665936964; bh=RTEJlTDR5uGqgtZdCSkmRAbT4l82YlBd079FwUaEpuc=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=Veq/xOWKFQe5QtWUvPzt2BT30D1/5PB0C146c5b3hViZ71cb391KHaPrhUXEOpdDT T7BP7gS+MuVNXByDkB27nBqL6c9WWrJockdXZKMAztY9Jei1G3H/ncIdu0Y1IE8Qqf Tttc6ANUT1WbMySloJJNQdVNmtRGqHnpdmGPTNBk= From: Luca Weiss To: linux-arm-msm@vger.kernel.org Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, Vladimir Lypak , Luca Weiss , Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 2/3] arm64: dts: qcom: msm8953: add APPS IOMMU Date: Sun, 16 Oct 2022 18:15:52 +0200 Message-Id: <20221016161554.673006-3-luca@z3ntu.xyz> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20221016161554.673006-1-luca@z3ntu.xyz> References: <20221016161554.673006-1-luca@z3ntu.xyz> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Vladimir Lypak Add the nodes describing the iommu and its context banks that are found on msm8953 SoCs. Signed-off-by: Vladimir Lypak Signed-off-by: Luca Weiss --- Changes since v3: - no changes arch/arm64/boot/dts/qcom/msm8953.dtsi | 36 +++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index 6b992a6d56c1..6d9a2a34737d 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -726,6 +726,42 @@ tcsr_phy_clk_scheme_sel: syscon@193f044 { reg = <0x193f044 0x4>; }; + apps_iommu: iommu@1e00000 { + compatible = "qcom,msm8953-iommu", "qcom,msm-iommu-v1"; + ranges = <0 0x1e20000 0x20000>; + + clocks = <&gcc GCC_SMMU_CFG_CLK>, + <&gcc GCC_APSS_TCU_ASYNC_CLK>; + clock-names = "iface", "bus"; + + qcom,iommu-secure-id = <17>; + + #address-cells = <1>; + #iommu-cells = <1>; + #size-cells = <1>; + + // vfe + iommu-ctx@14000 { + compatible = "qcom,msm-iommu-v1-ns"; + reg = <0x14000 0x1000>; + interrupts = ; + }; + + // mdp_0 + iommu-ctx@15000 { + compatible = "qcom,msm-iommu-v1-ns"; + reg = <0x15000 0x1000>; + interrupts = ; + }; + + // venus_ns + iommu-ctx@16000 { + compatible = "qcom,msm-iommu-v1-ns"; + reg = <0x16000 0x1000>; + interrupts = ; + }; + }; + spmi_bus: spmi@200f000 { compatible = "qcom,spmi-pmic-arb"; reg = <0x200f000 0x1000>, From patchwork Sun Oct 16 16:15:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luca Weiss X-Patchwork-Id: 13007870 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CD564C43217 for ; Sun, 16 Oct 2022 16:16:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229845AbiJPQQK (ORCPT ); Sun, 16 Oct 2022 12:16:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45452 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229763AbiJPQQI (ORCPT ); Sun, 16 Oct 2022 12:16:08 -0400 Received: from mail.z3ntu.xyz (mail.z3ntu.xyz [128.199.32.197]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B1AF8624F; Sun, 16 Oct 2022 09:16:06 -0700 (PDT) Received: from g550jk.arnhem.chello.nl (31-151-115-246.dynamic.upc.nl [31.151.115.246]) by mail.z3ntu.xyz (Postfix) with ESMTPSA id 16617CE594; Sun, 16 Oct 2022 16:16:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=z3ntu.xyz; s=z3ntu; t=1665936965; bh=/o6J0l5x0I1EKZzlMMKLf+DDJOoiSCtcgUSlTGCz/oE=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=yXzvf4FmCslYJsLyaK+DwCcpDCzPJsdDaUdAtp7ExfRwlohzzVQ1eg78nTa+fM3oN /pnyV0gKhwgT5GSANAk6CklVClQLbzxA+IwZ+nF66j1nNKoeQnbAX/VvYasHwBZNl8 F6XEJ+2vDCZ1JlG6s9nvk7BfGMiBpSnlx/KO24hQ= From: Luca Weiss To: linux-arm-msm@vger.kernel.org Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, Vladimir Lypak , Luca Weiss , Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 3/3] arm64: dts: qcom: msm8953: add MDSS Date: Sun, 16 Oct 2022 18:15:53 +0200 Message-Id: <20221016161554.673006-4-luca@z3ntu.xyz> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20221016161554.673006-1-luca@z3ntu.xyz> References: <20221016161554.673006-1-luca@z3ntu.xyz> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Vladimir Lypak Add the MDSS, MDP and DSI nodes that are found on msm8953 SoC. Signed-off-by: Vladimir Lypak Signed-off-by: Luca Weiss --- Changes since v3: - rename dsi-phy@ to phy@ - drop phy-names - use double compatible for qcom,mdp5 arch/arm64/boot/dts/qcom/msm8953.dtsi | 208 ++++++++++++++++++++++++++ 1 file changed, 208 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index 6d9a2a34737d..707477e4254c 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -726,6 +726,214 @@ tcsr_phy_clk_scheme_sel: syscon@193f044 { reg = <0x193f044 0x4>; }; + mdss: mdss@1a00000 { + compatible = "qcom,mdss"; + + reg = <0x1a00000 0x1000>, + <0x1ab0000 0x1040>; + reg-names = "mdss_phys", + "vbif_phys"; + + power-domains = <&gcc MDSS_GDSC>; + interrupts = ; + + interrupt-controller; + #interrupt-cells = <1>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>, + <&gcc GCC_MDSS_MDP_CLK>; + clock-names = "iface", + "bus", + "vsync", + "core"; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + status = "disabled"; + + mdp: mdp@1a01000 { + compatible = "qcom,msm8953-mdp5", "qcom,mdp5"; + reg = <0x1a01000 0x89000>; + reg-names = "mdp_phys"; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + power-domains = <&gcc MDSS_GDSC>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>; + clock-names = "iface", + "bus", + "core", + "vsync"; + + iommus = <&apps_iommu 0x15>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdp5_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + mdp5_intf2_out: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + }; + + dsi0: dsi@1a94000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0x1a94000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + assigned-clocks = <&gcc BYTE0_CLK_SRC>, + <&gcc PCLK0_CLK_SRC>; + assigned-clock-parents = <&dsi0_phy 0>, + <&dsi0_phy 1>; + + clocks = <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_BYTE0_CLK>, + <&gcc GCC_MDSS_PCLK0_CLK>, + <&gcc GCC_MDSS_ESC0_CLK>; + clock-names = "mdp_core", + "iface", + "bus", + "byte", + "pixel", + "core"; + + phys = <&dsi0_phy>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&mdp5_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + }; + + dsi0_phy: phy@1a94400 { + compatible = "qcom,dsi-phy-14nm-8953"; + reg = <0x1a94400 0x100>, + <0x1a94500 0x300>, + <0x1a94800 0x188>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, <&xo_board>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + + dsi1: dsi@1a96000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0x1a96000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <5>; + + assigned-clocks = <&gcc BYTE1_CLK_SRC>, + <&gcc PCLK1_CLK_SRC>; + assigned-clock-parents = <&dsi1_phy 0>, + <&dsi1_phy 1>; + + clocks = <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_BYTE1_CLK>, + <&gcc GCC_MDSS_PCLK1_CLK>, + <&gcc GCC_MDSS_ESC1_CLK>; + clock-names = "mdp_core", + "iface", + "bus", + "byte", + "pixel", + "core"; + + phys = <&dsi1_phy>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi1_in: endpoint { + remote-endpoint = <&mdp5_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + dsi1_out: endpoint { + }; + }; + }; + }; + + dsi1_phy: phy@1a96400 { + compatible = "qcom,dsi-phy-14nm-8953"; + reg = <0x1a96400 0x100>, + <0x1a96500 0x300>, + <0x1a96800 0x188>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, <&xo_board>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + }; + apps_iommu: iommu@1e00000 { compatible = "qcom,msm8953-iommu", "qcom,msm-iommu-v1"; ranges = <0 0x1e20000 0x20000>;