From patchwork Mon Oct 17 07:04:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Hoo X-Patchwork-Id: 13008236 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C0666C433FE for ; Mon, 17 Oct 2022 07:05:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230103AbiJQHFh (ORCPT ); Mon, 17 Oct 2022 03:05:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33816 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229990AbiJQHF2 (ORCPT ); Mon, 17 Oct 2022 03:05:28 -0400 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 12ADD2E6A6 for ; Mon, 17 Oct 2022 00:05:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1665990326; x=1697526326; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=JZ0Wik+LCEwumjlrsLRjoMFh4E/OTHqRJyHJYoqp/Ug=; b=XKpB+hLt2A7sn0bjsuw5yxNPz+qYc6Gfs+h9SFAq/U95VTs+lT/6Zr4V kWy8XC9aol6WrPPo6iGFSsjaiHShGLdAFchOk5of1SAAApxiD35cqGdmW Rew228xF3VFCDH3LtoXTv5ttsQ6PrpBFJ0KaGO1+RWuswiH4Qm0DidwAo DqDui7gaKjN2u4BD6SwCC4BsxqTV/Pw5xKTTMJos0KjC29ni/NdGuw4fm iiIy2Neyl9qLUK0y5P/UNT3aA6NcwFcxhuxYxaY09VQHytoHucJ0neVSx hcqAQ3DqjI+WkrQw2d4qgZXl5ZA11uob6KyN5mllvN40iSVX1fHDPB3DT Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10502"; a="306805985" X-IronPort-AV: E=Sophos;i="5.95,190,1661842800"; d="scan'208";a="306805985" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Oct 2022 00:05:23 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10502"; a="579271366" X-IronPort-AV: E=Sophos;i="5.95,190,1661842800"; d="scan'208";a="579271366" Received: from sqa-gate.sh.intel.com (HELO robert-clx2.tsp.org) ([10.239.48.212]) by orsmga003.jf.intel.com with ESMTP; 17 Oct 2022 00:05:14 -0700 From: Robert Hoo To: seanjc@google.com, pbonzini@redhat.com Cc: kvm@vger.kernel.org, Robert Hoo Subject: [PATCH 1/9] KVM: x86: Rename cr4_reserved/rsvd_* variables to be more readable Date: Mon, 17 Oct 2022 15:04:42 +0800 Message-Id: <20221017070450.23031-2-robert.hu@linux.intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20221017070450.23031-1-robert.hu@linux.intel.com> References: <20221017070450.23031-1-robert.hu@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org kvm_vcpu_arch::cr4_guest_owned_bits and kvm_vcpu_arch::cr4_guest_rsvd_bits looks confusing. Rename latter to cr4_host_rsvd_bits, because it in fact decribes the effective host reserved cr4 bits from the vcpu's perspective. Meanwhile, rename other related variables/macros to be better descriptive: * CR4_RESERVED_BITS --> CR4_HOST_RESERVED_BITS, which describes host bare metal CR4 reserved bits. * cr4_reserved_bits --> cr4_kvm_reserved_bits, which describes CR4_HOST_RESERVED_BITS + !kvm_cap_has() = kvm level cr4 reserved bits. * __cr4_reserved_bits() --> __cr4_calc_reserved_bits(), which to calc effective cr4 reserved bits for kvm or vm level, by corresponding x_cpu_has() input. Thus, by these renames, the hierarchical relations of those reserved CR4 bits is more clear. Just renames, no functional changes intended. Signed-off-by: Robert Hoo --- arch/x86/include/asm/kvm_host.h | 4 ++-- arch/x86/kvm/cpuid.c | 4 ++-- arch/x86/kvm/vmx/vmx.c | 2 +- arch/x86/kvm/x86.c | 12 ++++++------ arch/x86/kvm/x86.h | 4 ++-- 5 files changed, 13 insertions(+), 13 deletions(-) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h index 5ffa578cafe1..4858436c64ef 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -114,7 +114,7 @@ | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \ | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG)) -#define CR4_RESERVED_BITS \ +#define CR4_HOST_RESERVED_BITS \ (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\ | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \ | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR | X86_CR4_PCIDE \ @@ -654,7 +654,7 @@ struct kvm_vcpu_arch { unsigned long cr3; unsigned long cr4; unsigned long cr4_guest_owned_bits; - unsigned long cr4_guest_rsvd_bits; + unsigned long cr4_host_rsvd_bits; unsigned long cr8; u32 host_pkru; u32 pkru; diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index 75dcf7a72605..b935b3b04a7e 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -338,8 +338,8 @@ static void kvm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu) vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu); kvm_pmu_refresh(vcpu); - vcpu->arch.cr4_guest_rsvd_bits = - __cr4_reserved_bits(guest_cpuid_has, vcpu); + vcpu->arch.cr4_host_rsvd_bits = + __cr4_calc_reserved_bits(guest_cpuid_has, vcpu); kvm_hv_set_cpuid(vcpu); diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index d7f8331d6f7e..97a2b8759ce8 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -4294,7 +4294,7 @@ void set_cr4_guest_host_mask(struct vcpu_vmx *vmx) struct kvm_vcpu *vcpu = &vmx->vcpu; vcpu->arch.cr4_guest_owned_bits = KVM_POSSIBLE_CR4_GUEST_BITS & - ~vcpu->arch.cr4_guest_rsvd_bits; + ~vcpu->arch.cr4_host_rsvd_bits; if (!enable_ept) { vcpu->arch.cr4_guest_owned_bits &= ~X86_CR4_TLBFLUSH_BITS; vcpu->arch.cr4_guest_owned_bits &= ~X86_CR4_PDPTR_BITS; diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 205ebdc2b11b..05a40ab7cda2 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -108,7 +108,7 @@ u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); #endif -static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS; +static u64 __read_mostly cr4_kvm_reserved_bits = CR4_HOST_RESERVED_BITS; #define KVM_EXIT_HYPERCALL_VALID_MASK (1 << KVM_HC_MAP_GPA_RANGE) @@ -1082,10 +1082,10 @@ EXPORT_SYMBOL_GPL(kvm_emulate_xsetbv); bool __kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) { - if (cr4 & cr4_reserved_bits) + if (cr4 & cr4_kvm_reserved_bits) return false; - if (cr4 & vcpu->arch.cr4_guest_rsvd_bits) + if (cr4 & vcpu->arch.cr4_host_rsvd_bits) return false; return true; @@ -11965,7 +11965,7 @@ int kvm_arch_hardware_setup(void *opaque) kvm_caps.supported_xss = 0; #define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f) - cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_); + cr4_kvm_reserved_bits = __cr4_calc_reserved_bits(__kvm_cpu_cap_has, UNUSED_); #undef __kvm_cpu_cap_has if (kvm_caps.has_tsc_control) { @@ -11998,8 +11998,8 @@ int kvm_arch_check_processor_compat(void *opaque) WARN_ON(!irqs_disabled()); - if (__cr4_reserved_bits(cpu_has, c) != - __cr4_reserved_bits(cpu_has, &boot_cpu_data)) + if (__cr4_calc_reserved_bits(cpu_has, c) != + __cr4_calc_reserved_bits(cpu_has, &boot_cpu_data)) return -EIO; return ops->check_processor_compatibility(); diff --git a/arch/x86/kvm/x86.h b/arch/x86/kvm/x86.h index 1926d2cb8e79..4473bc0ba0f1 100644 --- a/arch/x86/kvm/x86.h +++ b/arch/x86/kvm/x86.h @@ -448,9 +448,9 @@ bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type); #define KVM_MSR_RET_INVALID 2 /* in-kernel MSR emulation #GP condition */ #define KVM_MSR_RET_FILTERED 3 /* #GP due to userspace MSR filter */ -#define __cr4_reserved_bits(__cpu_has, __c) \ +#define __cr4_calc_reserved_bits(__cpu_has, __c) \ ({ \ - u64 __reserved_bits = CR4_RESERVED_BITS; \ + u64 __reserved_bits = CR4_HOST_RESERVED_BITS; \ \ if (!__cpu_has(__c, X86_FEATURE_XSAVE)) \ __reserved_bits |= X86_CR4_OSXSAVE; \ From patchwork Mon Oct 17 07:04:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Hoo X-Patchwork-Id: 13008238 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 59BC0C433FE for ; Mon, 17 Oct 2022 07:05:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230076AbiJQHFk (ORCPT ); Mon, 17 Oct 2022 03:05:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33850 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230063AbiJQHF3 (ORCPT ); Mon, 17 Oct 2022 03:05:29 -0400 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D180C2E9E3 for ; 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a="579271394" X-IronPort-AV: E=Sophos;i="5.95,190,1661842800"; d="scan'208";a="579271394" Received: from sqa-gate.sh.intel.com (HELO robert-clx2.tsp.org) ([10.239.48.212]) by orsmga003.jf.intel.com with ESMTP; 17 Oct 2022 00:05:15 -0700 From: Robert Hoo To: seanjc@google.com, pbonzini@redhat.com Cc: kvm@vger.kernel.org, Robert Hoo , Jingqi Liu Subject: [PATCH 2/9] KVM: x86: Add CR4.LAM_SUP in guest owned bits Date: Mon, 17 Oct 2022 15:04:43 +0800 Message-Id: <20221017070450.23031-3-robert.hu@linux.intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20221017070450.23031-1-robert.hu@linux.intel.com> References: <20221017070450.23031-1-robert.hu@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org If LAM enabled, CR4.LAM_SUP is owned by guest; otherwise, reserved. Signed-off-by: Robert Hoo Reviewed-by: Jingqi Liu --- arch/x86/include/asm/kvm_host.h | 3 ++- arch/x86/kvm/kvm_cache_regs.h | 3 ++- arch/x86/kvm/x86.h | 2 ++ 3 files changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h index 4858436c64ef..e961fbd12833 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -120,7 +120,8 @@ | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR | X86_CR4_PCIDE \ | X86_CR4_OSXSAVE | X86_CR4_SMEP | X86_CR4_FSGSBASE \ | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_VMXE \ - | X86_CR4_SMAP | X86_CR4_PKE | X86_CR4_UMIP)) + | X86_CR4_SMAP | X86_CR4_PKE | X86_CR4_UMIP \ + | X86_CR4_LAM_SUP)) #define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR) diff --git a/arch/x86/kvm/kvm_cache_regs.h b/arch/x86/kvm/kvm_cache_regs.h index 3febc342360c..917f1b770839 100644 --- a/arch/x86/kvm/kvm_cache_regs.h +++ b/arch/x86/kvm/kvm_cache_regs.h @@ -7,7 +7,8 @@ #define KVM_POSSIBLE_CR0_GUEST_BITS X86_CR0_TS #define KVM_POSSIBLE_CR4_GUEST_BITS \ (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \ - | X86_CR4_OSXMMEXCPT | X86_CR4_PGE | X86_CR4_TSD | X86_CR4_FSGSBASE) + | X86_CR4_OSXMMEXCPT | X86_CR4_PGE | X86_CR4_TSD | X86_CR4_FSGSBASE \ + | X86_CR4_LAM_SUP) #define X86_CR0_PDPTR_BITS (X86_CR0_CD | X86_CR0_NW | X86_CR0_PG) #define X86_CR4_TLBFLUSH_BITS (X86_CR4_PGE | X86_CR4_PCIDE | X86_CR4_PAE | X86_CR4_SMEP) diff --git a/arch/x86/kvm/x86.h b/arch/x86/kvm/x86.h index 4473bc0ba0f1..c55d9e517d01 100644 --- a/arch/x86/kvm/x86.h +++ b/arch/x86/kvm/x86.h @@ -470,6 +470,8 @@ bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type); __reserved_bits |= X86_CR4_VMXE; \ if (!__cpu_has(__c, X86_FEATURE_PCID)) \ __reserved_bits |= X86_CR4_PCIDE; \ + if (!__cpu_has(__c, X86_FEATURE_LAM)) \ + __reserved_bits |= X86_CR4_LAM_SUP; \ __reserved_bits; \ }) From patchwork Mon Oct 17 07:04:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Hoo X-Patchwork-Id: 13008237 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6297EC43217 for ; Mon, 17 Oct 2022 07:05:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230091AbiJQHFj (ORCPT ); Mon, 17 Oct 2022 03:05:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34210 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230108AbiJQHF2 (ORCPT ); Mon, 17 Oct 2022 03:05:28 -0400 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 45CFD2E6AC for ; Mon, 17 Oct 2022 00:05:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1665990326; x=1697526326; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=zrt18il+PKnuY2T446RChBFIqI76pHMOFWN+kr/7deg=; b=UFnVKyYKssDlu/GSIrNUgluitKAXcHvNQgtIe7NkirNN4duIaHsELX6N /R53AN9qbY058m9aAsE8qza+ILrRBaCALTZET4osO8Rj3kSL/nS5xz7cY 7CpmOI8JByZEk3/fj+sy8RqOrezxkDzDfWaLJ4PvxdpBJlPE4fa2/Yf8c k2cBIEQt2IdHWSDvtOoGpUTXZWX4WxfVFRpFK+rFWM3VCxqeX8H+swpuh qyWMeE/aOqRmlaPSuNEpbrPS/TFnswJOuz+k6jmO5q5swA2hDT0cmVaNq zGhshPmd8J6F2nkDUKX0rfBlmzxCxb7SdaA+QKtpoz4dCT3icy6swFkDV g==; X-IronPort-AV: E=McAfee;i="6500,9779,10502"; a="306805987" X-IronPort-AV: E=Sophos;i="5.95,190,1661842800"; d="scan'208";a="306805987" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Oct 2022 00:05:23 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10502"; a="579271396" X-IronPort-AV: E=Sophos;i="5.95,190,1661842800"; d="scan'208";a="579271396" Received: from sqa-gate.sh.intel.com (HELO robert-clx2.tsp.org) ([10.239.48.212]) by orsmga003.jf.intel.com with ESMTP; 17 Oct 2022 00:05:17 -0700 From: Robert Hoo To: seanjc@google.com, pbonzini@redhat.com Cc: kvm@vger.kernel.org, Robert Hoo , Jingqi Liu Subject: [PATCH 3/9] KVM: x86: MMU: Rename get_cr3() --> get_pgd() and clear high bits for pgd Date: Mon, 17 Oct 2022 15:04:44 +0800 Message-Id: <20221017070450.23031-4-robert.hu@linux.intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20221017070450.23031-1-robert.hu@linux.intel.com> References: <20221017070450.23031-1-robert.hu@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The get_cr3() is the implementation of kvm_mmu::get_guest_pgd(), well, CR3 cannot be naturally equivalent to pgd, SDM says CR3 high bits are reserved, must be zero. And now, with LAM feature's introduction, bit 61 ~ 62 are used. So, rename get_cr3() --> get_pgd() to better indicate function purpose and in it, filtered out CR3 high bits. Signed-off-by: Robert Hoo Reviewed-by: Jingqi Liu --- arch/x86/include/asm/processor-flags.h | 1 + arch/x86/kvm/mmu/mmu.c | 10 +++++----- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/arch/x86/include/asm/processor-flags.h b/arch/x86/include/asm/processor-flags.h index d8cccadc83a6..bb0f8dd16956 100644 --- a/arch/x86/include/asm/processor-flags.h +++ b/arch/x86/include/asm/processor-flags.h @@ -38,6 +38,7 @@ #ifdef CONFIG_X86_64 /* Mask off the address space ID and SME encryption bits. */ #define CR3_ADDR_MASK __sme_clr(PHYSICAL_PAGE_MASK) +#define CR3_HIGH_RSVD_MASK GENMASK_ULL(63, 52) #define CR3_PCID_MASK 0xFFFull #define CR3_NOFLUSH BIT_ULL(63) diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c index eccddb136954..385a1a9b1ac4 100644 --- a/arch/x86/kvm/mmu/mmu.c +++ b/arch/x86/kvm/mmu/mmu.c @@ -4473,9 +4473,9 @@ void kvm_mmu_new_pgd(struct kvm_vcpu *vcpu, gpa_t new_pgd) } EXPORT_SYMBOL_GPL(kvm_mmu_new_pgd); -static unsigned long get_cr3(struct kvm_vcpu *vcpu) +static unsigned long get_pgd(struct kvm_vcpu *vcpu) { - return kvm_read_cr3(vcpu); + return kvm_read_cr3(vcpu) & ~CR3_HIGH_RSVD_MASK; } static bool sync_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn, @@ -5028,7 +5028,7 @@ static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu, context->page_fault = kvm_tdp_page_fault; context->sync_page = nonpaging_sync_page; context->invlpg = NULL; - context->get_guest_pgd = get_cr3; + context->get_guest_pgd = get_pgd; context->get_pdptr = kvm_pdptr_read; context->inject_page_fault = kvm_inject_page_fault; @@ -5178,7 +5178,7 @@ static void init_kvm_softmmu(struct kvm_vcpu *vcpu, kvm_init_shadow_mmu(vcpu, cpu_role); - context->get_guest_pgd = get_cr3; + context->get_guest_pgd = get_pgd; context->get_pdptr = kvm_pdptr_read; context->inject_page_fault = kvm_inject_page_fault; } @@ -5192,7 +5192,7 @@ static void init_kvm_nested_mmu(struct kvm_vcpu *vcpu, return; g_context->cpu_role.as_u64 = new_mode.as_u64; - g_context->get_guest_pgd = get_cr3; + g_context->get_guest_pgd = get_pgd; g_context->get_pdptr = kvm_pdptr_read; g_context->inject_page_fault = kvm_inject_page_fault; From patchwork Mon Oct 17 07:04:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Hoo X-Patchwork-Id: 13008239 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 70706C4332F for ; Mon, 17 Oct 2022 07:05:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230083AbiJQHFl (ORCPT ); Mon, 17 Oct 2022 03:05:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33848 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230116AbiJQHF3 (ORCPT ); Mon, 17 Oct 2022 03:05:29 -0400 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EE1F92ED74 for ; Mon, 17 Oct 2022 00:05:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1665990328; x=1697526328; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=tu83SZoF/RacnhkbCYiD4Vw9+wYNgusGRn+uARJfeBo=; b=Dok1g1gLl6II+FRLKTB7uFc9rpkRBiSk6DiH01tK2HaX5KSNjfd6in3c vBZmNLLW2yRY73uqdubHVjOMBYPGfys+k5UQvNf0G/MJIgwCO0jOl3laz 8rO78OcO8NEm97f2bw+LatZD6U9JdepGBygmYvk6dmwdy+2SgngBgcz/G 3k+0u8e8hV+yfQxLgjjcqfbtwL1DXsQ9mpl8p39OlWsXMYOz3E46I2ztu wZflZeskvhZFMWcdbOYXzYgzPJNtfmkPxLS8mMgZIAxFE3N9ypEVUI6X2 6HZg6gLSD1M0Rce/pwc85TixLLOvJmmtCjQNbJFz1YNXqEIqcfL6OmF8P A==; X-IronPort-AV: E=McAfee;i="6500,9779,10502"; a="306805992" X-IronPort-AV: E=Sophos;i="5.95,190,1661842800"; d="scan'208";a="306805992" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Oct 2022 00:05:23 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10502"; a="579271376" X-IronPort-AV: E=Sophos;i="5.95,190,1661842800"; d="scan'208";a="579271376" Received: from sqa-gate.sh.intel.com (HELO robert-clx2.tsp.org) ([10.239.48.212]) by orsmga003.jf.intel.com with ESMTP; 17 Oct 2022 00:05:19 -0700 From: Robert Hoo To: seanjc@google.com, pbonzini@redhat.com Cc: kvm@vger.kernel.org, Robert Hoo Subject: [PATCH 4/9] [Trivial] KVM: x86: MMU: Commets update Date: Mon, 17 Oct 2022 15:04:45 +0800 Message-Id: <20221017070450.23031-5-robert.hu@linux.intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20221017070450.23031-1-robert.hu@linux.intel.com> References: <20221017070450.23031-1-robert.hu@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org kvm_mmu_ensure_valid_pgd() is stale. Update the comments according to latest code. No function changes. P.S. Sean firstly noticed this in https://lore.kernel.org/kvm/Yg%2FguAXFLJBmDflh@google.com/. Signed-off-by: Robert Hoo --- arch/x86/kvm/mmu/mmu.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c index 385a1a9b1ac4..315456f30964 100644 --- a/arch/x86/kvm/mmu/mmu.c +++ b/arch/x86/kvm/mmu/mmu.c @@ -4437,8 +4437,12 @@ void kvm_mmu_new_pgd(struct kvm_vcpu *vcpu, gpa_t new_pgd) struct kvm_mmu *mmu = vcpu->arch.mmu; union kvm_mmu_page_role new_role = mmu->root_role; + /* + * If no root is found in cache, current active root.hpa will be (set) + * INVALID_PAGE, a new root will be set up during vcpu_enter_guest() + * --> kvm_mmu_reload(). + */ if (!fast_pgd_switch(vcpu->kvm, mmu, new_pgd, new_role)) { - /* kvm_mmu_ensure_valid_pgd will set up a new root. */ return; } From patchwork Mon Oct 17 07:04:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Hoo X-Patchwork-Id: 13008240 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 12DC5C433FE for ; Mon, 17 Oct 2022 07:05:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230073AbiJQHFn (ORCPT ); Mon, 17 Oct 2022 03:05:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34272 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230117AbiJQHF3 (ORCPT ); Mon, 17 Oct 2022 03:05:29 -0400 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 004C42EF09 for ; Mon, 17 Oct 2022 00:05:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1665990328; x=1697526328; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=DL1NrWy8aJKqkxgKu4Cp4Zlan8SfvCNr6zBtR8Rpb9I=; b=EhZyhV2x6SKeIdg6uMCJvJn0GZW+tPL5zmauFc+y2wxpBrP3JfdCkbEu YjuIXT/kY3jI7Eq9lnEehehWq6Q+NoBKGiCIaMGJY1ct7kXaq+Vw/3Ql/ A2D1ByUeYnLSrabEX5WUMcxCkpT5/XPkiE72JlnYtu8q8Xz0zfckG/yFi GlnZd3iuQ8nVPqnPBad7D67hrIjt+LVWHe87MIT0HUOIP1KCHqSFGLVHe YCbT2bpLxVtVR71dyokhrdholcCEd9fk5R4Fa0jI8SR3U6A7n4hCPCD4K nbnEl7xSTKIcc+K1QO/mZCuNlcn9sucWdtgh0U+c9zyLGkdVoff75HFLC A==; X-IronPort-AV: E=McAfee;i="6500,9779,10502"; a="306805993" X-IronPort-AV: E=Sophos;i="5.95,190,1661842800"; d="scan'208";a="306805993" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Oct 2022 00:05:24 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10502"; a="579271398" X-IronPort-AV: E=Sophos;i="5.95,190,1661842800"; d="scan'208";a="579271398" Received: from sqa-gate.sh.intel.com (HELO robert-clx2.tsp.org) ([10.239.48.212]) by orsmga003.jf.intel.com with ESMTP; 17 Oct 2022 00:05:20 -0700 From: Robert Hoo To: seanjc@google.com, pbonzini@redhat.com Cc: kvm@vger.kernel.org, Robert Hoo , Jingqi Liu Subject: [PATCH 5/9] KVM: x86: MMU: Integrate LAM bits when build guest CR3 Date: Mon, 17 Oct 2022 15:04:46 +0800 Message-Id: <20221017070450.23031-6-robert.hu@linux.intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20221017070450.23031-1-robert.hu@linux.intel.com> References: <20221017070450.23031-1-robert.hu@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org When calc the new CR3 value, take LAM bits in. Signed-off-by: Robert Hoo Reviewed-by: Jingqi Liu --- arch/x86/kvm/mmu.h | 5 +++++ arch/x86/kvm/vmx/vmx.c | 3 ++- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/mmu.h b/arch/x86/kvm/mmu.h index 6bdaacb6faa0..866f2b7cb509 100644 --- a/arch/x86/kvm/mmu.h +++ b/arch/x86/kvm/mmu.h @@ -142,6 +142,11 @@ static inline unsigned long kvm_get_active_pcid(struct kvm_vcpu *vcpu) return kvm_get_pcid(vcpu, kvm_read_cr3(vcpu)); } +static inline u64 kvm_get_active_lam(struct kvm_vcpu *vcpu) +{ + return kvm_read_cr3(vcpu) & (X86_CR3_LAM_U48 | X86_CR3_LAM_U57); +} + static inline void kvm_mmu_load_pgd(struct kvm_vcpu *vcpu) { u64 root_hpa = vcpu->arch.mmu->root.hpa; diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 97a2b8759ce8..ffb82daee1d3 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -3305,7 +3305,8 @@ static void vmx_load_mmu_pgd(struct kvm_vcpu *vcpu, hpa_t root_hpa, update_guest_cr3 = false; vmx_ept_load_pdptrs(vcpu); } else { - guest_cr3 = root_hpa | kvm_get_active_pcid(vcpu); + guest_cr3 = root_hpa | kvm_get_active_pcid(vcpu) | + kvm_get_active_lam(vcpu); } if (update_guest_cr3) From patchwork Mon Oct 17 07:04:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Hoo X-Patchwork-Id: 13008241 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AB51FC433FE for ; Mon, 17 Oct 2022 07:05:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230121AbiJQHFp (ORCPT ); Mon, 17 Oct 2022 03:05:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35212 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230116AbiJQHFn (ORCPT ); Mon, 17 Oct 2022 03:05:43 -0400 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0B7F845982 for ; Mon, 17 Oct 2022 00:05:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1665990342; x=1697526342; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=e56Kd/zuQTaQ0xl1PtcJww/ZVN+6cSPiBumJ7fLIzTg=; b=Dfb94HT6mdfZG5+KBeCZaaZiGKXIfbwz619nWPa++qLSeu3+mXdQEeWj y8wf2jHeIYRVAW+mEI9j3UVvJlm1uKi1JTWOo7YZbkw0JdXD5unOHWgAf eOmpZYbUKKssRdwd6NjUFoKgXc+4AzdZ/ADCck6R3MnlNYF/oZf1StMpV Anqo2Fwul93HxYb16dzW9hYCgTi0OWepC0axpZg3hH8pY3Uoj7tIVUS0N 4iu2Y4HVTvwjkCUHqVrGBT3aTNGzvYIBYvzfWF/IbKJFeCZo7rZTikZB3 67qFFNHrxfFaQiooGZeswhbp1+8WXoBvkxtI5w6rppEfZ0Wnxn1tCK+mf A==; X-IronPort-AV: E=McAfee;i="6500,9779,10502"; a="392031202" X-IronPort-AV: E=Sophos;i="5.95,190,1661842800"; d="scan'208";a="392031202" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Oct 2022 00:05:41 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10502"; a="579271401" X-IronPort-AV: E=Sophos;i="5.95,190,1661842800"; d="scan'208";a="579271401" Received: from sqa-gate.sh.intel.com (HELO robert-clx2.tsp.org) ([10.239.48.212]) by orsmga003.jf.intel.com with ESMTP; 17 Oct 2022 00:05:22 -0700 From: Robert Hoo To: seanjc@google.com, pbonzini@redhat.com Cc: kvm@vger.kernel.org, Robert Hoo , Jingqi Liu Subject: [PATCH 6/9] KVM: x86: Untag LAM bits when applicable Date: Mon, 17 Oct 2022 15:04:47 +0800 Message-Id: <20221017070450.23031-7-robert.hu@linux.intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20221017070450.23031-1-robert.hu@linux.intel.com> References: <20221017070450.23031-1-robert.hu@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Define kvm_untagged_addr() per LAM feature spec: Address high bits are sign extended, from highest effective address bit. Note that LAM_U48 and LA57 has some effective bits overlap. This patch gives a WARN() on that case. Now the only applicable possible case that addresses passed down from VM with LAM bits is those for MPX MSRs. Signed-off-by: Robert Hoo Reviewed-by: Jingqi Liu --- arch/x86/kvm/vmx/vmx.c | 3 +++ arch/x86/kvm/x86.c | 5 +++++ arch/x86/kvm/x86.h | 37 +++++++++++++++++++++++++++++++++++++ 3 files changed, 45 insertions(+) diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index ffb82daee1d3..76c9f4b8b340 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -2116,6 +2116,9 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) (!msr_info->host_initiated && !guest_cpuid_has(vcpu, X86_FEATURE_MPX))) return 1; + + data = kvm_untagged_addr(data, vcpu); + if (is_noncanonical_address(data & PAGE_MASK, vcpu) || (data & MSR_IA32_BNDCFGS_RSVD)) return 1; diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 05a40ab7cda2..3fa532cd1911 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -1780,6 +1780,11 @@ static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data, case MSR_KERNEL_GS_BASE: case MSR_CSTAR: case MSR_LSTAR: + /* + * LAM applies only addresses used for data accesses. + * Tagged address should never reach here. + * Strict canonical check still applies here. + */ if (is_noncanonical_address(data, vcpu)) return 1; break; diff --git a/arch/x86/kvm/x86.h b/arch/x86/kvm/x86.h index c55d9e517d01..f01a2ed9d3c0 100644 --- a/arch/x86/kvm/x86.h +++ b/arch/x86/kvm/x86.h @@ -187,11 +187,48 @@ static inline u8 vcpu_virt_addr_bits(struct kvm_vcpu *vcpu) return kvm_read_cr4_bits(vcpu, X86_CR4_LA57) ? 57 : 48; } +static inline u64 get_canonical(u64 la, u8 vaddr_bits) +{ + return ((int64_t)la << (64 - vaddr_bits)) >> (64 - vaddr_bits); +} + static inline bool is_noncanonical_address(u64 la, struct kvm_vcpu *vcpu) { return !__is_canonical_address(la, vcpu_virt_addr_bits(vcpu)); } +#ifdef CONFIG_X86_64 +/* untag addr for guest, according to vCPU CR3 and CR4 settings */ +static inline u64 kvm_untagged_addr(u64 addr, struct kvm_vcpu *vcpu) +{ + if (addr >> 63 == 0) { + /* User pointers */ + if (kvm_read_cr3(vcpu) & X86_CR3_LAM_U57) + addr = get_canonical(addr, 57); + else if (kvm_read_cr3(vcpu) & X86_CR3_LAM_U48) { + /* + * If guest enabled 5-level paging and LAM_U48, + * bit 47 should be 0, bit 48:56 contains meta data + * although bit 47:56 are valid 5-level address + * bits. + * If LAM_U48 and 4-level paging, bit47 is 0. + */ + WARN_ON(addr & _BITUL(47)); + addr = get_canonical(addr, 48); + } + } else if (kvm_read_cr4(vcpu) & X86_CR4_LAM_SUP) { /* Supervisor pointers */ + if (kvm_read_cr4(vcpu) & X86_CR4_LA57) + addr = get_canonical(addr, 57); + else + addr = get_canonical(addr, 48); + } + + return addr; +} +#else +#define kvm_untagged_addr(addr, vcpu) (addr) +#endif + static inline void vcpu_cache_mmio_info(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn, unsigned access) { From patchwork Mon Oct 17 07:04:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Hoo X-Patchwork-Id: 13008242 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 95D1EC433FE for ; Mon, 17 Oct 2022 07:05:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230133AbiJQHFs (ORCPT ); Mon, 17 Oct 2022 03:05:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35276 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230127AbiJQHFq (ORCPT ); Mon, 17 Oct 2022 03:05:46 -0400 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1689122B1C for ; Mon, 17 Oct 2022 00:05:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1665990344; x=1697526344; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+Zz77OkhNZKF8tBU8sPdCcTsGxcasRZTz3tmsxf8znk=; b=Y3PyokIIJYhhK3Ab4ONsdkwjraGHdbe3kw/F4rg79otN3PBY/msDETfo 5T8q8pnZTcnC/jF+995tGz+3tsBzT8yo+w7Pqzs+wZnAIFhvjCF6B+1bX FvkH0nCCyu9nlY3JLQ2WBAkWecmI7sgrZqvf4JNeXGWnH6X+apGH2SZSM uRD7P03Wh7JpRGGRJwdCu3lkqkVIBM2DRW3KJFwzW/V6uY5wyNPqBWFeF Qu4c2gIovEyZ0NAJujkzaKS3lehifGIH0+/tMaUbKZbGJsgSpmwKxmGYn how50YWHMqYUGRlHy7Y1CRe8GzXmv8aUcLkJwn59qFqygrYtmjWsQ3wYj Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10502"; a="392031203" X-IronPort-AV: E=Sophos;i="5.95,190,1661842800"; d="scan'208";a="392031203" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Oct 2022 00:05:41 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10502"; a="579271413" X-IronPort-AV: E=Sophos;i="5.95,190,1661842800"; d="scan'208";a="579271413" Received: from sqa-gate.sh.intel.com (HELO robert-clx2.tsp.org) ([10.239.48.212]) by orsmga003.jf.intel.com with ESMTP; 17 Oct 2022 00:05:24 -0700 From: Robert Hoo To: seanjc@google.com, pbonzini@redhat.com Cc: kvm@vger.kernel.org, Robert Hoo , Jingqi Liu Subject: [PATCH 7/9] KVM: x86: When judging setting CR3 valid or not, consider LAM bits Date: Mon, 17 Oct 2022 15:04:48 +0800 Message-Id: <20221017070450.23031-8-robert.hu@linux.intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20221017070450.23031-1-robert.hu@linux.intel.com> References: <20221017070450.23031-1-robert.hu@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Before apply to kvm_vcpu_is_illegal_gpa(), clear LAM bits if it's valid. Signed-off-by: Robert Hoo Reviewed-by: Jingqi Liu --- arch/x86/kvm/x86.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 3fa532cd1911..e9b465bff8d3 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -1217,6 +1217,14 @@ static void kvm_invalidate_pcid(struct kvm_vcpu *vcpu, unsigned long pcid) kvm_mmu_free_roots(vcpu->kvm, mmu, roots_to_free); } +static bool kvm_is_valid_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) +{ + if (guest_cpuid_has(vcpu, X86_FEATURE_LAM)) + cr3 &= ~(X86_CR3_LAM_U48 | X86_CR3_LAM_U57); + + return kvm_vcpu_is_legal_gpa(vcpu, cr3); +} + int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) { bool skip_tlb_flush = false; @@ -1240,7 +1248,7 @@ int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) * stuff CR3, e.g. for RSM emulation, and there is no guarantee that * the current vCPU mode is accurate. */ - if (kvm_vcpu_is_illegal_gpa(vcpu, cr3)) + if (!kvm_is_valid_cr3(vcpu, cr3)) return 1; if (is_pae_paging(vcpu) && !load_pdptrs(vcpu, cr3)) From patchwork Mon Oct 17 07:04:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Hoo X-Patchwork-Id: 13008243 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7FF06C433FE for ; Mon, 17 Oct 2022 07:05:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230154AbiJQHFu (ORCPT ); Mon, 17 Oct 2022 03:05:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35296 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230128AbiJQHFr (ORCPT ); Mon, 17 Oct 2022 03:05:47 -0400 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C1E9F4DF3B for ; Mon, 17 Oct 2022 00:05:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1665990344; x=1697526344; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=7ifg6/sc+fwSQXD/jV2lw/ufITayAG1Yn/Gno+7xKRw=; b=UfsWQJo2KuCNr1EtNbJB1Hk0rvJrS8ZUyTlMKOMVBLIOVdsN/RhphMVQ AN0WdG1doSxKEyIuL/oM6efug917cZw6V1/mXcaG4xuLF2bvw4CXGwjgu wwMf3d46ceVzyp7BOnETn9kyB7if8EdMQZoqVNB/2gSz6yt2yVZhiwfS3 h++phhL8YH9ZOsW9qXlxcjsNEdxIbm25dGjsVqS819HYFiD6KaQNrh07U Lb3LSEWzQnXZHlwWMf7MQi+9U8PWS+8m7peaf/0Mjp8rBNlSWw6MfvSYW z59p3a/hfLLuJzfbDY1Z91U/bXXqV3gldgjCuj6QslW6Fqh/W3rDEQMzA w==; X-IronPort-AV: E=McAfee;i="6500,9779,10502"; a="392031205" X-IronPort-AV: E=Sophos;i="5.95,190,1661842800"; d="scan'208";a="392031205" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Oct 2022 00:05:41 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10502"; a="579271416" X-IronPort-AV: E=Sophos;i="5.95,190,1661842800"; d="scan'208";a="579271416" Received: from sqa-gate.sh.intel.com (HELO robert-clx2.tsp.org) ([10.239.48.212]) by orsmga003.jf.intel.com with ESMTP; 17 Oct 2022 00:05:26 -0700 From: Robert Hoo To: seanjc@google.com, pbonzini@redhat.com Cc: kvm@vger.kernel.org, Robert Hoo Subject: [PATCH 8/9] KVM: x86: When guest set CR3, handle LAM bits semantics Date: Mon, 17 Oct 2022 15:04:49 +0800 Message-Id: <20221017070450.23031-9-robert.hu@linux.intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20221017070450.23031-1-robert.hu@linux.intel.com> References: <20221017070450.23031-1-robert.hu@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org When only changes LAM bits, ask next vcpu run to load mmu pgd, so that it will build new CR3 with LAM bits updates. No TLB flush needed on this case. When changes on effective addresses, no matter LAM bits changes or not, go through normal pgd update process. Signed-off-by: Robert Hoo --- arch/x86/kvm/x86.c | 26 ++++++++++++++++++++++---- 1 file changed, 22 insertions(+), 4 deletions(-) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index e9b465bff8d3..fb779f88ae88 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -1228,9 +1228,9 @@ static bool kvm_is_valid_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) { bool skip_tlb_flush = false; - unsigned long pcid = 0; + unsigned long pcid = 0, old_cr3; #ifdef CONFIG_X86_64 - bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); + bool pcid_enabled = !!kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); if (pcid_enabled) { skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH; @@ -1243,6 +1243,10 @@ int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) if (cr3 == kvm_read_cr3(vcpu) && !is_pae_paging(vcpu)) goto handle_tlb_flush; + if (!guest_cpuid_has(vcpu, X86_FEATURE_LAM) && + (cr3 & (X86_CR3_LAM_U48 | X86_CR3_LAM_U57))) + return 1; + /* * Do not condition the GPA check on long mode, this helper is used to * stuff CR3, e.g. for RSM emulation, and there is no guarantee that @@ -1254,8 +1258,22 @@ int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) if (is_pae_paging(vcpu) && !load_pdptrs(vcpu, cr3)) return 1; - if (cr3 != kvm_read_cr3(vcpu)) - kvm_mmu_new_pgd(vcpu, cr3); + old_cr3 = kvm_read_cr3(vcpu); + if (cr3 != old_cr3) { + if ((cr3 ^ old_cr3) & CR3_ADDR_MASK) { + kvm_mmu_new_pgd(vcpu, cr3 & ~(X86_CR3_LAM_U48 | + X86_CR3_LAM_U57)); + } else { + /* Only LAM conf changes, no tlb flush needed */ + skip_tlb_flush = true; + /* + * Though effective addr no change, mark the + * request so that LAM bits will take effect + * when enter guest. + */ + kvm_make_request(KVM_REQ_LOAD_MMU_PGD, vcpu); + } + } vcpu->arch.cr3 = cr3; kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3); From patchwork Mon Oct 17 07:04:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Hoo X-Patchwork-Id: 13008244 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A4A84C4332F for ; Mon, 17 Oct 2022 07:05:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230110AbiJQHFw (ORCPT ); Mon, 17 Oct 2022 03:05:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35402 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230135AbiJQHFt (ORCPT ); Mon, 17 Oct 2022 03:05:49 -0400 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 985EA45062 for ; Mon, 17 Oct 2022 00:05:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1665990346; x=1697526346; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=99ZJJ5HzQnjNx0/bsTWN33j47deBGn1IFbZmaJKs6hQ=; b=bJsFEmq/ZO63MCDJ8xf3kdQu8kCNOjS71HThKTBGPfQkH5dgzMQnL3UK N9ElPJQvdkegBAl1KEc0b22zdQVXps/ozXlt2pFylKl0Urt/PfxtQOKHN nbKLkz3IgDbjMJ60ORpGpWHP7PVvs6ZIhyhHWZHgf5hvfjV2rmH6E+9MB 0i4ADlIIM03dqvw23wWLdZ1X6C/HMYM2ik5uD779HqPlIuxXK7QvwqVCq PMXIs1OCxZZsFPlLRHAt4fpiBEe5sjueGgztz6tIWBVPZ6HhgCVu+0iCB WU0kLx6NaPQb/OdZwKGOtgQ0lRQQ2BVttqYZi1+WlR1cjRx9hCreogIgq Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10502"; a="392031207" X-IronPort-AV: E=Sophos;i="5.95,190,1661842800"; d="scan'208";a="392031207" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Oct 2022 00:05:41 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10502"; a="579271491" X-IronPort-AV: E=Sophos;i="5.95,190,1661842800"; d="scan'208";a="579271491" Received: from sqa-gate.sh.intel.com (HELO robert-clx2.tsp.org) ([10.239.48.212]) by orsmga003.jf.intel.com with ESMTP; 17 Oct 2022 00:05:27 -0700 From: Robert Hoo To: seanjc@google.com, pbonzini@redhat.com Cc: kvm@vger.kernel.org, Robert Hoo , Jingqi Liu Subject: [PATCH 9/9] KVM: x86: LAM: Expose LAM CPUID to user space VMM Date: Mon, 17 Oct 2022 15:04:50 +0800 Message-Id: <20221017070450.23031-10-robert.hu@linux.intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20221017070450.23031-1-robert.hu@linux.intel.com> References: <20221017070450.23031-1-robert.hu@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org LAM feature is enumerated by (EAX=07H, ECX=01H):EAX.LAM[bit26]. Signed-off-by: Robert Hoo Reviewed-by: Jingqi Liu --- arch/x86/kvm/cpuid.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index b935b3b04a7e..89bcac3e4ac4 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -636,7 +636,7 @@ void kvm_set_cpu_caps(void) kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL_SSBD); kvm_cpu_cap_mask(CPUID_7_1_EAX, - F(AVX_VNNI) | F(AVX512_BF16) + F(AVX_VNNI) | F(AVX512_BF16) | F(LAM) ); kvm_cpu_cap_mask(CPUID_D_1_EAX,